drivers/media/video/cx23885/cx23885-417.c

   1 /*
   2  *
   3  *  Support for a cx23417 mpeg encoder via cx23885 host port.
   4  *
   5  *    (c) 2004 Jelle Foks <jelle@foks.us>
   6  *    (c) 2004 Gerd Knorr <kraxel@bytesex.org>
   7  *    (c) 2008 Steven Toth <stoth@linuxtv.org>
   8  *      - CX23885/7/8 support
   9  *
  10  *  Includes parts from the ivtv driver <http://sourceforge.net/projects/ivtv/>
  11  *
  12  *  This program is free software; you can redistribute it and/or modify
  13  *  it under the terms of the GNU General Public License as published by
  14  *  the Free Software Foundation; either version 2 of the License, or
  15  *  (at your option) any later version.
  16  *
  17  *  This program is distributed in the hope that it will be useful,
  18  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  *  GNU General Public License for more details.
  21  *
  22  *  You should have received a copy of the GNU General Public License
  23  *  along with this program; if not, write to the Free Software
  24  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/init.h>
  30 #include <linux/fs.h>
  31 #include <linux/delay.h>
  32 #include <linux/device.h>
  33 #include <linux/firmware.h>
  34 #include <linux/smp_lock.h>
  35 #include <linux/slab.h>
  36 #include <media/v4l2-common.h>
  37 #include <media/v4l2-ioctl.h>
  38 #include <media/cx2341x.h>
  39
  40 #include "cx23885.h"
  41 #include "cx23885-ioctl.h"
  42
  43 #define CX23885_FIRM_IMAGE_SIZE 376836
  44 #define CX23885_FIRM_IMAGE_NAME "v4l-cx23885-enc.fw"
  45
  46 static unsigned int mpegbufs = 32;
  47 module_param(mpegbufs, int, 0644);
  48 MODULE_PARM_DESC(mpegbufs, "number of mpeg buffers, range 2-32");
  49 static unsigned int mpeglines = 32;
  50 module_param(mpeglines, int, 0644);
  51 MODULE_PARM_DESC(mpeglines, "number of lines in an MPEG buffer, range 2-32");
  52 static unsigned int mpeglinesize = 512;
  53 module_param(mpeglinesize, int, 0644);
  54 MODULE_PARM_DESC(mpeglinesize,
  55         "number of bytes in each line of an MPEG buffer, range 512-1024");
  56
  57 static unsigned int v4l_debug;
  58 module_param(v4l_debug, int, 0644);
  59 MODULE_PARM_DESC(v4l_debug, "enable V4L debug messages");
  60
  61 #define dprintk(level, fmt, arg...)\
  62         do { if (v4l_debug >= level) \
  63                 printk(KERN_DEBUG "%s: " fmt, \
  64                 (dev) ? dev->name : "cx23885[?]", ## arg); \
  65         } while (0)
  66
  67 static struct cx23885_tvnorm cx23885_tvnorms[] = {
  68         {
  69                 .name      = "NTSC-M",
  70                 .id        = V4L2_STD_NTSC_M,
  71         }, {
  72                 .name      = "NTSC-JP",
  73                 .id        = V4L2_STD_NTSC_M_JP,
  74         }, {
  75                 .name      = "PAL-BG",
  76                 .id        = V4L2_STD_PAL_BG,
  77         }, {
  78                 .name      = "PAL-DK",
  79                 .id        = V4L2_STD_PAL_DK,
  80         }, {
  81                 .name      = "PAL-I",
  82                 .id        = V4L2_STD_PAL_I,
  83         }, {
  84                 .name      = "PAL-M",
  85                 .id        = V4L2_STD_PAL_M,
  86         }, {
  87                 .name      = "PAL-N",
  88                 .id        = V4L2_STD_PAL_N,
  89         }, {
  90                 .name      = "PAL-Nc",
  91                 .id        = V4L2_STD_PAL_Nc,
  92         }, {
  93                 .name      = "PAL-60",
  94                 .id        = V4L2_STD_PAL_60,
  95         }, {
  96                 .name      = "SECAM-L",
  97                 .id        = V4L2_STD_SECAM_L,
  98         }, {
  99                 .name      = "SECAM-DK",
 100                 .id        = V4L2_STD_SECAM_DK,
 101         }
 102 };
 103
 104 /* ------------------------------------------------------------------ */
 105 enum cx23885_capture_type {
 106         CX23885_MPEG_CAPTURE,
 107         CX23885_RAW_CAPTURE,
 108         CX23885_RAW_PASSTHRU_CAPTURE
 109 };
 110 enum cx23885_capture_bits {
 111         CX23885_RAW_BITS_NONE             = 0x00,
 112         CX23885_RAW_BITS_YUV_CAPTURE      = 0x01,
 113         CX23885_RAW_BITS_PCM_CAPTURE      = 0x02,
 114         CX23885_RAW_BITS_VBI_CAPTURE      = 0x04,
 115         CX23885_RAW_BITS_PASSTHRU_CAPTURE = 0x08,
 116         CX23885_RAW_BITS_TO_HOST_CAPTURE  = 0x10
 117 };
 118 enum cx23885_capture_end {
 119         CX23885_END_AT_GOP, /* stop at the end of gop, generate irq */
 120         CX23885_END_NOW, /* stop immediately, no irq */
 121 };
 122 enum cx23885_framerate {
 123         CX23885_FRAMERATE_NTSC_30, /* NTSC: 30fps */
 124         CX23885_FRAMERATE_PAL_25   /* PAL: 25fps */
 125 };
 126 enum cx23885_stream_port {
 127         CX23885_OUTPUT_PORT_MEMORY,
 128         CX23885_OUTPUT_PORT_STREAMING,
 129         CX23885_OUTPUT_PORT_SERIAL
 130 };
 131 enum cx23885_data_xfer_status {
 132         CX23885_MORE_BUFFERS_FOLLOW,
 133         CX23885_LAST_BUFFER,
 134 };
 135 enum cx23885_picture_mask {
 136         CX23885_PICTURE_MASK_NONE,
 137         CX23885_PICTURE_MASK_I_FRAMES,
 138         CX23885_PICTURE_MASK_I_P_FRAMES = 0x3,
 139         CX23885_PICTURE_MASK_ALL_FRAMES = 0x7,
 140 };
 141 enum cx23885_vbi_mode_bits {
 142         CX23885_VBI_BITS_SLICED,
 143         CX23885_VBI_BITS_RAW,
 144 };
 145 enum cx23885_vbi_insertion_bits {
 146         CX23885_VBI_BITS_INSERT_IN_XTENSION_USR_DATA,
 147         CX23885_VBI_BITS_INSERT_IN_PRIVATE_PACKETS = 0x1 << 1,
 148         CX23885_VBI_BITS_SEPARATE_STREAM = 0x2 << 1,
 149         CX23885_VBI_BITS_SEPARATE_STREAM_USR_DATA = 0x4 << 1,
 150         CX23885_VBI_BITS_SEPARATE_STREAM_PRV_DATA = 0x5 << 1,
 151 };
 152 enum cx23885_dma_unit {
 153         CX23885_DMA_BYTES,
 154         CX23885_DMA_FRAMES,
 155 };
 156 enum cx23885_dma_transfer_status_bits {
 157         CX23885_DMA_TRANSFER_BITS_DONE = 0x01,
 158         CX23885_DMA_TRANSFER_BITS_ERROR = 0x04,
 159         CX23885_DMA_TRANSFER_BITS_LL_ERROR = 0x10,
 160 };
 161 enum cx23885_pause {
 162         CX23885_PAUSE_ENCODING,
 163         CX23885_RESUME_ENCODING,
 164 };
 165 enum cx23885_copyright {
 166         CX23885_COPYRIGHT_OFF,
 167         CX23885_COPYRIGHT_ON,
 168 };
 169 enum cx23885_notification_type {
 170         CX23885_NOTIFICATION_REFRESH,
 171 };
 172 enum cx23885_notification_status {
 173         CX23885_NOTIFICATION_OFF,
 174         CX23885_NOTIFICATION_ON,
 175 };
 176 enum cx23885_notification_mailbox {
 177         CX23885_NOTIFICATION_NO_MAILBOX = -1,
 178 };
 179 enum cx23885_field1_lines {
 180         CX23885_FIELD1_SAA7114 = 0x00EF, /* 239 */
 181         CX23885_FIELD1_SAA7115 = 0x00F0, /* 240 */
 182         CX23885_FIELD1_MICRONAS = 0x0105, /* 261 */
 183 };
 184 enum cx23885_field2_lines {
 185         CX23885_FIELD2_SAA7114 = 0x00EF, /* 239 */
 186         CX23885_FIELD2_SAA7115 = 0x00F0, /* 240 */
 187         CX23885_FIELD2_MICRONAS = 0x0106, /* 262 */
 188 };
 189 enum cx23885_custom_data_type {
 190         CX23885_CUSTOM_EXTENSION_USR_DATA,
 191         CX23885_CUSTOM_PRIVATE_PACKET,
 192 };
 193 enum cx23885_mute {
 194         CX23885_UNMUTE,
 195         CX23885_MUTE,
 196 };
 197 enum cx23885_mute_video_mask {
 198         CX23885_MUTE_VIDEO_V_MASK = 0x0000FF00,
 199         CX23885_MUTE_VIDEO_U_MASK = 0x00FF0000,
 200         CX23885_MUTE_VIDEO_Y_MASK = 0xFF000000,
 201 };
 202 enum cx23885_mute_video_shift {
 203         CX23885_MUTE_VIDEO_V_SHIFT = 8,
 204         CX23885_MUTE_VIDEO_U_SHIFT = 16,
 205         CX23885_MUTE_VIDEO_Y_SHIFT = 24,
 206 };
 207
 208 /* defines below are from ivtv-driver.h */
 209 #define IVTV_CMD_HW_BLOCKS_RST 0xFFFFFFFF
 210
 211 /* Firmware API commands */
 212 #define IVTV_API_STD_TIMEOUT 500
 213
 214 /* Registers */
 215 /* IVTV_REG_OFFSET */
 216 #define IVTV_REG_ENC_SDRAM_REFRESH (0x07F8)
 217 #define IVTV_REG_ENC_SDRAM_PRECHARGE (0x07FC)
 218 #define IVTV_REG_SPU (0x9050)
 219 #define IVTV_REG_HW_BLOCKS (0x9054)
 220 #define IVTV_REG_VPU (0x9058)
 221 #define IVTV_REG_APU (0xA064)
 222
 223 /**** Bit definitions for MC417_RWD and MC417_OEN registers  ***
 224   bits 31-16
 225 +-----------+
 226 | Reserved  |
 227 +-----------+
 228   bit 15  bit 14  bit 13 bit 12  bit 11  bit 10  bit 9   bit 8
 229 +-------+-------+-------+-------+-------+-------+-------+-------+
 230 | MIWR# | MIRD# | MICS# |MIRDY# |MIADDR3|MIADDR2|MIADDR1|MIADDR0|
 231 +-------+-------+-------+-------+-------+-------+-------+-------+
 232  bit 7   bit 6   bit 5   bit 4   bit 3   bit 2   bit 1   bit 0
 233 +-------+-------+-------+-------+-------+-------+-------+-------+
 234 |MIDATA7|MIDATA6|MIDATA5|MIDATA4|MIDATA3|MIDATA2|MIDATA1|MIDATA0|
 235 +-------+-------+-------+-------+-------+-------+-------+-------+
 236 ***/
 237 #define MC417_MIWR      0x8000
 238 #define MC417_MIRD      0x4000
 239 #define MC417_MICS      0x2000
 240 #define MC417_MIRDY     0x1000
 241 #define MC417_MIADDR    0x0F00
 242 #define MC417_MIDATA    0x00FF
 243
 244 /* MIADDR* nibble definitions */
 245 #define  MCI_MEMORY_DATA_BYTE0          0x000
 246 #define  MCI_MEMORY_DATA_BYTE1          0x100
 247 #define  MCI_MEMORY_DATA_BYTE2          0x200
 248 #define  MCI_MEMORY_DATA_BYTE3          0x300
 249 #define  MCI_MEMORY_ADDRESS_BYTE2       0x400
 250 #define  MCI_MEMORY_ADDRESS_BYTE1       0x500
 251 #define  MCI_MEMORY_ADDRESS_BYTE0       0x600
 252 #define  MCI_REGISTER_DATA_BYTE0        0x800
 253 #define  MCI_REGISTER_DATA_BYTE1        0x900
 254 #define  MCI_REGISTER_DATA_BYTE2        0xA00
 255 #define  MCI_REGISTER_DATA_BYTE3        0xB00
 256 #define  MCI_REGISTER_ADDRESS_BYTE0     0xC00
 257 #define  MCI_REGISTER_ADDRESS_BYTE1     0xD00
 258 #define  MCI_REGISTER_MODE              0xE00
 259
 260 /* Read and write modes */
 261 #define  MCI_MODE_REGISTER_READ         0
 262 #define  MCI_MODE_REGISTER_WRITE        1
 263 #define  MCI_MODE_MEMORY_READ           0
 264 #define  MCI_MODE_MEMORY_WRITE          0x40
 265
 266 /*** Bit definitions for MC417_CTL register ****
 267  bits 31-6   bits 5-4   bit 3    bits 2-1       Bit 0
 268 +--------+-------------+--------+--------------+------------+
 269 |Reserved|MC417_SPD_CTL|Reserved|MC417_GPIO_SEL|UART_GPIO_EN|
 270 +--------+-------------+--------+--------------+------------+
 271 ***/
 272 #define MC417_SPD_CTL(x)        (((x) << 4) & 0x00000030)
 273 #define MC417_GPIO_SEL(x)       (((x) << 1) & 0x00000006)
 274 #define MC417_UART_GPIO_EN      0x00000001
 275
 276 /* Values for speed control */
 277 #define MC417_SPD_CTL_SLOW      0x1
 278 #define MC417_SPD_CTL_MEDIUM    0x0
 279 #define MC417_SPD_CTL_FAST      0x3     /* b'1x, but we use b'11 */
 280
 281 /* Values for GPIO select */
 282 #define MC417_GPIO_SEL_GPIO3    0x3
 283 #define MC417_GPIO_SEL_GPIO2    0x2
 284 #define MC417_GPIO_SEL_GPIO1    0x1
 285 #define MC417_GPIO_SEL_GPIO0    0x0
 286
 287 void cx23885_mc417_init(struct cx23885_dev *dev)
 288 {
 289         u32 regval;
 290
 291         dprintk(2, "%s()\n", __func__);
 292
 293         /* Configure MC417_CTL register to defaults. */
 294         regval = MC417_SPD_CTL(MC417_SPD_CTL_FAST)      |
 295                  MC417_GPIO_SEL(MC417_GPIO_SEL_GPIO3)   |
 296                  MC417_UART_GPIO_EN;
 297         cx_write(MC417_CTL, regval);
 298
 299         /* Configure MC417_OEN to defaults. */
 300         regval = MC417_MIRDY;
 301         cx_write(MC417_OEN, regval);
 302
 303         /* Configure MC417_RWD to defaults. */
 304         regval = MC417_MIWR | MC417_MIRD | MC417_MICS;
 305         cx_write(MC417_RWD, regval);
 306 }
 307
 308 static int mc417_wait_ready(struct cx23885_dev *dev)
 309 {
 310         u32 mi_ready;
 311         unsigned long timeout = jiffies + msecs_to_jiffies(1);
 312
 313         for (;;) {
 314                 mi_ready = cx_read(MC417_RWD) & MC417_MIRDY;
 315                 if (mi_ready != 0)
 316                         return 0;
 317                 if (time_after(jiffies, timeout))
 318                         return -1;
 319                 udelay(1);
 320         }
 321 }
 322
 323 int mc417_register_write(struct cx23885_dev *dev, u16 address, u32 value)
 324 {
 325         u32 regval;
 326
 327         /* Enable MC417 GPIO outputs except for MC417_MIRDY,
 328          * which is an input.
 329          */
 330         cx_write(MC417_OEN, MC417_MIRDY);
 331
 332         /* Write data byte 0 */
 333         regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0 |
 334                 (value & 0x000000FF);
 335         cx_write(MC417_RWD, regval);
 336
 337         /* Transition CS/WR to effect write transaction across bus. */
 338         regval |= MC417_MICS | MC417_MIWR;
 339         cx_write(MC417_RWD, regval);
 340
 341         /* Write data byte 1 */
 342         regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE1 |
 343                 ((value >> 8) & 0x000000FF);
 344         cx_write(MC417_RWD, regval);
 345         regval |= MC417_MICS | MC417_MIWR;
 346         cx_write(MC417_RWD, regval);
 347
 348         /* Write data byte 2 */
 349         regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE2 |
 350                 ((value >> 16) & 0x000000FF);
 351         cx_write(MC417_RWD, regval);
 352         regval |= MC417_MICS | MC417_MIWR;
 353         cx_write(MC417_RWD, regval);
 354
 355         /* Write data byte 3 */
 356         regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE3 |
 357                 ((value >> 24) & 0x000000FF);
 358         cx_write(MC417_RWD, regval);
 359         regval |= MC417_MICS | MC417_MIWR;
 360         cx_write(MC417_RWD, regval);
 361
 362         /* Write address byte 0 */
 363         regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE0 |
 364                 (address & 0xFF);
 365         cx_write(MC417_RWD, regval);
 366         regval |= MC417_MICS | MC417_MIWR;
 367         cx_write(MC417_RWD, regval);
 368
 369         /* Write address byte 1 */
 370         regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE1 |
 371                 ((address >> 8) & 0xFF);
 372         cx_write(MC417_RWD, regval);
 373         regval |= MC417_MICS | MC417_MIWR;
 374         cx_write(MC417_RWD, regval);
 375
 376         /* Indicate that this is a write. */
 377         regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_MODE |
 378                 MCI_MODE_REGISTER_WRITE;
 379         cx_write(MC417_RWD, regval);
 380         regval |= MC417_MICS | MC417_MIWR;
 381         cx_write(MC417_RWD, regval);
 382
 383         /* Wait for the trans to complete (MC417_MIRDY asserted). */
 384         return mc417_wait_ready(dev);
 385 }
 386
 387 int mc417_register_read(struct cx23885_dev *dev, u16 address, u32 *value)
 388 {
 389         int retval;
 390         u32 regval;
 391         u32 tempval;
 392         u32 dataval;
 393
 394         /* Enable MC417 GPIO outputs except for MC417_MIRDY,
 395          * which is an input.
 396          */
 397         cx_write(MC417_OEN, MC417_MIRDY);
 398
 399         /* Write address byte 0 */
 400         regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE0 |
 401                 ((address & 0x00FF));
 402         cx_write(MC417_RWD, regval);
 403         regval |= MC417_MICS | MC417_MIWR;
 404         cx_write(MC417_RWD, regval);
 405
 406         /* Write address byte 1 */
 407         regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE1 |
 408                 ((address >> 8) & 0xFF);
 409         cx_write(MC417_RWD, regval);
 410         regval |= MC417_MICS | MC417_MIWR;
 411         cx_write(MC417_RWD, regval);
 412
 413         /* Indicate that this is a register read. */
 414         regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_MODE |
 415                 MCI_MODE_REGISTER_READ;
 416         cx_write(MC417_RWD, regval);
 417         regval |= MC417_MICS | MC417_MIWR;
 418         cx_write(MC417_RWD, regval);
 419
 420         /* Wait for the trans to complete (MC417_MIRDY asserted). */
 421         retval = mc417_wait_ready(dev);
 422
 423         /* switch the DAT0-7 GPIO[10:3] to input mode */
 424         cx_write(MC417_OEN, MC417_MIRDY | MC417_MIDATA);
 425
 426         /* Read data byte 0 */
 427         regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0;
 428         cx_write(MC417_RWD, regval);
 429
 430         /* Transition RD to effect read transaction across bus.
 431          * Transtion 0x5000 -> 0x9000 correct (RD/RDY -> WR/RDY)?
 432          * Should it be 0x9000 -> 0xF000 (also why is RDY being set, its
 433          * input only...)
 434          */
 435         regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0;
 436         cx_write(MC417_RWD, regval);
 437
 438         /* Collect byte */
 439         tempval = cx_read(MC417_RWD);
 440         dataval = tempval & 0x000000FF;
 441
 442         /* Bring CS and RD high. */
 443         regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
 444         cx_write(MC417_RWD, regval);
 445
 446         /* Read data byte 1 */
 447         regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE1;
 448         cx_write(MC417_RWD, regval);
 449         regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE1;
 450         cx_write(MC417_RWD, regval);
 451         tempval = cx_read(MC417_RWD);
 452         dataval |= ((tempval & 0x000000FF) << 8);
 453         regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
 454         cx_write(MC417_RWD, regval);
 455
 456         /* Read data byte 2 */
 457         regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE2;
 458         cx_write(MC417_RWD, regval);
 459         regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE2;
 460         cx_write(MC417_RWD, regval);
 461         tempval = cx_read(MC417_RWD);
 462         dataval |= ((tempval & 0x000000FF) << 16);
 463         regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
 464         cx_write(MC417_RWD, regval);
 465
 466         /* Read data byte 3 */
 467         regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE3;
 468         cx_write(MC417_RWD, regval);
 469         regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE3;
 470         cx_write(MC417_RWD, regval);
 471         tempval = cx_read(MC417_RWD);
 472         dataval |= ((tempval & 0x000000FF) << 24);
 473         regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
 474         cx_write(MC417_RWD, regval);
 475
 476         *value  = dataval;
 477
 478         return retval;
 479 }
 480
 481 int mc417_memory_write(struct cx23885_dev *dev, u32 address, u32 value)
 482 {
 483         u32 regval;
 484
 485         /* Enable MC417 GPIO outputs except for MC417_MIRDY,
 486          * which is an input.
 487          */
 488         cx_write(MC417_OEN, MC417_MIRDY);
 489
 490         /* Write data byte 0 */
 491         regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE0 |
 492                 (value & 0x000000FF);
 493         cx_write(MC417_RWD, regval);
 494
 495         /* Transition CS/WR to effect write transaction across bus. */
 496         regval |= MC417_MICS | MC417_MIWR;
 497         cx_write(MC417_RWD, regval);
 498
 499         /* Write data byte 1 */
 500         regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE1 |
 501                 ((value >> 8) & 0x000000FF);
 502         cx_write(MC417_RWD, regval);
 503         regval |= MC417_MICS | MC417_MIWR;
 504         cx_write(MC417_RWD, regval);
 505
 506         /* Write data byte 2 */
 507         regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE2 |
 508                 ((value >> 16) & 0x000000FF);
 509         cx_write(MC417_RWD, regval);
 510         regval |= MC417_MICS | MC417_MIWR;
 511         cx_write(MC417_RWD, regval);
 512
 513         /* Write data byte 3 */
 514         regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE3 |
 515                 ((value >> 24) & 0x000000FF);
 516         cx_write(MC417_RWD, regval);
 517         regval |= MC417_MICS | MC417_MIWR;
 518         cx_write(MC417_RWD, regval);
 519
 520         /* Write address byte 2 */
 521         regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE2 |
 522                 MCI_MODE_MEMORY_WRITE | ((address >> 16) & 0x3F);
 523         cx_write(MC417_RWD, regval);
 524         regval |= MC417_MICS | MC417_MIWR;
 525         cx_write(MC417_RWD, regval);
 526
 527         /* Write address byte 1 */
 528         regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE1 |
 529                 ((address >> 8) & 0xFF);
 530         cx_write(MC417_RWD, regval);
 531         regval |= MC417_MICS | MC417_MIWR;
 532         cx_write(MC417_RWD, regval);
 533
 534         /* Write address byte 0 */
 535         regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE0 |
 536                 (address & 0xFF);
 537         cx_write(MC417_RWD, regval);
 538         regval |= MC417_MICS | MC417_MIWR;
 539         cx_write(MC417_RWD, regval);
 540
 541         /* Wait for the trans to complete (MC417_MIRDY asserted). */
 542         return mc417_wait_ready(dev);
 543 }
 544
 545 int mc417_memory_read(struct cx23885_dev *dev, u32 address, u32 *value)
 546 {
 547         int retval;
 548         u32 regval;
 549         u32 tempval;
 550         u32 dataval;
 551
 552         /* Enable MC417 GPIO outputs except for MC417_MIRDY,
 553          * which is an input.
 554          */
 555         cx_write(MC417_OEN, MC417_MIRDY);
 556
 557         /* Write address byte 2 */
 558         regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE2 |
 559                 MCI_MODE_MEMORY_READ | ((address >> 16) & 0x3F);
 560         cx_write(MC417_RWD, regval);
 561         regval |= MC417_MICS | MC417_MIWR;
 562         cx_write(MC417_RWD, regval);
 563
 564         /* Write address byte 1 */
 565         regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE1 |
 566                 ((address >> 8) & 0xFF);
 567         cx_write(MC417_RWD, regval);
 568         regval |= MC417_MICS | MC417_MIWR;
 569         cx_write(MC417_RWD, regval);
 570
 571         /* Write address byte 0 */
 572         regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE0 |
 573                 (address & 0xFF);
 574         cx_write(MC417_RWD, regval);
 575         regval |= MC417_MICS | MC417_MIWR;
 576         cx_write(MC417_RWD, regval);
 577
 578         /* Wait for the trans to complete (MC417_MIRDY asserted). */
 579         retval = mc417_wait_ready(dev);
 580
 581         /* switch the DAT0-7 GPIO[10:3] to input mode */
 582         cx_write(MC417_OEN, MC417_MIRDY | MC417_MIDATA);
 583
 584         /* Read data byte 3 */
 585         regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE3;
 586         cx_write(MC417_RWD, regval);
 587
 588         /* Transition RD to effect read transaction across bus. */
 589         regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE3;
 590         cx_write(MC417_RWD, regval);
 591
 592         /* Collect byte */
 593         tempval = cx_read(MC417_RWD);
 594         dataval = ((tempval & 0x000000FF) << 24);
 595
 596         /* Bring CS and RD high. */
 597         regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
 598         cx_write(MC417_RWD, regval);
 599
 600         /* Read data byte 2 */
 601         regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE2;
 602         cx_write(MC417_RWD, regval);
 603         regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE2;
 604         cx_write(MC417_RWD, regval);
 605         tempval = cx_read(MC417_RWD);
 606         dataval |= ((tempval & 0x000000FF) << 16);
 607         regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
 608         cx_write(MC417_RWD, regval);
 609
 610         /* Read data byte 1 */
 611         regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE1;
 612         cx_write(MC417_RWD, regval);
 613         regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE1;
 614         cx_write(MC417_RWD, regval);
 615         tempval = cx_read(MC417_RWD);
 616         dataval |= ((tempval & 0x000000FF) << 8);
 617         regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
 618         cx_write(MC417_RWD, regval);
 619
 620         /* Read data byte 0 */
 621         regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE0;
 622         cx_write(MC417_RWD, regval);
 623         regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE0;
 624         cx_write(MC417_RWD, regval);
 625         tempval = cx_read(MC417_RWD);
 626         dataval |= (tempval & 0x000000FF);
 627         regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
 628         cx_write(MC417_RWD, regval);
 629
 630         *value  = dataval;
 631
 632         return retval;
 633 }
 634
 635 void mc417_gpio_set(struct cx23885_dev *dev, u32 mask)
 636 {
 637         u32 val;
 638
 639         /* Set the gpio value */
 640         mc417_register_read(dev, 0x900C, &val);
 641         val |= (mask & 0x000ffff);
 642         mc417_register_write(dev, 0x900C, val);
 643 }
 644
 645 void mc417_gpio_clear(struct cx23885_dev *dev, u32 mask)
 646 {
 647         u32 val;
 648
 649         /* Clear the gpio value */
 650         mc417_register_read(dev, 0x900C, &val);
 651         val &= ~(mask & 0x0000ffff);
 652         mc417_register_write(dev, 0x900C, val);
 653 }
 654
 655 void mc417_gpio_enable(struct cx23885_dev *dev, u32 mask, int asoutput)
 656 {
 657         u32 val;
 658
 659         /* Enable GPIO direction bits */
 660         mc417_register_read(dev, 0x9020, &val);
 661         if (asoutput)
 662                 val |= (mask & 0x0000ffff);
 663         else
 664                 val &= ~(mask & 0x0000ffff);
 665
 666         mc417_register_write(dev, 0x9020, val);
 667 }
 668 /* ------------------------------------------------------------------ */
 669
 670 /* MPEG encoder API */
 671 static char *cmd_to_str(int cmd)
 672 {
 673         switch (cmd) {
 674         case CX2341X_ENC_PING_FW:
 675                 return  "PING_FW";
 676         case CX2341X_ENC_START_CAPTURE:
 677                 return  "START_CAPTURE";
 678         case CX2341X_ENC_STOP_CAPTURE:
 679                 return  "STOP_CAPTURE";
 680         case CX2341X_ENC_SET_AUDIO_ID:
 681                 return  "SET_AUDIO_ID";
 682         case CX2341X_ENC_SET_VIDEO_ID:
 683                 return  "SET_VIDEO_ID";
 684         case CX2341X_ENC_SET_PCR_ID:
 685                 return  "SET_PCR_ID";
 686         case CX2341X_ENC_SET_FRAME_RATE:
 687                 return  "SET_FRAME_RATE";
 688         case CX2341X_ENC_SET_FRAME_SIZE:
 689                 return  "SET_FRAME_SIZE";
 690         case CX2341X_ENC_SET_BIT_RATE:
 691                 return  "SET_BIT_RATE";
 692         case CX2341X_ENC_SET_GOP_PROPERTIES:
 693                 return  "SET_GOP_PROPERTIES";
 694         case CX2341X_ENC_SET_ASPECT_RATIO:
 695                 return  "SET_ASPECT_RATIO";
 696         case CX2341X_ENC_SET_DNR_FILTER_MODE:
 697                 return  "SET_DNR_FILTER_MODE";
 698         case CX2341X_ENC_SET_DNR_FILTER_PROPS:
 699                 return  "SET_DNR_FILTER_PROPS";
 700         case CX2341X_ENC_SET_CORING_LEVELS:
 701                 return  "SET_CORING_LEVELS";
 702         case CX2341X_ENC_SET_SPATIAL_FILTER_TYPE:
 703                 return  "SET_SPATIAL_FILTER_TYPE";
 704         case CX2341X_ENC_SET_VBI_LINE:
 705                 return  "SET_VBI_LINE";
 706         case CX2341X_ENC_SET_STREAM_TYPE:
 707                 return  "SET_STREAM_TYPE";
 708         case CX2341X_ENC_SET_OUTPUT_PORT:
 709                 return  "SET_OUTPUT_PORT";
 710         case CX2341X_ENC_SET_AUDIO_PROPERTIES:
 711                 return  "SET_AUDIO_PROPERTIES";
 712         case CX2341X_ENC_HALT_FW:
 713                 return  "HALT_FW";
 714         case CX2341X_ENC_GET_VERSION:
 715                 return  "GET_VERSION";
 716         case CX2341X_ENC_SET_GOP_CLOSURE:
 717                 return  "SET_GOP_CLOSURE";
 718         case CX2341X_ENC_GET_SEQ_END:
 719                 return  "GET_SEQ_END";
 720         case CX2341X_ENC_SET_PGM_INDEX_INFO:
 721                 return  "SET_PGM_INDEX_INFO";
 722         case CX2341X_ENC_SET_VBI_CONFIG:
 723                 return  "SET_VBI_CONFIG";
 724         case CX2341X_ENC_SET_DMA_BLOCK_SIZE:
 725                 return  "SET_DMA_BLOCK_SIZE";
 726         case CX2341X_ENC_GET_PREV_DMA_INFO_MB_10:
 727                 return  "GET_PREV_DMA_INFO_MB_10";
 728         case CX2341X_ENC_GET_PREV_DMA_INFO_MB_9:
 729                 return  "GET_PREV_DMA_INFO_MB_9";
 730         case CX2341X_ENC_SCHED_DMA_TO_HOST:
 731                 return  "SCHED_DMA_TO_HOST";
 732         case CX2341X_ENC_INITIALIZE_INPUT:
 733                 return  "INITIALIZE_INPUT";
 734         case CX2341X_ENC_SET_FRAME_DROP_RATE:
 735                 return  "SET_FRAME_DROP_RATE";
 736         case CX2341X_ENC_PAUSE_ENCODER:
 737                 return  "PAUSE_ENCODER";
 738         case CX2341X_ENC_REFRESH_INPUT:
 739                 return  "REFRESH_INPUT";
 740         case CX2341X_ENC_SET_COPYRIGHT:
 741                 return  "SET_COPYRIGHT";
 742         case CX2341X_ENC_SET_EVENT_NOTIFICATION:
 743                 return  "SET_EVENT_NOTIFICATION";
 744         case CX2341X_ENC_SET_NUM_VSYNC_LINES:
 745                 return  "SET_NUM_VSYNC_LINES";
 746         case CX2341X_ENC_SET_PLACEHOLDER:
 747                 return  "SET_PLACEHOLDER";
 748         case CX2341X_ENC_MUTE_VIDEO:
 749                 return  "MUTE_VIDEO";
 750         case CX2341X_ENC_MUTE_AUDIO:
 751                 return  "MUTE_AUDIO";
 752         case CX2341X_ENC_MISC:
 753                 return  "MISC";
 754         default:
 755                 return "UNKNOWN";
 756         }
 757 }
 758
 759 static int cx23885_mbox_func(void *priv,
 760                              u32 command,
 761                              int in,
 762                              int out,
 763                              u32 data[CX2341X_MBOX_MAX_DATA])
 764 {
 765         struct cx23885_dev *dev = priv;
 766         unsigned long timeout;
 767         u32 value, flag, retval = 0;
 768         int i;
 769
 770         dprintk(3, "%s: command(0x%X) = %s\n", __func__, command,
 771                 cmd_to_str(command));
 772
 773         /* this may not be 100% safe if we can't read any memory location
 774            without side effects */
 775         mc417_memory_read(dev, dev->cx23417_mailbox - 4, &value);
 776         if (value != 0x12345678) {
 777                 printk(KERN_ERR
 778                         "Firmware and/or mailbox pointer not initialized "
 779                         "or corrupted, signature = 0x%x, cmd = %s\n", value,
 780                         cmd_to_str(command));
 781                 return -1;
 782         }
 783
 784         /* This read looks at 32 bits, but flag is only 8 bits.
 785          * Seems we also bail if CMD or TIMEOUT bytes are set???
 786          */
 787         mc417_memory_read(dev, dev->cx23417_mailbox, &flag);
 788         if (flag) {
 789                 printk(KERN_ERR "ERROR: Mailbox appears to be in use "
 790                         "(%x), cmd = %s\n", flag, cmd_to_str(command));
 791                 return -1;
 792         }
 793
 794         flag |= 1; /* tell 'em we're working on it */
 795         mc417_memory_write(dev, dev->cx23417_mailbox, flag);
 796
 797         /* write command + args + fill remaining with zeros */
 798         /* command code */
 799         mc417_memory_write(dev, dev->cx23417_mailbox + 1, command);
 800         mc417_memory_write(dev, dev->cx23417_mailbox + 3,
 801                 IVTV_API_STD_TIMEOUT); /* timeout */
 802         for (i = 0; i < in; i++) {
 803                 mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, data[i]);
 804                 dprintk(3, "API Input %d = %d\n", i, data[i]);
 805         }
 806         for (; i < CX2341X_MBOX_MAX_DATA; i++)
 807                 mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, 0);
 808
 809         flag |= 3; /* tell 'em we're done writing */
 810         mc417_memory_write(dev, dev->cx23417_mailbox, flag);
 811
 812         /* wait for firmware to handle the API command */
 813         timeout = jiffies + msecs_to_jiffies(10);
 814         for (;;) {
 815                 mc417_memory_read(dev, dev->cx23417_mailbox, &flag);
 816                 if (0 != (flag & 4))
 817                         break;
 818                 if (time_after(jiffies, timeout)) {
 819                         printk(KERN_ERR "ERROR: API Mailbox timeout\n");
 820                         return -1;
 821                 }
 822                 udelay(10);
 823         }
 824
 825         /* read output values */
 826         for (i = 0; i < out; i++) {
 827                 mc417_memory_read(dev, dev->cx23417_mailbox + 4 + i, data + i);
 828                 dprintk(3, "API Output %d = %d\n", i, data[i]);
 829         }
 830
 831         mc417_memory_read(dev, dev->cx23417_mailbox + 2, &retval);
 832         dprintk(3, "API result = %d\n", retval);
 833
 834         flag = 0;
 835         mc417_memory_write(dev, dev->cx23417_mailbox, flag);
 836
 837         return retval;
 838 }
 839
 840 /* We don't need to call the API often, so using just one
 841  * mailbox will probably suffice
 842  */
 843 static int cx23885_api_cmd(struct cx23885_dev *dev,
 844                            u32 command,
 845                            u32 inputcnt,
 846                            u32 outputcnt,
 847                            ...)
 848 {
 849         u32 data[CX2341X_MBOX_MAX_DATA];
 850         va_list vargs;
 851         int i, err;
 852
 853         dprintk(3, "%s() cmds = 0x%08x\n", __func__, command);
 854
 855         va_start(vargs, outputcnt);
 856         for (i = 0; i < inputcnt; i++)
 857                 data[i] = va_arg(vargs, int);
 858
 859         err = cx23885_mbox_func(dev, command, inputcnt, outputcnt, data);
 860         for (i = 0; i < outputcnt; i++) {
 861                 int *vptr = va_arg(vargs, int *);
 862                 *vptr = data[i];
 863         }
 864         va_end(vargs);
 865
 866         return err;
 867 }
 868
 869 static int cx23885_find_mailbox(struct cx23885_dev *dev)
 870 {
 871         u32 signature[4] = {
 872                 0x12345678, 0x34567812, 0x56781234, 0x78123456
 873         };
 874         int signaturecnt = 0;
 875         u32 value;
 876         int i;
 877
 878         dprintk(2, "%s()\n", __func__);
 879
 880         for (i = 0; i < CX23885_FIRM_IMAGE_SIZE; i++) {
 881                 mc417_memory_read(dev, i, &value);
 882                 if (value == signature[signaturecnt])
 883                         signaturecnt++;
 884                 else
 885                         signaturecnt = 0;
 886                 if (4 == signaturecnt) {
 887                         dprintk(1, "Mailbox signature found at 0x%x\n", i+1);
 888                         return i+1;
 889                 }
 890         }
 891         printk(KERN_ERR "Mailbox signature values not found!\n");
 892         return -1;
 893 }
 894
 895 static int cx23885_load_firmware(struct cx23885_dev *dev)
 896 {
 897         static const unsigned char magic[8] = {
 898                 0xa7, 0x0d, 0x00, 0x00, 0x66, 0xbb, 0x55, 0xaa
 899         };
 900         const struct firmware *firmware;
 901         int i, retval = 0;
 902         u32 value = 0;
 903         u32 gpio_output = 0;
 904         u32 checksum = 0;
 905         u32 *dataptr;
 906
 907         dprintk(2, "%s()\n", __func__);
 908
 909         /* Save GPIO settings before reset of APU */
 910         retval |= mc417_memory_read(dev, 0x9020, &gpio_output);
 911         retval |= mc417_memory_read(dev, 0x900C, &value);
 912
 913         retval  = mc417_register_write(dev,
 914                 IVTV_REG_VPU, 0xFFFFFFED);
 915         retval |= mc417_register_write(dev,
 916                 IVTV_REG_HW_BLOCKS, IVTV_CMD_HW_BLOCKS_RST);
 917         retval |= mc417_register_write(dev,
 918                 IVTV_REG_ENC_SDRAM_REFRESH, 0x80000800);
 919         retval |= mc417_register_write(dev,
 920                 IVTV_REG_ENC_SDRAM_PRECHARGE, 0x1A);
 921         retval |= mc417_register_write(dev,
 922                 IVTV_REG_APU, 0);
 923
 924         if (retval != 0) {
 925                 printk(KERN_ERR "%s: Error with mc417_register_write\n",
 926                         __func__);
 927                 return -1;
 928         }
 929
 930         retval = request_firmware(&firmware, CX23885_FIRM_IMAGE_NAME,
 931                                   &dev->pci->dev);
 932
 933         if (retval != 0) {
 934                 printk(KERN_ERR
 935                         "ERROR: Hotplug firmware request failed (%s).\n",
 936                         CX23885_FIRM_IMAGE_NAME);
 937                 printk(KERN_ERR "Please fix your hotplug setup, the board will "
 938                         "not work without firmware loaded!\n");
 939                 return -1;
 940         }
 941
 942         if (firmware->size != CX23885_FIRM_IMAGE_SIZE) {
 943                 printk(KERN_ERR "ERROR: Firmware size mismatch "
 944                         "(have %zd, expected %d)\n",
 945                         firmware->size, CX23885_FIRM_IMAGE_SIZE);
 946                 release_firmware(firmware);
 947                 return -1;
 948         }
 949
 950         if (0 != memcmp(firmware->data, magic, 8)) {
 951                 printk(KERN_ERR
 952                         "ERROR: Firmware magic mismatch, wrong file?\n");
 953                 release_firmware(firmware);
 954                 return -1;
 955         }
 956
 957         /* transfer to the chip */
 958         dprintk(2, "Loading firmware ...\n");
 959         dataptr = (u32 *)firmware->data;
 960         for (i = 0; i < (firmware->size >> 2); i++) {
 961                 value = *dataptr;
 962                 checksum += ~value;
 963                 if (mc417_memory_write(dev, i, value) != 0) {
 964                         printk(KERN_ERR "ERROR: Loading firmware failed!\n");
 965                         release_firmware(firmware);
 966                         return -1;
 967                 }
 968                 dataptr++;
 969         }
 970
 971         /* read back to verify with the checksum */
 972         dprintk(1, "Verifying firmware ...\n");
 973         for (i--; i >= 0; i--) {
 974                 if (mc417_memory_read(dev, i, &value) != 0) {
 975                         printk(KERN_ERR "ERROR: Reading firmware failed!\n");
 976                         release_firmware(firmware);
 977                         return -1;
 978                 }
 979                 checksum -= ~value;
 980         }
 981         if (checksum) {
 982                 printk(KERN_ERR
 983                         "ERROR: Firmware load failed (checksum mismatch).\n");
 984                 release_firmware(firmware);
 985                 return -1;
 986         }
 987         release_firmware(firmware);
 988         dprintk(1, "Firmware upload successful.\n");
 989
 990         retval |= mc417_register_write(dev, IVTV_REG_HW_BLOCKS,
 991                 IVTV_CMD_HW_BLOCKS_RST);
 992
 993         /* F/W power up disturbs the GPIOs, restore state */
 994         retval |= mc417_register_write(dev, 0x9020, gpio_output);
 995         retval |= mc417_register_write(dev, 0x900C, value);
 996
 997         retval |= mc417_register_read(dev, IVTV_REG_VPU, &value);
 998         retval |= mc417_register_write(dev, IVTV_REG_VPU, value & 0xFFFFFFE8);
 999
1000         if (retval < 0)
1001                 printk(KERN_ERR "%s: Error with mc417_register_write\n",
1002                         __func__);
1003         return 0;
1004 }
1005
1006 void cx23885_417_check_encoder(struct cx23885_dev *dev)
1007 {
1008         u32 status, seq;
1009
1010         status = seq = 0;
1011         cx23885_api_cmd(dev, CX2341X_ENC_GET_SEQ_END, 0, 2, &status, &seq);
1012         dprintk(1, "%s() status = %d, seq = %d\n", __func__, status, seq);
1013 }
1014
1015 static void cx23885_codec_settings(struct cx23885_dev *dev)
1016 {
1017         dprintk(1, "%s()\n", __func__);
1018
1019         /* assign frame size */
1020         cx23885_api_cmd(dev, CX2341X_ENC_SET_FRAME_SIZE, 2, 0,
1021                                 dev->ts1.height, dev->ts1.width);
1022
1023         dev->mpeg_params.width = dev->ts1.width;
1024         dev->mpeg_params.height = dev->ts1.height;
1025         dev->mpeg_params.is_50hz =
1026                 (dev->encodernorm.id & V4L2_STD_625_50) != 0;
1027
1028         cx2341x_update(dev, cx23885_mbox_func, NULL, &dev->mpeg_params);
1029
1030         cx23885_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 3, 1);
1031         cx23885_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 4, 1);
1032 }
1033
1034 static int cx23885_initialize_codec(struct cx23885_dev *dev)
1035 {
1036         int version;
1037         int retval;
1038         u32 i, data[7];
1039
1040         dprintk(1, "%s()\n", __func__);
1041
1042         retval = cx23885_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0); /* ping */
1043         if (retval < 0) {
1044                 dprintk(2, "%s() PING OK\n", __func__);
1045                 retval = cx23885_load_firmware(dev);
1046                 if (retval < 0) {
1047                         printk(KERN_ERR "%s() f/w load failed\n", __func__);
1048                         return retval;
1049                 }
1050                 retval = cx23885_find_mailbox(dev);
1051                 if (retval < 0) {
1052                         printk(KERN_ERR "%s() mailbox < 0, error\n",
1053                                 __func__);
1054                         return -1;
1055                 }
1056                 dev->cx23417_mailbox = retval;
1057                 retval = cx23885_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0);
1058                 if (retval < 0) {
1059                         printk(KERN_ERR
1060                                 "ERROR: cx23417 firmware ping failed!\n");
1061                         return -1;
1062                 }
1063                 retval = cx23885_api_cmd(dev, CX2341X_ENC_GET_VERSION, 0, 1,
1064                         &version);
1065                 if (retval < 0) {
1066                         printk(KERN_ERR "ERROR: cx23417 firmware get encoder :"
1067                                 "version failed!\n");
1068                         return -1;
1069                 }
1070                 dprintk(1, "cx23417 firmware version is 0x%08x\n", version);
1071                 msleep(200);
1072         }
1073
1074         cx23885_codec_settings(dev);
1075         msleep(60);
1076
1077         cx23885_api_cmd(dev, CX2341X_ENC_SET_NUM_VSYNC_LINES, 2, 0,
1078                 CX23885_FIELD1_SAA7115, CX23885_FIELD2_SAA7115);
1079         cx23885_api_cmd(dev, CX2341X_ENC_SET_PLACEHOLDER, 12, 0,
1080                 CX23885_CUSTOM_EXTENSION_USR_DATA, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1081                 0, 0);
1082
1083         /* Setup to capture VBI */
1084         data[0] = 0x0001BD00;
1085         data[1] = 1;          /* frames per interrupt */
1086         data[2] = 4;          /* total bufs */
1087         data[3] = 0x91559155; /* start codes */
1088         data[4] = 0x206080C0; /* stop codes */
1089         data[5] = 6;          /* lines */
1090         data[6] = 64;         /* BPL */
1091
1092         cx23885_api_cmd(dev, CX2341X_ENC_SET_VBI_CONFIG, 7, 0, data[0], data[1],
1093                 data[2], data[3], data[4], data[5], data[6]);
1094
1095         for (i = 2; i <= 24; i++) {
1096                 int valid;
1097
1098                 valid = ((i >= 19) && (i <= 21));
1099                 cx23885_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0, i,
1100                                 valid, 0 , 0, 0);
1101                 cx23885_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0,
1102                                 i | 0x80000000, valid, 0, 0, 0);
1103         }
1104
1105         cx23885_api_cmd(dev, CX2341X_ENC_MUTE_AUDIO, 1, 0, CX23885_UNMUTE);
1106         msleep(60);
1107
1108         /* initialize the video input */
1109         cx23885_api_cmd(dev, CX2341X_ENC_INITIALIZE_INPUT, 0, 0);
1110         msleep(60);
1111
1112         /* Enable VIP style pixel invalidation so we work with scaled mode */
1113         mc417_memory_write(dev, 2120, 0x00000080);
1114
1115         /* start capturing to the host interface */
1116         cx23885_api_cmd(dev, CX2341X_ENC_START_CAPTURE, 2, 0,
1117                 CX23885_MPEG_CAPTURE, CX23885_RAW_BITS_NONE);
1118         msleep(10);
1119
1120         return 0;
1121 }
1122
1123 /* ------------------------------------------------------------------ */
1124
1125 static int bb_buf_setup(struct videobuf_queue *q,
1126         unsigned int *count, unsigned int *size)
1127 {
1128         struct cx23885_fh *fh = q->priv_data;
1129
1130         fh->dev->ts1.ts_packet_size  = mpeglinesize;
1131         fh->dev->ts1.ts_packet_count = mpeglines;
1132
1133         *size = fh->dev->ts1.ts_packet_size * fh->dev->ts1.ts_packet_count;
1134         *count = mpegbufs;
1135
1136         return 0;
1137 }
1138
1139 static int bb_buf_prepare(struct videobuf_queue *q,
1140         struct videobuf_buffer *vb, enum v4l2_field field)
1141 {
1142         struct cx23885_fh *fh = q->priv_data;
1143         return cx23885_buf_prepare(q, &fh->dev->ts1,
1144                 (struct cx23885_buffer *)vb,
1145                 field);
1146 }
1147
1148 static void bb_buf_queue(struct videobuf_queue *q,
1149         struct videobuf_buffer *vb)
1150 {
1151         struct cx23885_fh *fh = q->priv_data;
1152         cx23885_buf_queue(&fh->dev->ts1, (struct cx23885_buffer *)vb);
1153 }
1154
1155 static void bb_buf_release(struct videobuf_queue *q,
1156         struct videobuf_buffer *vb)
1157 {
1158         cx23885_free_buffer(q, (struct cx23885_buffer *)vb);
1159 }
1160
1161 static struct videobuf_queue_ops cx23885_qops = {
1162         .buf_setup    = bb_buf_setup,
1163         .buf_prepare  = bb_buf_prepare,
1164         .buf_queue    = bb_buf_queue,
1165         .buf_release  = bb_buf_release,
1166 };
1167
1168 /* ------------------------------------------------------------------ */
1169
1170 static const u32 *ctrl_classes[] = {
1171         cx2341x_mpeg_ctrls,
1172         NULL
1173 };
1174
1175 static int cx23885_queryctrl(struct cx23885_dev *dev,
1176         struct v4l2_queryctrl *qctrl)
1177 {
1178         qctrl->id = v4l2_ctrl_next(ctrl_classes, qctrl->id);
1179         if (qctrl->id == 0)
1180                 return -EINVAL;
1181
1182         /* MPEG V4L2 controls */
1183         if (cx2341x_ctrl_query(&dev->mpeg_params, qctrl))
1184                 qctrl->flags |= V4L2_CTRL_FLAG_DISABLED;
1185
1186         return 0;
1187 }
1188
1189 static int cx23885_querymenu(struct cx23885_dev *dev,
1190         struct v4l2_querymenu *qmenu)
1191 {
1192         struct v4l2_queryctrl qctrl;
1193
1194         qctrl.id = qmenu->id;
1195         cx23885_queryctrl(dev, &qctrl);
1196         return v4l2_ctrl_query_menu(qmenu, &qctrl,
1197                 cx2341x_ctrl_get_menu(&dev->mpeg_params, qmenu->id));
1198 }
1199
1200 static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id *id)
1201 {
1202         struct cx23885_fh  *fh  = file->private_data;
1203         struct cx23885_dev *dev = fh->dev;
1204         unsigned int i;
1205
1206         for (i = 0; i < ARRAY_SIZE(cx23885_tvnorms); i++)
1207                 if (*id & cx23885_tvnorms[i].id)
1208                         break;
1209         if (i == ARRAY_SIZE(cx23885_tvnorms))
1210                 return -EINVAL;
1211         dev->encodernorm = cx23885_tvnorms[i];
1212         return 0;
1213 }
1214
1215 static int vidioc_enum_input(struct file *file, void *priv,
1216                                 struct v4l2_input *i)
1217 {
1218         struct cx23885_fh  *fh  = file->private_data;
1219         struct cx23885_dev *dev = fh->dev;
1220         struct cx23885_input *input;
1221         int n;
1222
1223         if (i->index >= 4)
1224                 return -EINVAL;
1225
1226         input = &cx23885_boards[dev->board].input[i->index];
1227
1228         if (input->type == 0)
1229                 return -EINVAL;
1230
1231         /* FIXME
1232          * strcpy(i->name, input->name); */
1233         strcpy(i->name, "unset");
1234
1235         if (input->type == CX23885_VMUX_TELEVISION ||
1236             input->type == CX23885_VMUX_CABLE)
1237                 i->type = V4L2_INPUT_TYPE_TUNER;
1238         else
1239                 i->type  = V4L2_INPUT_TYPE_CAMERA;
1240
1241         for (n = 0; n < ARRAY_SIZE(cx23885_tvnorms); n++)
1242                 i->std |= cx23885_tvnorms[n].id;
1243         return 0;
1244 }
1245
1246 static int vidioc_g_input(struct file *file, void *priv, unsigned int *i)
1247 {
1248         struct cx23885_fh  *fh  = file->private_data;
1249         struct cx23885_dev *dev = fh->dev;
1250
1251         *i = dev->input;
1252         return 0;
1253 }
1254
1255 static int vidioc_s_input(struct file *file, void *priv, unsigned int i)
1256 {
1257         if (i >= 4)
1258                 return -EINVAL;
1259
1260         return 0;
1261 }
1262
1263 static int vidioc_g_tuner(struct file *file, void *priv,
1264                                 struct v4l2_tuner *t)
1265 {
1266         struct cx23885_fh  *fh  = file->private_data;
1267         struct cx23885_dev *dev = fh->dev;
1268
1269         if (UNSET == dev->tuner_type)
1270                 return -EINVAL;
1271         if (0 != t->index)
1272                 return -EINVAL;
1273         strcpy(t->name, "Television");
1274         call_all(dev, tuner, g_tuner, t);
1275
1276         dprintk(1, "VIDIOC_G_TUNER: tuner type %d\n", t->type);
1277
1278         return 0;
1279 }
1280
1281 static int vidioc_s_tuner(struct file *file, void *priv,
1282                                 struct v4l2_tuner *t)
1283 {
1284         struct cx23885_fh  *fh  = file->private_data;
1285         struct cx23885_dev *dev = fh->dev;
1286
1287         if (UNSET == dev->tuner_type)
1288                 return -EINVAL;
1289
1290         /* Update the A/V core */
1291         call_all(dev, tuner, s_tuner, t);
1292
1293         return 0;
1294 }
1295
1296 static int vidioc_g_frequency(struct file *file, void *priv,
1297                                 struct v4l2_frequency *f)
1298 {
1299         struct cx23885_fh  *fh  = file->private_data;
1300         struct cx23885_dev *dev = fh->dev;
1301
1302         if (UNSET == dev->tuner_type)
1303                 return -EINVAL;
1304         f->type = V4L2_TUNER_ANALOG_TV;
1305         f->frequency = dev->freq;
1306
1307         call_all(dev, tuner, g_frequency, f);
1308
1309         return 0;
1310 }
1311
1312 static int vidioc_s_frequency(struct file *file, void *priv,
1313                                 struct v4l2_frequency *f)
1314 {
1315         struct cx23885_fh  *fh  = file->private_data;
1316         struct cx23885_dev *dev = fh->dev;
1317
1318         cx23885_api_cmd(fh->dev, CX2341X_ENC_STOP_CAPTURE, 3, 0,
1319                 CX23885_END_NOW, CX23885_MPEG_CAPTURE,
1320                 CX23885_RAW_BITS_NONE);
1321
1322         dprintk(1, "VIDIOC_S_FREQUENCY: dev type %d, f\n",
1323                 dev->tuner_type);
1324         dprintk(1, "VIDIOC_S_FREQUENCY: f tuner %d, f type %d\n",
1325                 f->tuner, f->type);
1326         if (UNSET == dev->tuner_type)
1327                 return -EINVAL;
1328         if (f->tuner != 0)
1329                 return -EINVAL;
1330         if (f->type != V4L2_TUNER_ANALOG_TV)
1331                 return -EINVAL;
1332         dev->freq = f->frequency;
1333
1334         call_all(dev, tuner, s_frequency, f);
1335
1336         cx23885_initialize_codec(dev);
1337
1338         return 0;
1339 }
1340
1341 static int vidioc_s_ctrl(struct file *file, void *priv,
1342                                 struct v4l2_control *ctl)
1343 {
1344         struct cx23885_fh  *fh  = file->private_data;
1345         struct cx23885_dev *dev = fh->dev;
1346
1347         /* Update the A/V core */
1348         call_all(dev, core, s_ctrl, ctl);
1349         return 0;
1350 }
1351
1352 static int vidioc_querycap(struct file *file, void  *priv,
1353                                 struct v4l2_capability *cap)
1354 {
1355         struct cx23885_fh  *fh  = file->private_data;
1356         struct cx23885_dev *dev = fh->dev;
1357         struct cx23885_tsport  *tsport = &dev->ts1;
1358
1359         strlcpy(cap->driver, dev->name, sizeof(cap->driver));
1360         strlcpy(cap->card, cx23885_boards[tsport->dev->board].name,
1361                 sizeof(cap->card));
1362         sprintf(cap->bus_info, "PCI:%s", pci_name(dev->pci));
1363         cap->version = CX23885_VERSION_CODE;
1364         cap->capabilities =
1365                 V4L2_CAP_VIDEO_CAPTURE |
1366                 V4L2_CAP_READWRITE     |
1367                 V4L2_CAP_STREAMING     |
1368                 0;
1369         if (UNSET != dev->tuner_type)
1370                 cap->capabilities |= V4L2_CAP_TUNER;
1371
1372         return 0;
1373 }
1374
1375 static int vidioc_enum_fmt_vid_cap(struct file *file, void  *priv,
1376                                         struct v4l2_fmtdesc *f)
1377 {
1378         if (f->index != 0)
1379                 return -EINVAL;
1380
1381         strlcpy(f->description, "MPEG", sizeof(f->description));
1382         f->pixelformat = V4L2_PIX_FMT_MPEG;
1383
1384         return 0;
1385 }
1386
1387 static int vidioc_g_fmt_vid_cap(struct file *file, void *priv,
1388                                 struct v4l2_format *f)
1389 {
1390         struct cx23885_fh  *fh  = file->private_data;
1391         struct cx23885_dev *dev = fh->dev;
1392
1393         f->fmt.pix.pixelformat  = V4L2_PIX_FMT_MPEG;
1394         f->fmt.pix.bytesperline = 0;
1395         f->fmt.pix.sizeimage    =
1396                 dev->ts1.ts_packet_size * dev->ts1.ts_packet_count;
1397         f->fmt.pix.colorspace   = 0;
1398         f->fmt.pix.width        = dev->ts1.width;
1399         f->fmt.pix.height       = dev->ts1.height;
1400         f->fmt.pix.field        = fh->mpegq.field;
1401         dprintk(1, "VIDIOC_G_FMT: w: %d, h: %d, f: %d\n",
1402                 dev->ts1.width, dev->ts1.height, fh->mpegq.field);
1403         return 0;
1404 }
1405
1406 static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
1407                                 struct v4l2_format *f)
1408 {
1409         struct cx23885_fh  *fh  = file->private_data;
1410         struct cx23885_dev *dev = fh->dev;
1411
1412         f->fmt.pix.pixelformat  = V4L2_PIX_FMT_MPEG;
1413         f->fmt.pix.bytesperline = 0;
1414         f->fmt.pix.sizeimage    =
1415                 dev->ts1.ts_packet_size * dev->ts1.ts_packet_count;
1416         f->fmt.pix.colorspace   = 0;
1417         dprintk(1, "VIDIOC_TRY_FMT: w: %d, h: %d, f: %d\n",
1418                 dev->ts1.width, dev->ts1.height, fh->mpegq.field);
1419         return 0;
1420 }
1421
1422 static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
1423                                 struct v4l2_format *f)
1424 {
1425         struct cx23885_fh  *fh  = file->private_data;
1426         struct cx23885_dev *dev = fh->dev;
1427
1428         f->fmt.pix.pixelformat  = V4L2_PIX_FMT_MPEG;
1429         f->fmt.pix.bytesperline = 0;
1430         f->fmt.pix.sizeimage    =
1431                 dev->ts1.ts_packet_size * dev->ts1.ts_packet_count;
1432         f->fmt.pix.colorspace   = 0;
1433         dprintk(1, "VIDIOC_S_FMT: w: %d, h: %d, f: %d\n",
1434                 f->fmt.pix.width, f->fmt.pix.height, f->fmt.pix.field);
1435         return 0;
1436 }
1437
1438 static int vidioc_reqbufs(struct file *file, void *priv,
1439                                 struct v4l2_requestbuffers *p)
1440 {
1441         struct cx23885_fh  *fh  = file->private_data;
1442
1443         return videobuf_reqbufs(&fh->mpegq, p);
1444 }
1445
1446 static int vidioc_querybuf(struct file *file, void *priv,
1447                                 struct v4l2_buffer *p)
1448 {
1449         struct cx23885_fh  *fh  = file->private_data;
1450
1451         return videobuf_querybuf(&fh->mpegq, p);
1452 }
1453
1454 static int vidioc_qbuf(struct file *file, void *priv,
1455                                 struct v4l2_buffer *p)
1456 {
1457         struct cx23885_fh  *fh  = file->private_data;
1458
1459         return videobuf_qbuf(&fh->mpegq, p);
1460 }
1461
1462 static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *b)
1463 {
1464         struct cx23885_fh  *fh  = priv;
1465
1466         return videobuf_dqbuf(&fh->mpegq, b, file->f_flags & O_NONBLOCK);
1467 }
1468
1469
1470 static int vidioc_streamon(struct file *file, void *priv,
1471                                 enum v4l2_buf_type i)
1472 {
1473         struct cx23885_fh  *fh  = file->private_data;
1474
1475         return videobuf_streamon(&fh->mpegq);
1476 }
1477
1478 static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i)
1479 {
1480         struct cx23885_fh  *fh  = file->private_data;
1481
1482         return videobuf_streamoff(&fh->mpegq);
1483 }
1484
1485 static int vidioc_g_ext_ctrls(struct file *file, void *priv,
1486                                 struct v4l2_ext_controls *f)
1487 {
1488         struct cx23885_fh  *fh  = priv;
1489         struct cx23885_dev *dev = fh->dev;
1490
1491         if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG)
1492                 return -EINVAL;
1493         return cx2341x_ext_ctrls(&dev->mpeg_params, 0, f, VIDIOC_G_EXT_CTRLS);
1494 }
1495
1496 static int vidioc_s_ext_ctrls(struct file *file, void *priv,
1497                                 struct v4l2_ext_controls *f)
1498 {
1499         struct cx23885_fh  *fh  = priv;
1500         struct cx23885_dev *dev = fh->dev;
1501         struct cx2341x_mpeg_params p;
1502         int err;
1503
1504         if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG)
1505                 return -EINVAL;
1506
1507         p = dev->mpeg_params;
1508         err = cx2341x_ext_ctrls(&p, 0, f, VIDIOC_S_EXT_CTRLS);
1509
1510         if (err == 0) {
1511                 err = cx2341x_update(dev, cx23885_mbox_func,
1512                         &dev->mpeg_params, &p);
1513                 dev->mpeg_params = p;
1514         }
1515         return err;
1516 }
1517
1518 static int vidioc_try_ext_ctrls(struct file *file, void *priv,
1519                                 struct v4l2_ext_controls *f)
1520 {
1521         struct cx23885_fh  *fh  = priv;
1522         struct cx23885_dev *dev = fh->dev;
1523         struct cx2341x_mpeg_params p;
1524         int err;
1525
1526         if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG)
1527                 return -EINVAL;
1528
1529         p = dev->mpeg_params;
1530         err = cx2341x_ext_ctrls(&p, 0, f, VIDIOC_TRY_EXT_CTRLS);
1531         return err;
1532 }
1533
1534 static int vidioc_log_status(struct file *file, void *priv)
1535 {
1536         struct cx23885_fh  *fh  = priv;
1537         struct cx23885_dev *dev = fh->dev;
1538         char name[32 + 2];
1539
1540         snprintf(name, sizeof(name), "%s/2", dev->name);
1541         printk(KERN_INFO
1542                 "%s/2: ============  START LOG STATUS  ============\n",
1543                dev->name);
1544         call_all(dev, core, log_status);
1545         cx2341x_log_status(&dev->mpeg_params, name);
1546         printk(KERN_INFO
1547                 "%s/2: =============  END LOG STATUS  =============\n",
1548                dev->name);
1549         return 0;
1550 }
1551
1552 static int vidioc_querymenu(struct file *file, void *priv,
1553                                 struct v4l2_querymenu *a)
1554 {
1555         struct cx23885_fh  *fh  = priv;
1556         struct cx23885_dev *dev = fh->dev;
1557
1558         return cx23885_querymenu(dev, a);
1559 }
1560
1561 static int vidioc_queryctrl(struct file *file, void *priv,
1562                                 struct v4l2_queryctrl *c)
1563 {
1564         struct cx23885_fh  *fh  = priv;
1565         struct cx23885_dev *dev = fh->dev;
1566
1567         return cx23885_queryctrl(dev, c);
1568 }
1569
1570 static int mpeg_open(struct file *file)
1571 {
1572         struct cx23885_dev *dev = video_drvdata(file);
1573         struct cx23885_fh *fh;
1574
1575         dprintk(2, "%s()\n", __func__);
1576
1577         /* allocate + initialize per filehandle data */
1578         fh = kzalloc(sizeof(*fh), GFP_KERNEL);
1579         if (NULL == fh) {
1580                 unlock_kernel();
1581                 return -ENOMEM;
1582         }
1583
1584         lock_kernel();
1585
1586         file->private_data = fh;
1587         fh->dev      = dev;
1588
1589         videobuf_queue_sg_init(&fh->mpegq, &cx23885_qops,
1590                             &dev->pci->dev, &dev->ts1.slock,
1591                             V4L2_BUF_TYPE_VIDEO_CAPTURE,
1592                             V4L2_FIELD_INTERLACED,
1593                             sizeof(struct cx23885_buffer),
1594                             fh, NULL);
1595         unlock_kernel();
1596
1597         return 0;
1598 }
1599
1600 static int mpeg_release(struct file *file)
1601 {
1602         struct cx23885_fh  *fh  = file->private_data;
1603         struct cx23885_dev *dev = fh->dev;
1604
1605         dprintk(2, "%s()\n", __func__);
1606
1607         /* FIXME: Review this crap */
1608         /* Shut device down on last close */
1609         if (atomic_cmpxchg(&fh->v4l_reading, 1, 0) == 1) {
1610                 if (atomic_dec_return(&dev->v4l_reader_count) == 0) {
1611                         /* stop mpeg capture */
1612                         cx23885_api_cmd(fh->dev, CX2341X_ENC_STOP_CAPTURE, 3, 0,
1613                                 CX23885_END_NOW, CX23885_MPEG_CAPTURE,
1614                                 CX23885_RAW_BITS_NONE);
1615
1616                         msleep(500);
1617                         cx23885_417_check_encoder(dev);
1618
1619                         cx23885_cancel_buffers(&fh->dev->ts1);
1620                 }
1621         }
1622
1623         if (fh->mpegq.streaming)
1624                 videobuf_streamoff(&fh->mpegq);
1625         if (fh->mpegq.reading)
1626                 videobuf_read_stop(&fh->mpegq);
1627
1628         videobuf_mmap_free(&fh->mpegq);
1629         file->private_data = NULL;
1630         kfree(fh);
1631
1632         return 0;
1633 }
1634
1635 static ssize_t mpeg_read(struct file *file, char __user *data,
1636         size_t count, loff_t *ppos)
1637 {
1638         struct cx23885_fh *fh = file->private_data;
1639         struct cx23885_dev *dev = fh->dev;
1640
1641         dprintk(2, "%s()\n", __func__);
1642
1643         /* Deal w/ A/V decoder * and mpeg encoder sync issues. */
1644         /* Start mpeg encoder on first read. */
1645         if (atomic_cmpxchg(&fh->v4l_reading, 0, 1) == 0) {
1646                 if (atomic_inc_return(&dev->v4l_reader_count) == 1) {
1647                         if (cx23885_initialize_codec(dev) < 0)
1648                                 return -EINVAL;
1649                 }
1650         }
1651
1652         return videobuf_read_stream(&fh->mpegq, data, count, ppos, 0,
1653                                     file->f_flags & O_NONBLOCK);
1654 }
1655
1656 static unsigned int mpeg_poll(struct file *file,
1657         struct poll_table_struct *wait)
1658 {
1659         struct cx23885_fh *fh = file->private_data;
1660         struct cx23885_dev *dev = fh->dev;
1661
1662         dprintk(2, "%s\n", __func__);
1663
1664         return videobuf_poll_stream(file, &fh->mpegq, wait);
1665 }
1666
1667 static int mpeg_mmap(struct file *file, struct vm_area_struct *vma)
1668 {
1669         struct cx23885_fh *fh = file->private_data;
1670         struct cx23885_dev *dev = fh->dev;
1671
1672         dprintk(2, "%s()\n", __func__);
1673
1674         return videobuf_mmap_mapper(&fh->mpegq, vma);
1675 }
1676
1677 static struct v4l2_file_operations mpeg_fops = {
1678         .owner         = THIS_MODULE,
1679         .open          = mpeg_open,
1680         .release       = mpeg_release,
1681         .read          = mpeg_read,
1682         .poll          = mpeg_poll,
1683         .mmap          = mpeg_mmap,
1684         .ioctl         = video_ioctl2,
1685 };
1686
1687 static const struct v4l2_ioctl_ops mpeg_ioctl_ops = {
1688         .vidioc_s_std            = vidioc_s_std,
1689         .vidioc_enum_input       = vidioc_enum_input,
1690         .vidioc_g_input          = vidioc_g_input,
1691         .vidioc_s_input          = vidioc_s_input,
1692         .vidioc_g_tuner          = vidioc_g_tuner,
1693         .vidioc_s_tuner          = vidioc_s_tuner,
1694         .vidioc_g_frequency      = vidioc_g_frequency,
1695         .vidioc_s_frequency      = vidioc_s_frequency,
1696         .vidioc_s_ctrl           = vidioc_s_ctrl,
1697         .vidioc_querycap         = vidioc_querycap,
1698         .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
1699         .vidioc_g_fmt_vid_cap    = vidioc_g_fmt_vid_cap,
1700         .vidioc_try_fmt_vid_cap  = vidioc_try_fmt_vid_cap,
1701         .vidioc_s_fmt_vid_cap    = vidioc_s_fmt_vid_cap,
1702         .vidioc_reqbufs          = vidioc_reqbufs,
1703         .vidioc_querybuf         = vidioc_querybuf,
1704         .vidioc_qbuf             = vidioc_qbuf,
1705         .vidioc_dqbuf            = vidioc_dqbuf,
1706         .vidioc_streamon         = vidioc_streamon,
1707         .vidioc_streamoff        = vidioc_streamoff,
1708         .vidioc_g_ext_ctrls      = vidioc_g_ext_ctrls,
1709         .vidioc_s_ext_ctrls      = vidioc_s_ext_ctrls,
1710         .vidioc_try_ext_ctrls    = vidioc_try_ext_ctrls,
1711         .vidioc_log_status       = vidioc_log_status,
1712         .vidioc_querymenu        = vidioc_querymenu,
1713         .vidioc_queryctrl        = vidioc_queryctrl,
1714         .vidioc_g_chip_ident     = cx23885_g_chip_ident,
1715 #ifdef CONFIG_VIDEO_ADV_DEBUG
1716         .vidioc_g_register       = cx23885_g_register,
1717         .vidioc_s_register       = cx23885_s_register,
1718 #endif
1719 };
1720
1721 static struct video_device cx23885_mpeg_template = {
1722         .name          = "cx23885",
1723         .fops          = &mpeg_fops,
1724         .ioctl_ops     = &mpeg_ioctl_ops,
1725         .tvnorms       = CX23885_NORMS,
1726         .current_norm  = V4L2_STD_NTSC_M,
1727 };
1728
1729 void cx23885_417_unregister(struct cx23885_dev *dev)
1730 {
1731         dprintk(1, "%s()\n", __func__);
1732
1733         if (dev->v4l_device) {
1734                 if (video_is_registered(dev->v4l_device))
1735                         video_unregister_device(dev->v4l_device);
1736                 else
1737                         video_device_release(dev->v4l_device);
1738                 dev->v4l_device = NULL;
1739         }
1740 }
1741
1742 static struct video_device *cx23885_video_dev_alloc(
1743         struct cx23885_tsport *tsport,
1744         struct pci_dev *pci,
1745         struct video_device *template,
1746         char *type)
1747 {
1748         struct video_device *vfd;
1749         struct cx23885_dev *dev = tsport->dev;
1750
1751         dprintk(1, "%s()\n", __func__);
1752
1753         vfd = video_device_alloc();
1754         if (NULL == vfd)
1755                 return NULL;
1756         *vfd = *template;
1757         snprintf(vfd->name, sizeof(vfd->name), "%s %s (%s)", dev->name,
1758                 type, cx23885_boards[tsport->dev->board].name);
1759         vfd->parent  = &pci->dev;
1760         vfd->release = video_device_release;
1761         return vfd;
1762 }
1763
1764 int cx23885_417_register(struct cx23885_dev *dev)
1765 {
1766         /* FIXME: Port1 hardcoded here */
1767         int err = -ENODEV;
1768         struct cx23885_tsport *tsport = &dev->ts1;
1769
1770         dprintk(1, "%s()\n", __func__);
1771
1772         if (cx23885_boards[dev->board].portb != CX23885_MPEG_ENCODER)
1773                 return err;
1774
1775         /* Set default TV standard */
1776         dev->encodernorm = cx23885_tvnorms[0];
1777
1778         if (dev->encodernorm.id & V4L2_STD_525_60)
1779                 tsport->height = 480;
1780         else
1781                 tsport->height = 576;
1782
1783         tsport->width = 720;
1784         cx2341x_fill_defaults(&dev->mpeg_params);
1785
1786         dev->mpeg_params.port = CX2341X_PORT_SERIAL;
1787
1788         /* Allocate and initialize V4L video device */
1789         dev->v4l_device = cx23885_video_dev_alloc(tsport,
1790                 dev->pci, &cx23885_mpeg_template, "mpeg");
1791         video_set_drvdata(dev->v4l_device, dev);
1792         err = video_register_device(dev->v4l_device,
1793                 VFL_TYPE_GRABBER, -1);
1794         if (err < 0) {
1795                 printk(KERN_INFO "%s: can't register mpeg device\n", dev->name);
1796                 return err;
1797         }
1798
1799         printk(KERN_INFO "%s: registered device %s [mpeg]\n",
1800                dev->name, video_device_node_name(dev->v4l_device));
1801
1802         return 0;
1803 }