drivers/media/video/cx231xx/cx231xx-417.c

   1 /*
   2  *
   3  *  Support for a cx23417 mpeg encoder via cx231xx host port.
   4  *
   5  *    (c) 2004 Jelle Foks <jelle@foks.us>
   6  *    (c) 2004 Gerd Knorr <kraxel@bytesex.org>
   7  *    (c) 2008 Steven Toth <stoth@linuxtv.org>
   8  *      - CX23885/7/8 support
   9  *
  10  *  Includes parts from the ivtv driver( http://ivtv.sourceforge.net/),
  11  *
  12  *  This program is free software; you can redistribute it and/or modify
  13  *  it under the terms of the GNU General Public License as published by
  14  *  the Free Software Foundation; either version 2 of the License, or
  15  *  (at your option) any later version.
  16  *
  17  *  This program is distributed in the hope that it will be useful,
  18  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  *  GNU General Public License for more details.
  21  *
  22  *  You should have received a copy of the GNU General Public License
  23  *  along with this program; if not, write to the Free Software
  24  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/init.h>
  30 #include <linux/fs.h>
  31 #include <linux/delay.h>
  32 #include <linux/device.h>
  33 #include <linux/firmware.h>
  34 #include <linux/smp_lock.h>
  35 #include <linux/vmalloc.h>
  36 #include <media/v4l2-common.h>
  37 #include <media/v4l2-ioctl.h>
  38 #include <media/cx2341x.h>
  39 #include <linux/usb.h>
  40
  41 #include "cx231xx.h"
  42 /*#include "cx23885-ioctl.h"*/
  43
  44 #define CX231xx_FIRM_IMAGE_SIZE 376836
  45 #define CX231xx_FIRM_IMAGE_NAME "v4l-cx23885-enc.fw"
  46
  47 /* for polaris ITVC */
  48 #define ITVC_WRITE_DIR          0x03FDFC00
  49 #define ITVC_READ_DIR            0x0001FC00
  50
  51 #define  MCI_MEMORY_DATA_BYTE0          0x00
  52 #define  MCI_MEMORY_DATA_BYTE1          0x08
  53 #define  MCI_MEMORY_DATA_BYTE2          0x10
  54 #define  MCI_MEMORY_DATA_BYTE3          0x18
  55
  56 #define  MCI_MEMORY_ADDRESS_BYTE2       0x20
  57 #define  MCI_MEMORY_ADDRESS_BYTE1       0x28
  58 #define  MCI_MEMORY_ADDRESS_BYTE0       0x30
  59
  60 #define  MCI_REGISTER_DATA_BYTE0        0x40
  61 #define  MCI_REGISTER_DATA_BYTE1        0x48
  62 #define  MCI_REGISTER_DATA_BYTE2        0x50
  63 #define  MCI_REGISTER_DATA_BYTE3        0x58
  64
  65 #define  MCI_REGISTER_ADDRESS_BYTE0     0x60
  66 #define  MCI_REGISTER_ADDRESS_BYTE1     0x68
  67
  68 #define  MCI_REGISTER_MODE              0x70
  69
  70 /* Read and write modes for polaris ITVC */
  71 #define  MCI_MODE_REGISTER_READ         0x000
  72 #define  MCI_MODE_REGISTER_WRITE        0x100
  73 #define  MCI_MODE_MEMORY_READ           0x000
  74 #define  MCI_MODE_MEMORY_WRITE          0x4000
  75
  76 static unsigned int mpegbufs = 8;
  77 module_param(mpegbufs, int, 0644);
  78 MODULE_PARM_DESC(mpegbufs, "number of mpeg buffers, range 2-32");
  79 static unsigned int mpeglines = 128;
  80 module_param(mpeglines, int, 0644);
  81 MODULE_PARM_DESC(mpeglines, "number of lines in an MPEG buffer, range 2-32");
  82 static unsigned int mpeglinesize = 512;
  83 module_param(mpeglinesize, int, 0644);
  84 MODULE_PARM_DESC(mpeglinesize,
  85         "number of bytes in each line of an MPEG buffer, range 512-1024");
  86
  87 static unsigned int v4l_debug = 1;
  88 module_param(v4l_debug, int, 0644);
  89 MODULE_PARM_DESC(v4l_debug, "enable V4L debug messages");
  90 struct cx231xx_dmaqueue *dma_qq;
  91 #define dprintk(level, fmt, arg...)\
  92         do { if (v4l_debug >= level) \
  93                 printk(KERN_INFO "%s: " fmt, \
  94                 (dev) ? dev->name : "cx231xx[?]", ## arg); \
  95         } while (0)
  96
  97 static struct cx231xx_tvnorm cx231xx_tvnorms[] = {
  98         {
  99                 .name      = "NTSC-M",
 100                 .id        = V4L2_STD_NTSC_M,
 101         }, {
 102                 .name      = "NTSC-JP",
 103                 .id        = V4L2_STD_NTSC_M_JP,
 104         }, {
 105                 .name      = "PAL-BG",
 106                 .id        = V4L2_STD_PAL_BG,
 107         }, {
 108                 .name      = "PAL-DK",
 109                 .id        = V4L2_STD_PAL_DK,
 110         }, {
 111                 .name      = "PAL-I",
 112                 .id        = V4L2_STD_PAL_I,
 113         }, {
 114                 .name      = "PAL-M",
 115                 .id        = V4L2_STD_PAL_M,
 116         }, {
 117                 .name      = "PAL-N",
 118                 .id        = V4L2_STD_PAL_N,
 119         }, {
 120                 .name      = "PAL-Nc",
 121                 .id        = V4L2_STD_PAL_Nc,
 122         }, {
 123                 .name      = "PAL-60",
 124                 .id        = V4L2_STD_PAL_60,
 125         }, {
 126                 .name      = "SECAM-L",
 127                 .id        = V4L2_STD_SECAM_L,
 128         }, {
 129                 .name      = "SECAM-DK",
 130                 .id        = V4L2_STD_SECAM_DK,
 131         }
 132 };
 133
 134 /* ------------------------------------------------------------------ */
 135 enum cx231xx_capture_type {
 136         CX231xx_MPEG_CAPTURE,
 137         CX231xx_RAW_CAPTURE,
 138         CX231xx_RAW_PASSTHRU_CAPTURE
 139 };
 140 enum cx231xx_capture_bits {
 141         CX231xx_RAW_BITS_NONE             = 0x00,
 142         CX231xx_RAW_BITS_YUV_CAPTURE      = 0x01,
 143         CX231xx_RAW_BITS_PCM_CAPTURE      = 0x02,
 144         CX231xx_RAW_BITS_VBI_CAPTURE      = 0x04,
 145         CX231xx_RAW_BITS_PASSTHRU_CAPTURE = 0x08,
 146         CX231xx_RAW_BITS_TO_HOST_CAPTURE  = 0x10
 147 };
 148 enum cx231xx_capture_end {
 149         CX231xx_END_AT_GOP, /* stop at the end of gop, generate irq */
 150         CX231xx_END_NOW, /* stop immediately, no irq */
 151 };
 152 enum cx231xx_framerate {
 153         CX231xx_FRAMERATE_NTSC_30, /* NTSC: 30fps */
 154         CX231xx_FRAMERATE_PAL_25   /* PAL: 25fps */
 155 };
 156 enum cx231xx_stream_port {
 157         CX231xx_OUTPUT_PORT_MEMORY,
 158         CX231xx_OUTPUT_PORT_STREAMING,
 159         CX231xx_OUTPUT_PORT_SERIAL
 160 };
 161 enum cx231xx_data_xfer_status {
 162         CX231xx_MORE_BUFFERS_FOLLOW,
 163         CX231xx_LAST_BUFFER,
 164 };
 165 enum cx231xx_picture_mask {
 166         CX231xx_PICTURE_MASK_NONE,
 167         CX231xx_PICTURE_MASK_I_FRAMES,
 168         CX231xx_PICTURE_MASK_I_P_FRAMES = 0x3,
 169         CX231xx_PICTURE_MASK_ALL_FRAMES = 0x7,
 170 };
 171 enum cx231xx_vbi_mode_bits {
 172         CX231xx_VBI_BITS_SLICED,
 173         CX231xx_VBI_BITS_RAW,
 174 };
 175 enum cx231xx_vbi_insertion_bits {
 176         CX231xx_VBI_BITS_INSERT_IN_XTENSION_USR_DATA,
 177         CX231xx_VBI_BITS_INSERT_IN_PRIVATE_PACKETS = 0x1 << 1,
 178         CX231xx_VBI_BITS_SEPARATE_STREAM = 0x2 << 1,
 179         CX231xx_VBI_BITS_SEPARATE_STREAM_USR_DATA = 0x4 << 1,
 180         CX231xx_VBI_BITS_SEPARATE_STREAM_PRV_DATA = 0x5 << 1,
 181 };
 182 enum cx231xx_dma_unit {
 183         CX231xx_DMA_BYTES,
 184         CX231xx_DMA_FRAMES,
 185 };
 186 enum cx231xx_dma_transfer_status_bits {
 187         CX231xx_DMA_TRANSFER_BITS_DONE = 0x01,
 188         CX231xx_DMA_TRANSFER_BITS_ERROR = 0x04,
 189         CX231xx_DMA_TRANSFER_BITS_LL_ERROR = 0x10,
 190 };
 191 enum cx231xx_pause {
 192         CX231xx_PAUSE_ENCODING,
 193         CX231xx_RESUME_ENCODING,
 194 };
 195 enum cx231xx_copyright {
 196         CX231xx_COPYRIGHT_OFF,
 197         CX231xx_COPYRIGHT_ON,
 198 };
 199 enum cx231xx_notification_type {
 200         CX231xx_NOTIFICATION_REFRESH,
 201 };
 202 enum cx231xx_notification_status {
 203         CX231xx_NOTIFICATION_OFF,
 204         CX231xx_NOTIFICATION_ON,
 205 };
 206 enum cx231xx_notification_mailbox {
 207         CX231xx_NOTIFICATION_NO_MAILBOX = -1,
 208 };
 209 enum cx231xx_field1_lines {
 210         CX231xx_FIELD1_SAA7114 = 0x00EF, /* 239 */
 211         CX231xx_FIELD1_SAA7115 = 0x00F0, /* 240 */
 212         CX231xx_FIELD1_MICRONAS = 0x0105, /* 261 */
 213 };
 214 enum cx231xx_field2_lines {
 215         CX231xx_FIELD2_SAA7114 = 0x00EF, /* 239 */
 216         CX231xx_FIELD2_SAA7115 = 0x00F0, /* 240 */
 217         CX231xx_FIELD2_MICRONAS = 0x0106, /* 262 */
 218 };
 219 enum cx231xx_custom_data_type {
 220         CX231xx_CUSTOM_EXTENSION_USR_DATA,
 221         CX231xx_CUSTOM_PRIVATE_PACKET,
 222 };
 223 enum cx231xx_mute {
 224         CX231xx_UNMUTE,
 225         CX231xx_MUTE,
 226 };
 227 enum cx231xx_mute_video_mask {
 228         CX231xx_MUTE_VIDEO_V_MASK = 0x0000FF00,
 229         CX231xx_MUTE_VIDEO_U_MASK = 0x00FF0000,
 230         CX231xx_MUTE_VIDEO_Y_MASK = 0xFF000000,
 231 };
 232 enum cx231xx_mute_video_shift {
 233         CX231xx_MUTE_VIDEO_V_SHIFT = 8,
 234         CX231xx_MUTE_VIDEO_U_SHIFT = 16,
 235         CX231xx_MUTE_VIDEO_Y_SHIFT = 24,
 236 };
 237
 238 /* defines below are from ivtv-driver.h */
 239 #define IVTV_CMD_HW_BLOCKS_RST 0xFFFFFFFF
 240
 241 /* Firmware API commands */
 242 #define IVTV_API_STD_TIMEOUT 500
 243
 244 /* Registers */
 245 /* IVTV_REG_OFFSET */
 246 #define IVTV_REG_ENC_SDRAM_REFRESH (0x07F8)
 247 #define IVTV_REG_ENC_SDRAM_PRECHARGE (0x07FC)
 248 #define IVTV_REG_SPU (0x9050)
 249 #define IVTV_REG_HW_BLOCKS (0x9054)
 250 #define IVTV_REG_VPU (0x9058)
 251 #define IVTV_REG_APU (0xA064)
 252
 253 /*
 254  * Bit definitions for MC417_RWD and MC417_OEN registers
 255  *
 256  * bits 31-16
 257  *+-----------+
 258  *| Reserved  |
 259  *|+-----------+
 260  *|  bit 15  bit 14  bit 13 bit 12  bit 11  bit 10  bit 9   bit 8
 261  *|+-------+-------+-------+-------+-------+-------+-------+-------+
 262  *|| MIWR# | MIRD# | MICS# |MIRDY# |MIADDR3|MIADDR2|MIADDR1|MIADDR0|
 263  *|+-------+-------+-------+-------+-------+-------+-------+-------+
 264  *| bit 7   bit 6   bit 5   bit 4   bit 3   bit 2   bit 1   bit 0
 265  *|+-------+-------+-------+-------+-------+-------+-------+-------+
 266  *||MIDATA7|MIDATA6|MIDATA5|MIDATA4|MIDATA3|MIDATA2|MIDATA1|MIDATA0|
 267  *|+-------+-------+-------+-------+-------+-------+-------+-------+
 268  */
 269 #define MC417_MIWR      0x8000
 270 #define MC417_MIRD      0x4000
 271 #define MC417_MICS      0x2000
 272 #define MC417_MIRDY     0x1000
 273 #define MC417_MIADDR    0x0F00
 274 #define MC417_MIDATA    0x00FF
 275
 276
 277 /* Bit definitions for MC417_CTL register ****
 278  *bits 31-6   bits 5-4   bit 3    bits 2-1       Bit 0
 279  *+--------+-------------+--------+--------------+------------+
 280  *|Reserved|MC417_SPD_CTL|Reserved|MC417_GPIO_SEL|UART_GPIO_EN|
 281  *+--------+-------------+--------+--------------+------------+
 282  */
 283 #define MC417_SPD_CTL(x)        (((x) << 4) & 0x00000030)
 284 #define MC417_GPIO_SEL(x)       (((x) << 1) & 0x00000006)
 285 #define MC417_UART_GPIO_EN      0x00000001
 286
 287 /* Values for speed control */
 288 #define MC417_SPD_CTL_SLOW      0x1
 289 #define MC417_SPD_CTL_MEDIUM    0x0
 290 #define MC417_SPD_CTL_FAST      0x3     /* b'1x, but we use b'11 */
 291
 292 /* Values for GPIO select */
 293 #define MC417_GPIO_SEL_GPIO3    0x3
 294 #define MC417_GPIO_SEL_GPIO2    0x2
 295 #define MC417_GPIO_SEL_GPIO1    0x1
 296 #define MC417_GPIO_SEL_GPIO0    0x0
 297
 298
 299 #define CX23417_GPIO_MASK 0xFC0003FF
 300 static int setITVCReg(struct cx231xx *dev, u32 gpio_direction, u32 value)
 301 {
 302         int status = 0;
 303         u32 _gpio_direction = 0;
 304
 305         _gpio_direction = _gpio_direction & CX23417_GPIO_MASK;
 306         _gpio_direction = _gpio_direction|gpio_direction;
 307         status = cx231xx_send_gpio_cmd(dev, _gpio_direction,
 308                          (u8 *)&value, 4, 0, 0);
 309         return status;
 310 }
 311 static int getITVCReg(struct cx231xx *dev, u32 gpio_direction, u32 *pValue)
 312 {
 313         int status = 0;
 314         u32 _gpio_direction = 0;
 315
 316         _gpio_direction = _gpio_direction & CX23417_GPIO_MASK;
 317         _gpio_direction = _gpio_direction|gpio_direction;
 318
 319         status = cx231xx_send_gpio_cmd(dev, _gpio_direction,
 320                  (u8 *)pValue, 4, 0, 1);
 321         return status;
 322 }
 323
 324 static int waitForMciComplete(struct cx231xx *dev)
 325 {
 326         u32 gpio;
 327         u32 gpio_driection = 0;
 328         u8 count = 0;
 329         getITVCReg(dev, gpio_driection, &gpio);
 330
 331         while (!(gpio&0x020000)) {
 332                 msleep(10);
 333
 334                 getITVCReg(dev, gpio_driection, &gpio);
 335
 336                 if (count++ > 100) {
 337                         dprintk(3, "ERROR: Timeout - gpio=%x\n", gpio);
 338                         return -1;
 339                 }
 340         }
 341         return 0;
 342 }
 343
 344 static int mc417_register_write(struct cx231xx *dev, u16 address, u32 value)
 345 {
 346         u32 temp;
 347         int status = 0;
 348
 349         temp = 0x82|MCI_REGISTER_DATA_BYTE0|((value&0x000000FF)<<8);
 350         temp = temp<<10;
 351         status = setITVCReg(dev, ITVC_WRITE_DIR, temp);
 352         if (status < 0)
 353                 return status;
 354         temp = temp|((0x05)<<10);
 355         setITVCReg(dev, ITVC_WRITE_DIR, temp);
 356
 357         /*write data byte 1;*/
 358         temp = 0x82|MCI_REGISTER_DATA_BYTE1|(value&0x0000FF00);
 359         temp = temp<<10;
 360         setITVCReg(dev, ITVC_WRITE_DIR, temp);
 361         temp = temp|((0x05)<<10);
 362         setITVCReg(dev, ITVC_WRITE_DIR, temp);
 363
 364         /*write data byte 2;*/
 365         temp = 0x82|MCI_REGISTER_DATA_BYTE2|((value&0x00FF0000)>>8);
 366         temp = temp<<10;
 367         setITVCReg(dev, ITVC_WRITE_DIR, temp);
 368         temp = temp|((0x05)<<10);
 369         setITVCReg(dev, ITVC_WRITE_DIR, temp);
 370
 371         /*write data byte 3;*/
 372         temp = 0x82|MCI_REGISTER_DATA_BYTE3|((value&0xFF000000)>>16);
 373         temp = temp<<10;
 374         setITVCReg(dev, ITVC_WRITE_DIR, temp);
 375         temp = temp|((0x05)<<10);
 376         setITVCReg(dev, ITVC_WRITE_DIR, temp);
 377
 378         /*write address byte 0;*/
 379         temp = 0x82|MCI_REGISTER_ADDRESS_BYTE0|((address&0x000000FF)<<8);
 380         temp = temp<<10;
 381         setITVCReg(dev, ITVC_WRITE_DIR, temp);
 382         temp = temp|((0x05)<<10);
 383         setITVCReg(dev, ITVC_WRITE_DIR, temp);
 384
 385         /*write address byte 1;*/
 386         temp = 0x82|MCI_REGISTER_ADDRESS_BYTE1|(address&0x0000FF00);
 387         temp = temp<<10;
 388         setITVCReg(dev, ITVC_WRITE_DIR, temp);
 389         temp = temp|((0x05)<<10);
 390         setITVCReg(dev, ITVC_WRITE_DIR, temp);
 391
 392         /*Write that the mode is write.*/
 393         temp = 0x82 | MCI_REGISTER_MODE | MCI_MODE_REGISTER_WRITE;
 394         temp = temp<<10;
 395         setITVCReg(dev, ITVC_WRITE_DIR, temp);
 396         temp = temp|((0x05)<<10);
 397         setITVCReg(dev, ITVC_WRITE_DIR, temp);
 398
 399         return waitForMciComplete(dev);
 400 }
 401
 402 static int mc417_register_read(struct cx231xx *dev, u16 address, u32 *value)
 403 {
 404         /*write address byte 0;*/
 405         u32 temp;
 406         u32 return_value = 0;
 407         int ret = 0;
 408
 409         temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE0 | ((address & 0x00FF) << 8);
 410         temp = temp << 10;
 411         setITVCReg(dev, ITVC_WRITE_DIR, temp);
 412         temp = temp | ((0x05) << 10);
 413         setITVCReg(dev, ITVC_WRITE_DIR, temp);
 414
 415         /*write address byte 1;*/
 416         temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE1 | (address & 0xFF00);
 417         temp = temp << 10;
 418         setITVCReg(dev, ITVC_WRITE_DIR, temp);
 419         temp = temp | ((0x05) << 10);
 420         setITVCReg(dev, ITVC_WRITE_DIR, temp);
 421
 422         /*write that the mode is read;*/
 423         temp = 0x82 | MCI_REGISTER_MODE | MCI_MODE_REGISTER_READ;
 424         temp = temp << 10;
 425         setITVCReg(dev, ITVC_WRITE_DIR, temp);
 426         temp = temp | ((0x05) << 10);
 427         setITVCReg(dev, ITVC_WRITE_DIR, temp);
 428
 429         /*wait for the MIRDY line to be asserted ,
 430         signalling that the read is done;*/
 431         ret = waitForMciComplete(dev);
 432
 433         /*switch the DATA- GPIO to input mode;*/
 434
 435         /*Read data byte 0;*/
 436         temp = (0x82 | MCI_REGISTER_DATA_BYTE0) << 10;
 437         setITVCReg(dev, ITVC_READ_DIR, temp);
 438         temp = ((0x81 | MCI_REGISTER_DATA_BYTE0) << 10);
 439         setITVCReg(dev, ITVC_READ_DIR, temp);
 440         getITVCReg(dev, ITVC_READ_DIR, &temp);
 441         return_value |= ((temp & 0x03FC0000) >> 18);
 442         setITVCReg(dev, ITVC_READ_DIR, (0x87 << 10));
 443
 444         /* Read data byte 1;*/
 445         temp = (0x82 | MCI_REGISTER_DATA_BYTE1) << 10;
 446         setITVCReg(dev, ITVC_READ_DIR, temp);
 447         temp = ((0x81 | MCI_REGISTER_DATA_BYTE1) << 10);
 448         setITVCReg(dev, ITVC_READ_DIR, temp);
 449         getITVCReg(dev, ITVC_READ_DIR, &temp);
 450
 451         return_value |= ((temp & 0x03FC0000) >> 10);
 452         setITVCReg(dev, ITVC_READ_DIR, (0x87 << 10));
 453
 454         /*Read data byte 2;*/
 455         temp = (0x82 | MCI_REGISTER_DATA_BYTE2) << 10;
 456         setITVCReg(dev, ITVC_READ_DIR, temp);
 457         temp = ((0x81 | MCI_REGISTER_DATA_BYTE2) << 10);
 458         setITVCReg(dev, ITVC_READ_DIR, temp);
 459         getITVCReg(dev, ITVC_READ_DIR, &temp);
 460         return_value |= ((temp & 0x03FC0000) >> 2);
 461         setITVCReg(dev, ITVC_READ_DIR, (0x87 << 10));
 462
 463         /*Read data byte 3;*/
 464         temp = (0x82 | MCI_REGISTER_DATA_BYTE3) << 10;
 465         setITVCReg(dev, ITVC_READ_DIR, temp);
 466         temp = ((0x81 | MCI_REGISTER_DATA_BYTE3) << 10);
 467         setITVCReg(dev, ITVC_READ_DIR, temp);
 468         getITVCReg(dev, ITVC_READ_DIR, &temp);
 469         return_value |= ((temp & 0x03FC0000) << 6);
 470         setITVCReg(dev, ITVC_READ_DIR, (0x87 << 10));
 471
 472         *value  = return_value;
 473
 474
 475         return ret;
 476 }
 477
 478 static int mc417_memory_write(struct cx231xx *dev, u32 address, u32 value)
 479 {
 480         /*write data byte 0;*/
 481
 482         u32 temp;
 483         int ret = 0;
 484
 485         temp = 0x82 | MCI_MEMORY_DATA_BYTE0|((value & 0x000000FF) << 8);
 486         temp = temp << 10;
 487         ret = setITVCReg(dev, ITVC_WRITE_DIR, temp);
 488         if (ret < 0)
 489                 return ret;
 490         temp = temp | ((0x05) << 10);
 491         setITVCReg(dev, ITVC_WRITE_DIR, temp);
 492
 493         /*write data byte 1;*/
 494         temp = 0x82 | MCI_MEMORY_DATA_BYTE1 | (value & 0x0000FF00);
 495         temp = temp << 10;
 496         setITVCReg(dev, ITVC_WRITE_DIR, temp);
 497         temp = temp | ((0x05) << 10);
 498         setITVCReg(dev, ITVC_WRITE_DIR, temp);
 499
 500         /*write data byte 2;*/
 501         temp = 0x82|MCI_MEMORY_DATA_BYTE2|((value&0x00FF0000)>>8);
 502         temp = temp<<10;
 503         setITVCReg(dev, ITVC_WRITE_DIR, temp);
 504         temp = temp|((0x05)<<10);
 505         setITVCReg(dev, ITVC_WRITE_DIR, temp);
 506
 507         /*write data byte 3;*/
 508         temp = 0x82|MCI_MEMORY_DATA_BYTE3|((value&0xFF000000)>>16);
 509         temp = temp<<10;
 510         setITVCReg(dev, ITVC_WRITE_DIR, temp);
 511         temp = temp|((0x05)<<10);
 512         setITVCReg(dev, ITVC_WRITE_DIR, temp);
 513
 514         /* write address byte 2;*/
 515         temp = 0x82|MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_WRITE |
 516                 ((address & 0x003F0000)>>8);
 517         temp = temp<<10;
 518         setITVCReg(dev, ITVC_WRITE_DIR, temp);
 519         temp = temp|((0x05)<<10);
 520         setITVCReg(dev, ITVC_WRITE_DIR, temp);
 521
 522         /* write address byte 1;*/
 523         temp = 0x82|MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00);
 524         temp = temp<<10;
 525         setITVCReg(dev, ITVC_WRITE_DIR, temp);
 526         temp = temp|((0x05)<<10);
 527         setITVCReg(dev, ITVC_WRITE_DIR, temp);
 528
 529         /* write address byte 0;*/
 530         temp = 0x82|MCI_MEMORY_ADDRESS_BYTE0|((address & 0x00FF)<<8);
 531         temp = temp<<10;
 532         setITVCReg(dev, ITVC_WRITE_DIR, temp);
 533         temp = temp|((0x05)<<10);
 534         setITVCReg(dev, ITVC_WRITE_DIR, temp);
 535
 536         /*wait for MIRDY line;*/
 537         waitForMciComplete(dev);
 538
 539         return 0;
 540 }
 541
 542 static int mc417_memory_read(struct cx231xx *dev, u32 address, u32 *value)
 543 {
 544         u32 temp = 0;
 545         u32 return_value = 0;
 546         int ret = 0;
 547
 548         /*write address byte 2;*/
 549         temp = 0x82|MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_READ |
 550                 ((address & 0x003F0000)>>8);
 551         temp = temp<<10;
 552         ret = setITVCReg(dev, ITVC_WRITE_DIR, temp);
 553         if (ret < 0)
 554                 return ret;
 555         temp = temp|((0x05)<<10);
 556         setITVCReg(dev, ITVC_WRITE_DIR, temp);
 557
 558         /*write address byte 1*/
 559         temp = 0x82|MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00);
 560         temp = temp<<10;
 561         setITVCReg(dev, ITVC_WRITE_DIR, temp);
 562         temp = temp|((0x05)<<10);
 563         setITVCReg(dev, ITVC_WRITE_DIR, temp);
 564
 565         /*write address byte 0*/
 566         temp = 0x82|MCI_MEMORY_ADDRESS_BYTE0 | ((address & 0x00FF)<<8);
 567         temp = temp<<10;
 568         setITVCReg(dev, ITVC_WRITE_DIR, temp);
 569         temp = temp|((0x05)<<10);
 570         setITVCReg(dev, ITVC_WRITE_DIR, temp);
 571
 572         /*Wait for MIRDY line*/
 573         ret = waitForMciComplete(dev);
 574
 575
 576         /*Read data byte 3;*/
 577         temp = (0x82|MCI_MEMORY_DATA_BYTE3)<<10;
 578         setITVCReg(dev, ITVC_READ_DIR, temp);
 579         temp = ((0x81|MCI_MEMORY_DATA_BYTE3)<<10);
 580         setITVCReg(dev, ITVC_READ_DIR, temp);
 581         getITVCReg(dev, ITVC_READ_DIR, &temp);
 582         return_value |= ((temp&0x03FC0000)<<6);
 583         setITVCReg(dev, ITVC_READ_DIR, (0x87<<10));
 584
 585         /*Read data byte 2;*/
 586         temp = (0x82|MCI_MEMORY_DATA_BYTE2)<<10;
 587         setITVCReg(dev, ITVC_READ_DIR, temp);
 588         temp = ((0x81|MCI_MEMORY_DATA_BYTE2)<<10);
 589         setITVCReg(dev, ITVC_READ_DIR, temp);
 590         getITVCReg(dev, ITVC_READ_DIR, &temp);
 591         return_value |= ((temp&0x03FC0000)>>2);
 592         setITVCReg(dev, ITVC_READ_DIR, (0x87<<10));
 593
 594         /* Read data byte 1;*/
 595         temp = (0x82|MCI_MEMORY_DATA_BYTE1)<<10;
 596         setITVCReg(dev, ITVC_READ_DIR, temp);
 597         temp = ((0x81|MCI_MEMORY_DATA_BYTE1)<<10);
 598         setITVCReg(dev, ITVC_READ_DIR, temp);
 599         getITVCReg(dev, ITVC_READ_DIR, &temp);
 600         return_value |= ((temp&0x03FC0000)>>10);
 601         setITVCReg(dev, ITVC_READ_DIR, (0x87<<10));
 602
 603         /*Read data byte 0;*/
 604         temp = (0x82|MCI_MEMORY_DATA_BYTE0)<<10;
 605         setITVCReg(dev, ITVC_READ_DIR, temp);
 606         temp = ((0x81|MCI_MEMORY_DATA_BYTE0)<<10);
 607         setITVCReg(dev, ITVC_READ_DIR, temp);
 608         getITVCReg(dev, ITVC_READ_DIR, &temp);
 609         return_value |= ((temp&0x03FC0000)>>18);
 610         setITVCReg(dev, ITVC_READ_DIR, (0x87<<10));
 611
 612         *value  = return_value;
 613         return ret;
 614 }
 615
 616 /* ------------------------------------------------------------------ */
 617
 618 /* MPEG encoder API */
 619 static char *cmd_to_str(int cmd)
 620 {
 621         switch (cmd) {
 622         case CX2341X_ENC_PING_FW:
 623                 return  "PING_FW";
 624         case CX2341X_ENC_START_CAPTURE:
 625                 return  "START_CAPTURE";
 626         case CX2341X_ENC_STOP_CAPTURE:
 627                 return  "STOP_CAPTURE";
 628         case CX2341X_ENC_SET_AUDIO_ID:
 629                 return  "SET_AUDIO_ID";
 630         case CX2341X_ENC_SET_VIDEO_ID:
 631                 return  "SET_VIDEO_ID";
 632         case CX2341X_ENC_SET_PCR_ID:
 633                 return  "SET_PCR_PID";
 634         case CX2341X_ENC_SET_FRAME_RATE:
 635                 return  "SET_FRAME_RATE";
 636         case CX2341X_ENC_SET_FRAME_SIZE:
 637                 return  "SET_FRAME_SIZE";
 638         case CX2341X_ENC_SET_BIT_RATE:
 639                 return  "SET_BIT_RATE";
 640         case CX2341X_ENC_SET_GOP_PROPERTIES:
 641                 return  "SET_GOP_PROPERTIES";
 642         case CX2341X_ENC_SET_ASPECT_RATIO:
 643                 return  "SET_ASPECT_RATIO";
 644         case CX2341X_ENC_SET_DNR_FILTER_MODE:
 645                 return  "SET_DNR_FILTER_PROPS";
 646         case CX2341X_ENC_SET_DNR_FILTER_PROPS:
 647                 return  "SET_DNR_FILTER_PROPS";
 648         case CX2341X_ENC_SET_CORING_LEVELS:
 649                 return  "SET_CORING_LEVELS";
 650         case CX2341X_ENC_SET_SPATIAL_FILTER_TYPE:
 651                 return  "SET_SPATIAL_FILTER_TYPE";
 652         case CX2341X_ENC_SET_VBI_LINE:
 653                 return  "SET_VBI_LINE";
 654         case CX2341X_ENC_SET_STREAM_TYPE:
 655                 return  "SET_STREAM_TYPE";
 656         case CX2341X_ENC_SET_OUTPUT_PORT:
 657                 return  "SET_OUTPUT_PORT";
 658         case CX2341X_ENC_SET_AUDIO_PROPERTIES:
 659                 return  "SET_AUDIO_PROPERTIES";
 660         case CX2341X_ENC_HALT_FW:
 661                 return  "HALT_FW";
 662         case CX2341X_ENC_GET_VERSION:
 663                 return  "GET_VERSION";
 664         case CX2341X_ENC_SET_GOP_CLOSURE:
 665                 return  "SET_GOP_CLOSURE";
 666         case CX2341X_ENC_GET_SEQ_END:
 667                 return  "GET_SEQ_END";
 668         case CX2341X_ENC_SET_PGM_INDEX_INFO:
 669                 return  "SET_PGM_INDEX_INFO";
 670         case CX2341X_ENC_SET_VBI_CONFIG:
 671                 return  "SET_VBI_CONFIG";
 672         case CX2341X_ENC_SET_DMA_BLOCK_SIZE:
 673                 return  "SET_DMA_BLOCK_SIZE";
 674         case CX2341X_ENC_GET_PREV_DMA_INFO_MB_10:
 675                 return  "GET_PREV_DMA_INFO_MB_10";
 676         case CX2341X_ENC_GET_PREV_DMA_INFO_MB_9:
 677                 return  "GET_PREV_DMA_INFO_MB_9";
 678         case CX2341X_ENC_SCHED_DMA_TO_HOST:
 679                 return  "SCHED_DMA_TO_HOST";
 680         case CX2341X_ENC_INITIALIZE_INPUT:
 681                 return  "INITIALIZE_INPUT";
 682         case CX2341X_ENC_SET_FRAME_DROP_RATE:
 683                 return  "SET_FRAME_DROP_RATE";
 684         case CX2341X_ENC_PAUSE_ENCODER:
 685                 return  "PAUSE_ENCODER";
 686         case CX2341X_ENC_REFRESH_INPUT:
 687                 return  "REFRESH_INPUT";
 688         case CX2341X_ENC_SET_COPYRIGHT:
 689                 return  "SET_COPYRIGHT";
 690         case CX2341X_ENC_SET_EVENT_NOTIFICATION:
 691                 return  "SET_EVENT_NOTIFICATION";
 692         case CX2341X_ENC_SET_NUM_VSYNC_LINES:
 693                 return  "SET_NUM_VSYNC_LINES";
 694         case CX2341X_ENC_SET_PLACEHOLDER:
 695                 return  "SET_PLACEHOLDER";
 696         case CX2341X_ENC_MUTE_VIDEO:
 697                 return  "MUTE_VIDEO";
 698         case CX2341X_ENC_MUTE_AUDIO:
 699                 return  "MUTE_AUDIO";
 700         case CX2341X_ENC_MISC:
 701                 return  "MISC";
 702         default:
 703                 return "UNKNOWN";
 704         }
 705 }
 706
 707 static int cx231xx_mbox_func(void *priv,
 708                              u32 command,
 709                              int in,
 710                              int out,
 711                              u32 data[CX2341X_MBOX_MAX_DATA])
 712 {
 713         struct cx231xx *dev = priv;
 714         unsigned long timeout;
 715         u32 value, flag, retval = 0;
 716         int i;
 717
 718         dprintk(3, "%s: command(0x%X) = %s\n", __func__, command,
 719                 cmd_to_str(command));
 720
 721         /* this may not be 100% safe if we can't read any memory location
 722            without side effects */
 723         mc417_memory_read(dev, dev->cx23417_mailbox - 4, &value);
 724         if (value != 0x12345678) {
 725                 dprintk(3,
 726                         "Firmware and/or mailbox pointer not initialized "
 727                         "or corrupted, signature = 0x%x, cmd = %s\n", value,
 728                         cmd_to_str(command));
 729                 return -1;
 730         }
 731
 732         /* This read looks at 32 bits, but flag is only 8 bits.
 733          * Seems we also bail if CMD or TIMEOUT bytes are set???
 734          */
 735         mc417_memory_read(dev, dev->cx23417_mailbox, &flag);
 736         if (flag) {
 737                 dprintk(3, "ERROR: Mailbox appears to be in use "
 738                         "(%x), cmd = %s\n", flag, cmd_to_str(command));
 739                 return -1;
 740         }
 741
 742         flag |= 1; /* tell 'em we're working on it */
 743         mc417_memory_write(dev, dev->cx23417_mailbox, flag);
 744
 745         /* write command + args + fill remaining with zeros */
 746         /* command code */
 747         mc417_memory_write(dev, dev->cx23417_mailbox + 1, command);
 748         mc417_memory_write(dev, dev->cx23417_mailbox + 3,
 749                 IVTV_API_STD_TIMEOUT); /* timeout */
 750         for (i = 0; i < in; i++) {
 751                 mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, data[i]);
 752                 dprintk(3, "API Input %d = %d\n", i, data[i]);
 753         }
 754         for (; i < CX2341X_MBOX_MAX_DATA; i++)
 755                 mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, 0);
 756
 757         flag |= 3; /* tell 'em we're done writing */
 758         mc417_memory_write(dev, dev->cx23417_mailbox, flag);
 759
 760         /* wait for firmware to handle the API command */
 761         timeout = jiffies + msecs_to_jiffies(10);
 762         for (;;) {
 763                 mc417_memory_read(dev, dev->cx23417_mailbox, &flag);
 764                 if (0 != (flag & 4))
 765                         break;
 766                 if (time_after(jiffies, timeout)) {
 767                         dprintk(3, "ERROR: API Mailbox timeout\n");
 768                         return -1;
 769                 }
 770                 udelay(10);
 771         }
 772
 773         /* read output values */
 774         for (i = 0; i < out; i++) {
 775                 mc417_memory_read(dev, dev->cx23417_mailbox + 4 + i, data + i);
 776                 dprintk(3, "API Output %d = %d\n", i, data[i]);
 777         }
 778
 779         mc417_memory_read(dev, dev->cx23417_mailbox + 2, &retval);
 780         dprintk(3, "API result = %d\n", retval);
 781
 782         flag = 0;
 783         mc417_memory_write(dev, dev->cx23417_mailbox, flag);
 784
 785         return retval;
 786 }
 787
 788 /* We don't need to call the API often, so using just one
 789  * mailbox will probably suffice
 790  */
 791 static int cx231xx_api_cmd(struct cx231xx *dev,
 792                            u32 command,
 793                            u32 inputcnt,
 794                            u32 outputcnt,
 795                            ...)
 796 {
 797         u32 data[CX2341X_MBOX_MAX_DATA];
 798         va_list vargs;
 799         int i, err;
 800
 801         dprintk(3, "%s() cmds = 0x%08x\n", __func__, command);
 802
 803         va_start(vargs, outputcnt);
 804         for (i = 0; i < inputcnt; i++)
 805                 data[i] = va_arg(vargs, int);
 806
 807         err = cx231xx_mbox_func(dev, command, inputcnt, outputcnt, data);
 808         for (i = 0; i < outputcnt; i++) {
 809                 int *vptr = va_arg(vargs, int *);
 810                 *vptr = data[i];
 811         }
 812         va_end(vargs);
 813
 814         return err;
 815 }
 816
 817 static int cx231xx_find_mailbox(struct cx231xx *dev)
 818 {
 819         u32 signature[4] = {
 820                 0x12345678, 0x34567812, 0x56781234, 0x78123456
 821         };
 822         int signaturecnt = 0;
 823         u32 value;
 824         int i;
 825         int ret = 0;
 826
 827         dprintk(2, "%s()\n", __func__);
 828
 829         for (i = 0; i < 0x100; i++) {/*CX231xx_FIRM_IMAGE_SIZE*/
 830                 ret = mc417_memory_read(dev, i, &value);
 831                 if (ret < 0)
 832                         return ret;
 833                 if (value == signature[signaturecnt])
 834                         signaturecnt++;
 835                 else
 836                         signaturecnt = 0;
 837                 if (4 == signaturecnt) {
 838                         dprintk(1, "Mailbox signature found at 0x%x\n", i+1);
 839                         return i+1;
 840                 }
 841         }
 842         dprintk(3, "Mailbox signature values not found!\n");
 843         return -1;
 844 }
 845
 846 static void mciWriteMemoryToGPIO(struct cx231xx *dev, u32 address, u32 value,
 847                 u32 *p_fw_image)
 848 {
 849
 850         u32 temp = 0;
 851         int i = 0;
 852
 853         temp = 0x82|MCI_MEMORY_DATA_BYTE0|((value&0x000000FF)<<8);
 854         temp = temp<<10;
 855         *p_fw_image = temp;
 856         p_fw_image++;
 857         temp = temp|((0x05)<<10);
 858         *p_fw_image = temp;
 859         p_fw_image++;
 860
 861         /*write data byte 1;*/
 862         temp = 0x82|MCI_MEMORY_DATA_BYTE1|(value&0x0000FF00);
 863         temp = temp<<10;
 864         *p_fw_image = temp;
 865         p_fw_image++;
 866         temp = temp|((0x05)<<10);
 867         *p_fw_image = temp;
 868         p_fw_image++;
 869
 870         /*write data byte 2;*/
 871         temp = 0x82|MCI_MEMORY_DATA_BYTE2|((value&0x00FF0000)>>8);
 872         temp = temp<<10;
 873         *p_fw_image = temp;
 874         p_fw_image++;
 875         temp = temp|((0x05)<<10);
 876         *p_fw_image = temp;
 877         p_fw_image++;
 878
 879         /*write data byte 3;*/
 880         temp = 0x82|MCI_MEMORY_DATA_BYTE3|((value&0xFF000000)>>16);
 881         temp = temp<<10;
 882         *p_fw_image = temp;
 883         p_fw_image++;
 884         temp = temp|((0x05)<<10);
 885         *p_fw_image = temp;
 886         p_fw_image++;
 887
 888         /* write address byte 2;*/
 889         temp = 0x82|MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_WRITE |
 890                 ((address & 0x003F0000)>>8);
 891         temp = temp<<10;
 892         *p_fw_image = temp;
 893         p_fw_image++;
 894         temp = temp|((0x05)<<10);
 895         *p_fw_image = temp;
 896         p_fw_image++;
 897
 898         /* write address byte 1;*/
 899         temp = 0x82|MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00);
 900         temp = temp<<10;
 901         *p_fw_image = temp;
 902         p_fw_image++;
 903         temp = temp|((0x05)<<10);
 904         *p_fw_image = temp;
 905         p_fw_image++;
 906
 907         /* write address byte 0;*/
 908         temp = 0x82|MCI_MEMORY_ADDRESS_BYTE0|((address & 0x00FF)<<8);
 909         temp = temp<<10;
 910         *p_fw_image = temp;
 911         p_fw_image++;
 912         temp = temp|((0x05)<<10);
 913         *p_fw_image = temp;
 914         p_fw_image++;
 915
 916         for (i = 0; i < 6; i++) {
 917                 *p_fw_image = 0xFFFFFFFF;
 918                 p_fw_image++;
 919         }
 920 }
 921
 922
 923 static int cx231xx_load_firmware(struct cx231xx *dev)
 924 {
 925         static const unsigned char magic[8] = {
 926                 0xa7, 0x0d, 0x00, 0x00, 0x66, 0xbb, 0x55, 0xaa
 927         };
 928         const struct firmware *firmware;
 929         int i, retval = 0;
 930         u32 value = 0;
 931         u32 gpio_output = 0;
 932         /*u32 checksum = 0;*/
 933         /*u32 *dataptr;*/
 934         u32 transfer_size = 0;
 935         u32 fw_data = 0;
 936         u32 address = 0;
 937         /*u32 current_fw[800];*/
 938         u32 *p_current_fw, *p_fw;
 939         u32 *p_fw_data;
 940         int frame = 0;
 941         u16 _buffer_size = 4096;
 942         u8 *p_buffer;
 943
 944         p_current_fw = (u32 *)vmalloc(1884180*4);
 945         p_fw = p_current_fw;
 946         if (p_current_fw == 0) {
 947                 dprintk(2, "FAIL!!!\n");
 948                 return -1;
 949         }
 950
 951         p_buffer = (u8 *)vmalloc(4096);
 952         if (p_buffer == 0) {
 953                 dprintk(2, "FAIL!!!\n");
 954                 return -1;
 955         }
 956
 957         dprintk(2, "%s()\n", __func__);
 958
 959         /* Save GPIO settings before reset of APU */
 960         retval |= mc417_memory_read(dev, 0x9020, &gpio_output);
 961         retval |= mc417_memory_read(dev, 0x900C, &value);
 962
 963         retval  = mc417_register_write(dev,
 964                 IVTV_REG_VPU, 0xFFFFFFED);
 965         retval |= mc417_register_write(dev,
 966                 IVTV_REG_HW_BLOCKS, IVTV_CMD_HW_BLOCKS_RST);
 967         retval |= mc417_register_write(dev,
 968                 IVTV_REG_ENC_SDRAM_REFRESH, 0x80000800);
 969         retval |= mc417_register_write(dev,
 970                 IVTV_REG_ENC_SDRAM_PRECHARGE, 0x1A);
 971         retval |= mc417_register_write(dev,
 972                 IVTV_REG_APU, 0);
 973
 974         if (retval != 0) {
 975                 printk(KERN_ERR "%s: Error with mc417_register_write\n",
 976                         __func__);
 977                 return -1;
 978         }
 979
 980         retval = request_firmware(&firmware, CX231xx_FIRM_IMAGE_NAME,
 981                                   &dev->udev->dev);
 982
 983         if (retval != 0) {
 984                 printk(KERN_ERR
 985                         "ERROR: Hotplug firmware request failed (%s).\n",
 986                         CX231xx_FIRM_IMAGE_NAME);
 987                 printk(KERN_ERR "Please fix your hotplug setup, the board will "
 988                         "not work without firmware loaded!\n");
 989                 return -1;
 990         }
 991
 992         if (firmware->size != CX231xx_FIRM_IMAGE_SIZE) {
 993                 printk(KERN_ERR "ERROR: Firmware size mismatch "
 994                         "(have %zd, expected %d)\n",
 995                         firmware->size, CX231xx_FIRM_IMAGE_SIZE);
 996                 release_firmware(firmware);
 997                 return -1;
 998         }
 999
1000         if (0 != memcmp(firmware->data, magic, 8)) {
1001                 printk(KERN_ERR
1002                         "ERROR: Firmware magic mismatch, wrong file?\n");
1003                 release_firmware(firmware);
1004                 return -1;
1005         }
1006
1007         initGPIO(dev);
1008
1009         /* transfer to the chip */
1010         dprintk(2, "Loading firmware to GPIO...\n");
1011         p_fw_data = (u32 *)firmware->data;
1012         dprintk(2, "firmware->size=%zd\n", firmware->size);
1013         for (transfer_size = 0; transfer_size < firmware->size;
1014                  transfer_size += 4) {
1015                 fw_data = *p_fw_data;
1016
1017                  mciWriteMemoryToGPIO(dev, address, fw_data, p_current_fw);
1018                 address = address + 1;
1019                 p_current_fw += 20;
1020                 p_fw_data += 1;
1021         }
1022
1023         /*download the firmware by ep5-out*/
1024
1025         for (frame = 0; frame < (int)(CX231xx_FIRM_IMAGE_SIZE*20/_buffer_size);
1026              frame++) {
1027                 for (i = 0; i < _buffer_size; i++) {
1028                         *(p_buffer + i) = (u8)(*(p_fw + (frame * 128 * 8 + (i / 4))) & 0x000000FF);
1029                         i++;
1030                         *(p_buffer + i) = (u8)((*(p_fw + (frame * 128 * 8 + (i / 4))) & 0x0000FF00) >> 8);
1031                         i++;
1032                         *(p_buffer + i) = (u8)((*(p_fw + (frame * 128 * 8 + (i / 4))) & 0x00FF0000) >> 16);
1033                         i++;
1034                         *(p_buffer + i) = (u8)((*(p_fw + (frame * 128 * 8 + (i / 4))) & 0xFF000000) >> 24);
1035                 }
1036                 cx231xx_ep5_bulkout(dev, p_buffer, _buffer_size);
1037         }
1038
1039         p_current_fw = p_fw;
1040         vfree(p_current_fw);
1041         p_current_fw = NULL;
1042         uninitGPIO(dev);
1043         release_firmware(firmware);
1044         dprintk(1, "Firmware upload successful.\n");
1045
1046         retval |= mc417_register_write(dev, IVTV_REG_HW_BLOCKS,
1047                 IVTV_CMD_HW_BLOCKS_RST);
1048         if (retval < 0) {
1049                 printk(KERN_ERR "%s: Error with mc417_register_write\n",
1050                         __func__);
1051                 return retval;
1052         }
1053         /* F/W power up disturbs the GPIOs, restore state */
1054         retval |= mc417_register_write(dev, 0x9020, gpio_output);
1055         retval |= mc417_register_write(dev, 0x900C, value);
1056
1057         retval |= mc417_register_read(dev, IVTV_REG_VPU, &value);
1058         retval |= mc417_register_write(dev, IVTV_REG_VPU, value & 0xFFFFFFE8);
1059
1060         if (retval < 0) {
1061                 printk(KERN_ERR "%s: Error with mc417_register_write\n",
1062                         __func__);
1063                 return retval;
1064         }
1065         return 0;
1066 }
1067
1068 static void cx231xx_417_check_encoder(struct cx231xx *dev)
1069 {
1070         u32 status, seq;
1071
1072         status = 0;
1073         seq = 0;
1074         cx231xx_api_cmd(dev, CX2341X_ENC_GET_SEQ_END, 0, 2, &status, &seq);
1075         dprintk(1, "%s() status = %d, seq = %d\n", __func__, status, seq);
1076 }
1077
1078 static void cx231xx_codec_settings(struct cx231xx *dev)
1079 {
1080         dprintk(1, "%s()\n", __func__);
1081
1082         /* assign frame size */
1083         cx231xx_api_cmd(dev, CX2341X_ENC_SET_FRAME_SIZE, 2, 0,
1084                                 dev->ts1.height, dev->ts1.width);
1085
1086         dev->mpeg_params.width = dev->ts1.width;
1087         dev->mpeg_params.height = dev->ts1.height;
1088
1089         cx2341x_update(dev, cx231xx_mbox_func, NULL, &dev->mpeg_params);
1090
1091         cx231xx_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 3, 1);
1092         cx231xx_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 4, 1);
1093 }
1094
1095 static int cx231xx_initialize_codec(struct cx231xx *dev)
1096 {
1097         int version;
1098         int retval;
1099         u32 i, data[7];
1100         u32 val = 0;
1101
1102         dprintk(1, "%s()\n", __func__);
1103         cx231xx_disable656(dev);
1104         retval = cx231xx_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0); /* ping */
1105         if (retval < 0) {
1106                 dprintk(2, "%s() PING OK\n", __func__);
1107                 retval = cx231xx_load_firmware(dev);
1108                 if (retval < 0) {
1109                         printk(KERN_ERR "%s() f/w load failed\n", __func__);
1110                         return retval;
1111                 }
1112                 retval = cx231xx_find_mailbox(dev);
1113                 if (retval < 0) {
1114                         printk(KERN_ERR "%s() mailbox < 0, error\n",
1115                                 __func__);
1116                         return -1;
1117                 }
1118                 dev->cx23417_mailbox = retval;
1119                 retval = cx231xx_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0);
1120                 if (retval < 0) {
1121                         printk(KERN_ERR
1122                                 "ERROR: cx23417 firmware ping failed!\n");
1123                         return -1;
1124                 }
1125                 retval = cx231xx_api_cmd(dev, CX2341X_ENC_GET_VERSION, 0, 1,
1126                         &version);
1127                 if (retval < 0) {
1128                         printk(KERN_ERR "ERROR: cx23417 firmware get encoder :"
1129                                 "version failed!\n");
1130                         return -1;
1131                 }
1132                 dprintk(1, "cx23417 firmware version is 0x%08x\n", version);
1133                 msleep(200);
1134         }
1135
1136         for (i = 0; i < 1; i++) {
1137                 retval = mc417_register_read(dev, 0x20f8, &val);
1138                 dprintk(3, "***before enable656() VIM Capture Lines =%d ***\n",
1139                                  val);
1140                 if (retval < 0)
1141                         return retval;
1142         }
1143
1144         cx231xx_enable656(dev);
1145                         /* stop mpeg capture */
1146                         cx231xx_api_cmd(dev, CX2341X_ENC_STOP_CAPTURE,
1147                                  3, 0, 1, 3, 4);
1148
1149         cx231xx_codec_settings(dev);
1150         msleep(60);
1151
1152 /*      cx231xx_api_cmd(dev, CX2341X_ENC_SET_NUM_VSYNC_LINES, 2, 0,
1153                 CX231xx_FIELD1_SAA7115, CX231xx_FIELD2_SAA7115);
1154         cx231xx_api_cmd(dev, CX2341X_ENC_SET_PLACEHOLDER, 12, 0,
1155                 CX231xx_CUSTOM_EXTENSION_USR_DATA, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1156                 0, 0);
1157 */
1158         /* Setup to capture VBI */
1159         data[0] = 0x0001BD00;
1160         data[1] = 1;          /* frames per interrupt */
1161         data[2] = 4;          /* total bufs */
1162         data[3] = 0x91559155; /* start codes */
1163         data[4] = 0x206080C0; /* stop codes */
1164         data[5] = 6;          /* lines */
1165         data[6] = 64;         /* BPL */
1166 /*
1167         cx231xx_api_cmd(dev, CX2341X_ENC_SET_VBI_CONFIG, 7, 0, data[0], data[1],
1168                 data[2], data[3], data[4], data[5], data[6]);
1169
1170         for (i = 2; i <= 24; i++) {
1171                 int valid;
1172
1173                 valid = ((i >= 19) && (i <= 21));
1174                 cx231xx_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0, i,
1175                                 valid, 0 , 0, 0);
1176                 cx231xx_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0,
1177                                 i | 0x80000000, valid, 0, 0, 0);
1178         }
1179 */
1180 /*      cx231xx_api_cmd(dev, CX2341X_ENC_MUTE_AUDIO, 1, 0, CX231xx_UNMUTE);
1181         msleep(60);
1182 */
1183         /* initialize the video input */
1184         retval = cx231xx_api_cmd(dev, CX2341X_ENC_INITIALIZE_INPUT, 0, 0);
1185         if (retval < 0)
1186                 return retval;
1187         msleep(60);
1188
1189         /* Enable VIP style pixel invalidation so we work with scaled mode */
1190         mc417_memory_write(dev, 2120, 0x00000080);
1191
1192         /* start capturing to the host interface */
1193         retval = cx231xx_api_cmd(dev, CX2341X_ENC_START_CAPTURE, 2, 0,
1194                 CX231xx_MPEG_CAPTURE, CX231xx_RAW_BITS_NONE);
1195         if (retval < 0)
1196                 return retval;
1197         msleep(10);
1198
1199         for (i = 0; i < 1; i++) {
1200                 mc417_register_read(dev, 0x20f8, &val);
1201         dprintk(3, "***VIM Capture Lines =%d ***\n", val);
1202         }
1203
1204         return 0;
1205 }
1206
1207 /* ------------------------------------------------------------------ */
1208
1209 static int bb_buf_setup(struct videobuf_queue *q,
1210         unsigned int *count, unsigned int *size)
1211 {
1212         struct cx231xx_fh *fh = q->priv_data;
1213
1214         fh->dev->ts1.ts_packet_size  = mpeglinesize;
1215         fh->dev->ts1.ts_packet_count = mpeglines;
1216
1217         *size = fh->dev->ts1.ts_packet_size * fh->dev->ts1.ts_packet_count;
1218         *count = mpegbufs;
1219
1220         return 0;
1221 }
1222 static void free_buffer(struct videobuf_queue *vq, struct cx231xx_buffer *buf)
1223 {
1224         struct cx231xx_fh *fh = vq->priv_data;
1225         struct cx231xx *dev = fh->dev;
1226         unsigned long flags = 0;
1227
1228         if (in_interrupt())
1229                 BUG();
1230
1231         spin_lock_irqsave(&dev->video_mode.slock, flags);
1232         if (dev->USE_ISO) {
1233                 if (dev->video_mode.isoc_ctl.buf == buf)
1234                         dev->video_mode.isoc_ctl.buf = NULL;
1235         } else {
1236                 if (dev->video_mode.bulk_ctl.buf == buf)
1237                         dev->video_mode.bulk_ctl.buf = NULL;
1238         }
1239         spin_unlock_irqrestore(&dev->video_mode.slock, flags);
1240         videobuf_waiton(vq, &buf->vb, 0, 0);
1241         videobuf_vmalloc_free(&buf->vb);
1242         buf->vb.state = VIDEOBUF_NEEDS_INIT;
1243 }
1244
1245 static void buffer_copy(struct cx231xx *dev, char *data, int len, struct urb *urb,
1246                 struct cx231xx_dmaqueue *dma_q)
1247 {
1248                 void *vbuf;
1249                 struct cx231xx_buffer *buf;
1250                 u32 tail_data = 0;
1251                 char *p_data;
1252
1253                 if (dma_q->mpeg_buffer_done == 0) {
1254                         if (list_empty(&dma_q->active))
1255                                 return;
1256
1257                         buf = list_entry(dma_q->active.next,
1258                                         struct cx231xx_buffer, vb.queue);
1259                         dev->video_mode.isoc_ctl.buf = buf;
1260                         dma_q->mpeg_buffer_done = 1;
1261                 }
1262                 /* Fill buffer */
1263                 buf = dev->video_mode.isoc_ctl.buf;
1264                 vbuf = videobuf_to_vmalloc(&buf->vb);
1265
1266                 if ((dma_q->mpeg_buffer_completed+len) <
1267                    mpeglines*mpeglinesize) {
1268                         if (dma_q->add_ps_package_head ==
1269                            CX231XX_NEED_ADD_PS_PACKAGE_HEAD) {
1270                                 memcpy(vbuf+dma_q->mpeg_buffer_completed,
1271                                        dma_q->ps_head, 3);
1272                                 dma_q->mpeg_buffer_completed =
1273                                   dma_q->mpeg_buffer_completed + 3;
1274                                 dma_q->add_ps_package_head =
1275                                   CX231XX_NONEED_PS_PACKAGE_HEAD;
1276                         }
1277                         memcpy(vbuf+dma_q->mpeg_buffer_completed, data, len);
1278                         dma_q->mpeg_buffer_completed =
1279                           dma_q->mpeg_buffer_completed + len;
1280                 } else {
1281                         dma_q->mpeg_buffer_done = 0;
1282
1283                         tail_data =
1284                           mpeglines*mpeglinesize - dma_q->mpeg_buffer_completed;
1285                         memcpy(vbuf+dma_q->mpeg_buffer_completed,
1286                                data, tail_data);
1287
1288                         buf->vb.state = VIDEOBUF_DONE;
1289                         buf->vb.field_count++;
1290                         do_gettimeofday(&buf->vb.ts);
1291                         list_del(&buf->vb.queue);
1292                         wake_up(&buf->vb.done);
1293                         dma_q->mpeg_buffer_completed = 0;
1294
1295                         if (len - tail_data > 0) {
1296                                 p_data = data + tail_data;
1297                                 dma_q->left_data_count = len - tail_data;
1298                                 memcpy(dma_q->p_left_data,
1299                                        p_data, len - tail_data);
1300                         }
1301
1302                 }
1303
1304             return;
1305 }
1306
1307 static void buffer_filled(char *data, int len, struct urb *urb,
1308                 struct cx231xx_dmaqueue *dma_q)
1309 {
1310                 void *vbuf;
1311                 struct cx231xx_buffer *buf;
1312
1313                 if (list_empty(&dma_q->active))
1314                         return;
1315
1316
1317                 buf = list_entry(dma_q->active.next,
1318                                  struct cx231xx_buffer, vb.queue);
1319
1320
1321                 /* Fill buffer */
1322                 vbuf = videobuf_to_vmalloc(&buf->vb);
1323                 memcpy(vbuf, data, len);
1324                 buf->vb.state = VIDEOBUF_DONE;
1325                 buf->vb.field_count++;
1326                 do_gettimeofday(&buf->vb.ts);
1327                 list_del(&buf->vb.queue);
1328                 wake_up(&buf->vb.done);
1329
1330             return;
1331 }
1332 static inline int cx231xx_isoc_copy(struct cx231xx *dev, struct urb *urb)
1333 {
1334         struct cx231xx_dmaqueue *dma_q = urb->context;
1335         unsigned char *p_buffer;
1336         u32 buffer_size = 0;
1337         u32 i = 0;
1338
1339         for (i = 0; i < urb->number_of_packets; i++) {
1340                 if (dma_q->left_data_count > 0) {
1341                         buffer_copy(dev, dma_q->p_left_data,
1342                                     dma_q->left_data_count, urb, dma_q);
1343                         dma_q->mpeg_buffer_completed = dma_q->left_data_count;
1344                         dma_q->left_data_count = 0;
1345                 }
1346
1347                 p_buffer = urb->transfer_buffer +
1348                                 urb->iso_frame_desc[i].offset;
1349                 buffer_size = urb->iso_frame_desc[i].actual_length;
1350
1351                 if (buffer_size > 0)
1352                         buffer_copy(dev, p_buffer, buffer_size, urb, dma_q);
1353         }
1354
1355         return 0;
1356 }
1357 static inline int cx231xx_bulk_copy(struct cx231xx *dev, struct urb *urb)
1358 {
1359
1360         /*char *outp;*/
1361         /*struct cx231xx_buffer *buf;*/
1362         struct cx231xx_dmaqueue *dma_q = urb->context;
1363         unsigned char *p_buffer, *buffer;
1364         u32 buffer_size = 0;
1365
1366         p_buffer = urb->transfer_buffer;
1367         buffer_size = urb->actual_length;
1368
1369         buffer = kmalloc(buffer_size, GFP_ATOMIC);
1370
1371         memcpy(buffer, dma_q->ps_head, 3);
1372         memcpy(buffer+3, p_buffer, buffer_size-3);
1373         memcpy(dma_q->ps_head, p_buffer+buffer_size-3, 3);
1374
1375         p_buffer = buffer;
1376         buffer_filled(p_buffer, buffer_size, urb, dma_q);
1377
1378         kfree(buffer);
1379         return 0;
1380 }
1381
1382 static int bb_buf_prepare(struct videobuf_queue *q,
1383         struct videobuf_buffer *vb, enum v4l2_field field)
1384 {
1385         struct cx231xx_fh *fh = q->priv_data;
1386         struct cx231xx_buffer *buf =
1387             container_of(vb, struct cx231xx_buffer, vb);
1388         struct cx231xx *dev = fh->dev;
1389         int rc = 0, urb_init = 0;
1390         int size = fh->dev->ts1.ts_packet_size * fh->dev->ts1.ts_packet_count;
1391
1392         dma_qq = &dev->video_mode.vidq;
1393
1394         if (0 != buf->vb.baddr  &&  buf->vb.bsize < size)
1395                 return -EINVAL;
1396         buf->vb.width = fh->dev->ts1.ts_packet_size;
1397         buf->vb.height = fh->dev->ts1.ts_packet_count;
1398         buf->vb.size = size;
1399         buf->vb.field = field;
1400
1401         if (VIDEOBUF_NEEDS_INIT == buf->vb.state) {
1402                 rc = videobuf_iolock(q, &buf->vb, NULL);
1403                 if (rc < 0)
1404                         goto fail;
1405         }
1406
1407         if (dev->USE_ISO) {
1408                 if (!dev->video_mode.isoc_ctl.num_bufs)
1409                         urb_init = 1;
1410         } else {
1411                 if (!dev->video_mode.bulk_ctl.num_bufs)
1412                         urb_init = 1;
1413         }
1414         /*cx231xx_info("urb_init=%d dev->video_mode.max_pkt_size=%d\n",
1415                 urb_init, dev->video_mode.max_pkt_size);*/
1416         dev->mode_tv = 1;
1417
1418         if (urb_init) {
1419                 rc = cx231xx_set_mode(dev, CX231XX_DIGITAL_MODE);
1420                 rc = cx231xx_unmute_audio(dev);
1421                 if (dev->USE_ISO) {
1422                         cx231xx_set_alt_setting(dev, INDEX_TS1, 4);
1423                         rc = cx231xx_init_isoc(dev, mpeglines,
1424                                        mpegbufs,
1425                                        dev->ts1_mode.max_pkt_size,
1426                                        cx231xx_isoc_copy);
1427                 } else {
1428                         cx231xx_set_alt_setting(dev, INDEX_TS1, 0);
1429                         rc = cx231xx_init_bulk(dev, mpeglines,
1430                                        mpegbufs,
1431                                        dev->ts1_mode.max_pkt_size,
1432                                        cx231xx_bulk_copy);
1433                 }
1434                 if (rc < 0)
1435                         goto fail;
1436         }
1437
1438         buf->vb.state = VIDEOBUF_PREPARED;
1439         return 0;
1440
1441 fail:
1442         free_buffer(q, buf);
1443         return rc;
1444 }
1445
1446 static void bb_buf_queue(struct videobuf_queue *q,
1447         struct videobuf_buffer *vb)
1448 {
1449         struct cx231xx_fh *fh = q->priv_data;
1450
1451         struct cx231xx_buffer *buf =
1452             container_of(vb, struct cx231xx_buffer, vb);
1453         struct cx231xx *dev = fh->dev;
1454         struct cx231xx_dmaqueue *vidq = &dev->video_mode.vidq;
1455
1456         buf->vb.state = VIDEOBUF_QUEUED;
1457         list_add_tail(&buf->vb.queue, &vidq->active);
1458
1459 }
1460
1461 static void bb_buf_release(struct videobuf_queue *q,
1462         struct videobuf_buffer *vb)
1463 {
1464         struct cx231xx_buffer *buf =
1465             container_of(vb, struct cx231xx_buffer, vb);
1466         /*struct cx231xx_fh *fh = q->priv_data;*/
1467         /*struct cx231xx *dev = (struct cx231xx *)fh->dev;*/
1468
1469         free_buffer(q, buf);
1470 }
1471
1472 static struct videobuf_queue_ops cx231xx_qops = {
1473         .buf_setup    = bb_buf_setup,
1474         .buf_prepare  = bb_buf_prepare,
1475         .buf_queue    = bb_buf_queue,
1476         .buf_release  = bb_buf_release,
1477 };
1478
1479 /* ------------------------------------------------------------------ */
1480
1481 static const u32 *ctrl_classes[] = {
1482         cx2341x_mpeg_ctrls,
1483         NULL
1484 };
1485
1486 static int cx231xx_queryctrl(struct cx231xx *dev,
1487         struct v4l2_queryctrl *qctrl)
1488 {
1489         qctrl->id = v4l2_ctrl_next(ctrl_classes, qctrl->id);
1490         if (qctrl->id == 0)
1491                 return -EINVAL;
1492
1493         /* MPEG V4L2 controls */
1494         if (cx2341x_ctrl_query(&dev->mpeg_params, qctrl))
1495                 qctrl->flags |= V4L2_CTRL_FLAG_DISABLED;
1496
1497         return 0;
1498 }
1499
1500 static int cx231xx_querymenu(struct cx231xx *dev,
1501         struct v4l2_querymenu *qmenu)
1502 {
1503         struct v4l2_queryctrl qctrl;
1504
1505         qctrl.id = qmenu->id;
1506         cx231xx_queryctrl(dev, &qctrl);
1507         return v4l2_ctrl_query_menu(qmenu, &qctrl,
1508                 cx2341x_ctrl_get_menu(&dev->mpeg_params, qmenu->id));
1509 }
1510
1511 static int vidioc_g_std(struct file *file, void *fh0, v4l2_std_id *norm)
1512 {
1513         struct cx231xx_fh  *fh  = file->private_data;
1514         struct cx231xx *dev = fh->dev;
1515
1516         *norm = dev->encodernorm.id;
1517         return 0;
1518 }
1519 static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id *id)
1520 {
1521         struct cx231xx_fh  *fh  = file->private_data;
1522         struct cx231xx *dev = fh->dev;
1523         unsigned int i;
1524
1525         for (i = 0; i < ARRAY_SIZE(cx231xx_tvnorms); i++)
1526                 if (*id & cx231xx_tvnorms[i].id)
1527                         break;
1528         if (i == ARRAY_SIZE(cx231xx_tvnorms))
1529                 return -EINVAL;
1530         dev->encodernorm = cx231xx_tvnorms[i];
1531
1532         if (dev->encodernorm.id & 0xb000) {
1533                 dprintk(3, "encodernorm set to NTSC\n");
1534                 dev->norm = V4L2_STD_NTSC;
1535                 dev->ts1.height = 480;
1536                 dev->mpeg_params.is_50hz = 0;
1537         } else {
1538                 dprintk(3, "encodernorm set to PAL\n");
1539                 dev->norm = V4L2_STD_PAL_B;
1540                 dev->ts1.height = 576;
1541                 dev->mpeg_params.is_50hz = 1;
1542         }
1543         call_all(dev, core, s_std, dev->norm);
1544         /* do mode control overrides */
1545         cx231xx_do_mode_ctrl_overrides(dev);
1546
1547         dprintk(3, "exit vidioc_s_std() i=0x%x\n", i);
1548         return 0;
1549 }
1550 static int vidioc_g_audio(struct file *file, void *fh,
1551                                         struct v4l2_audio *a)
1552 {
1553                 struct v4l2_audio *vin = a;
1554
1555                 int ret = -EINVAL;
1556                 if (vin->index > 0)
1557                         return ret;
1558                 strncpy(vin->name, "VideoGrabber Audio", 14);
1559                 vin->capability = V4L2_AUDCAP_STEREO;
1560 return 0;
1561 }
1562 static int vidioc_enumaudio(struct file *file, void *fh,
1563                                         struct v4l2_audio *a)
1564 {
1565                 struct v4l2_audio *vin = a;
1566
1567                 int ret = -EINVAL;
1568
1569                 if (vin->index > 0)
1570                         return ret;
1571                 strncpy(vin->name, "VideoGrabber Audio", 14);
1572                 vin->capability = V4L2_AUDCAP_STEREO;
1573
1574
1575 return 0;
1576 }
1577 static const char *iname[] = {
1578         [CX231XX_VMUX_COMPOSITE1] = "Composite1",
1579         [CX231XX_VMUX_SVIDEO]     = "S-Video",
1580         [CX231XX_VMUX_TELEVISION] = "Television",
1581         [CX231XX_VMUX_CABLE]      = "Cable TV",
1582         [CX231XX_VMUX_DVB]        = "DVB",
1583         [CX231XX_VMUX_DEBUG]      = "for debug only",
1584 };
1585 static int vidioc_enum_input(struct file *file, void *priv,
1586                                 struct v4l2_input *i)
1587 {
1588         struct cx231xx_fh  *fh  = file->private_data;
1589         struct cx231xx *dev = fh->dev;
1590         struct cx231xx_input *input;
1591         int n;
1592         dprintk(3, "enter vidioc_enum_input()i->index=%d\n", i->index);
1593
1594         if (i->index >= 4)
1595                 return -EINVAL;
1596
1597
1598         input = &cx231xx_boards[dev->model].input[i->index];
1599
1600         if (input->type == 0)
1601                 return -EINVAL;
1602
1603         /* FIXME
1604          * strcpy(i->name, input->name); */
1605
1606         n = i->index;
1607         strcpy(i->name, iname[INPUT(n)->type]);
1608
1609         if (input->type == CX231XX_VMUX_TELEVISION ||
1610             input->type == CX231XX_VMUX_CABLE)
1611                 i->type = V4L2_INPUT_TYPE_TUNER;
1612         else
1613                 i->type  = V4L2_INPUT_TYPE_CAMERA;
1614
1615
1616         return 0;
1617 }
1618
1619 static int vidioc_g_input(struct file *file, void *priv, unsigned int *i)
1620 {
1621         *i = 0;
1622         return  0;
1623 }
1624
1625 static int vidioc_s_input(struct file *file, void *priv, unsigned int i)
1626 {
1627         struct cx231xx_fh  *fh  = file->private_data;
1628         struct cx231xx *dev = fh->dev;
1629
1630         dprintk(3, "enter vidioc_s_input() i=%d\n", i);
1631
1632         mutex_lock(&dev->lock);
1633
1634         video_mux(dev, i);
1635
1636         mutex_unlock(&dev->lock);
1637
1638         if (i >= 4)
1639                 return -EINVAL;
1640         dev->input = i;
1641         dprintk(3, "exit vidioc_s_input()\n");
1642         return 0;
1643 }
1644
1645 static int vidioc_g_tuner(struct file *file, void *priv,
1646                                 struct v4l2_tuner *t)
1647 {
1648         return 0;
1649 }
1650
1651 static int vidioc_s_tuner(struct file *file, void *priv,
1652                                 struct v4l2_tuner *t)
1653 {
1654         return 0;
1655 }
1656
1657 static int vidioc_g_frequency(struct file *file, void *priv,
1658                                 struct v4l2_frequency *f)
1659 {
1660         return 0;
1661 }
1662
1663 static int vidioc_s_frequency(struct file *file, void *priv,
1664                                 struct v4l2_frequency *f)
1665 {
1666
1667
1668         return 0;
1669 }
1670
1671 static int vidioc_s_ctrl(struct file *file, void *priv,
1672                                 struct v4l2_control *ctl)
1673 {
1674         struct cx231xx_fh  *fh  = file->private_data;
1675         struct cx231xx *dev = fh->dev;
1676         dprintk(3, "enter vidioc_s_ctrl()\n");
1677         /* Update the A/V core */
1678         call_all(dev, core, s_ctrl, ctl);
1679         dprintk(3, "exit vidioc_s_ctrl()\n");
1680         return 0;
1681 }
1682 static struct v4l2_capability pvr_capability = {
1683         .driver         = "cx231xx",
1684         .card           = "VideoGrabber",
1685         .bus_info       = "usb",
1686         .version        = 1,
1687         .capabilities   = (V4L2_CAP_VIDEO_CAPTURE |
1688                            V4L2_CAP_TUNER | V4L2_CAP_AUDIO | V4L2_CAP_RADIO |
1689                          V4L2_CAP_STREAMING | V4L2_CAP_READWRITE),
1690         .reserved       = {0, 0, 0, 0}
1691 };
1692 static int vidioc_querycap(struct file *file, void  *priv,
1693                                 struct v4l2_capability *cap)
1694 {
1695
1696
1697
1698                 memcpy(cap, &pvr_capability, sizeof(struct v4l2_capability));
1699         return 0;
1700 }
1701
1702 static int vidioc_enum_fmt_vid_cap(struct file *file, void  *priv,
1703                                         struct v4l2_fmtdesc *f)
1704 {
1705
1706         if (f->index != 0)
1707                 return -EINVAL;
1708
1709         strlcpy(f->description, "MPEG", sizeof(f->description));
1710         f->pixelformat = V4L2_PIX_FMT_MPEG;
1711
1712         return 0;
1713 }
1714
1715 static int vidioc_g_fmt_vid_cap(struct file *file, void *priv,
1716                                 struct v4l2_format *f)
1717 {
1718         struct cx231xx_fh  *fh  = file->private_data;
1719         struct cx231xx *dev = fh->dev;
1720         dprintk(3, "enter vidioc_g_fmt_vid_cap()\n");
1721         f->fmt.pix.pixelformat  = V4L2_PIX_FMT_MPEG;
1722         f->fmt.pix.bytesperline = 0;
1723         f->fmt.pix.sizeimage    =
1724                 dev->ts1.ts_packet_size * dev->ts1.ts_packet_count;
1725         f->fmt.pix.colorspace   = 0;
1726         f->fmt.pix.width        = dev->ts1.width;
1727         f->fmt.pix.height       = dev->ts1.height;
1728         f->fmt.pix.field        = fh->vidq.field;
1729         dprintk(1, "VIDIOC_G_FMT: w: %d, h: %d, f: %d\n",
1730                 dev->ts1.width, dev->ts1.height, fh->vidq.field);
1731         dprintk(3, "exit vidioc_g_fmt_vid_cap()\n");
1732         return 0;
1733 }
1734
1735 static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
1736                                 struct v4l2_format *f)
1737 {
1738         struct cx231xx_fh  *fh  = file->private_data;
1739         struct cx231xx *dev = fh->dev;
1740         dprintk(3, "enter vidioc_try_fmt_vid_cap()\n");
1741         f->fmt.pix.pixelformat  = V4L2_PIX_FMT_MPEG;
1742         f->fmt.pix.bytesperline = 0;
1743         f->fmt.pix.sizeimage    =
1744                 dev->ts1.ts_packet_size * dev->ts1.ts_packet_count;
1745         f->fmt.pix.colorspace   = 0;
1746         dprintk(1, "VIDIOC_TRY_FMT: w: %d, h: %d, f: %d\n",
1747                 dev->ts1.width, dev->ts1.height, fh->vidq.field);
1748         dprintk(3, "exit vidioc_try_fmt_vid_cap()\n");
1749         return 0;
1750 }
1751
1752 static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
1753                                 struct v4l2_format *f)
1754 {
1755
1756         return 0;
1757 }
1758
1759 static int vidioc_reqbufs(struct file *file, void *priv,
1760                                 struct v4l2_requestbuffers *p)
1761 {
1762         struct cx231xx_fh  *fh  = file->private_data;
1763
1764         return videobuf_reqbufs(&fh->vidq, p);
1765 }
1766
1767 static int vidioc_querybuf(struct file *file, void *priv,
1768                                 struct v4l2_buffer *p)
1769 {
1770         struct cx231xx_fh  *fh  = file->private_data;
1771
1772         return videobuf_querybuf(&fh->vidq, p);
1773 }
1774
1775 static int vidioc_qbuf(struct file *file, void *priv,
1776                                 struct v4l2_buffer *p)
1777 {
1778         struct cx231xx_fh  *fh  = file->private_data;
1779
1780         return videobuf_qbuf(&fh->vidq, p);
1781 }
1782
1783 static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *b)
1784 {
1785         struct cx231xx_fh  *fh  = priv;
1786
1787         return videobuf_dqbuf(&fh->vidq, b, file->f_flags & O_NONBLOCK);
1788 }
1789
1790
1791 static int vidioc_streamon(struct file *file, void *priv,
1792                                 enum v4l2_buf_type i)
1793 {
1794         struct cx231xx_fh  *fh  = file->private_data;
1795
1796         struct cx231xx *dev = fh->dev;
1797         int rc = 0;
1798         dprintk(3, "enter vidioc_streamon()\n");
1799                 cx231xx_set_alt_setting(dev, INDEX_TS1, 0);
1800                 rc = cx231xx_set_mode(dev, CX231XX_DIGITAL_MODE);
1801                 if (dev->USE_ISO)
1802                         rc = cx231xx_init_isoc(dev, CX231XX_NUM_PACKETS,
1803                                        CX231XX_NUM_BUFS,
1804                                        dev->video_mode.max_pkt_size,
1805                                        cx231xx_isoc_copy);
1806                 else {
1807                         rc = cx231xx_init_bulk(dev, 320,
1808                                        5,
1809                                        dev->ts1_mode.max_pkt_size,
1810                                        cx231xx_bulk_copy);
1811                 }
1812         dprintk(3, "exit vidioc_streamon()\n");
1813         return videobuf_streamon(&fh->vidq);
1814 }
1815
1816 static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i)
1817 {
1818         struct cx231xx_fh  *fh  = file->private_data;
1819
1820         return videobuf_streamoff(&fh->vidq);
1821 }
1822
1823 static int vidioc_g_ext_ctrls(struct file *file, void *priv,
1824                                 struct v4l2_ext_controls *f)
1825 {
1826         struct cx231xx_fh  *fh  = priv;
1827         struct cx231xx *dev = fh->dev;
1828         dprintk(3, "enter vidioc_g_ext_ctrls()\n");
1829         if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG)
1830                 return -EINVAL;
1831         dprintk(3, "exit vidioc_g_ext_ctrls()\n");
1832         return cx2341x_ext_ctrls(&dev->mpeg_params, 0, f, VIDIOC_G_EXT_CTRLS);
1833 }
1834
1835 static int vidioc_s_ext_ctrls(struct file *file, void *priv,
1836                                 struct v4l2_ext_controls *f)
1837 {
1838         struct cx231xx_fh  *fh  = priv;
1839         struct cx231xx *dev = fh->dev;
1840         struct cx2341x_mpeg_params p;
1841         int err;
1842         dprintk(3, "enter vidioc_s_ext_ctrls()\n");
1843         if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG)
1844                 return -EINVAL;
1845
1846         p = dev->mpeg_params;
1847         err = cx2341x_ext_ctrls(&p, 0, f, VIDIOC_TRY_EXT_CTRLS);
1848         if (err == 0) {
1849                 err = cx2341x_update(dev, cx231xx_mbox_func,
1850                         &dev->mpeg_params, &p);
1851                 dev->mpeg_params = p;
1852         }
1853
1854         return err;
1855
1856
1857 return 0;
1858 }
1859
1860 static int vidioc_try_ext_ctrls(struct file *file, void *priv,
1861                                 struct v4l2_ext_controls *f)
1862 {
1863         struct cx231xx_fh  *fh  = priv;
1864         struct cx231xx *dev = fh->dev;
1865         struct cx2341x_mpeg_params p;
1866         int err;
1867         dprintk(3, "enter vidioc_try_ext_ctrls()\n");
1868         if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG)
1869                 return -EINVAL;
1870
1871         p = dev->mpeg_params;
1872         err = cx2341x_ext_ctrls(&p, 0, f, VIDIOC_TRY_EXT_CTRLS);
1873         dprintk(3, "exit vidioc_try_ext_ctrls() err=%d\n", err);
1874         return err;
1875 }
1876
1877 static int vidioc_log_status(struct file *file, void *priv)
1878 {
1879         struct cx231xx_fh  *fh  = priv;
1880         struct cx231xx *dev = fh->dev;
1881         char name[32 + 2];
1882
1883         snprintf(name, sizeof(name), "%s/2", dev->name);
1884         dprintk(3,
1885                 "%s/2: ============  START LOG STATUS  ============\n",
1886                dev->name);
1887         call_all(dev, core, log_status);
1888         cx2341x_log_status(&dev->mpeg_params, name);
1889         dprintk(3,
1890                 "%s/2: =============  END LOG STATUS  =============\n",
1891                dev->name);
1892         return 0;
1893 }
1894
1895 static int vidioc_querymenu(struct file *file, void *priv,
1896                                 struct v4l2_querymenu *a)
1897 {
1898         struct cx231xx_fh  *fh  = priv;
1899         struct cx231xx *dev = fh->dev;
1900         dprintk(3, "enter vidioc_querymenu()\n");
1901         dprintk(3, "exit vidioc_querymenu()\n");
1902         return cx231xx_querymenu(dev, a);
1903 }
1904
1905 static int vidioc_queryctrl(struct file *file, void *priv,
1906                                 struct v4l2_queryctrl *c)
1907 {
1908         struct cx231xx_fh  *fh  = priv;
1909         struct cx231xx *dev = fh->dev;
1910         dprintk(3, "enter vidioc_queryctrl()\n");
1911         dprintk(3, "exit vidioc_queryctrl()\n");
1912         return cx231xx_queryctrl(dev, c);
1913 }
1914
1915 static int mpeg_open(struct file *file)
1916 {
1917         int minor = video_devdata(file)->minor;
1918         struct cx231xx *h, *dev = NULL;
1919         /*struct list_head *list;*/
1920         struct cx231xx_fh *fh;
1921         /*u32 value = 0;*/
1922
1923         dprintk(2, "%s()\n", __func__);
1924
1925         list_for_each_entry(h, &cx231xx_devlist, devlist) {
1926                 if (h->v4l_device->minor == minor)
1927                         dev = h;
1928         }
1929
1930         if (dev == NULL) {
1931                 unlock_kernel();
1932                 return -ENODEV;
1933         }
1934         mutex_lock(&dev->lock);
1935
1936         /* allocate + initialize per filehandle data */
1937         fh = kzalloc(sizeof(*fh), GFP_KERNEL);
1938         if (NULL == fh) {
1939                 mutex_unlock(&dev->lock);
1940                 return -ENOMEM;
1941         }
1942
1943         file->private_data = fh;
1944         fh->dev      = dev;
1945
1946
1947         videobuf_queue_vmalloc_init(&fh->vidq, &cx231xx_qops,
1948                             NULL, &dev->video_mode.slock,
1949                             V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_INTERLACED,
1950                             sizeof(struct cx231xx_buffer), fh, NULL);
1951 /*
1952         videobuf_queue_sg_init(&fh->vidq, &cx231xx_qops,
1953                             &dev->udev->dev, &dev->ts1.slock,
1954                             V4L2_BUF_TYPE_VIDEO_CAPTURE,
1955                             V4L2_FIELD_INTERLACED,
1956                             sizeof(struct cx231xx_buffer),
1957                             fh, NULL);
1958 */
1959
1960
1961         cx231xx_set_alt_setting(dev, INDEX_VANC, 1);
1962         cx231xx_set_gpio_value(dev, 2, 0);
1963
1964         cx231xx_initialize_codec(dev);
1965
1966         mutex_unlock(&dev->lock);
1967         cx231xx_start_TS1(dev);
1968
1969         return 0;
1970 }
1971
1972 static int mpeg_release(struct file *file)
1973 {
1974         struct cx231xx_fh  *fh  = file->private_data;
1975         struct cx231xx *dev = fh->dev;
1976
1977         dprintk(3, "mpeg_release()! dev=0x%p\n", dev);
1978
1979         if (!dev) {
1980                 dprintk(3, "abort!!!\n");
1981                 return 0;
1982         }
1983
1984         mutex_lock(&dev->lock);
1985
1986         cx231xx_stop_TS1(dev);
1987
1988                 /* do this before setting alternate! */
1989                 if (dev->USE_ISO)
1990                         cx231xx_uninit_isoc(dev);
1991                 else
1992                         cx231xx_uninit_bulk(dev);
1993                 cx231xx_set_mode(dev, CX231XX_SUSPEND);
1994
1995                 cx231xx_api_cmd(fh->dev, CX2341X_ENC_STOP_CAPTURE, 3, 0,
1996                                 CX231xx_END_NOW, CX231xx_MPEG_CAPTURE,
1997                                 CX231xx_RAW_BITS_NONE);
1998
1999         /* FIXME: Review this crap */
2000         /* Shut device down on last close */
2001         if (atomic_cmpxchg(&fh->v4l_reading, 1, 0) == 1) {
2002                 if (atomic_dec_return(&dev->v4l_reader_count) == 0) {
2003                         /* stop mpeg capture */
2004
2005                         msleep(500);
2006                         cx231xx_417_check_encoder(dev);
2007
2008                 }
2009         }
2010
2011         if (fh->vidq.streaming)
2012                 videobuf_streamoff(&fh->vidq);
2013         if (fh->vidq.reading)
2014                 videobuf_read_stop(&fh->vidq);
2015
2016         videobuf_mmap_free(&fh->vidq);
2017         file->private_data = NULL;
2018         kfree(fh);
2019         mutex_unlock(&dev->lock);
2020         return 0;
2021 }
2022
2023 static ssize_t mpeg_read(struct file *file, char __user *data,
2024         size_t count, loff_t *ppos)
2025 {
2026         struct cx231xx_fh *fh = file->private_data;
2027         struct cx231xx *dev = fh->dev;
2028
2029
2030         /* Deal w/ A/V decoder * and mpeg encoder sync issues. */
2031         /* Start mpeg encoder on first read. */
2032         if (atomic_cmpxchg(&fh->v4l_reading, 0, 1) == 0) {
2033                 if (atomic_inc_return(&dev->v4l_reader_count) == 1) {
2034                         if (cx231xx_initialize_codec(dev) < 0)
2035                                 return -EINVAL;
2036                 }
2037         }
2038
2039         return videobuf_read_stream(&fh->vidq, data, count, ppos, 0,
2040                                     file->f_flags & O_NONBLOCK);
2041 }
2042
2043 static unsigned int mpeg_poll(struct file *file,
2044         struct poll_table_struct *wait)
2045 {
2046         struct cx231xx_fh *fh = file->private_data;
2047         /*struct cx231xx *dev = fh->dev;*/
2048
2049         /*dprintk(2, "%s\n", __func__);*/
2050
2051         return videobuf_poll_stream(file, &fh->vidq, wait);
2052 }
2053
2054 static int mpeg_mmap(struct file *file, struct vm_area_struct *vma)
2055 {
2056         struct cx231xx_fh *fh = file->private_data;
2057         struct cx231xx *dev = fh->dev;
2058
2059         dprintk(2, "%s()\n", __func__);
2060
2061         return videobuf_mmap_mapper(&fh->vidq, vma);
2062 }
2063
2064 static struct v4l2_file_operations mpeg_fops = {
2065         .owner         = THIS_MODULE,
2066         .open          = mpeg_open,
2067         .release       = mpeg_release,
2068         .read          = mpeg_read,
2069         .poll          = mpeg_poll,
2070         .mmap          = mpeg_mmap,
2071         .ioctl         = video_ioctl2,
2072 };
2073
2074 static const struct v4l2_ioctl_ops mpeg_ioctl_ops = {
2075         .vidioc_s_std            = vidioc_s_std,
2076         .vidioc_g_std            = vidioc_g_std,
2077         .vidioc_enum_input       = vidioc_enum_input,
2078         .vidioc_enumaudio        = vidioc_enumaudio,
2079         .vidioc_g_audio          = vidioc_g_audio,
2080         .vidioc_g_input          = vidioc_g_input,
2081         .vidioc_s_input          = vidioc_s_input,
2082         .vidioc_g_tuner          = vidioc_g_tuner,
2083         .vidioc_s_tuner          = vidioc_s_tuner,
2084         .vidioc_g_frequency      = vidioc_g_frequency,
2085         .vidioc_s_frequency      = vidioc_s_frequency,
2086         .vidioc_s_ctrl           = vidioc_s_ctrl,
2087         .vidioc_querycap         = vidioc_querycap,
2088         .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
2089         .vidioc_g_fmt_vid_cap    = vidioc_g_fmt_vid_cap,
2090         .vidioc_try_fmt_vid_cap  = vidioc_try_fmt_vid_cap,
2091         .vidioc_s_fmt_vid_cap    = vidioc_s_fmt_vid_cap,
2092         .vidioc_reqbufs          = vidioc_reqbufs,
2093         .vidioc_querybuf         = vidioc_querybuf,
2094         .vidioc_qbuf             = vidioc_qbuf,
2095         .vidioc_dqbuf            = vidioc_dqbuf,
2096         .vidioc_streamon         = vidioc_streamon,
2097         .vidioc_streamoff        = vidioc_streamoff,
2098         .vidioc_g_ext_ctrls      = vidioc_g_ext_ctrls,
2099         .vidioc_s_ext_ctrls      = vidioc_s_ext_ctrls,
2100         .vidioc_try_ext_ctrls    = vidioc_try_ext_ctrls,
2101         .vidioc_log_status       = vidioc_log_status,
2102         .vidioc_querymenu        = vidioc_querymenu,
2103         .vidioc_queryctrl        = vidioc_queryctrl,
2104 /*      .vidioc_g_chip_ident     = cx231xx_g_chip_ident,*/
2105 #ifdef CONFIG_VIDEO_ADV_DEBUG
2106 /*      .vidioc_g_register       = cx231xx_g_register,*/
2107 /*      .vidioc_s_register       = cx231xx_s_register,*/
2108 #endif
2109 };
2110
2111 static struct video_device cx231xx_mpeg_template = {
2112         .name          = "cx231xx",
2113         .fops          = &mpeg_fops,
2114         .ioctl_ops     = &mpeg_ioctl_ops,
2115         .minor         = -1,
2116         .tvnorms       = CX231xx_NORMS,
2117         .current_norm  = V4L2_STD_NTSC_M,
2118 };
2119
2120 void cx231xx_417_unregister(struct cx231xx *dev)
2121 {
2122         dprintk(1, "%s()\n", __func__);
2123         dprintk(3, "%s()\n", __func__);
2124
2125         if (dev->v4l_device) {
2126                 if (-1 != dev->v4l_device->minor)
2127                         video_unregister_device(dev->v4l_device);
2128                 else
2129                         video_device_release(dev->v4l_device);
2130                 dev->v4l_device = NULL;
2131         }
2132 }
2133
2134 static struct video_device *cx231xx_video_dev_alloc(
2135         struct cx231xx *dev,
2136         struct usb_device *usbdev,
2137         struct video_device *template,
2138         char *type)
2139 {
2140         struct video_device *vfd;
2141
2142         dprintk(1, "%s()\n", __func__);
2143         vfd = video_device_alloc();
2144         if (NULL == vfd)
2145                 return NULL;
2146         *vfd = *template;
2147         vfd->minor = -1;
2148         snprintf(vfd->name, sizeof(vfd->name), "%s %s (%s)", dev->name,
2149                 type, cx231xx_boards[dev->model].name);
2150
2151         vfd->v4l2_dev = &dev->v4l2_dev;
2152         vfd->release = video_device_release;
2153
2154         return vfd;
2155
2156 }
2157
2158 int cx231xx_417_register(struct cx231xx *dev)
2159 {
2160         /* FIXME: Port1 hardcoded here */
2161         int err = -ENODEV;
2162         struct cx231xx_tsport *tsport = &dev->ts1;
2163
2164         dprintk(1, "%s()\n", __func__);
2165
2166         /* Set default TV standard */
2167         dev->encodernorm = cx231xx_tvnorms[0];
2168
2169         if (dev->encodernorm.id & V4L2_STD_525_60)
2170                 tsport->height = 480;
2171         else
2172                 tsport->height = 576;
2173
2174         tsport->width = 720;
2175         cx2341x_fill_defaults(&dev->mpeg_params);
2176         dev->norm = V4L2_STD_NTSC;
2177
2178         dev->mpeg_params.port = CX2341X_PORT_SERIAL;
2179
2180         /* Allocate and initialize V4L video device */
2181         dev->v4l_device = cx231xx_video_dev_alloc(dev,
2182                 dev->udev, &cx231xx_mpeg_template, "mpeg");
2183         err = video_register_device(dev->v4l_device,
2184                 VFL_TYPE_GRABBER, -1);
2185         if (err < 0) {
2186                 dprintk(3, "%s: can't register mpeg device\n", dev->name);
2187                 return err;
2188         }
2189
2190         dprintk(3, "%s: registered device video%d [mpeg]\n",
2191                dev->name, dev->v4l_device->num);
2192
2193         return 0;
2194 }