drivers/media/dvb/ngene/ngene-core.c

   1 /*
   2  * ngene.c: nGene PCIe bridge driver
   3  *
   4  * Copyright (C) 2005-2007 Micronas
   5  *
   6  * Copyright (C) 2008-2009 Ralph Metzler <rjkm@metzlerbros.de>
   7  *                         Modifications for new nGene firmware,
   8  *                         support for EEPROM-copying,
   9  *                         support for new dual DVB-S2 card prototype
  10  *
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * version 2 only, as published by the Free Software Foundation.
  15  *
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  26  * 02110-1301, USA
  27  * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
  28  */
  29
  30 #include <linux/module.h>
  31 #include <linux/init.h>
  32 #include <linux/delay.h>
  33 #include <linux/poll.h>
  34 #include <linux/io.h>
  35 #include <asm/div64.h>
  36 #include <linux/pci.h>
  37 #include <linux/smp_lock.h>
  38 #include <linux/timer.h>
  39 #include <linux/byteorder/generic.h>
  40 #include <linux/firmware.h>
  41 #include <linux/vmalloc.h>
  42
  43 #include "ngene.h"
  44
  45 static int one_adapter = 1;
  46 module_param(one_adapter, int, 0444);
  47 MODULE_PARM_DESC(one_adapter, "Use only one adapter.");
  48
  49
  50 static int debug;
  51 module_param(debug, int, 0444);
  52 MODULE_PARM_DESC(debug, "Print debugging information.");
  53
  54 DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  55
  56 #define dprintk if (debug) printk
  57
  58 #define ngwriteb(dat, adr)         writeb((dat), (char *)(dev->iomem + (adr)))
  59 #define ngwritel(dat, adr)         writel((dat), (char *)(dev->iomem + (adr)))
  60 #define ngwriteb(dat, adr)         writeb((dat), (char *)(dev->iomem + (adr)))
  61 #define ngreadl(adr)               readl(dev->iomem + (adr))
  62 #define ngreadb(adr)               readb(dev->iomem + (adr))
  63 #define ngcpyto(adr, src, count)   memcpy_toio((char *) \
  64                                    (dev->iomem + (adr)), (src), (count))
  65 #define ngcpyfrom(dst, adr, count) memcpy_fromio((dst), (char *) \
  66                                    (dev->iomem + (adr)), (count))
  67
  68 /****************************************************************************/
  69 /* nGene interrupt handler **************************************************/
  70 /****************************************************************************/
  71
  72 static void event_tasklet(unsigned long data)
  73 {
  74         struct ngene *dev = (struct ngene *)data;
  75
  76         while (dev->EventQueueReadIndex != dev->EventQueueWriteIndex) {
  77                 struct EVENT_BUFFER Event =
  78                         dev->EventQueue[dev->EventQueueReadIndex];
  79                 dev->EventQueueReadIndex =
  80                         (dev->EventQueueReadIndex + 1) & (EVENT_QUEUE_SIZE - 1);
  81
  82                 if ((Event.UARTStatus & 0x01) && (dev->TxEventNotify))
  83                         dev->TxEventNotify(dev, Event.TimeStamp);
  84                 if ((Event.UARTStatus & 0x02) && (dev->RxEventNotify))
  85                         dev->RxEventNotify(dev, Event.TimeStamp,
  86                                            Event.RXCharacter);
  87         }
  88 }
  89
  90 static void demux_tasklet(unsigned long data)
  91 {
  92         struct ngene_channel *chan = (struct ngene_channel *)data;
  93         struct SBufferHeader *Cur = chan->nextBuffer;
  94
  95         spin_lock_irq(&chan->state_lock);
  96
  97         while (Cur->ngeneBuffer.SR.Flags & 0x80) {
  98                 if (chan->mode & NGENE_IO_TSOUT) {
  99                         u32 Flags = chan->DataFormatFlags;
 100                         if (Cur->ngeneBuffer.SR.Flags & 0x20)
 101                                 Flags |= BEF_OVERFLOW;
 102                         if (chan->pBufferExchange) {
 103                                 if (!chan->pBufferExchange(chan,
 104                                                            Cur->Buffer1,
 105                                                            chan->Capture1Length,
 106                                                            Cur->ngeneBuffer.SR.
 107                                                            Clock, Flags)) {
 108                                         /*
 109                                            We didn't get data
 110                                            Clear in service flag to make sure we
 111                                            get called on next interrupt again.
 112                                            leave fill/empty (0x80) flag alone
 113                                            to avoid hardware running out of
 114                                            buffers during startup, we hold only
 115                                            in run state ( the source may be late
 116                                            delivering data )
 117                                         */
 118
 119                                         if (chan->HWState == HWSTATE_RUN) {
 120                                                 Cur->ngeneBuffer.SR.Flags &=
 121                                                         ~0x40;
 122                                                 break;
 123                                                 /* Stop proccessing stream */
 124                                         }
 125                                 } else {
 126                                         /* We got a valid buffer,
 127                                            so switch to run state */
 128                                         chan->HWState = HWSTATE_RUN;
 129                                 }
 130                         } else {
 131                                 printk(KERN_ERR DEVICE_NAME ": OOPS\n");
 132                                 if (chan->HWState == HWSTATE_RUN) {
 133                                         Cur->ngeneBuffer.SR.Flags &= ~0x40;
 134                                         break;  /* Stop proccessing stream */
 135                                 }
 136                         }
 137                         if (chan->AudioDTOUpdated) {
 138                                 printk(KERN_INFO DEVICE_NAME
 139                                        ": Update AudioDTO = %d\n",
 140                                        chan->AudioDTOValue);
 141                                 Cur->ngeneBuffer.SR.DTOUpdate =
 142                                         chan->AudioDTOValue;
 143                                 chan->AudioDTOUpdated = 0;
 144                         }
 145                 } else {
 146                         if (chan->HWState == HWSTATE_RUN) {
 147                                 u32 Flags = 0;
 148                                 IBufferExchange *exch1 = chan->pBufferExchange;
 149                                 IBufferExchange *exch2 = chan->pBufferExchange2;
 150                                 if (Cur->ngeneBuffer.SR.Flags & 0x01)
 151                                         Flags |= BEF_EVEN_FIELD;
 152                                 if (Cur->ngeneBuffer.SR.Flags & 0x20)
 153                                         Flags |= BEF_OVERFLOW;
 154                                 spin_unlock_irq(&chan->state_lock);
 155                                 if (exch1)
 156                                         exch1(chan, Cur->Buffer1,
 157                                                 chan->Capture1Length,
 158                                                 Cur->ngeneBuffer.SR.Clock,
 159                                                 Flags);
 160                                 if (exch2)
 161                                         exch2(chan, Cur->Buffer2,
 162                                                 chan->Capture2Length,
 163                                                 Cur->ngeneBuffer.SR.Clock,
 164                                                 Flags);
 165                                 spin_lock_irq(&chan->state_lock);
 166                         } else if (chan->HWState != HWSTATE_STOP)
 167                                 chan->HWState = HWSTATE_RUN;
 168                 }
 169                 Cur->ngeneBuffer.SR.Flags = 0x00;
 170                 Cur = Cur->Next;
 171         }
 172         chan->nextBuffer = Cur;
 173
 174         spin_unlock_irq(&chan->state_lock);
 175 }
 176
 177 static irqreturn_t irq_handler(int irq, void *dev_id)
 178 {
 179         struct ngene *dev = (struct ngene *)dev_id;
 180         u32 icounts = 0;
 181         irqreturn_t rc = IRQ_NONE;
 182         u32 i = MAX_STREAM;
 183         u8 *tmpCmdDoneByte;
 184
 185         if (dev->BootFirmware) {
 186                 icounts = ngreadl(NGENE_INT_COUNTS);
 187                 if (icounts != dev->icounts) {
 188                         ngwritel(0, FORCE_NMI);
 189                         dev->cmd_done = 1;
 190                         wake_up(&dev->cmd_wq);
 191                         dev->icounts = icounts;
 192                         rc = IRQ_HANDLED;
 193                 }
 194                 return rc;
 195         }
 196
 197         ngwritel(0, FORCE_NMI);
 198
 199         spin_lock(&dev->cmd_lock);
 200         tmpCmdDoneByte = dev->CmdDoneByte;
 201         if (tmpCmdDoneByte &&
 202             (*tmpCmdDoneByte ||
 203             (dev->ngenetohost[0] == 1 && dev->ngenetohost[1] != 0))) {
 204                 dev->CmdDoneByte = NULL;
 205                 dev->cmd_done = 1;
 206                 wake_up(&dev->cmd_wq);
 207                 rc = IRQ_HANDLED;
 208         }
 209         spin_unlock(&dev->cmd_lock);
 210
 211         if (dev->EventBuffer->EventStatus & 0x80) {
 212                 u8 nextWriteIndex =
 213                         (dev->EventQueueWriteIndex + 1) &
 214                         (EVENT_QUEUE_SIZE - 1);
 215                 if (nextWriteIndex != dev->EventQueueReadIndex) {
 216                         dev->EventQueue[dev->EventQueueWriteIndex] =
 217                                 *(dev->EventBuffer);
 218                         dev->EventQueueWriteIndex = nextWriteIndex;
 219                 } else {
 220                         printk(KERN_ERR DEVICE_NAME ": event overflow\n");
 221                         dev->EventQueueOverflowCount += 1;
 222                         dev->EventQueueOverflowFlag = 1;
 223                 }
 224                 dev->EventBuffer->EventStatus &= ~0x80;
 225                 tasklet_schedule(&dev->event_tasklet);
 226                 rc = IRQ_HANDLED;
 227         }
 228
 229         while (i > 0) {
 230                 i--;
 231                 spin_lock(&dev->channel[i].state_lock);
 232                 /* if (dev->channel[i].State>=KSSTATE_RUN) { */
 233                 if (dev->channel[i].nextBuffer) {
 234                         if ((dev->channel[i].nextBuffer->
 235                              ngeneBuffer.SR.Flags & 0xC0) == 0x80) {
 236                                 dev->channel[i].nextBuffer->
 237                                         ngeneBuffer.SR.Flags |= 0x40;
 238                                 tasklet_schedule(
 239                                         &dev->channel[i].demux_tasklet);
 240                                 rc = IRQ_HANDLED;
 241                         }
 242                 }
 243                 spin_unlock(&dev->channel[i].state_lock);
 244         }
 245
 246         /* Request might have been processed by a previous call. */
 247         return IRQ_HANDLED;
 248 }
 249
 250 /****************************************************************************/
 251 /* nGene command interface **************************************************/
 252 /****************************************************************************/
 253
 254 static void dump_command_io(struct ngene *dev)
 255 {
 256         u8 buf[8], *b;
 257
 258         ngcpyfrom(buf, HOST_TO_NGENE, 8);
 259         printk(KERN_ERR "host_to_ngene (%04x): %02x %02x %02x %02x %02x %02x %02x %02x\n",
 260                 HOST_TO_NGENE, buf[0], buf[1], buf[2], buf[3],
 261                 buf[4], buf[5], buf[6], buf[7]);
 262
 263         ngcpyfrom(buf, NGENE_TO_HOST, 8);
 264         printk(KERN_ERR "ngene_to_host (%04x): %02x %02x %02x %02x %02x %02x %02x %02x\n",
 265                 NGENE_TO_HOST, buf[0], buf[1], buf[2], buf[3],
 266                 buf[4], buf[5], buf[6], buf[7]);
 267
 268         b = dev->hosttongene;
 269         printk(KERN_ERR "dev->hosttongene (%p): %02x %02x %02x %02x %02x %02x %02x %02x\n",
 270                 b, b[0], b[1], b[2], b[3], b[4], b[5], b[6], b[7]);
 271
 272         b = dev->ngenetohost;
 273         printk(KERN_ERR "dev->ngenetohost (%p): %02x %02x %02x %02x %02x %02x %02x %02x\n",
 274                 b, b[0], b[1], b[2], b[3], b[4], b[5], b[6], b[7]);
 275 }
 276
 277 static int ngene_command_mutex(struct ngene *dev, struct ngene_command *com)
 278 {
 279         int ret;
 280         u8 *tmpCmdDoneByte;
 281
 282         dev->cmd_done = 0;
 283
 284         if (com->cmd.hdr.Opcode == CMD_FWLOAD_PREPARE) {
 285                 dev->BootFirmware = 1;
 286                 dev->icounts = ngreadl(NGENE_INT_COUNTS);
 287                 ngwritel(0, NGENE_COMMAND);
 288                 ngwritel(0, NGENE_COMMAND_HI);
 289                 ngwritel(0, NGENE_STATUS);
 290                 ngwritel(0, NGENE_STATUS_HI);
 291                 ngwritel(0, NGENE_EVENT);
 292                 ngwritel(0, NGENE_EVENT_HI);
 293         } else if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH) {
 294                 u64 fwio = dev->PAFWInterfaceBuffer;
 295
 296                 ngwritel(fwio & 0xffffffff, NGENE_COMMAND);
 297                 ngwritel(fwio >> 32, NGENE_COMMAND_HI);
 298                 ngwritel((fwio + 256) & 0xffffffff, NGENE_STATUS);
 299                 ngwritel((fwio + 256) >> 32, NGENE_STATUS_HI);
 300                 ngwritel((fwio + 512) & 0xffffffff, NGENE_EVENT);
 301                 ngwritel((fwio + 512) >> 32, NGENE_EVENT_HI);
 302         }
 303
 304         memcpy(dev->FWInterfaceBuffer, com->cmd.raw8, com->in_len + 2);
 305
 306         if (dev->BootFirmware)
 307                 ngcpyto(HOST_TO_NGENE, com->cmd.raw8, com->in_len + 2);
 308
 309         spin_lock_irq(&dev->cmd_lock);
 310         tmpCmdDoneByte = dev->ngenetohost + com->out_len;
 311         if (!com->out_len)
 312                 tmpCmdDoneByte++;
 313         *tmpCmdDoneByte = 0;
 314         dev->ngenetohost[0] = 0;
 315         dev->ngenetohost[1] = 0;
 316         dev->CmdDoneByte = tmpCmdDoneByte;
 317         spin_unlock_irq(&dev->cmd_lock);
 318
 319         /* Notify 8051. */
 320         ngwritel(1, FORCE_INT);
 321
 322         ret = wait_event_timeout(dev->cmd_wq, dev->cmd_done == 1, 2 * HZ);
 323         if (!ret) {
 324                 /*ngwritel(0, FORCE_NMI);*/
 325
 326                 printk(KERN_ERR DEVICE_NAME
 327                        ": Command timeout cmd=%02x prev=%02x\n",
 328                        com->cmd.hdr.Opcode, dev->prev_cmd);
 329                 dump_command_io(dev);
 330                 return -1;
 331         }
 332         if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH)
 333                 dev->BootFirmware = 0;
 334
 335         dev->prev_cmd = com->cmd.hdr.Opcode;
 336
 337         if (!com->out_len)
 338                 return 0;
 339
 340         memcpy(com->cmd.raw8, dev->ngenetohost, com->out_len);
 341
 342         return 0;
 343 }
 344
 345 int ngene_command(struct ngene *dev, struct ngene_command *com)
 346 {
 347         int result;
 348
 349         down(&dev->cmd_mutex);
 350         result = ngene_command_mutex(dev, com);
 351         up(&dev->cmd_mutex);
 352         return result;
 353 }
 354
 355
 356 static int ngene_command_load_firmware(struct ngene *dev,
 357                                        u8 *ngene_fw, u32 size)
 358 {
 359 #define FIRSTCHUNK (1024)
 360         u32 cleft;
 361         struct ngene_command com;
 362
 363         com.cmd.hdr.Opcode = CMD_FWLOAD_PREPARE;
 364         com.cmd.hdr.Length = 0;
 365         com.in_len = 0;
 366         com.out_len = 0;
 367
 368         ngene_command(dev, &com);
 369
 370         cleft = (size + 3) & ~3;
 371         if (cleft > FIRSTCHUNK) {
 372                 ngcpyto(PROGRAM_SRAM + FIRSTCHUNK, ngene_fw + FIRSTCHUNK,
 373                         cleft - FIRSTCHUNK);
 374                 cleft = FIRSTCHUNK;
 375         }
 376         ngcpyto(DATA_FIFO_AREA, ngene_fw, cleft);
 377
 378         memset(&com, 0, sizeof(struct ngene_command));
 379         com.cmd.hdr.Opcode = CMD_FWLOAD_FINISH;
 380         com.cmd.hdr.Length = 4;
 381         com.cmd.FWLoadFinish.Address = DATA_FIFO_AREA;
 382         com.cmd.FWLoadFinish.Length = (unsigned short)cleft;
 383         com.in_len = 4;
 384         com.out_len = 0;
 385
 386         return ngene_command(dev, &com);
 387 }
 388
 389
 390 static int ngene_command_config_buf(struct ngene *dev, u8 config)
 391 {
 392         struct ngene_command com;
 393
 394         com.cmd.hdr.Opcode = CMD_CONFIGURE_BUFFER;
 395         com.cmd.hdr.Length = 1;
 396         com.cmd.ConfigureBuffers.config = config;
 397         com.in_len = 1;
 398         com.out_len = 0;
 399
 400         if (ngene_command(dev, &com) < 0)
 401                 return -EIO;
 402         return 0;
 403 }
 404
 405 static int ngene_command_config_free_buf(struct ngene *dev, u8 *config)
 406 {
 407         struct ngene_command com;
 408
 409         com.cmd.hdr.Opcode = CMD_CONFIGURE_FREE_BUFFER;
 410         com.cmd.hdr.Length = 6;
 411         memcpy(&com.cmd.ConfigureBuffers.config, config, 6);
 412         com.in_len = 6;
 413         com.out_len = 0;
 414
 415         if (ngene_command(dev, &com) < 0)
 416                 return -EIO;
 417
 418         return 0;
 419 }
 420
 421 int ngene_command_gpio_set(struct ngene *dev, u8 select, u8 level)
 422 {
 423         struct ngene_command com;
 424
 425         com.cmd.hdr.Opcode = CMD_SET_GPIO_PIN;
 426         com.cmd.hdr.Length = 1;
 427         com.cmd.SetGpioPin.select = select | (level << 7);
 428         com.in_len = 1;
 429         com.out_len = 0;
 430
 431         return ngene_command(dev, &com);
 432 }
 433
 434
 435 /*
 436  02000640 is sample on rising edge.
 437  02000740 is sample on falling edge.
 438  02000040 is ignore "valid" signal
 439
 440  0: FD_CTL1 Bit 7,6 must be 0,1
 441     7   disable(fw controlled)
 442     6   0-AUX,1-TS
 443     5   0-par,1-ser
 444     4   0-lsb/1-msb
 445     3,2 reserved
 446     1,0 0-no sync, 1-use ext. start, 2-use 0x47, 3-both
 447  1: FD_CTL2 has 3-valid must be hi, 2-use valid, 1-edge
 448  2: FD_STA is read-only. 0-sync
 449  3: FD_INSYNC is number of 47s to trigger "in sync".
 450  4: FD_OUTSYNC is number of 47s to trigger "out of sync".
 451  5: FD_MAXBYTE1 is low-order of bytes per packet.
 452  6: FD_MAXBYTE2 is high-order of bytes per packet.
 453  7: Top byte is unused.
 454 */
 455
 456 /****************************************************************************/
 457
 458 static u8 TSFeatureDecoderSetup[8 * 5] = {
 459         0x42, 0x00, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00,
 460         0x40, 0x06, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXH */
 461         0x71, 0x07, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXHser */
 462         0x72, 0x06, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* S2ser */
 463         0x40, 0x07, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* LGDT3303 */
 464 };
 465
 466 /* Set NGENE I2S Config to 16 bit packed */
 467 static u8 I2SConfiguration[] = {
 468         0x00, 0x10, 0x00, 0x00,
 469         0x80, 0x10, 0x00, 0x00,
 470 };
 471
 472 static u8 SPDIFConfiguration[10] = {
 473         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
 474 };
 475
 476 /* Set NGENE I2S Config to transport stream compatible mode */
 477
 478 static u8 TS_I2SConfiguration[4] = { 0x3E, 0x1A, 0x00, 0x00 }; /*3e 18 00 00 ?*/
 479
 480 static u8 TS_I2SOutConfiguration[4] = { 0x80, 0x20, 0x00, 0x00 };
 481
 482 static u8 ITUDecoderSetup[4][16] = {
 483         {0x1c, 0x13, 0x01, 0x68, 0x3d, 0x90, 0x14, 0x20,  /* SDTV */
 484          0x00, 0x00, 0x01, 0xb0, 0x9c, 0x00, 0x00, 0x00},
 485         {0x9c, 0x03, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00,
 486          0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
 487         {0x9f, 0x00, 0x23, 0xC0, 0x60, 0x0F, 0x13, 0x00,  /* HDTV 1080i50 */
 488          0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
 489         {0x9c, 0x01, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00,  /* HDTV 1080i60 */
 490          0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
 491 };
 492
 493 /*
 494  * 50 48 60 gleich
 495  * 27p50 9f 00 22 80 42 69 18 ...
 496  * 27p60 93 00 22 80 82 69 1c ...
 497  */
 498
 499 /* Maxbyte to 1144 (for raw data) */
 500 static u8 ITUFeatureDecoderSetup[8] = {
 501         0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x04, 0x00
 502 };
 503
 504 void FillTSBuffer(void *Buffer, int Length, u32 Flags)
 505 {
 506         u32 *ptr = Buffer;
 507
 508         memset(Buffer, 0xff, Length);
 509         while (Length > 0) {
 510                 if (Flags & DF_SWAP32)
 511                         *ptr = 0x471FFF10;
 512                 else
 513                         *ptr = 0x10FF1F47;
 514                 ptr += (188 / 4);
 515                 Length -= 188;
 516         }
 517 }
 518
 519
 520 static void flush_buffers(struct ngene_channel *chan)
 521 {
 522         u8 val;
 523
 524         do {
 525                 msleep(1);
 526                 spin_lock_irq(&chan->state_lock);
 527                 val = chan->nextBuffer->ngeneBuffer.SR.Flags & 0x80;
 528                 spin_unlock_irq(&chan->state_lock);
 529         } while (val);
 530 }
 531
 532 static void clear_buffers(struct ngene_channel *chan)
 533 {
 534         struct SBufferHeader *Cur = chan->nextBuffer;
 535
 536         do {
 537                 memset(&Cur->ngeneBuffer.SR, 0, sizeof(Cur->ngeneBuffer.SR));
 538                 if (chan->mode & NGENE_IO_TSOUT)
 539                         FillTSBuffer(Cur->Buffer1,
 540                                      chan->Capture1Length,
 541                                      chan->DataFormatFlags);
 542                 Cur = Cur->Next;
 543         } while (Cur != chan->nextBuffer);
 544
 545         if (chan->mode & NGENE_IO_TSOUT) {
 546                 chan->nextBuffer->ngeneBuffer.SR.DTOUpdate =
 547                         chan->AudioDTOValue;
 548                 chan->AudioDTOUpdated = 0;
 549
 550                 Cur = chan->TSIdleBuffer.Head;
 551
 552                 do {
 553                         memset(&Cur->ngeneBuffer.SR, 0,
 554                                sizeof(Cur->ngeneBuffer.SR));
 555                         FillTSBuffer(Cur->Buffer1,
 556                                      chan->Capture1Length,
 557                                      chan->DataFormatFlags);
 558                         Cur = Cur->Next;
 559                 } while (Cur != chan->TSIdleBuffer.Head);
 560         }
 561 }
 562
 563 static int ngene_command_stream_control(struct ngene *dev, u8 stream,
 564                                         u8 control, u8 mode, u8 flags)
 565 {
 566         struct ngene_channel *chan = &dev->channel[stream];
 567         struct ngene_command com;
 568         u16 BsUVI = ((stream & 1) ? 0x9400 : 0x9300);
 569         u16 BsSDI = ((stream & 1) ? 0x9600 : 0x9500);
 570         u16 BsSPI = ((stream & 1) ? 0x9800 : 0x9700);
 571         u16 BsSDO = 0x9B00;
 572
 573         down(&dev->stream_mutex);
 574         memset(&com, 0, sizeof(com));
 575         com.cmd.hdr.Opcode = CMD_CONTROL;
 576         com.cmd.hdr.Length = sizeof(struct FW_STREAM_CONTROL) - 2;
 577         com.cmd.StreamControl.Stream = stream | (control ? 8 : 0);
 578         if (chan->mode & NGENE_IO_TSOUT)
 579                 com.cmd.StreamControl.Stream |= 0x07;
 580         com.cmd.StreamControl.Control = control |
 581                 (flags & SFLAG_ORDER_LUMA_CHROMA);
 582         com.cmd.StreamControl.Mode = mode;
 583         com.in_len = sizeof(struct FW_STREAM_CONTROL);
 584         com.out_len = 0;
 585
 586         dprintk(KERN_INFO DEVICE_NAME
 587                 ": Stream=%02x, Control=%02x, Mode=%02x\n",
 588                 com.cmd.StreamControl.Stream, com.cmd.StreamControl.Control,
 589                 com.cmd.StreamControl.Mode);
 590
 591         chan->Mode = mode;
 592
 593         if (!(control & 0x80)) {
 594                 spin_lock_irq(&chan->state_lock);
 595                 if (chan->State == KSSTATE_RUN) {
 596                         chan->State = KSSTATE_ACQUIRE;
 597                         chan->HWState = HWSTATE_STOP;
 598                         spin_unlock_irq(&chan->state_lock);
 599                         if (ngene_command(dev, &com) < 0) {
 600                                 up(&dev->stream_mutex);
 601                                 return -1;
 602                         }
 603                         /* clear_buffers(chan); */
 604                         flush_buffers(chan);
 605                         up(&dev->stream_mutex);
 606                         return 0;
 607                 }
 608                 spin_unlock_irq(&chan->state_lock);
 609                 up(&dev->stream_mutex);
 610                 return 0;
 611         }
 612
 613         if (mode & SMODE_AUDIO_CAPTURE) {
 614                 com.cmd.StreamControl.CaptureBlockCount =
 615                         chan->Capture1Length / AUDIO_BLOCK_SIZE;
 616                 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead;
 617         } else if (mode & SMODE_TRANSPORT_STREAM) {
 618                 com.cmd.StreamControl.CaptureBlockCount =
 619                         chan->Capture1Length / TS_BLOCK_SIZE;
 620                 com.cmd.StreamControl.MaxLinesPerField =
 621                         chan->Capture1Length / TS_BLOCK_SIZE;
 622                 com.cmd.StreamControl.Buffer_Address =
 623                         chan->TSRingBuffer.PAHead;
 624                 if (chan->mode & NGENE_IO_TSOUT) {
 625                         com.cmd.StreamControl.BytesPerVBILine =
 626                                 chan->Capture1Length / TS_BLOCK_SIZE;
 627                         com.cmd.StreamControl.Stream |= 0x07;
 628                 }
 629         } else {
 630                 com.cmd.StreamControl.BytesPerVideoLine = chan->nBytesPerLine;
 631                 com.cmd.StreamControl.MaxLinesPerField = chan->nLines;
 632                 com.cmd.StreamControl.MinLinesPerField = 100;
 633                 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead;
 634
 635                 if (mode & SMODE_VBI_CAPTURE) {
 636                         com.cmd.StreamControl.MaxVBILinesPerField =
 637                                 chan->nVBILines;
 638                         com.cmd.StreamControl.MinVBILinesPerField = 0;
 639                         com.cmd.StreamControl.BytesPerVBILine =
 640                                 chan->nBytesPerVBILine;
 641                 }
 642                 if (flags & SFLAG_COLORBAR)
 643                         com.cmd.StreamControl.Stream |= 0x04;
 644         }
 645
 646         spin_lock_irq(&chan->state_lock);
 647         if (mode & SMODE_AUDIO_CAPTURE) {
 648                 chan->nextBuffer = chan->RingBuffer.Head;
 649                 if (mode & SMODE_AUDIO_SPDIF) {
 650                         com.cmd.StreamControl.SetupDataLen =
 651                                 sizeof(SPDIFConfiguration);
 652                         com.cmd.StreamControl.SetupDataAddr = BsSPI;
 653                         memcpy(com.cmd.StreamControl.SetupData,
 654                                SPDIFConfiguration, sizeof(SPDIFConfiguration));
 655                 } else {
 656                         com.cmd.StreamControl.SetupDataLen = 4;
 657                         com.cmd.StreamControl.SetupDataAddr = BsSDI;
 658                         memcpy(com.cmd.StreamControl.SetupData,
 659                                I2SConfiguration +
 660                                4 * dev->card_info->i2s[stream], 4);
 661                 }
 662         } else if (mode & SMODE_TRANSPORT_STREAM) {
 663                 chan->nextBuffer = chan->TSRingBuffer.Head;
 664                 if (stream >= STREAM_AUDIOIN1) {
 665                         if (chan->mode & NGENE_IO_TSOUT) {
 666                                 com.cmd.StreamControl.SetupDataLen =
 667                                         sizeof(TS_I2SOutConfiguration);
 668                                 com.cmd.StreamControl.SetupDataAddr = BsSDO;
 669                                 memcpy(com.cmd.StreamControl.SetupData,
 670                                        TS_I2SOutConfiguration,
 671                                        sizeof(TS_I2SOutConfiguration));
 672                         } else {
 673                                 com.cmd.StreamControl.SetupDataLen =
 674                                         sizeof(TS_I2SConfiguration);
 675                                 com.cmd.StreamControl.SetupDataAddr = BsSDI;
 676                                 memcpy(com.cmd.StreamControl.SetupData,
 677                                        TS_I2SConfiguration,
 678                                        sizeof(TS_I2SConfiguration));
 679                         }
 680                 } else {
 681                         com.cmd.StreamControl.SetupDataLen = 8;
 682                         com.cmd.StreamControl.SetupDataAddr = BsUVI + 0x10;
 683                         memcpy(com.cmd.StreamControl.SetupData,
 684                                TSFeatureDecoderSetup +
 685                                8 * dev->card_info->tsf[stream], 8);
 686                 }
 687         } else {
 688                 chan->nextBuffer = chan->RingBuffer.Head;
 689                 com.cmd.StreamControl.SetupDataLen =
 690                         16 + sizeof(ITUFeatureDecoderSetup);
 691                 com.cmd.StreamControl.SetupDataAddr = BsUVI;
 692                 memcpy(com.cmd.StreamControl.SetupData,
 693                        ITUDecoderSetup[chan->itumode], 16);
 694                 memcpy(com.cmd.StreamControl.SetupData + 16,
 695                        ITUFeatureDecoderSetup, sizeof(ITUFeatureDecoderSetup));
 696         }
 697         clear_buffers(chan);
 698         chan->State = KSSTATE_RUN;
 699         if (mode & SMODE_TRANSPORT_STREAM)
 700                 chan->HWState = HWSTATE_RUN;
 701         else
 702                 chan->HWState = HWSTATE_STARTUP;
 703         spin_unlock_irq(&chan->state_lock);
 704
 705         if (ngene_command(dev, &com) < 0) {
 706                 up(&dev->stream_mutex);
 707                 return -1;
 708         }
 709         up(&dev->stream_mutex);
 710         return 0;
 711 }
 712
 713 void set_transfer(struct ngene_channel *chan, int state)
 714 {
 715         u8 control = 0, mode = 0, flags = 0;
 716         struct ngene *dev = chan->dev;
 717         int ret;
 718
 719         /*
 720         printk(KERN_INFO DEVICE_NAME ": st %d\n", state);
 721         msleep(100);
 722         */
 723
 724         if (state) {
 725                 if (chan->running) {
 726                         printk(KERN_INFO DEVICE_NAME ": already running\n");
 727                         return;
 728                 }
 729         } else {
 730                 if (!chan->running) {
 731                         printk(KERN_INFO DEVICE_NAME ": already stopped\n");
 732                         return;
 733                 }
 734         }
 735
 736         if (dev->card_info->switch_ctrl)
 737                 dev->card_info->switch_ctrl(chan, 1, state ^ 1);
 738
 739         if (state) {
 740                 spin_lock_irq(&chan->state_lock);
 741
 742                 /* printk(KERN_INFO DEVICE_NAME ": lock=%08x\n",
 743                           ngreadl(0x9310)); */
 744                 dvb_ringbuffer_flush(&dev->tsout_rbuf);
 745                 control = 0x80;
 746                 if (chan->mode & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
 747                         chan->Capture1Length = 512 * 188;
 748                         mode = SMODE_TRANSPORT_STREAM;
 749                 }
 750                 if (chan->mode & NGENE_IO_TSOUT) {
 751                         chan->pBufferExchange = tsout_exchange;
 752                         /* 0x66666666 = 50MHz *2^33 /250MHz */
 753                         chan->AudioDTOValue = 0x66666666;
 754                         /* set_dto(chan, 38810700+1000); */
 755                         /* set_dto(chan, 19392658); */
 756                 }
 757                 if (chan->mode & NGENE_IO_TSIN)
 758                         chan->pBufferExchange = tsin_exchange;
 759                 /* ngwritel(0, 0x9310); */
 760                 spin_unlock_irq(&chan->state_lock);
 761         } else
 762                 ;/* printk(KERN_INFO DEVICE_NAME ": lock=%08x\n",
 763                            ngreadl(0x9310)); */
 764
 765         ret = ngene_command_stream_control(dev, chan->number,
 766                                            control, mode, flags);
 767         if (!ret)
 768                 chan->running = state;
 769         else
 770                 printk(KERN_ERR DEVICE_NAME ": set_transfer %d failed\n",
 771                        state);
 772         if (!state) {
 773                 spin_lock_irq(&chan->state_lock);
 774                 chan->pBufferExchange = NULL;
 775                 dvb_ringbuffer_flush(&dev->tsout_rbuf);
 776                 spin_unlock_irq(&chan->state_lock);
 777         }
 778 }
 779
 780
 781 /****************************************************************************/
 782 /* nGene hardware init and release functions ********************************/
 783 /****************************************************************************/
 784
 785 static void free_ringbuffer(struct ngene *dev, struct SRingBufferDescriptor *rb)
 786 {
 787         struct SBufferHeader *Cur = rb->Head;
 788         u32 j;
 789
 790         if (!Cur)
 791                 return;
 792
 793         for (j = 0; j < rb->NumBuffers; j++, Cur = Cur->Next) {
 794                 if (Cur->Buffer1)
 795                         pci_free_consistent(dev->pci_dev,
 796                                             rb->Buffer1Length,
 797                                             Cur->Buffer1,
 798                                             Cur->scList1->Address);
 799
 800                 if (Cur->Buffer2)
 801                         pci_free_consistent(dev->pci_dev,
 802                                             rb->Buffer2Length,
 803                                             Cur->Buffer2,
 804                                             Cur->scList2->Address);
 805         }
 806
 807         if (rb->SCListMem)
 808                 pci_free_consistent(dev->pci_dev, rb->SCListMemSize,
 809                                     rb->SCListMem, rb->PASCListMem);
 810
 811         pci_free_consistent(dev->pci_dev, rb->MemSize, rb->Head, rb->PAHead);
 812 }
 813
 814 static void free_idlebuffer(struct ngene *dev,
 815                      struct SRingBufferDescriptor *rb,
 816                      struct SRingBufferDescriptor *tb)
 817 {
 818         int j;
 819         struct SBufferHeader *Cur = tb->Head;
 820
 821         if (!rb->Head)
 822                 return;
 823         free_ringbuffer(dev, rb);
 824         for (j = 0; j < tb->NumBuffers; j++, Cur = Cur->Next) {
 825                 Cur->Buffer2 = NULL;
 826                 Cur->scList2 = NULL;
 827                 Cur->ngeneBuffer.Address_of_first_entry_2 = 0;
 828                 Cur->ngeneBuffer.Number_of_entries_2 = 0;
 829         }
 830 }
 831
 832 static void free_common_buffers(struct ngene *dev)
 833 {
 834         u32 i;
 835         struct ngene_channel *chan;
 836
 837         for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) {
 838                 chan = &dev->channel[i];
 839                 free_idlebuffer(dev, &chan->TSIdleBuffer, &chan->TSRingBuffer);
 840                 free_ringbuffer(dev, &chan->RingBuffer);
 841                 free_ringbuffer(dev, &chan->TSRingBuffer);
 842         }
 843
 844         if (dev->OverflowBuffer)
 845                 pci_free_consistent(dev->pci_dev,
 846                                     OVERFLOW_BUFFER_SIZE,
 847                                     dev->OverflowBuffer, dev->PAOverflowBuffer);
 848
 849         if (dev->FWInterfaceBuffer)
 850                 pci_free_consistent(dev->pci_dev,
 851                                     4096,
 852                                     dev->FWInterfaceBuffer,
 853                                     dev->PAFWInterfaceBuffer);
 854 }
 855
 856 /****************************************************************************/
 857 /* Ring buffer handling *****************************************************/
 858 /****************************************************************************/
 859
 860 static int create_ring_buffer(struct pci_dev *pci_dev,
 861                        struct SRingBufferDescriptor *descr, u32 NumBuffers)
 862 {
 863         dma_addr_t tmp;
 864         struct SBufferHeader *Head;
 865         u32 i;
 866         u32 MemSize = SIZEOF_SBufferHeader * NumBuffers;
 867         u64 PARingBufferHead;
 868         u64 PARingBufferCur;
 869         u64 PARingBufferNext;
 870         struct SBufferHeader *Cur, *Next;
 871
 872         descr->Head = NULL;
 873         descr->MemSize = 0;
 874         descr->PAHead = 0;
 875         descr->NumBuffers = 0;
 876
 877         if (MemSize < 4096)
 878                 MemSize = 4096;
 879
 880         Head = pci_alloc_consistent(pci_dev, MemSize, &tmp);
 881         PARingBufferHead = tmp;
 882
 883         if (!Head)
 884                 return -ENOMEM;
 885
 886         memset(Head, 0, MemSize);
 887
 888         PARingBufferCur = PARingBufferHead;
 889         Cur = Head;
 890
 891         for (i = 0; i < NumBuffers - 1; i++) {
 892                 Next = (struct SBufferHeader *)
 893                         (((u8 *) Cur) + SIZEOF_SBufferHeader);
 894                 PARingBufferNext = PARingBufferCur + SIZEOF_SBufferHeader;
 895                 Cur->Next = Next;
 896                 Cur->ngeneBuffer.Next = PARingBufferNext;
 897                 Cur = Next;
 898                 PARingBufferCur = PARingBufferNext;
 899         }
 900         /* Last Buffer points back to first one */
 901         Cur->Next = Head;
 902         Cur->ngeneBuffer.Next = PARingBufferHead;
 903
 904         descr->Head       = Head;
 905         descr->MemSize    = MemSize;
 906         descr->PAHead     = PARingBufferHead;
 907         descr->NumBuffers = NumBuffers;
 908
 909         return 0;
 910 }
 911
 912 static int AllocateRingBuffers(struct pci_dev *pci_dev,
 913                                dma_addr_t of,
 914                                struct SRingBufferDescriptor *pRingBuffer,
 915                                u32 Buffer1Length, u32 Buffer2Length)
 916 {
 917         dma_addr_t tmp;
 918         u32 i, j;
 919         int status = 0;
 920         u32 SCListMemSize = pRingBuffer->NumBuffers
 921                 * ((Buffer2Length != 0) ? (NUM_SCATTER_GATHER_ENTRIES * 2) :
 922                     NUM_SCATTER_GATHER_ENTRIES)
 923                 * sizeof(struct HW_SCATTER_GATHER_ELEMENT);
 924
 925         u64 PASCListMem;
 926         struct HW_SCATTER_GATHER_ELEMENT *SCListEntry;
 927         u64 PASCListEntry;
 928         struct SBufferHeader *Cur;
 929         void *SCListMem;
 930
 931         if (SCListMemSize < 4096)
 932                 SCListMemSize = 4096;
 933
 934         SCListMem = pci_alloc_consistent(pci_dev, SCListMemSize, &tmp);
 935
 936         PASCListMem = tmp;
 937         if (SCListMem == NULL)
 938                 return -ENOMEM;
 939
 940         memset(SCListMem, 0, SCListMemSize);
 941
 942         pRingBuffer->SCListMem = SCListMem;
 943         pRingBuffer->PASCListMem = PASCListMem;
 944         pRingBuffer->SCListMemSize = SCListMemSize;
 945         pRingBuffer->Buffer1Length = Buffer1Length;
 946         pRingBuffer->Buffer2Length = Buffer2Length;
 947
 948         SCListEntry = SCListMem;
 949         PASCListEntry = PASCListMem;
 950         Cur = pRingBuffer->Head;
 951
 952         for (i = 0; i < pRingBuffer->NumBuffers; i += 1, Cur = Cur->Next) {
 953                 u64 PABuffer;
 954
 955                 void *Buffer = pci_alloc_consistent(pci_dev, Buffer1Length,
 956                                                     &tmp);
 957                 PABuffer = tmp;
 958
 959                 if (Buffer == NULL)
 960                         return -ENOMEM;
 961
 962                 Cur->Buffer1 = Buffer;
 963
 964                 SCListEntry->Address = PABuffer;
 965                 SCListEntry->Length  = Buffer1Length;
 966
 967                 Cur->scList1 = SCListEntry;
 968                 Cur->ngeneBuffer.Address_of_first_entry_1 = PASCListEntry;
 969                 Cur->ngeneBuffer.Number_of_entries_1 =
 970                         NUM_SCATTER_GATHER_ENTRIES;
 971
 972                 SCListEntry += 1;
 973                 PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT);
 974
 975 #if NUM_SCATTER_GATHER_ENTRIES > 1
 976                 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j += 1) {
 977                         SCListEntry->Address = of;
 978                         SCListEntry->Length = OVERFLOW_BUFFER_SIZE;
 979                         SCListEntry += 1;
 980                         PASCListEntry +=
 981                                 sizeof(struct HW_SCATTER_GATHER_ELEMENT);
 982                 }
 983 #endif
 984
 985                 if (!Buffer2Length)
 986                         continue;
 987
 988                 Buffer = pci_alloc_consistent(pci_dev, Buffer2Length, &tmp);
 989                 PABuffer = tmp;
 990
 991                 if (Buffer == NULL)
 992                         return -ENOMEM;
 993
 994                 Cur->Buffer2 = Buffer;
 995
 996                 SCListEntry->Address = PABuffer;
 997                 SCListEntry->Length  = Buffer2Length;
 998
 999                 Cur->scList2 = SCListEntry;
1000                 Cur->ngeneBuffer.Address_of_first_entry_2 = PASCListEntry;
1001                 Cur->ngeneBuffer.Number_of_entries_2 =
1002                         NUM_SCATTER_GATHER_ENTRIES;
1003
1004                 SCListEntry   += 1;
1005                 PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1006
1007 #if NUM_SCATTER_GATHER_ENTRIES > 1
1008                 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j++) {
1009                         SCListEntry->Address = of;
1010                         SCListEntry->Length = OVERFLOW_BUFFER_SIZE;
1011                         SCListEntry += 1;
1012                         PASCListEntry +=
1013                                 sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1014                 }
1015 #endif
1016
1017         }
1018
1019         return status;
1020 }
1021
1022 static int FillTSIdleBuffer(struct SRingBufferDescriptor *pIdleBuffer,
1023                             struct SRingBufferDescriptor *pRingBuffer)
1024 {
1025         int status = 0;
1026
1027         /* Copy pointer to scatter gather list in TSRingbuffer
1028            structure for buffer 2
1029            Load number of buffer
1030         */
1031         u32 n = pRingBuffer->NumBuffers;
1032
1033         /* Point to first buffer entry */
1034         struct SBufferHeader *Cur = pRingBuffer->Head;
1035         int i;
1036         /* Loop thru all buffer and set Buffer 2 pointers to TSIdlebuffer */
1037         for (i = 0; i < n; i++) {
1038                 Cur->Buffer2 = pIdleBuffer->Head->Buffer1;
1039                 Cur->scList2 = pIdleBuffer->Head->scList1;
1040                 Cur->ngeneBuffer.Address_of_first_entry_2 =
1041                         pIdleBuffer->Head->ngeneBuffer.
1042                         Address_of_first_entry_1;
1043                 Cur->ngeneBuffer.Number_of_entries_2 =
1044                         pIdleBuffer->Head->ngeneBuffer.Number_of_entries_1;
1045                 Cur = Cur->Next;
1046         }
1047         return status;
1048 }
1049
1050 static u32 RingBufferSizes[MAX_STREAM] = {
1051         RING_SIZE_VIDEO,
1052         RING_SIZE_VIDEO,
1053         RING_SIZE_AUDIO,
1054         RING_SIZE_AUDIO,
1055         RING_SIZE_AUDIO,
1056 };
1057
1058 static u32 Buffer1Sizes[MAX_STREAM] = {
1059         MAX_VIDEO_BUFFER_SIZE,
1060         MAX_VIDEO_BUFFER_SIZE,
1061         MAX_AUDIO_BUFFER_SIZE,
1062         MAX_AUDIO_BUFFER_SIZE,
1063         MAX_AUDIO_BUFFER_SIZE
1064 };
1065
1066 static u32 Buffer2Sizes[MAX_STREAM] = {
1067         MAX_VBI_BUFFER_SIZE,
1068         MAX_VBI_BUFFER_SIZE,
1069         0,
1070         0,
1071         0
1072 };
1073
1074
1075 static int AllocCommonBuffers(struct ngene *dev)
1076 {
1077         int status = 0, i;
1078
1079         dev->FWInterfaceBuffer = pci_alloc_consistent(dev->pci_dev, 4096,
1080                                                      &dev->PAFWInterfaceBuffer);
1081         if (!dev->FWInterfaceBuffer)
1082                 return -ENOMEM;
1083         dev->hosttongene = dev->FWInterfaceBuffer;
1084         dev->ngenetohost = dev->FWInterfaceBuffer + 256;
1085         dev->EventBuffer = dev->FWInterfaceBuffer + 512;
1086
1087         dev->OverflowBuffer = pci_alloc_consistent(dev->pci_dev,
1088                                                    OVERFLOW_BUFFER_SIZE,
1089                                                    &dev->PAOverflowBuffer);
1090         if (!dev->OverflowBuffer)
1091                 return -ENOMEM;
1092         memset(dev->OverflowBuffer, 0, OVERFLOW_BUFFER_SIZE);
1093
1094         for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) {
1095                 int type = dev->card_info->io_type[i];
1096
1097                 dev->channel[i].State = KSSTATE_STOP;
1098
1099                 if (type & (NGENE_IO_TV | NGENE_IO_HDTV | NGENE_IO_AIN)) {
1100                         status = create_ring_buffer(dev->pci_dev,
1101                                                     &dev->channel[i].RingBuffer,
1102                                                     RingBufferSizes[i]);
1103                         if (status < 0)
1104                                 break;
1105
1106                         if (type & (NGENE_IO_TV | NGENE_IO_AIN)) {
1107                                 status = AllocateRingBuffers(dev->pci_dev,
1108                                                              dev->
1109                                                              PAOverflowBuffer,
1110                                                              &dev->channel[i].
1111                                                              RingBuffer,
1112                                                              Buffer1Sizes[i],
1113                                                              Buffer2Sizes[i]);
1114                                 if (status < 0)
1115                                         break;
1116                         } else if (type & NGENE_IO_HDTV) {
1117                                 status = AllocateRingBuffers(dev->pci_dev,
1118                                                              dev->
1119                                                              PAOverflowBuffer,
1120                                                              &dev->channel[i].
1121                                                              RingBuffer,
1122                                                            MAX_HDTV_BUFFER_SIZE,
1123                                                              0);
1124                                 if (status < 0)
1125                                         break;
1126                         }
1127                 }
1128
1129                 if (type & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
1130
1131                         status = create_ring_buffer(dev->pci_dev,
1132                                                     &dev->channel[i].
1133                                                     TSRingBuffer, RING_SIZE_TS);
1134                         if (status < 0)
1135                                 break;
1136
1137                         status = AllocateRingBuffers(dev->pci_dev,
1138                                                      dev->PAOverflowBuffer,
1139                                                      &dev->channel[i].
1140                                                      TSRingBuffer,
1141                                                      MAX_TS_BUFFER_SIZE, 0);
1142                         if (status)
1143                                 break;
1144                 }
1145
1146                 if (type & NGENE_IO_TSOUT) {
1147                         status = create_ring_buffer(dev->pci_dev,
1148                                                     &dev->channel[i].
1149                                                     TSIdleBuffer, 1);
1150                         if (status < 0)
1151                                 break;
1152                         status = AllocateRingBuffers(dev->pci_dev,
1153                                                      dev->PAOverflowBuffer,
1154                                                      &dev->channel[i].
1155                                                      TSIdleBuffer,
1156                                                      MAX_TS_BUFFER_SIZE, 0);
1157                         if (status)
1158                                 break;
1159                         FillTSIdleBuffer(&dev->channel[i].TSIdleBuffer,
1160                                          &dev->channel[i].TSRingBuffer);
1161                 }
1162         }
1163         return status;
1164 }
1165
1166 static void ngene_release_buffers(struct ngene *dev)
1167 {
1168         if (dev->iomem)
1169                 iounmap(dev->iomem);
1170         free_common_buffers(dev);
1171         vfree(dev->tsout_buf);
1172         vfree(dev->ain_buf);
1173         vfree(dev->vin_buf);
1174         vfree(dev);
1175 }
1176
1177 static int ngene_get_buffers(struct ngene *dev)
1178 {
1179         if (AllocCommonBuffers(dev))
1180                 return -ENOMEM;
1181         if (dev->card_info->io_type[4] & NGENE_IO_TSOUT) {
1182                 dev->tsout_buf = vmalloc(TSOUT_BUF_SIZE);
1183                 if (!dev->tsout_buf)
1184                         return -ENOMEM;
1185                 dvb_ringbuffer_init(&dev->tsout_rbuf,
1186                                     dev->tsout_buf, TSOUT_BUF_SIZE);
1187         }
1188         if (dev->card_info->io_type[2] & NGENE_IO_AIN) {
1189                 dev->ain_buf = vmalloc(AIN_BUF_SIZE);
1190                 if (!dev->ain_buf)
1191                         return -ENOMEM;
1192                 dvb_ringbuffer_init(&dev->ain_rbuf, dev->ain_buf, AIN_BUF_SIZE);
1193         }
1194         if (dev->card_info->io_type[0] & NGENE_IO_HDTV) {
1195                 dev->vin_buf = vmalloc(VIN_BUF_SIZE);
1196                 if (!dev->vin_buf)
1197                         return -ENOMEM;
1198                 dvb_ringbuffer_init(&dev->vin_rbuf, dev->vin_buf, VIN_BUF_SIZE);
1199         }
1200         dev->iomem = ioremap(pci_resource_start(dev->pci_dev, 0),
1201                              pci_resource_len(dev->pci_dev, 0));
1202         if (!dev->iomem)
1203                 return -ENOMEM;
1204
1205         return 0;
1206 }
1207
1208 static void ngene_init(struct ngene *dev)
1209 {
1210         int i;
1211
1212         tasklet_init(&dev->event_tasklet, event_tasklet, (unsigned long)dev);
1213
1214         memset_io(dev->iomem + 0xc000, 0x00, 0x220);
1215         memset_io(dev->iomem + 0xc400, 0x00, 0x100);
1216
1217         for (i = 0; i < MAX_STREAM; i++) {
1218                 dev->channel[i].dev = dev;
1219                 dev->channel[i].number = i;
1220         }
1221
1222         dev->fw_interface_version = 0;
1223
1224         ngwritel(0, NGENE_INT_ENABLE);
1225
1226         dev->icounts = ngreadl(NGENE_INT_COUNTS);
1227
1228         dev->device_version = ngreadl(DEV_VER) & 0x0f;
1229         printk(KERN_INFO DEVICE_NAME ": Device version %d\n",
1230                dev->device_version);
1231 }
1232
1233 static int ngene_load_firm(struct ngene *dev)
1234 {
1235         u32 size;
1236         const struct firmware *fw = NULL;
1237         u8 *ngene_fw;
1238         char *fw_name;
1239         int err, version;
1240
1241         version = dev->card_info->fw_version;
1242
1243         switch (version) {
1244         default:
1245         case 15:
1246                 version = 15;
1247                 size = 23466;
1248                 fw_name = "ngene_15.fw";
1249                 dev->cmd_timeout_workaround = true;
1250                 break;
1251         case 16:
1252                 size = 23498;
1253                 fw_name = "ngene_16.fw";
1254                 dev->cmd_timeout_workaround = true;
1255                 break;
1256         case 17:
1257                 size = 24446;
1258                 fw_name = "ngene_17.fw";
1259                 dev->cmd_timeout_workaround = true;
1260                 break;
1261         }
1262
1263         if (request_firmware(&fw, fw_name, &dev->pci_dev->dev) < 0) {
1264                 printk(KERN_ERR DEVICE_NAME
1265                         ": Could not load firmware file %s.\n", fw_name);
1266                 printk(KERN_INFO DEVICE_NAME
1267                         ": Copy %s to your hotplug directory!\n", fw_name);
1268                 return -1;
1269         }
1270         if (size != fw->size) {
1271                 printk(KERN_ERR DEVICE_NAME
1272                         ": Firmware %s has invalid size!", fw_name);
1273                 err = -1;
1274         } else {
1275                 printk(KERN_INFO DEVICE_NAME
1276                         ": Loading firmware file %s.\n", fw_name);
1277                 ngene_fw = (u8 *) fw->data;
1278                 err = ngene_command_load_firmware(dev, ngene_fw, size);
1279         }
1280
1281         release_firmware(fw);
1282
1283         return err;
1284 }
1285
1286 static void ngene_stop(struct ngene *dev)
1287 {
1288         down(&dev->cmd_mutex);
1289         i2c_del_adapter(&(dev->channel[0].i2c_adapter));
1290         i2c_del_adapter(&(dev->channel[1].i2c_adapter));
1291         ngwritel(0, NGENE_INT_ENABLE);
1292         ngwritel(0, NGENE_COMMAND);
1293         ngwritel(0, NGENE_COMMAND_HI);
1294         ngwritel(0, NGENE_STATUS);
1295         ngwritel(0, NGENE_STATUS_HI);
1296         ngwritel(0, NGENE_EVENT);
1297         ngwritel(0, NGENE_EVENT_HI);
1298         free_irq(dev->pci_dev->irq, dev);
1299 #ifdef CONFIG_PCI_MSI
1300         if (dev->msi_enabled)
1301                 pci_disable_msi(dev->pci_dev);
1302 #endif
1303 }
1304
1305 static int ngene_start(struct ngene *dev)
1306 {
1307         int stat;
1308         unsigned long flags;
1309         int i;
1310
1311         pci_set_master(dev->pci_dev);
1312         ngene_init(dev);
1313
1314         stat = request_irq(dev->pci_dev->irq, irq_handler,
1315                            IRQF_SHARED, "nGene",
1316                            (void *)dev);
1317         if (stat < 0)
1318                 return stat;
1319
1320         init_waitqueue_head(&dev->cmd_wq);
1321         init_waitqueue_head(&dev->tx_wq);
1322         init_waitqueue_head(&dev->rx_wq);
1323         sema_init(&dev->cmd_mutex, 1);
1324         sema_init(&dev->stream_mutex, 1);
1325         sema_init(&dev->pll_mutex, 1);
1326         sema_init(&dev->i2c_switch_mutex, 1);
1327         spin_lock_init(&dev->cmd_lock);
1328         for (i = 0; i < MAX_STREAM; i++)
1329                 spin_lock_init(&dev->channel[i].state_lock);
1330         ngwritel(1, TIMESTAMPS);
1331
1332         ngwritel(1, NGENE_INT_ENABLE);
1333
1334         stat = ngene_load_firm(dev);
1335         if (stat < 0)
1336                 goto fail;
1337
1338 #ifdef CONFIG_PCI_MSI
1339         /* enable MSI if kernel and card support it */
1340         if (pci_msi_enabled() && dev->card_info->msi_supported) {
1341                 ngwritel(0, NGENE_INT_ENABLE);
1342                 free_irq(dev->pci_dev->irq, dev);
1343                 stat = pci_enable_msi(dev->pci_dev);
1344                 if (stat) {
1345                         printk(KERN_INFO DEVICE_NAME
1346                                 ": MSI not available\n");
1347                         flags = IRQF_SHARED;
1348                 } else {
1349                         flags = 0;
1350                         dev->msi_enabled = true;
1351                 }
1352                 stat = request_irq(dev->pci_dev->irq, irq_handler,
1353                                         flags, "nGene", dev);
1354                 if (stat < 0)
1355                         goto fail2;
1356                 ngwritel(1, NGENE_INT_ENABLE);
1357         }
1358 #endif
1359
1360         stat = ngene_i2c_init(dev, 0);
1361         if (stat < 0)
1362                 goto fail;
1363
1364         stat = ngene_i2c_init(dev, 1);
1365         if (stat < 0)
1366                 goto fail;
1367
1368         if (dev->card_info->fw_version == 17) {
1369                 u8 tsin4_config[6] = {
1370                         3072 / 64, 3072 / 64, 0, 3072 / 64, 3072 / 64, 0};
1371                 u8 default_config[6] = {
1372                         4096 / 64, 4096 / 64, 0, 2048 / 64, 2048 / 64, 0};
1373                 u8 *bconf = default_config;
1374
1375                 if (dev->card_info->io_type[3] == NGENE_IO_TSIN)
1376                         bconf = tsin4_config;
1377                 dprintk(KERN_DEBUG DEVICE_NAME ": FW 17 buffer config\n");
1378                 stat = ngene_command_config_free_buf(dev, bconf);
1379         } else {
1380                 int bconf = BUFFER_CONFIG_4422;
1381                 if (dev->card_info->io_type[3] == NGENE_IO_TSIN)
1382                         bconf = BUFFER_CONFIG_3333;
1383                 stat = ngene_command_config_buf(dev, bconf);
1384         }
1385         if (!stat)
1386                 return stat;
1387
1388         /* otherwise error: fall through */
1389 fail:
1390         ngwritel(0, NGENE_INT_ENABLE);
1391         free_irq(dev->pci_dev->irq, dev);
1392 #ifdef CONFIG_PCI_MSI
1393 fail2:
1394         if (dev->msi_enabled)
1395                 pci_disable_msi(dev->pci_dev);
1396 #endif
1397         return stat;
1398 }
1399
1400
1401
1402
1403 /****************************************************************************/
1404 /****************************************************************************/
1405 /****************************************************************************/
1406
1407 static void release_channel(struct ngene_channel *chan)
1408 {
1409         struct dvb_demux *dvbdemux = &chan->demux;
1410         struct ngene *dev = chan->dev;
1411         struct ngene_info *ni = dev->card_info;
1412         int io = ni->io_type[chan->number];
1413
1414         if (chan->dev->cmd_timeout_workaround && chan->running)
1415                 set_transfer(chan, 0);
1416
1417         tasklet_kill(&chan->demux_tasklet);
1418
1419         if (io & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
1420                 if (chan->fe) {
1421                         dvb_unregister_frontend(chan->fe);
1422                         dvb_frontend_detach(chan->fe);
1423                         chan->fe = NULL;
1424                 }
1425                 dvbdemux->dmx.close(&dvbdemux->dmx);
1426                 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
1427                                               &chan->hw_frontend);
1428                 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
1429                                               &chan->mem_frontend);
1430                 dvb_dmxdev_release(&chan->dmxdev);
1431                 dvb_dmx_release(&chan->demux);
1432
1433                 if (chan->number == 0 || !one_adapter)
1434                         dvb_unregister_adapter(&dev->adapter[chan->number]);
1435         }
1436 }
1437
1438 static int init_channel(struct ngene_channel *chan)
1439 {
1440         int ret = 0, nr = chan->number;
1441         struct dvb_adapter *adapter = NULL;
1442         struct dvb_demux *dvbdemux = &chan->demux;
1443         struct ngene *dev = chan->dev;
1444         struct ngene_info *ni = dev->card_info;
1445         int io = ni->io_type[nr];
1446
1447         tasklet_init(&chan->demux_tasklet, demux_tasklet, (unsigned long)chan);
1448         chan->users = 0;
1449         chan->type = io;
1450         chan->mode = chan->type;        /* for now only one mode */
1451
1452         if (io & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
1453                 if (nr >= STREAM_AUDIOIN1)
1454                         chan->DataFormatFlags = DF_SWAP32;
1455                 if (nr == 0 || !one_adapter || dev->first_adapter == NULL) {
1456                         adapter = &dev->adapter[nr];
1457                         ret = dvb_register_adapter(adapter, "nGene",
1458                                                    THIS_MODULE,
1459                                                    &chan->dev->pci_dev->dev,
1460                                                    adapter_nr);
1461                         if (ret < 0)
1462                                 return ret;
1463                         if (dev->first_adapter == NULL)
1464                                 dev->first_adapter = adapter;
1465                 } else {
1466                         adapter = dev->first_adapter;
1467                 }
1468
1469                 ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux",
1470                                               ngene_start_feed,
1471                                               ngene_stop_feed, chan);
1472                 ret = my_dvb_dmxdev_ts_card_init(&chan->dmxdev, &chan->demux,
1473                                                  &chan->hw_frontend,
1474                                                  &chan->mem_frontend, adapter);
1475         }
1476
1477         if (io & NGENE_IO_TSIN) {
1478                 chan->fe = NULL;
1479                 if (ni->demod_attach[nr])
1480                         ni->demod_attach[nr](chan);
1481                 if (chan->fe) {
1482                         if (dvb_register_frontend(adapter, chan->fe) < 0) {
1483                                 if (chan->fe->ops.release)
1484                                         chan->fe->ops.release(chan->fe);
1485                                 chan->fe = NULL;
1486                         }
1487                 }
1488                 if (chan->fe && ni->tuner_attach[nr])
1489                         if (ni->tuner_attach[nr] (chan) < 0) {
1490                                 printk(KERN_ERR DEVICE_NAME
1491                                        ": Tuner attach failed on channel %d!\n",
1492                                        nr);
1493                         }
1494         }
1495         return ret;
1496 }
1497
1498 static int init_channels(struct ngene *dev)
1499 {
1500         int i, j;
1501
1502         for (i = 0; i < MAX_STREAM; i++) {
1503                 dev->channel[i].number = i;
1504                 if (init_channel(&dev->channel[i]) < 0) {
1505                         for (j = i - 1; j >= 0; j--)
1506                                 release_channel(&dev->channel[j]);
1507                         return -1;
1508                 }
1509         }
1510         return 0;
1511 }
1512
1513 /****************************************************************************/
1514 /* device probe/remove calls ************************************************/
1515 /****************************************************************************/
1516
1517 void __devexit ngene_remove(struct pci_dev *pdev)
1518 {
1519         struct ngene *dev = (struct ngene *)pci_get_drvdata(pdev);
1520         int i;
1521
1522         tasklet_kill(&dev->event_tasklet);
1523         for (i = MAX_STREAM - 1; i >= 0; i--)
1524                 release_channel(&dev->channel[i]);
1525         ngene_stop(dev);
1526         ngene_release_buffers(dev);
1527         pci_set_drvdata(pdev, NULL);
1528         pci_disable_device(pdev);
1529 }
1530
1531 int __devinit ngene_probe(struct pci_dev *pci_dev,
1532                           const struct pci_device_id *id)
1533 {
1534         struct ngene *dev;
1535         int stat = 0;
1536
1537         if (pci_enable_device(pci_dev) < 0)
1538                 return -ENODEV;
1539
1540         dev = vmalloc(sizeof(struct ngene));
1541         if (dev == NULL) {
1542                 stat = -ENOMEM;
1543                 goto fail0;
1544         }
1545         memset(dev, 0, sizeof(struct ngene));
1546
1547         dev->pci_dev = pci_dev;
1548         dev->card_info = (struct ngene_info *)id->driver_data;
1549         printk(KERN_INFO DEVICE_NAME ": Found %s\n", dev->card_info->name);
1550
1551         pci_set_drvdata(pci_dev, dev);
1552
1553         /* Alloc buffers and start nGene */
1554         stat = ngene_get_buffers(dev);
1555         if (stat < 0)
1556                 goto fail1;
1557         stat = ngene_start(dev);
1558         if (stat < 0)
1559                 goto fail1;
1560
1561         dev->i2c_current_bus = -1;
1562
1563         /* Register DVB adapters and devices for both channels */
1564         if (init_channels(dev) < 0)
1565                 goto fail2;
1566
1567         return 0;
1568
1569 fail2:
1570         ngene_stop(dev);
1571 fail1:
1572         ngene_release_buffers(dev);
1573 fail0:
1574         pci_disable_device(pci_dev);
1575         pci_set_drvdata(pci_dev, NULL);
1576         return stat;
1577 }