drivers/media/dvb/ngene/ngene-core.c

   1 /*
   2  * ngene.c: nGene PCIe bridge driver
   3  *
   4  * Copyright (C) 2005-2007 Micronas
   5  *
   6  * Copyright (C) 2008-2009 Ralph Metzler <rjkm@metzlerbros.de>
   7  *                         Modifications for new nGene firmware,
   8  *                         support for EEPROM-copying,
   9  *                         support for new dual DVB-S2 card prototype
  10  *
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * version 2 only, as published by the Free Software Foundation.
  15  *
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  26  * 02110-1301, USA
  27  * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
  28  */
  29
  30 #include <linux/module.h>
  31 #include <linux/init.h>
  32 #include <linux/delay.h>
  33 #include <linux/poll.h>
  34 #include <linux/io.h>
  35 #include <asm/div64.h>
  36 #include <linux/pci.h>
  37 #include <linux/timer.h>
  38 #include <linux/byteorder/generic.h>
  39 #include <linux/firmware.h>
  40 #include <linux/vmalloc.h>
  41
  42 #include "ngene.h"
  43
  44 static int one_adapter = 1;
  45 module_param(one_adapter, int, 0444);
  46 MODULE_PARM_DESC(one_adapter, "Use only one adapter.");
  47
  48
  49 static int debug;
  50 module_param(debug, int, 0444);
  51 MODULE_PARM_DESC(debug, "Print debugging information.");
  52
  53 DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  54
  55 #define dprintk if (debug) printk
  56
  57 #define ngwriteb(dat, adr)         writeb((dat), (char *)(dev->iomem + (adr)))
  58 #define ngwritel(dat, adr)         writel((dat), (char *)(dev->iomem + (adr)))
  59 #define ngwriteb(dat, adr)         writeb((dat), (char *)(dev->iomem + (adr)))
  60 #define ngreadl(adr)               readl(dev->iomem + (adr))
  61 #define ngreadb(adr)               readb(dev->iomem + (adr))
  62 #define ngcpyto(adr, src, count)   memcpy_toio((char *) \
  63                                    (dev->iomem + (adr)), (src), (count))
  64 #define ngcpyfrom(dst, adr, count) memcpy_fromio((dst), (char *) \
  65                                    (dev->iomem + (adr)), (count))
  66
  67 /****************************************************************************/
  68 /* nGene interrupt handler **************************************************/
  69 /****************************************************************************/
  70
  71 static void event_tasklet(unsigned long data)
  72 {
  73         struct ngene *dev = (struct ngene *)data;
  74
  75         while (dev->EventQueueReadIndex != dev->EventQueueWriteIndex) {
  76                 struct EVENT_BUFFER Event =
  77                         dev->EventQueue[dev->EventQueueReadIndex];
  78                 dev->EventQueueReadIndex =
  79                         (dev->EventQueueReadIndex + 1) & (EVENT_QUEUE_SIZE - 1);
  80
  81                 if ((Event.UARTStatus & 0x01) && (dev->TxEventNotify))
  82                         dev->TxEventNotify(dev, Event.TimeStamp);
  83                 if ((Event.UARTStatus & 0x02) && (dev->RxEventNotify))
  84                         dev->RxEventNotify(dev, Event.TimeStamp,
  85                                            Event.RXCharacter);
  86         }
  87 }
  88
  89 static void demux_tasklet(unsigned long data)
  90 {
  91         struct ngene_channel *chan = (struct ngene_channel *)data;
  92         struct SBufferHeader *Cur = chan->nextBuffer;
  93
  94         spin_lock_irq(&chan->state_lock);
  95
  96         while (Cur->ngeneBuffer.SR.Flags & 0x80) {
  97                 if (chan->mode & NGENE_IO_TSOUT) {
  98                         u32 Flags = chan->DataFormatFlags;
  99                         if (Cur->ngeneBuffer.SR.Flags & 0x20)
 100                                 Flags |= BEF_OVERFLOW;
 101                         if (chan->pBufferExchange) {
 102                                 if (!chan->pBufferExchange(chan,
 103                                                            Cur->Buffer1,
 104                                                            chan->Capture1Length,
 105                                                            Cur->ngeneBuffer.SR.
 106                                                            Clock, Flags)) {
 107                                         /*
 108                                            We didn't get data
 109                                            Clear in service flag to make sure we
 110                                            get called on next interrupt again.
 111                                            leave fill/empty (0x80) flag alone
 112                                            to avoid hardware running out of
 113                                            buffers during startup, we hold only
 114                                            in run state ( the source may be late
 115                                            delivering data )
 116                                         */
 117
 118                                         if (chan->HWState == HWSTATE_RUN) {
 119                                                 Cur->ngeneBuffer.SR.Flags &=
 120                                                         ~0x40;
 121                                                 break;
 122                                                 /* Stop proccessing stream */
 123                                         }
 124                                 } else {
 125                                         /* We got a valid buffer,
 126                                            so switch to run state */
 127                                         chan->HWState = HWSTATE_RUN;
 128                                 }
 129                         } else {
 130                                 printk(KERN_ERR DEVICE_NAME ": OOPS\n");
 131                                 if (chan->HWState == HWSTATE_RUN) {
 132                                         Cur->ngeneBuffer.SR.Flags &= ~0x40;
 133                                         break;  /* Stop proccessing stream */
 134                                 }
 135                         }
 136                         if (chan->AudioDTOUpdated) {
 137                                 printk(KERN_INFO DEVICE_NAME
 138                                        ": Update AudioDTO = %d\n",
 139                                        chan->AudioDTOValue);
 140                                 Cur->ngeneBuffer.SR.DTOUpdate =
 141                                         chan->AudioDTOValue;
 142                                 chan->AudioDTOUpdated = 0;
 143                         }
 144                 } else {
 145                         if (chan->HWState == HWSTATE_RUN) {
 146                                 u32 Flags = 0;
 147                                 IBufferExchange *exch1 = chan->pBufferExchange;
 148                                 IBufferExchange *exch2 = chan->pBufferExchange2;
 149                                 if (Cur->ngeneBuffer.SR.Flags & 0x01)
 150                                         Flags |= BEF_EVEN_FIELD;
 151                                 if (Cur->ngeneBuffer.SR.Flags & 0x20)
 152                                         Flags |= BEF_OVERFLOW;
 153                                 spin_unlock_irq(&chan->state_lock);
 154                                 if (exch1)
 155                                         exch1(chan, Cur->Buffer1,
 156                                                 chan->Capture1Length,
 157                                                 Cur->ngeneBuffer.SR.Clock,
 158                                                 Flags);
 159                                 if (exch2)
 160                                         exch2(chan, Cur->Buffer2,
 161                                                 chan->Capture2Length,
 162                                                 Cur->ngeneBuffer.SR.Clock,
 163                                                 Flags);
 164                                 spin_lock_irq(&chan->state_lock);
 165                         } else if (chan->HWState != HWSTATE_STOP)
 166                                 chan->HWState = HWSTATE_RUN;
 167                 }
 168                 Cur->ngeneBuffer.SR.Flags = 0x00;
 169                 Cur = Cur->Next;
 170         }
 171         chan->nextBuffer = Cur;
 172
 173         spin_unlock_irq(&chan->state_lock);
 174 }
 175
 176 static irqreturn_t irq_handler(int irq, void *dev_id)
 177 {
 178         struct ngene *dev = (struct ngene *)dev_id;
 179         u32 icounts = 0;
 180         irqreturn_t rc = IRQ_NONE;
 181         u32 i = MAX_STREAM;
 182         u8 *tmpCmdDoneByte;
 183
 184         if (dev->BootFirmware) {
 185                 icounts = ngreadl(NGENE_INT_COUNTS);
 186                 if (icounts != dev->icounts) {
 187                         ngwritel(0, FORCE_NMI);
 188                         dev->cmd_done = 1;
 189                         wake_up(&dev->cmd_wq);
 190                         dev->icounts = icounts;
 191                         rc = IRQ_HANDLED;
 192                 }
 193                 return rc;
 194         }
 195
 196         ngwritel(0, FORCE_NMI);
 197
 198         spin_lock(&dev->cmd_lock);
 199         tmpCmdDoneByte = dev->CmdDoneByte;
 200         if (tmpCmdDoneByte &&
 201             (*tmpCmdDoneByte ||
 202             (dev->ngenetohost[0] == 1 && dev->ngenetohost[1] != 0))) {
 203                 dev->CmdDoneByte = NULL;
 204                 dev->cmd_done = 1;
 205                 wake_up(&dev->cmd_wq);
 206                 rc = IRQ_HANDLED;
 207         }
 208         spin_unlock(&dev->cmd_lock);
 209
 210         if (dev->EventBuffer->EventStatus & 0x80) {
 211                 u8 nextWriteIndex =
 212                         (dev->EventQueueWriteIndex + 1) &
 213                         (EVENT_QUEUE_SIZE - 1);
 214                 if (nextWriteIndex != dev->EventQueueReadIndex) {
 215                         dev->EventQueue[dev->EventQueueWriteIndex] =
 216                                 *(dev->EventBuffer);
 217                         dev->EventQueueWriteIndex = nextWriteIndex;
 218                 } else {
 219                         printk(KERN_ERR DEVICE_NAME ": event overflow\n");
 220                         dev->EventQueueOverflowCount += 1;
 221                         dev->EventQueueOverflowFlag = 1;
 222                 }
 223                 dev->EventBuffer->EventStatus &= ~0x80;
 224                 tasklet_schedule(&dev->event_tasklet);
 225                 rc = IRQ_HANDLED;
 226         }
 227
 228         while (i > 0) {
 229                 i--;
 230                 spin_lock(&dev->channel[i].state_lock);
 231                 /* if (dev->channel[i].State>=KSSTATE_RUN) { */
 232                 if (dev->channel[i].nextBuffer) {
 233                         if ((dev->channel[i].nextBuffer->
 234                              ngeneBuffer.SR.Flags & 0xC0) == 0x80) {
 235                                 dev->channel[i].nextBuffer->
 236                                         ngeneBuffer.SR.Flags |= 0x40;
 237                                 tasklet_schedule(
 238                                         &dev->channel[i].demux_tasklet);
 239                                 rc = IRQ_HANDLED;
 240                         }
 241                 }
 242                 spin_unlock(&dev->channel[i].state_lock);
 243         }
 244
 245         /* Request might have been processed by a previous call. */
 246         return IRQ_HANDLED;
 247 }
 248
 249 /****************************************************************************/
 250 /* nGene command interface **************************************************/
 251 /****************************************************************************/
 252
 253 static void dump_command_io(struct ngene *dev)
 254 {
 255         u8 buf[8], *b;
 256
 257         ngcpyfrom(buf, HOST_TO_NGENE, 8);
 258         printk(KERN_ERR "host_to_ngene (%04x): %02x %02x %02x %02x %02x %02x %02x %02x\n",
 259                 HOST_TO_NGENE, buf[0], buf[1], buf[2], buf[3],
 260                 buf[4], buf[5], buf[6], buf[7]);
 261
 262         ngcpyfrom(buf, NGENE_TO_HOST, 8);
 263         printk(KERN_ERR "ngene_to_host (%04x): %02x %02x %02x %02x %02x %02x %02x %02x\n",
 264                 NGENE_TO_HOST, buf[0], buf[1], buf[2], buf[3],
 265                 buf[4], buf[5], buf[6], buf[7]);
 266
 267         b = dev->hosttongene;
 268         printk(KERN_ERR "dev->hosttongene (%p): %02x %02x %02x %02x %02x %02x %02x %02x\n",
 269                 b, b[0], b[1], b[2], b[3], b[4], b[5], b[6], b[7]);
 270
 271         b = dev->ngenetohost;
 272         printk(KERN_ERR "dev->ngenetohost (%p): %02x %02x %02x %02x %02x %02x %02x %02x\n",
 273                 b, b[0], b[1], b[2], b[3], b[4], b[5], b[6], b[7]);
 274 }
 275
 276 static int ngene_command_mutex(struct ngene *dev, struct ngene_command *com)
 277 {
 278         int ret;
 279         u8 *tmpCmdDoneByte;
 280
 281         dev->cmd_done = 0;
 282
 283         if (com->cmd.hdr.Opcode == CMD_FWLOAD_PREPARE) {
 284                 dev->BootFirmware = 1;
 285                 dev->icounts = ngreadl(NGENE_INT_COUNTS);
 286                 ngwritel(0, NGENE_COMMAND);
 287                 ngwritel(0, NGENE_COMMAND_HI);
 288                 ngwritel(0, NGENE_STATUS);
 289                 ngwritel(0, NGENE_STATUS_HI);
 290                 ngwritel(0, NGENE_EVENT);
 291                 ngwritel(0, NGENE_EVENT_HI);
 292         } else if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH) {
 293                 u64 fwio = dev->PAFWInterfaceBuffer;
 294
 295                 ngwritel(fwio & 0xffffffff, NGENE_COMMAND);
 296                 ngwritel(fwio >> 32, NGENE_COMMAND_HI);
 297                 ngwritel((fwio + 256) & 0xffffffff, NGENE_STATUS);
 298                 ngwritel((fwio + 256) >> 32, NGENE_STATUS_HI);
 299                 ngwritel((fwio + 512) & 0xffffffff, NGENE_EVENT);
 300                 ngwritel((fwio + 512) >> 32, NGENE_EVENT_HI);
 301         }
 302
 303         memcpy(dev->FWInterfaceBuffer, com->cmd.raw8, com->in_len + 2);
 304
 305         if (dev->BootFirmware)
 306                 ngcpyto(HOST_TO_NGENE, com->cmd.raw8, com->in_len + 2);
 307
 308         spin_lock_irq(&dev->cmd_lock);
 309         tmpCmdDoneByte = dev->ngenetohost + com->out_len;
 310         if (!com->out_len)
 311                 tmpCmdDoneByte++;
 312         *tmpCmdDoneByte = 0;
 313         dev->ngenetohost[0] = 0;
 314         dev->ngenetohost[1] = 0;
 315         dev->CmdDoneByte = tmpCmdDoneByte;
 316         spin_unlock_irq(&dev->cmd_lock);
 317
 318         /* Notify 8051. */
 319         ngwritel(1, FORCE_INT);
 320
 321         ret = wait_event_timeout(dev->cmd_wq, dev->cmd_done == 1, 2 * HZ);
 322         if (!ret) {
 323                 /*ngwritel(0, FORCE_NMI);*/
 324
 325                 printk(KERN_ERR DEVICE_NAME
 326                        ": Command timeout cmd=%02x prev=%02x\n",
 327                        com->cmd.hdr.Opcode, dev->prev_cmd);
 328                 dump_command_io(dev);
 329                 return -1;
 330         }
 331         if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH)
 332                 dev->BootFirmware = 0;
 333
 334         dev->prev_cmd = com->cmd.hdr.Opcode;
 335
 336         if (!com->out_len)
 337                 return 0;
 338
 339         memcpy(com->cmd.raw8, dev->ngenetohost, com->out_len);
 340
 341         return 0;
 342 }
 343
 344 int ngene_command(struct ngene *dev, struct ngene_command *com)
 345 {
 346         int result;
 347
 348         down(&dev->cmd_mutex);
 349         result = ngene_command_mutex(dev, com);
 350         up(&dev->cmd_mutex);
 351         return result;
 352 }
 353
 354
 355 static int ngene_command_load_firmware(struct ngene *dev,
 356                                        u8 *ngene_fw, u32 size)
 357 {
 358 #define FIRSTCHUNK (1024)
 359         u32 cleft;
 360         struct ngene_command com;
 361
 362         com.cmd.hdr.Opcode = CMD_FWLOAD_PREPARE;
 363         com.cmd.hdr.Length = 0;
 364         com.in_len = 0;
 365         com.out_len = 0;
 366
 367         ngene_command(dev, &com);
 368
 369         cleft = (size + 3) & ~3;
 370         if (cleft > FIRSTCHUNK) {
 371                 ngcpyto(PROGRAM_SRAM + FIRSTCHUNK, ngene_fw + FIRSTCHUNK,
 372                         cleft - FIRSTCHUNK);
 373                 cleft = FIRSTCHUNK;
 374         }
 375         ngcpyto(DATA_FIFO_AREA, ngene_fw, cleft);
 376
 377         memset(&com, 0, sizeof(struct ngene_command));
 378         com.cmd.hdr.Opcode = CMD_FWLOAD_FINISH;
 379         com.cmd.hdr.Length = 4;
 380         com.cmd.FWLoadFinish.Address = DATA_FIFO_AREA;
 381         com.cmd.FWLoadFinish.Length = (unsigned short)cleft;
 382         com.in_len = 4;
 383         com.out_len = 0;
 384
 385         return ngene_command(dev, &com);
 386 }
 387
 388
 389 static int ngene_command_config_buf(struct ngene *dev, u8 config)
 390 {
 391         struct ngene_command com;
 392
 393         com.cmd.hdr.Opcode = CMD_CONFIGURE_BUFFER;
 394         com.cmd.hdr.Length = 1;
 395         com.cmd.ConfigureBuffers.config = config;
 396         com.in_len = 1;
 397         com.out_len = 0;
 398
 399         if (ngene_command(dev, &com) < 0)
 400                 return -EIO;
 401         return 0;
 402 }
 403
 404 static int ngene_command_config_free_buf(struct ngene *dev, u8 *config)
 405 {
 406         struct ngene_command com;
 407
 408         com.cmd.hdr.Opcode = CMD_CONFIGURE_FREE_BUFFER;
 409         com.cmd.hdr.Length = 6;
 410         memcpy(&com.cmd.ConfigureBuffers.config, config, 6);
 411         com.in_len = 6;
 412         com.out_len = 0;
 413
 414         if (ngene_command(dev, &com) < 0)
 415                 return -EIO;
 416
 417         return 0;
 418 }
 419
 420 int ngene_command_gpio_set(struct ngene *dev, u8 select, u8 level)
 421 {
 422         struct ngene_command com;
 423
 424         com.cmd.hdr.Opcode = CMD_SET_GPIO_PIN;
 425         com.cmd.hdr.Length = 1;
 426         com.cmd.SetGpioPin.select = select | (level << 7);
 427         com.in_len = 1;
 428         com.out_len = 0;
 429
 430         return ngene_command(dev, &com);
 431 }
 432
 433
 434 /*
 435  02000640 is sample on rising edge.
 436  02000740 is sample on falling edge.
 437  02000040 is ignore "valid" signal
 438
 439  0: FD_CTL1 Bit 7,6 must be 0,1
 440     7   disable(fw controlled)
 441     6   0-AUX,1-TS
 442     5   0-par,1-ser
 443     4   0-lsb/1-msb
 444     3,2 reserved
 445     1,0 0-no sync, 1-use ext. start, 2-use 0x47, 3-both
 446  1: FD_CTL2 has 3-valid must be hi, 2-use valid, 1-edge
 447  2: FD_STA is read-only. 0-sync
 448  3: FD_INSYNC is number of 47s to trigger "in sync".
 449  4: FD_OUTSYNC is number of 47s to trigger "out of sync".
 450  5: FD_MAXBYTE1 is low-order of bytes per packet.
 451  6: FD_MAXBYTE2 is high-order of bytes per packet.
 452  7: Top byte is unused.
 453 */
 454
 455 /****************************************************************************/
 456
 457 static u8 TSFeatureDecoderSetup[8 * 5] = {
 458         0x42, 0x00, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00,
 459         0x40, 0x06, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXH */
 460         0x71, 0x07, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXHser */
 461         0x72, 0x06, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* S2ser */
 462         0x40, 0x07, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* LGDT3303 */
 463 };
 464
 465 /* Set NGENE I2S Config to 16 bit packed */
 466 static u8 I2SConfiguration[] = {
 467         0x00, 0x10, 0x00, 0x00,
 468         0x80, 0x10, 0x00, 0x00,
 469 };
 470
 471 static u8 SPDIFConfiguration[10] = {
 472         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
 473 };
 474
 475 /* Set NGENE I2S Config to transport stream compatible mode */
 476
 477 static u8 TS_I2SConfiguration[4] = { 0x3E, 0x1A, 0x00, 0x00 }; /*3e 18 00 00 ?*/
 478
 479 static u8 TS_I2SOutConfiguration[4] = { 0x80, 0x20, 0x00, 0x00 };
 480
 481 static u8 ITUDecoderSetup[4][16] = {
 482         {0x1c, 0x13, 0x01, 0x68, 0x3d, 0x90, 0x14, 0x20,  /* SDTV */
 483          0x00, 0x00, 0x01, 0xb0, 0x9c, 0x00, 0x00, 0x00},
 484         {0x9c, 0x03, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00,
 485          0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
 486         {0x9f, 0x00, 0x23, 0xC0, 0x60, 0x0F, 0x13, 0x00,  /* HDTV 1080i50 */
 487          0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
 488         {0x9c, 0x01, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00,  /* HDTV 1080i60 */
 489          0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
 490 };
 491
 492 /*
 493  * 50 48 60 gleich
 494  * 27p50 9f 00 22 80 42 69 18 ...
 495  * 27p60 93 00 22 80 82 69 1c ...
 496  */
 497
 498 /* Maxbyte to 1144 (for raw data) */
 499 static u8 ITUFeatureDecoderSetup[8] = {
 500         0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x04, 0x00
 501 };
 502
 503 void FillTSBuffer(void *Buffer, int Length, u32 Flags)
 504 {
 505         u32 *ptr = Buffer;
 506
 507         memset(Buffer, 0xff, Length);
 508         while (Length > 0) {
 509                 if (Flags & DF_SWAP32)
 510                         *ptr = 0x471FFF10;
 511                 else
 512                         *ptr = 0x10FF1F47;
 513                 ptr += (188 / 4);
 514                 Length -= 188;
 515         }
 516 }
 517
 518
 519 static void flush_buffers(struct ngene_channel *chan)
 520 {
 521         u8 val;
 522
 523         do {
 524                 msleep(1);
 525                 spin_lock_irq(&chan->state_lock);
 526                 val = chan->nextBuffer->ngeneBuffer.SR.Flags & 0x80;
 527                 spin_unlock_irq(&chan->state_lock);
 528         } while (val);
 529 }
 530
 531 static void clear_buffers(struct ngene_channel *chan)
 532 {
 533         struct SBufferHeader *Cur = chan->nextBuffer;
 534
 535         do {
 536                 memset(&Cur->ngeneBuffer.SR, 0, sizeof(Cur->ngeneBuffer.SR));
 537                 if (chan->mode & NGENE_IO_TSOUT)
 538                         FillTSBuffer(Cur->Buffer1,
 539                                      chan->Capture1Length,
 540                                      chan->DataFormatFlags);
 541                 Cur = Cur->Next;
 542         } while (Cur != chan->nextBuffer);
 543
 544         if (chan->mode & NGENE_IO_TSOUT) {
 545                 chan->nextBuffer->ngeneBuffer.SR.DTOUpdate =
 546                         chan->AudioDTOValue;
 547                 chan->AudioDTOUpdated = 0;
 548
 549                 Cur = chan->TSIdleBuffer.Head;
 550
 551                 do {
 552                         memset(&Cur->ngeneBuffer.SR, 0,
 553                                sizeof(Cur->ngeneBuffer.SR));
 554                         FillTSBuffer(Cur->Buffer1,
 555                                      chan->Capture1Length,
 556                                      chan->DataFormatFlags);
 557                         Cur = Cur->Next;
 558                 } while (Cur != chan->TSIdleBuffer.Head);
 559         }
 560 }
 561
 562 static int ngene_command_stream_control(struct ngene *dev, u8 stream,
 563                                         u8 control, u8 mode, u8 flags)
 564 {
 565         struct ngene_channel *chan = &dev->channel[stream];
 566         struct ngene_command com;
 567         u16 BsUVI = ((stream & 1) ? 0x9400 : 0x9300);
 568         u16 BsSDI = ((stream & 1) ? 0x9600 : 0x9500);
 569         u16 BsSPI = ((stream & 1) ? 0x9800 : 0x9700);
 570         u16 BsSDO = 0x9B00;
 571
 572         down(&dev->stream_mutex);
 573         memset(&com, 0, sizeof(com));
 574         com.cmd.hdr.Opcode = CMD_CONTROL;
 575         com.cmd.hdr.Length = sizeof(struct FW_STREAM_CONTROL) - 2;
 576         com.cmd.StreamControl.Stream = stream | (control ? 8 : 0);
 577         if (chan->mode & NGENE_IO_TSOUT)
 578                 com.cmd.StreamControl.Stream |= 0x07;
 579         com.cmd.StreamControl.Control = control |
 580                 (flags & SFLAG_ORDER_LUMA_CHROMA);
 581         com.cmd.StreamControl.Mode = mode;
 582         com.in_len = sizeof(struct FW_STREAM_CONTROL);
 583         com.out_len = 0;
 584
 585         dprintk(KERN_INFO DEVICE_NAME
 586                 ": Stream=%02x, Control=%02x, Mode=%02x\n",
 587                 com.cmd.StreamControl.Stream, com.cmd.StreamControl.Control,
 588                 com.cmd.StreamControl.Mode);
 589
 590         chan->Mode = mode;
 591
 592         if (!(control & 0x80)) {
 593                 spin_lock_irq(&chan->state_lock);
 594                 if (chan->State == KSSTATE_RUN) {
 595                         chan->State = KSSTATE_ACQUIRE;
 596                         chan->HWState = HWSTATE_STOP;
 597                         spin_unlock_irq(&chan->state_lock);
 598                         if (ngene_command(dev, &com) < 0) {
 599                                 up(&dev->stream_mutex);
 600                                 return -1;
 601                         }
 602                         /* clear_buffers(chan); */
 603                         flush_buffers(chan);
 604                         up(&dev->stream_mutex);
 605                         return 0;
 606                 }
 607                 spin_unlock_irq(&chan->state_lock);
 608                 up(&dev->stream_mutex);
 609                 return 0;
 610         }
 611
 612         if (mode & SMODE_AUDIO_CAPTURE) {
 613                 com.cmd.StreamControl.CaptureBlockCount =
 614                         chan->Capture1Length / AUDIO_BLOCK_SIZE;
 615                 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead;
 616         } else if (mode & SMODE_TRANSPORT_STREAM) {
 617                 com.cmd.StreamControl.CaptureBlockCount =
 618                         chan->Capture1Length / TS_BLOCK_SIZE;
 619                 com.cmd.StreamControl.MaxLinesPerField =
 620                         chan->Capture1Length / TS_BLOCK_SIZE;
 621                 com.cmd.StreamControl.Buffer_Address =
 622                         chan->TSRingBuffer.PAHead;
 623                 if (chan->mode & NGENE_IO_TSOUT) {
 624                         com.cmd.StreamControl.BytesPerVBILine =
 625                                 chan->Capture1Length / TS_BLOCK_SIZE;
 626                         com.cmd.StreamControl.Stream |= 0x07;
 627                 }
 628         } else {
 629                 com.cmd.StreamControl.BytesPerVideoLine = chan->nBytesPerLine;
 630                 com.cmd.StreamControl.MaxLinesPerField = chan->nLines;
 631                 com.cmd.StreamControl.MinLinesPerField = 100;
 632                 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead;
 633
 634                 if (mode & SMODE_VBI_CAPTURE) {
 635                         com.cmd.StreamControl.MaxVBILinesPerField =
 636                                 chan->nVBILines;
 637                         com.cmd.StreamControl.MinVBILinesPerField = 0;
 638                         com.cmd.StreamControl.BytesPerVBILine =
 639                                 chan->nBytesPerVBILine;
 640                 }
 641                 if (flags & SFLAG_COLORBAR)
 642                         com.cmd.StreamControl.Stream |= 0x04;
 643         }
 644
 645         spin_lock_irq(&chan->state_lock);
 646         if (mode & SMODE_AUDIO_CAPTURE) {
 647                 chan->nextBuffer = chan->RingBuffer.Head;
 648                 if (mode & SMODE_AUDIO_SPDIF) {
 649                         com.cmd.StreamControl.SetupDataLen =
 650                                 sizeof(SPDIFConfiguration);
 651                         com.cmd.StreamControl.SetupDataAddr = BsSPI;
 652                         memcpy(com.cmd.StreamControl.SetupData,
 653                                SPDIFConfiguration, sizeof(SPDIFConfiguration));
 654                 } else {
 655                         com.cmd.StreamControl.SetupDataLen = 4;
 656                         com.cmd.StreamControl.SetupDataAddr = BsSDI;
 657                         memcpy(com.cmd.StreamControl.SetupData,
 658                                I2SConfiguration +
 659                                4 * dev->card_info->i2s[stream], 4);
 660                 }
 661         } else if (mode & SMODE_TRANSPORT_STREAM) {
 662                 chan->nextBuffer = chan->TSRingBuffer.Head;
 663                 if (stream >= STREAM_AUDIOIN1) {
 664                         if (chan->mode & NGENE_IO_TSOUT) {
 665                                 com.cmd.StreamControl.SetupDataLen =
 666                                         sizeof(TS_I2SOutConfiguration);
 667                                 com.cmd.StreamControl.SetupDataAddr = BsSDO;
 668                                 memcpy(com.cmd.StreamControl.SetupData,
 669                                        TS_I2SOutConfiguration,
 670                                        sizeof(TS_I2SOutConfiguration));
 671                         } else {
 672                                 com.cmd.StreamControl.SetupDataLen =
 673                                         sizeof(TS_I2SConfiguration);
 674                                 com.cmd.StreamControl.SetupDataAddr = BsSDI;
 675                                 memcpy(com.cmd.StreamControl.SetupData,
 676                                        TS_I2SConfiguration,
 677                                        sizeof(TS_I2SConfiguration));
 678                         }
 679                 } else {
 680                         com.cmd.StreamControl.SetupDataLen = 8;
 681                         com.cmd.StreamControl.SetupDataAddr = BsUVI + 0x10;
 682                         memcpy(com.cmd.StreamControl.SetupData,
 683                                TSFeatureDecoderSetup +
 684                                8 * dev->card_info->tsf[stream], 8);
 685                 }
 686         } else {
 687                 chan->nextBuffer = chan->RingBuffer.Head;
 688                 com.cmd.StreamControl.SetupDataLen =
 689                         16 + sizeof(ITUFeatureDecoderSetup);
 690                 com.cmd.StreamControl.SetupDataAddr = BsUVI;
 691                 memcpy(com.cmd.StreamControl.SetupData,
 692                        ITUDecoderSetup[chan->itumode], 16);
 693                 memcpy(com.cmd.StreamControl.SetupData + 16,
 694                        ITUFeatureDecoderSetup, sizeof(ITUFeatureDecoderSetup));
 695         }
 696         clear_buffers(chan);
 697         chan->State = KSSTATE_RUN;
 698         if (mode & SMODE_TRANSPORT_STREAM)
 699                 chan->HWState = HWSTATE_RUN;
 700         else
 701                 chan->HWState = HWSTATE_STARTUP;
 702         spin_unlock_irq(&chan->state_lock);
 703
 704         if (ngene_command(dev, &com) < 0) {
 705                 up(&dev->stream_mutex);
 706                 return -1;
 707         }
 708         up(&dev->stream_mutex);
 709         return 0;
 710 }
 711
 712 void set_transfer(struct ngene_channel *chan, int state)
 713 {
 714         u8 control = 0, mode = 0, flags = 0;
 715         struct ngene *dev = chan->dev;
 716         int ret;
 717
 718         /*
 719         printk(KERN_INFO DEVICE_NAME ": st %d\n", state);
 720         msleep(100);
 721         */
 722
 723         if (state) {
 724                 if (chan->running) {
 725                         printk(KERN_INFO DEVICE_NAME ": already running\n");
 726                         return;
 727                 }
 728         } else {
 729                 if (!chan->running) {
 730                         printk(KERN_INFO DEVICE_NAME ": already stopped\n");
 731                         return;
 732                 }
 733         }
 734
 735         if (dev->card_info->switch_ctrl)
 736                 dev->card_info->switch_ctrl(chan, 1, state ^ 1);
 737
 738         if (state) {
 739                 spin_lock_irq(&chan->state_lock);
 740
 741                 /* printk(KERN_INFO DEVICE_NAME ": lock=%08x\n",
 742                           ngreadl(0x9310)); */
 743                 dvb_ringbuffer_flush(&dev->tsout_rbuf);
 744                 control = 0x80;
 745                 if (chan->mode & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
 746                         chan->Capture1Length = 512 * 188;
 747                         mode = SMODE_TRANSPORT_STREAM;
 748                 }
 749                 if (chan->mode & NGENE_IO_TSOUT) {
 750                         chan->pBufferExchange = tsout_exchange;
 751                         /* 0x66666666 = 50MHz *2^33 /250MHz */
 752                         chan->AudioDTOValue = 0x66666666;
 753                         /* set_dto(chan, 38810700+1000); */
 754                         /* set_dto(chan, 19392658); */
 755                 }
 756                 if (chan->mode & NGENE_IO_TSIN)
 757                         chan->pBufferExchange = tsin_exchange;
 758                 /* ngwritel(0, 0x9310); */
 759                 spin_unlock_irq(&chan->state_lock);
 760         } else
 761                 ;/* printk(KERN_INFO DEVICE_NAME ": lock=%08x\n",
 762                            ngreadl(0x9310)); */
 763
 764         ret = ngene_command_stream_control(dev, chan->number,
 765                                            control, mode, flags);
 766         if (!ret)
 767                 chan->running = state;
 768         else
 769                 printk(KERN_ERR DEVICE_NAME ": set_transfer %d failed\n",
 770                        state);
 771         if (!state) {
 772                 spin_lock_irq(&chan->state_lock);
 773                 chan->pBufferExchange = NULL;
 774                 dvb_ringbuffer_flush(&dev->tsout_rbuf);
 775                 spin_unlock_irq(&chan->state_lock);
 776         }
 777 }
 778
 779
 780 /****************************************************************************/
 781 /* nGene hardware init and release functions ********************************/
 782 /****************************************************************************/
 783
 784 static void free_ringbuffer(struct ngene *dev, struct SRingBufferDescriptor *rb)
 785 {
 786         struct SBufferHeader *Cur = rb->Head;
 787         u32 j;
 788
 789         if (!Cur)
 790                 return;
 791
 792         for (j = 0; j < rb->NumBuffers; j++, Cur = Cur->Next) {
 793                 if (Cur->Buffer1)
 794                         pci_free_consistent(dev->pci_dev,
 795                                             rb->Buffer1Length,
 796                                             Cur->Buffer1,
 797                                             Cur->scList1->Address);
 798
 799                 if (Cur->Buffer2)
 800                         pci_free_consistent(dev->pci_dev,
 801                                             rb->Buffer2Length,
 802                                             Cur->Buffer2,
 803                                             Cur->scList2->Address);
 804         }
 805
 806         if (rb->SCListMem)
 807                 pci_free_consistent(dev->pci_dev, rb->SCListMemSize,
 808                                     rb->SCListMem, rb->PASCListMem);
 809
 810         pci_free_consistent(dev->pci_dev, rb->MemSize, rb->Head, rb->PAHead);
 811 }
 812
 813 static void free_idlebuffer(struct ngene *dev,
 814                      struct SRingBufferDescriptor *rb,
 815                      struct SRingBufferDescriptor *tb)
 816 {
 817         int j;
 818         struct SBufferHeader *Cur = tb->Head;
 819
 820         if (!rb->Head)
 821                 return;
 822         free_ringbuffer(dev, rb);
 823         for (j = 0; j < tb->NumBuffers; j++, Cur = Cur->Next) {
 824                 Cur->Buffer2 = NULL;
 825                 Cur->scList2 = NULL;
 826                 Cur->ngeneBuffer.Address_of_first_entry_2 = 0;
 827                 Cur->ngeneBuffer.Number_of_entries_2 = 0;
 828         }
 829 }
 830
 831 static void free_common_buffers(struct ngene *dev)
 832 {
 833         u32 i;
 834         struct ngene_channel *chan;
 835
 836         for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) {
 837                 chan = &dev->channel[i];
 838                 free_idlebuffer(dev, &chan->TSIdleBuffer, &chan->TSRingBuffer);
 839                 free_ringbuffer(dev, &chan->RingBuffer);
 840                 free_ringbuffer(dev, &chan->TSRingBuffer);
 841         }
 842
 843         if (dev->OverflowBuffer)
 844                 pci_free_consistent(dev->pci_dev,
 845                                     OVERFLOW_BUFFER_SIZE,
 846                                     dev->OverflowBuffer, dev->PAOverflowBuffer);
 847
 848         if (dev->FWInterfaceBuffer)
 849                 pci_free_consistent(dev->pci_dev,
 850                                     4096,
 851                                     dev->FWInterfaceBuffer,
 852                                     dev->PAFWInterfaceBuffer);
 853 }
 854
 855 /****************************************************************************/
 856 /* Ring buffer handling *****************************************************/
 857 /****************************************************************************/
 858
 859 static int create_ring_buffer(struct pci_dev *pci_dev,
 860                        struct SRingBufferDescriptor *descr, u32 NumBuffers)
 861 {
 862         dma_addr_t tmp;
 863         struct SBufferHeader *Head;
 864         u32 i;
 865         u32 MemSize = SIZEOF_SBufferHeader * NumBuffers;
 866         u64 PARingBufferHead;
 867         u64 PARingBufferCur;
 868         u64 PARingBufferNext;
 869         struct SBufferHeader *Cur, *Next;
 870
 871         descr->Head = NULL;
 872         descr->MemSize = 0;
 873         descr->PAHead = 0;
 874         descr->NumBuffers = 0;
 875
 876         if (MemSize < 4096)
 877                 MemSize = 4096;
 878
 879         Head = pci_alloc_consistent(pci_dev, MemSize, &tmp);
 880         PARingBufferHead = tmp;
 881
 882         if (!Head)
 883                 return -ENOMEM;
 884
 885         memset(Head, 0, MemSize);
 886
 887         PARingBufferCur = PARingBufferHead;
 888         Cur = Head;
 889
 890         for (i = 0; i < NumBuffers - 1; i++) {
 891                 Next = (struct SBufferHeader *)
 892                         (((u8 *) Cur) + SIZEOF_SBufferHeader);
 893                 PARingBufferNext = PARingBufferCur + SIZEOF_SBufferHeader;
 894                 Cur->Next = Next;
 895                 Cur->ngeneBuffer.Next = PARingBufferNext;
 896                 Cur = Next;
 897                 PARingBufferCur = PARingBufferNext;
 898         }
 899         /* Last Buffer points back to first one */
 900         Cur->Next = Head;
 901         Cur->ngeneBuffer.Next = PARingBufferHead;
 902
 903         descr->Head       = Head;
 904         descr->MemSize    = MemSize;
 905         descr->PAHead     = PARingBufferHead;
 906         descr->NumBuffers = NumBuffers;
 907
 908         return 0;
 909 }
 910
 911 static int AllocateRingBuffers(struct pci_dev *pci_dev,
 912                                dma_addr_t of,
 913                                struct SRingBufferDescriptor *pRingBuffer,
 914                                u32 Buffer1Length, u32 Buffer2Length)
 915 {
 916         dma_addr_t tmp;
 917         u32 i, j;
 918         int status = 0;
 919         u32 SCListMemSize = pRingBuffer->NumBuffers
 920                 * ((Buffer2Length != 0) ? (NUM_SCATTER_GATHER_ENTRIES * 2) :
 921                     NUM_SCATTER_GATHER_ENTRIES)
 922                 * sizeof(struct HW_SCATTER_GATHER_ELEMENT);
 923
 924         u64 PASCListMem;
 925         struct HW_SCATTER_GATHER_ELEMENT *SCListEntry;
 926         u64 PASCListEntry;
 927         struct SBufferHeader *Cur;
 928         void *SCListMem;
 929
 930         if (SCListMemSize < 4096)
 931                 SCListMemSize = 4096;
 932
 933         SCListMem = pci_alloc_consistent(pci_dev, SCListMemSize, &tmp);
 934
 935         PASCListMem = tmp;
 936         if (SCListMem == NULL)
 937                 return -ENOMEM;
 938
 939         memset(SCListMem, 0, SCListMemSize);
 940
 941         pRingBuffer->SCListMem = SCListMem;
 942         pRingBuffer->PASCListMem = PASCListMem;
 943         pRingBuffer->SCListMemSize = SCListMemSize;
 944         pRingBuffer->Buffer1Length = Buffer1Length;
 945         pRingBuffer->Buffer2Length = Buffer2Length;
 946
 947         SCListEntry = SCListMem;
 948         PASCListEntry = PASCListMem;
 949         Cur = pRingBuffer->Head;
 950
 951         for (i = 0; i < pRingBuffer->NumBuffers; i += 1, Cur = Cur->Next) {
 952                 u64 PABuffer;
 953
 954                 void *Buffer = pci_alloc_consistent(pci_dev, Buffer1Length,
 955                                                     &tmp);
 956                 PABuffer = tmp;
 957
 958                 if (Buffer == NULL)
 959                         return -ENOMEM;
 960
 961                 Cur->Buffer1 = Buffer;
 962
 963                 SCListEntry->Address = PABuffer;
 964                 SCListEntry->Length  = Buffer1Length;
 965
 966                 Cur->scList1 = SCListEntry;
 967                 Cur->ngeneBuffer.Address_of_first_entry_1 = PASCListEntry;
 968                 Cur->ngeneBuffer.Number_of_entries_1 =
 969                         NUM_SCATTER_GATHER_ENTRIES;
 970
 971                 SCListEntry += 1;
 972                 PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT);
 973
 974 #if NUM_SCATTER_GATHER_ENTRIES > 1
 975                 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j += 1) {
 976                         SCListEntry->Address = of;
 977                         SCListEntry->Length = OVERFLOW_BUFFER_SIZE;
 978                         SCListEntry += 1;
 979                         PASCListEntry +=
 980                                 sizeof(struct HW_SCATTER_GATHER_ELEMENT);
 981                 }
 982 #endif
 983
 984                 if (!Buffer2Length)
 985                         continue;
 986
 987                 Buffer = pci_alloc_consistent(pci_dev, Buffer2Length, &tmp);
 988                 PABuffer = tmp;
 989
 990                 if (Buffer == NULL)
 991                         return -ENOMEM;
 992
 993                 Cur->Buffer2 = Buffer;
 994
 995                 SCListEntry->Address = PABuffer;
 996                 SCListEntry->Length  = Buffer2Length;
 997
 998                 Cur->scList2 = SCListEntry;
 999                 Cur->ngeneBuffer.Address_of_first_entry_2 = PASCListEntry;
1000                 Cur->ngeneBuffer.Number_of_entries_2 =
1001                         NUM_SCATTER_GATHER_ENTRIES;
1002
1003                 SCListEntry   += 1;
1004                 PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1005
1006 #if NUM_SCATTER_GATHER_ENTRIES > 1
1007                 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j++) {
1008                         SCListEntry->Address = of;
1009                         SCListEntry->Length = OVERFLOW_BUFFER_SIZE;
1010                         SCListEntry += 1;
1011                         PASCListEntry +=
1012                                 sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1013                 }
1014 #endif
1015
1016         }
1017
1018         return status;
1019 }
1020
1021 static int FillTSIdleBuffer(struct SRingBufferDescriptor *pIdleBuffer,
1022                             struct SRingBufferDescriptor *pRingBuffer)
1023 {
1024         int status = 0;
1025
1026         /* Copy pointer to scatter gather list in TSRingbuffer
1027            structure for buffer 2
1028            Load number of buffer
1029         */
1030         u32 n = pRingBuffer->NumBuffers;
1031
1032         /* Point to first buffer entry */
1033         struct SBufferHeader *Cur = pRingBuffer->Head;
1034         int i;
1035         /* Loop thru all buffer and set Buffer 2 pointers to TSIdlebuffer */
1036         for (i = 0; i < n; i++) {
1037                 Cur->Buffer2 = pIdleBuffer->Head->Buffer1;
1038                 Cur->scList2 = pIdleBuffer->Head->scList1;
1039                 Cur->ngeneBuffer.Address_of_first_entry_2 =
1040                         pIdleBuffer->Head->ngeneBuffer.
1041                         Address_of_first_entry_1;
1042                 Cur->ngeneBuffer.Number_of_entries_2 =
1043                         pIdleBuffer->Head->ngeneBuffer.Number_of_entries_1;
1044                 Cur = Cur->Next;
1045         }
1046         return status;
1047 }
1048
1049 static u32 RingBufferSizes[MAX_STREAM] = {
1050         RING_SIZE_VIDEO,
1051         RING_SIZE_VIDEO,
1052         RING_SIZE_AUDIO,
1053         RING_SIZE_AUDIO,
1054         RING_SIZE_AUDIO,
1055 };
1056
1057 static u32 Buffer1Sizes[MAX_STREAM] = {
1058         MAX_VIDEO_BUFFER_SIZE,
1059         MAX_VIDEO_BUFFER_SIZE,
1060         MAX_AUDIO_BUFFER_SIZE,
1061         MAX_AUDIO_BUFFER_SIZE,
1062         MAX_AUDIO_BUFFER_SIZE
1063 };
1064
1065 static u32 Buffer2Sizes[MAX_STREAM] = {
1066         MAX_VBI_BUFFER_SIZE,
1067         MAX_VBI_BUFFER_SIZE,
1068         0,
1069         0,
1070         0
1071 };
1072
1073
1074 static int AllocCommonBuffers(struct ngene *dev)
1075 {
1076         int status = 0, i;
1077
1078         dev->FWInterfaceBuffer = pci_alloc_consistent(dev->pci_dev, 4096,
1079                                                      &dev->PAFWInterfaceBuffer);
1080         if (!dev->FWInterfaceBuffer)
1081                 return -ENOMEM;
1082         dev->hosttongene = dev->FWInterfaceBuffer;
1083         dev->ngenetohost = dev->FWInterfaceBuffer + 256;
1084         dev->EventBuffer = dev->FWInterfaceBuffer + 512;
1085
1086         dev->OverflowBuffer = pci_alloc_consistent(dev->pci_dev,
1087                                                    OVERFLOW_BUFFER_SIZE,
1088                                                    &dev->PAOverflowBuffer);
1089         if (!dev->OverflowBuffer)
1090                 return -ENOMEM;
1091         memset(dev->OverflowBuffer, 0, OVERFLOW_BUFFER_SIZE);
1092
1093         for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) {
1094                 int type = dev->card_info->io_type[i];
1095
1096                 dev->channel[i].State = KSSTATE_STOP;
1097
1098                 if (type & (NGENE_IO_TV | NGENE_IO_HDTV | NGENE_IO_AIN)) {
1099                         status = create_ring_buffer(dev->pci_dev,
1100                                                     &dev->channel[i].RingBuffer,
1101                                                     RingBufferSizes[i]);
1102                         if (status < 0)
1103                                 break;
1104
1105                         if (type & (NGENE_IO_TV | NGENE_IO_AIN)) {
1106                                 status = AllocateRingBuffers(dev->pci_dev,
1107                                                              dev->
1108                                                              PAOverflowBuffer,
1109                                                              &dev->channel[i].
1110                                                              RingBuffer,
1111                                                              Buffer1Sizes[i],
1112                                                              Buffer2Sizes[i]);
1113                                 if (status < 0)
1114                                         break;
1115                         } else if (type & NGENE_IO_HDTV) {
1116                                 status = AllocateRingBuffers(dev->pci_dev,
1117                                                              dev->
1118                                                              PAOverflowBuffer,
1119                                                              &dev->channel[i].
1120                                                              RingBuffer,
1121                                                            MAX_HDTV_BUFFER_SIZE,
1122                                                              0);
1123                                 if (status < 0)
1124                                         break;
1125                         }
1126                 }
1127
1128                 if (type & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
1129
1130                         status = create_ring_buffer(dev->pci_dev,
1131                                                     &dev->channel[i].
1132                                                     TSRingBuffer, RING_SIZE_TS);
1133                         if (status < 0)
1134                                 break;
1135
1136                         status = AllocateRingBuffers(dev->pci_dev,
1137                                                      dev->PAOverflowBuffer,
1138                                                      &dev->channel[i].
1139                                                      TSRingBuffer,
1140                                                      MAX_TS_BUFFER_SIZE, 0);
1141                         if (status)
1142                                 break;
1143                 }
1144
1145                 if (type & NGENE_IO_TSOUT) {
1146                         status = create_ring_buffer(dev->pci_dev,
1147                                                     &dev->channel[i].
1148                                                     TSIdleBuffer, 1);
1149                         if (status < 0)
1150                                 break;
1151                         status = AllocateRingBuffers(dev->pci_dev,
1152                                                      dev->PAOverflowBuffer,
1153                                                      &dev->channel[i].
1154                                                      TSIdleBuffer,
1155                                                      MAX_TS_BUFFER_SIZE, 0);
1156                         if (status)
1157                                 break;
1158                         FillTSIdleBuffer(&dev->channel[i].TSIdleBuffer,
1159                                          &dev->channel[i].TSRingBuffer);
1160                 }
1161         }
1162         return status;
1163 }
1164
1165 static void ngene_release_buffers(struct ngene *dev)
1166 {
1167         if (dev->iomem)
1168                 iounmap(dev->iomem);
1169         free_common_buffers(dev);
1170         vfree(dev->tsout_buf);
1171         vfree(dev->ain_buf);
1172         vfree(dev->vin_buf);
1173         vfree(dev);
1174 }
1175
1176 static int ngene_get_buffers(struct ngene *dev)
1177 {
1178         if (AllocCommonBuffers(dev))
1179                 return -ENOMEM;
1180         if (dev->card_info->io_type[4] & NGENE_IO_TSOUT) {
1181                 dev->tsout_buf = vmalloc(TSOUT_BUF_SIZE);
1182                 if (!dev->tsout_buf)
1183                         return -ENOMEM;
1184                 dvb_ringbuffer_init(&dev->tsout_rbuf,
1185                                     dev->tsout_buf, TSOUT_BUF_SIZE);
1186         }
1187         if (dev->card_info->io_type[2] & NGENE_IO_AIN) {
1188                 dev->ain_buf = vmalloc(AIN_BUF_SIZE);
1189                 if (!dev->ain_buf)
1190                         return -ENOMEM;
1191                 dvb_ringbuffer_init(&dev->ain_rbuf, dev->ain_buf, AIN_BUF_SIZE);
1192         }
1193         if (dev->card_info->io_type[0] & NGENE_IO_HDTV) {
1194                 dev->vin_buf = vmalloc(VIN_BUF_SIZE);
1195                 if (!dev->vin_buf)
1196                         return -ENOMEM;
1197                 dvb_ringbuffer_init(&dev->vin_rbuf, dev->vin_buf, VIN_BUF_SIZE);
1198         }
1199         dev->iomem = ioremap(pci_resource_start(dev->pci_dev, 0),
1200                              pci_resource_len(dev->pci_dev, 0));
1201         if (!dev->iomem)
1202                 return -ENOMEM;
1203
1204         return 0;
1205 }
1206
1207 static void ngene_init(struct ngene *dev)
1208 {
1209         int i;
1210
1211         tasklet_init(&dev->event_tasklet, event_tasklet, (unsigned long)dev);
1212
1213         memset_io(dev->iomem + 0xc000, 0x00, 0x220);
1214         memset_io(dev->iomem + 0xc400, 0x00, 0x100);
1215
1216         for (i = 0; i < MAX_STREAM; i++) {
1217                 dev->channel[i].dev = dev;
1218                 dev->channel[i].number = i;
1219         }
1220
1221         dev->fw_interface_version = 0;
1222
1223         ngwritel(0, NGENE_INT_ENABLE);
1224
1225         dev->icounts = ngreadl(NGENE_INT_COUNTS);
1226
1227         dev->device_version = ngreadl(DEV_VER) & 0x0f;
1228         printk(KERN_INFO DEVICE_NAME ": Device version %d\n",
1229                dev->device_version);
1230 }
1231
1232 static int ngene_load_firm(struct ngene *dev)
1233 {
1234         u32 size;
1235         const struct firmware *fw = NULL;
1236         u8 *ngene_fw;
1237         char *fw_name;
1238         int err, version;
1239
1240         version = dev->card_info->fw_version;
1241
1242         switch (version) {
1243         default:
1244         case 15:
1245                 version = 15;
1246                 size = 23466;
1247                 fw_name = "ngene_15.fw";
1248                 dev->cmd_timeout_workaround = true;
1249                 break;
1250         case 16:
1251                 size = 23498;
1252                 fw_name = "ngene_16.fw";
1253                 dev->cmd_timeout_workaround = true;
1254                 break;
1255         case 17:
1256                 size = 24446;
1257                 fw_name = "ngene_17.fw";
1258                 dev->cmd_timeout_workaround = true;
1259                 break;
1260         }
1261
1262         if (request_firmware(&fw, fw_name, &dev->pci_dev->dev) < 0) {
1263                 printk(KERN_ERR DEVICE_NAME
1264                         ": Could not load firmware file %s.\n", fw_name);
1265                 printk(KERN_INFO DEVICE_NAME
1266                         ": Copy %s to your hotplug directory!\n", fw_name);
1267                 return -1;
1268         }
1269         if (size != fw->size) {
1270                 printk(KERN_ERR DEVICE_NAME
1271                         ": Firmware %s has invalid size!", fw_name);
1272                 err = -1;
1273         } else {
1274                 printk(KERN_INFO DEVICE_NAME
1275                         ": Loading firmware file %s.\n", fw_name);
1276                 ngene_fw = (u8 *) fw->data;
1277                 err = ngene_command_load_firmware(dev, ngene_fw, size);
1278         }
1279
1280         release_firmware(fw);
1281
1282         return err;
1283 }
1284
1285 static void ngene_stop(struct ngene *dev)
1286 {
1287         down(&dev->cmd_mutex);
1288         i2c_del_adapter(&(dev->channel[0].i2c_adapter));
1289         i2c_del_adapter(&(dev->channel[1].i2c_adapter));
1290         ngwritel(0, NGENE_INT_ENABLE);
1291         ngwritel(0, NGENE_COMMAND);
1292         ngwritel(0, NGENE_COMMAND_HI);
1293         ngwritel(0, NGENE_STATUS);
1294         ngwritel(0, NGENE_STATUS_HI);
1295         ngwritel(0, NGENE_EVENT);
1296         ngwritel(0, NGENE_EVENT_HI);
1297         free_irq(dev->pci_dev->irq, dev);
1298 #ifdef CONFIG_PCI_MSI
1299         if (dev->msi_enabled)
1300                 pci_disable_msi(dev->pci_dev);
1301 #endif
1302 }
1303
1304 static int ngene_start(struct ngene *dev)
1305 {
1306         int stat;
1307         unsigned long flags;
1308         int i;
1309
1310         pci_set_master(dev->pci_dev);
1311         ngene_init(dev);
1312
1313         stat = request_irq(dev->pci_dev->irq, irq_handler,
1314                            IRQF_SHARED, "nGene",
1315                            (void *)dev);
1316         if (stat < 0)
1317                 return stat;
1318
1319         init_waitqueue_head(&dev->cmd_wq);
1320         init_waitqueue_head(&dev->tx_wq);
1321         init_waitqueue_head(&dev->rx_wq);
1322         sema_init(&dev->cmd_mutex, 1);
1323         sema_init(&dev->stream_mutex, 1);
1324         sema_init(&dev->pll_mutex, 1);
1325         sema_init(&dev->i2c_switch_mutex, 1);
1326         spin_lock_init(&dev->cmd_lock);
1327         for (i = 0; i < MAX_STREAM; i++)
1328                 spin_lock_init(&dev->channel[i].state_lock);
1329         ngwritel(1, TIMESTAMPS);
1330
1331         ngwritel(1, NGENE_INT_ENABLE);
1332
1333         stat = ngene_load_firm(dev);
1334         if (stat < 0)
1335                 goto fail;
1336
1337 #ifdef CONFIG_PCI_MSI
1338         /* enable MSI if kernel and card support it */
1339         if (pci_msi_enabled() && dev->card_info->msi_supported) {
1340                 ngwritel(0, NGENE_INT_ENABLE);
1341                 free_irq(dev->pci_dev->irq, dev);
1342                 stat = pci_enable_msi(dev->pci_dev);
1343                 if (stat) {
1344                         printk(KERN_INFO DEVICE_NAME
1345                                 ": MSI not available\n");
1346                         flags = IRQF_SHARED;
1347                 } else {
1348                         flags = 0;
1349                         dev->msi_enabled = true;
1350                 }
1351                 stat = request_irq(dev->pci_dev->irq, irq_handler,
1352                                         flags, "nGene", dev);
1353                 if (stat < 0)
1354                         goto fail2;
1355                 ngwritel(1, NGENE_INT_ENABLE);
1356         }
1357 #endif
1358
1359         stat = ngene_i2c_init(dev, 0);
1360         if (stat < 0)
1361                 goto fail;
1362
1363         stat = ngene_i2c_init(dev, 1);
1364         if (stat < 0)
1365                 goto fail;
1366
1367         if (dev->card_info->fw_version == 17) {
1368                 u8 tsin4_config[6] = {
1369                         3072 / 64, 3072 / 64, 0, 3072 / 64, 3072 / 64, 0};
1370                 u8 default_config[6] = {
1371                         4096 / 64, 4096 / 64, 0, 2048 / 64, 2048 / 64, 0};
1372                 u8 *bconf = default_config;
1373
1374                 if (dev->card_info->io_type[3] == NGENE_IO_TSIN)
1375                         bconf = tsin4_config;
1376                 dprintk(KERN_DEBUG DEVICE_NAME ": FW 17 buffer config\n");
1377                 stat = ngene_command_config_free_buf(dev, bconf);
1378         } else {
1379                 int bconf = BUFFER_CONFIG_4422;
1380                 if (dev->card_info->io_type[3] == NGENE_IO_TSIN)
1381                         bconf = BUFFER_CONFIG_3333;
1382                 stat = ngene_command_config_buf(dev, bconf);
1383         }
1384         if (!stat)
1385                 return stat;
1386
1387         /* otherwise error: fall through */
1388 fail:
1389         ngwritel(0, NGENE_INT_ENABLE);
1390         free_irq(dev->pci_dev->irq, dev);
1391 #ifdef CONFIG_PCI_MSI
1392 fail2:
1393         if (dev->msi_enabled)
1394                 pci_disable_msi(dev->pci_dev);
1395 #endif
1396         return stat;
1397 }
1398
1399
1400
1401
1402 /****************************************************************************/
1403 /****************************************************************************/
1404 /****************************************************************************/
1405
1406 static void release_channel(struct ngene_channel *chan)
1407 {
1408         struct dvb_demux *dvbdemux = &chan->demux;
1409         struct ngene *dev = chan->dev;
1410         struct ngene_info *ni = dev->card_info;
1411         int io = ni->io_type[chan->number];
1412
1413         if (chan->dev->cmd_timeout_workaround && chan->running)
1414                 set_transfer(chan, 0);
1415
1416         tasklet_kill(&chan->demux_tasklet);
1417
1418         if (io & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
1419                 if (chan->fe) {
1420                         dvb_unregister_frontend(chan->fe);
1421                         dvb_frontend_detach(chan->fe);
1422                         chan->fe = NULL;
1423                 }
1424                 dvbdemux->dmx.close(&dvbdemux->dmx);
1425                 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
1426                                               &chan->hw_frontend);
1427                 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
1428                                               &chan->mem_frontend);
1429                 dvb_dmxdev_release(&chan->dmxdev);
1430                 dvb_dmx_release(&chan->demux);
1431
1432                 if (chan->number == 0 || !one_adapter)
1433                         dvb_unregister_adapter(&dev->adapter[chan->number]);
1434         }
1435 }
1436
1437 static int init_channel(struct ngene_channel *chan)
1438 {
1439         int ret = 0, nr = chan->number;
1440         struct dvb_adapter *adapter = NULL;
1441         struct dvb_demux *dvbdemux = &chan->demux;
1442         struct ngene *dev = chan->dev;
1443         struct ngene_info *ni = dev->card_info;
1444         int io = ni->io_type[nr];
1445
1446         tasklet_init(&chan->demux_tasklet, demux_tasklet, (unsigned long)chan);
1447         chan->users = 0;
1448         chan->type = io;
1449         chan->mode = chan->type;        /* for now only one mode */
1450
1451         if (io & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
1452                 if (nr >= STREAM_AUDIOIN1)
1453                         chan->DataFormatFlags = DF_SWAP32;
1454                 if (nr == 0 || !one_adapter || dev->first_adapter == NULL) {
1455                         adapter = &dev->adapter[nr];
1456                         ret = dvb_register_adapter(adapter, "nGene",
1457                                                    THIS_MODULE,
1458                                                    &chan->dev->pci_dev->dev,
1459                                                    adapter_nr);
1460                         if (ret < 0)
1461                                 return ret;
1462                         if (dev->first_adapter == NULL)
1463                                 dev->first_adapter = adapter;
1464                 } else {
1465                         adapter = dev->first_adapter;
1466                 }
1467
1468                 ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux",
1469                                               ngene_start_feed,
1470                                               ngene_stop_feed, chan);
1471                 ret = my_dvb_dmxdev_ts_card_init(&chan->dmxdev, &chan->demux,
1472                                                  &chan->hw_frontend,
1473                                                  &chan->mem_frontend, adapter);
1474         }
1475
1476         if (io & NGENE_IO_TSIN) {
1477                 chan->fe = NULL;
1478                 if (ni->demod_attach[nr])
1479                         ni->demod_attach[nr](chan);
1480                 if (chan->fe) {
1481                         if (dvb_register_frontend(adapter, chan->fe) < 0) {
1482                                 if (chan->fe->ops.release)
1483                                         chan->fe->ops.release(chan->fe);
1484                                 chan->fe = NULL;
1485                         }
1486                 }
1487                 if (chan->fe && ni->tuner_attach[nr])
1488                         if (ni->tuner_attach[nr] (chan) < 0) {
1489                                 printk(KERN_ERR DEVICE_NAME
1490                                        ": Tuner attach failed on channel %d!\n",
1491                                        nr);
1492                         }
1493         }
1494         return ret;
1495 }
1496
1497 static int init_channels(struct ngene *dev)
1498 {
1499         int i, j;
1500
1501         for (i = 0; i < MAX_STREAM; i++) {
1502                 dev->channel[i].number = i;
1503                 if (init_channel(&dev->channel[i]) < 0) {
1504                         for (j = i - 1; j >= 0; j--)
1505                                 release_channel(&dev->channel[j]);
1506                         return -1;
1507                 }
1508         }
1509         return 0;
1510 }
1511
1512 /****************************************************************************/
1513 /* device probe/remove calls ************************************************/
1514 /****************************************************************************/
1515
1516 void __devexit ngene_remove(struct pci_dev *pdev)
1517 {
1518         struct ngene *dev = (struct ngene *)pci_get_drvdata(pdev);
1519         int i;
1520
1521         tasklet_kill(&dev->event_tasklet);
1522         for (i = MAX_STREAM - 1; i >= 0; i--)
1523                 release_channel(&dev->channel[i]);
1524         ngene_stop(dev);
1525         ngene_release_buffers(dev);
1526         pci_set_drvdata(pdev, NULL);
1527         pci_disable_device(pdev);
1528 }
1529
1530 int __devinit ngene_probe(struct pci_dev *pci_dev,
1531                           const struct pci_device_id *id)
1532 {
1533         struct ngene *dev;
1534         int stat = 0;
1535
1536         if (pci_enable_device(pci_dev) < 0)
1537                 return -ENODEV;
1538
1539         dev = vmalloc(sizeof(struct ngene));
1540         if (dev == NULL) {
1541                 stat = -ENOMEM;
1542                 goto fail0;
1543         }
1544         memset(dev, 0, sizeof(struct ngene));
1545
1546         dev->pci_dev = pci_dev;
1547         dev->card_info = (struct ngene_info *)id->driver_data;
1548         printk(KERN_INFO DEVICE_NAME ": Found %s\n", dev->card_info->name);
1549
1550         pci_set_drvdata(pci_dev, dev);
1551
1552         /* Alloc buffers and start nGene */
1553         stat = ngene_get_buffers(dev);
1554         if (stat < 0)
1555                 goto fail1;
1556         stat = ngene_start(dev);
1557         if (stat < 0)
1558                 goto fail1;
1559
1560         dev->i2c_current_bus = -1;
1561
1562         /* Register DVB adapters and devices for both channels */
1563         if (init_channels(dev) < 0)
1564                 goto fail2;
1565
1566         return 0;
1567
1568 fail2:
1569         ngene_stop(dev);
1570 fail1:
1571         ngene_release_buffers(dev);
1572 fail0:
1573         pci_disable_device(pci_dev);
1574         pci_set_drvdata(pci_dev, NULL);
1575         return stat;
1576 }