2 * drxd_hard.c: DVB-T Demodulator Micronas DRX3975D-A2,DRX397xD-B1
4 * Copyright (C) 2003-2007 Micronas
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 only, as published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
21 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/init.h>
28 #include <linux/delay.h>
29 #include <linux/firmware.h>
30 #include <linux/i2c.h>
31 #include <asm/div64.h>
33 #include "dvb_frontend.h"
35 #include "drxd_firm.h"
37 #define DRX_FW_FILENAME_A2 "drxd-a2-1.1.fw"
38 #define DRX_FW_FILENAME_B1 "drxd-b1-1.1.fw"
42 #define DRX_I2C_RMW 0x10
43 #define DRX_I2C_BROADCAST 0x20
44 #define DRX_I2C_CLEARCRC 0x80
45 #define DRX_I2C_SINGLE_MASTER 0xC0
46 #define DRX_I2C_MODEFLAGS 0xC0
47 #define DRX_I2C_FLAGS 0xF0
50 #define SIZEOF_ARRAY(array) (sizeof((array))/sizeof((array)[0]))
53 #define DEFAULT_LOCK_TIMEOUT 1100
55 #define DRX_CHANNEL_AUTO 0
56 #define DRX_CHANNEL_HIGH 1
57 #define DRX_CHANNEL_LOW 2
59 #define DRX_LOCK_MPEG 1
60 #define DRX_LOCK_FEC 2
61 #define DRX_LOCK_DEMOD 4
63 /****************************************************************************/
72 DRXD_UNINITIALIZED = 0,
85 OM_DVBT_Diversity_Front,
90 enum AGC_CTRL_MODE ctrlMode;
91 u16 outputLevel; /* range [0, ... , 1023], 1/n of fullscale range */
92 u16 settleLevel; /* range [0, ... , 1023], 1/n of fullscale range */
93 u16 minOutputLevel; /* range [0, ... , 1023], 1/n of fullscale range */
94 u16 maxOutputLevel; /* range [0, ... , 1023], 1/n of fullscale range */
95 u16 speed; /* range [0, ... , 1023], 1/n of fullscale range */
117 IFFILTER_DISCRETE = 1
121 struct dvb_frontend frontend;
122 struct dvb_frontend_ops ops;
123 struct dvb_frontend_parameters param;
125 const struct firmware *fw;
128 struct i2c_adapter *i2c;
130 struct drxd_config config;
137 u16 hi_cfg_timing_div;
138 u16 hi_cfg_bridge_delay;
139 u16 hi_cfg_wakeup_key;
142 u16 intermediate_freq;
145 enum CSCDState cscd_state;
146 enum CDrxdState drxd_state;
149 s16 osc_clock_deviation;
150 u16 expected_sys_clock_freq;
157 struct SCfgAgc if_agc_cfg;
158 struct SCfgAgc rf_agc_cfg;
160 struct SNoiseCal noise_cal;
163 u32 org_fe_fs_add_incr;
164 u16 current_fe_if_incr;
167 u16 m_FeAgRegAgAgcSio;
169 u16 m_EcOcRegOcModeLop;
170 u16 m_EcOcRegSncSncLvl;
171 u8 *m_InitAtomicRead;
183 u8 *m_InitDiversityFront;
184 u8 *m_InitDiversityEnd;
185 u8 *m_DisableDiversity;
186 u8 *m_StartDiversityFront;
187 u8 *m_StartDiversityEnd;
189 u8 *m_DiversityDelay8MHZ;
190 u8 *m_DiversityDelay6MHZ;
193 u32 microcode_length;
200 enum app_env app_env_default;
201 enum app_env app_env_diversity;
205 /****************************************************************************/
206 /* I2C **********************************************************************/
207 /****************************************************************************/
209 static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 * data, int len)
211 struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = data, .len = len };
213 if (i2c_transfer(adap, &msg, 1) != 1)
218 static int i2c_read(struct i2c_adapter *adap,
219 u8 adr, u8 *msg, int len, u8 *answ, int alen)
221 struct i2c_msg msgs[2] = {
223 .addr = adr, .flags = 0,
224 .buf = msg, .len = len
226 .addr = adr, .flags = I2C_M_RD,
227 .buf = answ, .len = alen
230 if (i2c_transfer(adap, msgs, 2) != 2)
235 static inline u32 MulDiv32(u32 a, u32 b, u32 c)
239 tmp64 = (u64)a * (u64)b;
245 static int Read16(struct drxd_state *state, u32 reg, u16 *data, u8 flags)
247 u8 adr = state->config.demod_address;
248 u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff,
249 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
252 if (i2c_read(state->i2c, adr, mm1, 4, mm2, 2) < 0)
255 *data = mm2[0] | (mm2[1] << 8);
256 return mm2[0] | (mm2[1] << 8);
259 static int Read32(struct drxd_state *state, u32 reg, u32 *data, u8 flags)
261 u8 adr = state->config.demod_address;
262 u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff,
263 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
267 if (i2c_read(state->i2c, adr, mm1, 4, mm2, 4) < 0)
271 mm2[0] | (mm2[1] << 8) | (mm2[2] << 16) | (mm2[3] << 24);
275 static int Write16(struct drxd_state *state, u32 reg, u16 data, u8 flags)
277 u8 adr = state->config.demod_address;
278 u8 mm[6] = { reg & 0xff, (reg >> 16) & 0xff,
279 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff,
280 data & 0xff, (data >> 8) & 0xff
283 if (i2c_write(state->i2c, adr, mm, 6) < 0)
288 static int Write32(struct drxd_state *state, u32 reg, u32 data, u8 flags)
290 u8 adr = state->config.demod_address;
291 u8 mm[8] = { reg & 0xff, (reg >> 16) & 0xff,
292 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff,
293 data & 0xff, (data >> 8) & 0xff,
294 (data >> 16) & 0xff, (data >> 24) & 0xff
297 if (i2c_write(state->i2c, adr, mm, 8) < 0)
302 static int write_chunk(struct drxd_state *state,
303 u32 reg, u8 *data, u32 len, u8 flags)
305 u8 adr = state->config.demod_address;
306 u8 mm[CHUNK_SIZE + 4] = { reg & 0xff, (reg >> 16) & 0xff,
307 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
311 for (i = 0; i < len; i++)
313 if (i2c_write(state->i2c, adr, mm, 4 + len) < 0) {
314 printk(KERN_ERR "error in write_chunk\n");
320 static int WriteBlock(struct drxd_state *state,
321 u32 Address, u16 BlockSize, u8 *pBlock, u8 Flags)
323 while (BlockSize > 0) {
324 u16 Chunk = BlockSize > CHUNK_SIZE ? CHUNK_SIZE : BlockSize;
326 if (write_chunk(state, Address, pBlock, Chunk, Flags) < 0)
329 Address += (Chunk >> 1);
335 static int WriteTable(struct drxd_state *state, u8 * pTable)
344 u32 Address = pTable[0] | (pTable[1] << 8) |
345 (pTable[2] << 16) | (pTable[3] << 24);
347 if (Address == 0xFFFFFFFF)
349 pTable += sizeof(u32);
351 Length = pTable[0] | (pTable[1] << 8);
352 pTable += sizeof(u16);
355 status = WriteBlock(state, Address, Length * 2, pTable, 0);
356 pTable += (Length * 2);
361 /****************************************************************************/
362 /****************************************************************************/
363 /****************************************************************************/
365 static int ResetCEFR(struct drxd_state *state)
367 return WriteTable(state, state->m_ResetCEFR);
370 static int InitCP(struct drxd_state *state)
372 return WriteTable(state, state->m_InitCP);
375 static int InitCE(struct drxd_state *state)
378 enum app_env AppEnv = state->app_env_default;
381 status = WriteTable(state, state->m_InitCE);
385 if (state->operation_mode == OM_DVBT_Diversity_Front ||
386 state->operation_mode == OM_DVBT_Diversity_End) {
387 AppEnv = state->app_env_diversity;
389 if (AppEnv == APPENV_STATIC) {
390 status = Write16(state, CE_REG_TAPSET__A, 0x0000, 0);
393 } else if (AppEnv == APPENV_PORTABLE) {
394 status = Write16(state, CE_REG_TAPSET__A, 0x0001, 0);
397 } else if (AppEnv == APPENV_MOBILE && state->type_A) {
398 status = Write16(state, CE_REG_TAPSET__A, 0x0002, 0);
401 } else if (AppEnv == APPENV_MOBILE && !state->type_A) {
402 status = Write16(state, CE_REG_TAPSET__A, 0x0006, 0);
408 status = Write16(state, B_CE_REG_COMM_EXEC__A, 0x0001, 0);
415 static int StopOC(struct drxd_state *state)
419 u16 ocModeLop = state->m_EcOcRegOcModeLop;
424 /* Store output configuration */
425 status = Read16(state, EC_OC_REG_SNC_ISC_LVL__A, &ocSyncLvl, 0);
428 /* CHK_ERROR(Read16(EC_OC_REG_OC_MODE_LOP__A, &ocModeLop)); */
429 state->m_EcOcRegSncSncLvl = ocSyncLvl;
430 /* m_EcOcRegOcModeLop = ocModeLop; */
432 /* Flush FIFO (byte-boundary) at fixed rate */
433 status = Read16(state, EC_OC_REG_RCN_MAP_LOP__A, &dtoIncLop, 0);
436 status = Read16(state, EC_OC_REG_RCN_MAP_HIP__A, &dtoIncHip, 0);
439 status = Write16(state, EC_OC_REG_DTO_INC_LOP__A, dtoIncLop, 0);
442 status = Write16(state, EC_OC_REG_DTO_INC_HIP__A, dtoIncHip, 0);
445 ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M);
446 ocModeLop |= EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC;
447 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0);
450 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0);
455 /* Output pins to '0' */
456 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS__M, 0);
460 /* Force the OC out of sync */
461 ocSyncLvl &= ~(EC_OC_REG_SNC_ISC_LVL_OSC__M);
462 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, ocSyncLvl, 0);
465 ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M);
466 ocModeLop |= EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE;
467 ocModeLop |= 0x2; /* Magically-out-of-sync */
468 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0);
471 status = Write16(state, EC_OC_REG_COMM_INT_STA__A, 0x0, 0);
474 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0);
482 static int StartOC(struct drxd_state *state)
488 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0);
492 /* Restore output configuration */
493 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, state->m_EcOcRegSncSncLvl, 0);
496 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, state->m_EcOcRegOcModeLop, 0);
500 /* Output pins active again */
501 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS_INIT, 0);
506 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0);
513 static int InitEQ(struct drxd_state *state)
515 return WriteTable(state, state->m_InitEQ);
518 static int InitEC(struct drxd_state *state)
520 return WriteTable(state, state->m_InitEC);
523 static int InitSC(struct drxd_state *state)
525 return WriteTable(state, state->m_InitSC);
528 static int InitAtomicRead(struct drxd_state *state)
530 return WriteTable(state, state->m_InitAtomicRead);
533 static int CorrectSysClockDeviation(struct drxd_state *state);
535 static int DRX_GetLockStatus(struct drxd_state *state, u32 * pLockStatus)
538 const u16 mpeg_lock_mask = (SC_RA_RAM_LOCK_MPEG__M |
539 SC_RA_RAM_LOCK_FEC__M |
540 SC_RA_RAM_LOCK_DEMOD__M);
541 const u16 fec_lock_mask = (SC_RA_RAM_LOCK_FEC__M |
542 SC_RA_RAM_LOCK_DEMOD__M);
543 const u16 demod_lock_mask = SC_RA_RAM_LOCK_DEMOD__M;
549 status = Read16(state, SC_RA_RAM_LOCK__A, &ScRaRamLock, 0x0000);
551 printk(KERN_ERR "Can't read SC_RA_RAM_LOCK__A status = %08x\n", status);
555 if (state->drxd_state != DRXD_STARTED)
558 if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask) {
559 *pLockStatus |= DRX_LOCK_MPEG;
560 CorrectSysClockDeviation(state);
563 if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask)
564 *pLockStatus |= DRX_LOCK_FEC;
566 if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask)
567 *pLockStatus |= DRX_LOCK_DEMOD;
571 /****************************************************************************/
573 static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
577 if (cfg->outputLevel > DRXD_FE_CTRL_MAX)
580 if (cfg->ctrlMode == AGC_CTRL_USER) {
582 u16 FeAgRegPm1AgcWri;
583 u16 FeAgRegAgModeLop;
585 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0);
588 FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
589 FeAgRegAgModeLop |= FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC;
590 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0);
594 FeAgRegPm1AgcWri = (u16) (cfg->outputLevel &
595 FE_AG_REG_PM1_AGC_WRI__M);
596 status = Write16(state, FE_AG_REG_PM1_AGC_WRI__A, FeAgRegPm1AgcWri, 0);
600 } else if (cfg->ctrlMode == AGC_CTRL_AUTO) {
601 if (((cfg->maxOutputLevel) < (cfg->minOutputLevel)) ||
602 ((cfg->maxOutputLevel) > DRXD_FE_CTRL_MAX) ||
603 ((cfg->speed) > DRXD_FE_CTRL_MAX) ||
604 ((cfg->settleLevel) > DRXD_FE_CTRL_MAX)
608 u16 FeAgRegAgModeLop;
609 u16 FeAgRegEgcSetLvl;
614 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0);
617 FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
619 FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC;
620 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0);
624 /* == Settle level == */
626 FeAgRegEgcSetLvl = (u16) ((cfg->settleLevel >> 1) &
627 FE_AG_REG_EGC_SET_LVL__M);
628 status = Write16(state, FE_AG_REG_EGC_SET_LVL__A, FeAgRegEgcSetLvl, 0);
634 slope = (u16) ((cfg->maxOutputLevel -
635 cfg->minOutputLevel) / 2);
636 offset = (u16) ((cfg->maxOutputLevel +
637 cfg->minOutputLevel) / 2 - 511);
639 status = Write16(state, FE_AG_REG_GC1_AGC_RIC__A, slope, 0);
642 status = Write16(state, FE_AG_REG_GC1_AGC_OFF__A, offset, 0);
648 const u16 maxRur = 8;
649 const u16 slowIncrDecLUT[] = { 3, 4, 4, 5, 6 };
650 const u16 fastIncrDecLUT[] = { 14, 15, 15, 16,
657 u16 fineSteps = (DRXD_FE_CTRL_MAX + 1) /
659 u16 fineSpeed = (u16) (cfg->speed -
663 u16 invRurCount = (u16) (cfg->speed /
666 if (invRurCount > maxRur) {
668 fineSpeed += fineSteps;
670 rurCount = maxRur - invRurCount;
675 (2^(fineSpeed/fineSteps))
676 => range[default...2*default>
678 (2^(fineSpeed/fineSteps))
682 fastIncrDecLUT[fineSpeed /
686 slowIncrDecLUT[fineSpeed /
690 status = Write16(state, FE_AG_REG_EGC_RUR_CNT__A, rurCount, 0);
693 status = Write16(state, FE_AG_REG_EGC_FAS_INC__A, fastIncrDec, 0);
696 status = Write16(state, FE_AG_REG_EGC_FAS_DEC__A, fastIncrDec, 0);
699 status = Write16(state, FE_AG_REG_EGC_SLO_INC__A, slowIncrDec, 0);
702 status = Write16(state, FE_AG_REG_EGC_SLO_DEC__A, slowIncrDec, 0);
710 /* No OFF mode for IF control */
716 static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
720 if (cfg->outputLevel > DRXD_FE_CTRL_MAX)
723 if (cfg->ctrlMode == AGC_CTRL_USER) {
726 u16 level = (cfg->outputLevel);
728 if (level == DRXD_FE_CTRL_MAX)
731 status = Write16(state, FE_AG_REG_PM2_AGC_WRI__A, level, 0x0000);
737 /* Powerdown PD2, WRI source */
738 state->m_FeAgRegAgPwd &= ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
739 state->m_FeAgRegAgPwd |=
740 FE_AG_REG_AG_PWD_PWD_PD2_DISABLE;
741 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000);
745 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
748 AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
749 FE_AG_REG_AG_MODE_LOP_MODE_E__M));
750 AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
751 FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC);
752 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
756 /* enable AGC2 pin */
758 u16 FeAgRegAgAgcSio = 0;
759 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
763 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
765 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT;
766 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
772 } else if (cfg->ctrlMode == AGC_CTRL_AUTO) {
777 /* Automatic control */
778 /* Powerup PD2, AGC2 as output, TGC source */
779 (state->m_FeAgRegAgPwd) &=
780 ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
781 (state->m_FeAgRegAgPwd) |=
782 FE_AG_REG_AG_PWD_PWD_PD2_DISABLE;
783 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000);
787 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
790 AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
791 FE_AG_REG_AG_MODE_LOP_MODE_E__M));
792 AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
793 FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC);
794 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
798 level = (((cfg->settleLevel) >> 4) &
799 FE_AG_REG_TGC_SET_LVL__M);
800 status = Write16(state, FE_AG_REG_TGC_SET_LVL__A, level, 0x0000);
804 /* Min/max: don't care */
808 /* enable AGC2 pin */
810 u16 FeAgRegAgAgcSio = 0;
811 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
815 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
817 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT;
818 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
828 /* No RF AGC control */
829 /* Powerdown PD2, AGC2 as output, WRI source */
830 (state->m_FeAgRegAgPwd) &=
831 ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
832 (state->m_FeAgRegAgPwd) |=
833 FE_AG_REG_AG_PWD_PWD_PD2_ENABLE;
834 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000);
838 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
841 AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
842 FE_AG_REG_AG_MODE_LOP_MODE_E__M));
843 AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
844 FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC);
845 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
849 /* set FeAgRegAgAgcSio AGC2 (RF) as input */
851 u16 FeAgRegAgAgcSio = 0;
852 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
856 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
858 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT;
859 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
868 static int ReadIFAgc(struct drxd_state *state, u32 * pValue)
873 if (state->if_agc_cfg.ctrlMode != AGC_CTRL_OFF) {
875 status = Read16(state, FE_AG_REG_GC1_AGC_DAT__A, &Value, 0);
876 Value &= FE_AG_REG_GC1_AGC_DAT__M;
888 u32 R1 = state->if_agc_cfg.R1;
889 u32 R2 = state->if_agc_cfg.R2;
890 u32 R3 = state->if_agc_cfg.R3;
892 u32 Vmax, Rpar, Vmin, Vout;
894 if (R2 == 0 && (R1 == 0 || R3 == 0))
897 Vmax = (3300 * R2) / (R1 + R2);
898 Rpar = (R2 * R3) / (R3 + R2);
899 Vmin = (3300 * Rpar) / (R1 + Rpar);
900 Vout = Vmin + ((Vmax - Vmin) * Value) / 1024;
908 static int load_firmware(struct drxd_state *state, const char *fw_name)
910 const struct firmware *fw;
912 if (request_firmware(&fw, fw_name, state->dev) < 0) {
913 printk(KERN_ERR "drxd: firmware load failure [%s]\n", fw_name);
917 state->microcode = kmalloc(fw->size, GFP_KERNEL);
918 if (state->microcode == NULL) {
919 release_firmware(fw);
920 printk(KERN_ERR "drxd: firmware load failure: no memory\n");
924 memcpy(state->microcode, fw->data, fw->size);
925 state->microcode_length = fw->size;
926 release_firmware(fw);
930 static int DownloadMicrocode(struct drxd_state *state,
931 const u8 *pMCImage, u32 Length)
940 pSrc = (u8 *) pMCImage;
941 /* We're not using Flags */
942 /* Flags = (pSrc[0] << 8) | pSrc[1]; */
944 offset += sizeof(u16);
945 nBlocks = (pSrc[0] << 8) | pSrc[1];
947 offset += sizeof(u16);
949 for (i = 0; i < nBlocks; i++) {
950 Address = (pSrc[0] << 24) | (pSrc[1] << 16) |
951 (pSrc[2] << 8) | pSrc[3];
953 offset += sizeof(u32);
955 BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16);
957 offset += sizeof(u16);
959 /* We're not using Flags */
960 /* u16 Flags = (pSrc[0] << 8) | pSrc[1]; */
962 offset += sizeof(u16);
964 /* We're not using BlockCRC */
965 /* u16 BlockCRC = (pSrc[0] << 8) | pSrc[1]; */
967 offset += sizeof(u16);
969 status = WriteBlock(state, Address, BlockSize,
970 pSrc, DRX_I2C_CLEARCRC);
980 static int HI_Command(struct drxd_state *state, u16 cmd, u16 * pResult)
986 status = Write16(state, HI_RA_RAM_SRV_CMD__A, cmd, 0);
992 if (nrRetries > DRXD_MAX_RETRIES) {
996 status = Read16(state, HI_RA_RAM_SRV_CMD__A, &waitCmd, 0);
997 } while (waitCmd != 0);
1000 status = Read16(state, HI_RA_RAM_SRV_RES__A, pResult, 0);
1004 static int HI_CfgCommand(struct drxd_state *state)
1008 mutex_lock(&state->mutex);
1009 Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0);
1010 Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, state->hi_cfg_timing_div, 0);
1011 Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, state->hi_cfg_bridge_delay, 0);
1012 Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, state->hi_cfg_wakeup_key, 0);
1013 Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, state->hi_cfg_ctrl, 0);
1015 Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0);
1017 if ((state->hi_cfg_ctrl & HI_RA_RAM_SRV_CFG_ACT_PWD_EXE) ==
1018 HI_RA_RAM_SRV_CFG_ACT_PWD_EXE)
1019 status = Write16(state, HI_RA_RAM_SRV_CMD__A,
1020 HI_RA_RAM_SRV_CMD_CONFIG, 0);
1022 status = HI_Command(state, HI_RA_RAM_SRV_CMD_CONFIG, 0);
1023 mutex_unlock(&state->mutex);
1027 static int InitHI(struct drxd_state *state)
1029 state->hi_cfg_wakeup_key = (state->chip_adr);
1030 /* port/bridge/power down ctrl */
1031 state->hi_cfg_ctrl = HI_RA_RAM_SRV_CFG_ACT_SLV0_ON;
1032 return HI_CfgCommand(state);
1035 static int HI_ResetCommand(struct drxd_state *state)
1039 mutex_lock(&state->mutex);
1040 status = Write16(state, HI_RA_RAM_SRV_RST_KEY__A,
1041 HI_RA_RAM_SRV_RST_KEY_ACT, 0);
1043 status = HI_Command(state, HI_RA_RAM_SRV_CMD_RESET, 0);
1044 mutex_unlock(&state->mutex);
1049 static int DRX_ConfigureI2CBridge(struct drxd_state *state, int bEnableBridge)
1051 state->hi_cfg_ctrl &= (~HI_RA_RAM_SRV_CFG_ACT_BRD__M);
1053 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_ON;
1055 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_OFF;
1057 return HI_CfgCommand(state);
1060 #define HI_TR_WRITE 0x9
1061 #define HI_TR_READ 0xA
1062 #define HI_TR_READ_WRITE 0xB
1063 #define HI_TR_BROADCAST 0x4
1066 static int AtomicReadBlock(struct drxd_state *state,
1067 u32 Addr, u16 DataSize, u8 *pData, u8 Flags)
1072 /* Parameter check */
1073 if ((!pData) || ((DataSize & 1) != 0))
1076 mutex_lock(&state->mutex);
1079 /* Instruct HI to read n bytes */
1080 /* TODO use proper names forthese egisters */
1081 status = Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, (HI_TR_FUNC_ADDR & 0xFFFF), 0);
1084 status = Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, (u16) (Addr >> 16), 0);
1087 status = Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, (u16) (Addr & 0xFFFF), 0);
1090 status = Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, (u16) ((DataSize / 2) - 1), 0);
1093 status = Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, HI_TR_READ, 0);
1097 status = HI_Command(state, HI_RA_RAM_SRV_CMD_EXECUTE, 0);
1104 for (i = 0; i < (DataSize / 2); i += 1) {
1107 status = Read16(state, (HI_RA_RAM_USR_BEGIN__A + i),
1111 pData[2 * i] = (u8) (word & 0xFF);
1112 pData[(2 * i) + 1] = (u8) (word >> 8);
1115 mutex_unlock(&state->mutex);
1119 static int AtomicReadReg32(struct drxd_state *state,
1120 u32 Addr, u32 *pData, u8 Flags)
1122 u8 buf[sizeof(u32)];
1127 status = AtomicReadBlock(state, Addr, sizeof(u32), buf, Flags);
1128 *pData = (((u32) buf[0]) << 0) +
1129 (((u32) buf[1]) << 8) +
1130 (((u32) buf[2]) << 16) + (((u32) buf[3]) << 24);
1135 static int StopAllProcessors(struct drxd_state *state)
1137 return Write16(state, HI_COMM_EXEC__A,
1138 SC_COMM_EXEC_CTL_STOP, DRX_I2C_BROADCAST);
1141 static int EnableAndResetMB(struct drxd_state *state)
1143 if (state->type_A) {
1144 /* disable? monitor bus observe @ EC_OC */
1145 Write16(state, EC_OC_REG_OC_MON_SIO__A, 0x0000, 0x0000);
1148 /* do inverse broadcast, followed by explicit write to HI */
1149 Write16(state, HI_COMM_MB__A, 0x0000, DRX_I2C_BROADCAST);
1150 Write16(state, HI_COMM_MB__A, 0x0000, 0x0000);
1154 static int InitCC(struct drxd_state *state)
1156 if (state->osc_clock_freq == 0 ||
1157 state->osc_clock_freq > 20000 ||
1158 (state->osc_clock_freq % 4000) != 0) {
1159 printk(KERN_ERR "invalid osc frequency %d\n", state->osc_clock_freq);
1163 Write16(state, CC_REG_OSC_MODE__A, CC_REG_OSC_MODE_M20, 0);
1164 Write16(state, CC_REG_PLL_MODE__A, CC_REG_PLL_MODE_BYPASS_PLL |
1165 CC_REG_PLL_MODE_PUMP_CUR_12, 0);
1166 Write16(state, CC_REG_REF_DIVIDE__A, state->osc_clock_freq / 4000, 0);
1167 Write16(state, CC_REG_PWD_MODE__A, CC_REG_PWD_MODE_DOWN_PLL, 0);
1168 Write16(state, CC_REG_UPDATE__A, CC_REG_UPDATE_KEY, 0);
1173 static int ResetECOD(struct drxd_state *state)
1178 status = Write16(state, EC_OD_REG_SYNC__A, 0x0664, 0);
1180 status = Write16(state, B_EC_OD_REG_SYNC__A, 0x0664, 0);
1183 status = WriteTable(state, state->m_ResetECRAM);
1185 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0001, 0);
1189 /* Configure PGA switch */
1191 static int SetCfgPga(struct drxd_state *state, int pgaSwitch)
1200 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
1203 AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M));
1204 AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC;
1205 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
1210 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000);
1213 AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M));
1214 AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC;
1215 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000);
1219 /* enable fine and coarse gain, enable AAF,
1221 status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN, 0x0000);
1225 /* PGA off, bypass */
1228 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
1231 AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M));
1232 AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC;
1233 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
1238 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000);
1241 AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M));
1242 AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC;
1243 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000);
1247 /* disable fine and coarse gain, enable AAF,
1249 status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000);
1257 static int InitFE(struct drxd_state *state)
1262 status = WriteTable(state, state->m_InitFE_1);
1266 if (state->type_A) {
1267 status = Write16(state, FE_AG_REG_AG_PGA_MODE__A,
1268 FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN,
1272 status = SetCfgPga(state, 0);
1275 Write16(state, B_FE_AG_REG_AG_PGA_MODE__A,
1276 B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN,
1282 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, state->m_FeAgRegAgAgcSio, 0x0000);
1285 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000);
1289 status = WriteTable(state, state->m_InitFE_2);
1298 static int InitFT(struct drxd_state *state)
1301 norm OFFSET, MB says =2 voor 8K en =3 voor 2K waarschijnlijk
1304 return Write16(state, FT_REG_COMM_EXEC__A, 0x0001, 0x0000);
1307 static int SC_WaitForReady(struct drxd_state *state)
1312 for (i = 0; i < DRXD_MAX_RETRIES; i += 1) {
1313 int status = Read16(state, SC_RA_RAM_CMD__A, &curCmd, 0);
1314 if (status == 0 || curCmd == 0)
1320 static int SC_SendCommand(struct drxd_state *state, u16 cmd)
1325 Write16(state, SC_RA_RAM_CMD__A, cmd, 0);
1326 SC_WaitForReady(state);
1328 Read16(state, SC_RA_RAM_CMD_ADDR__A, &errCode, 0);
1330 if (errCode == 0xFFFF) {
1331 printk(KERN_ERR "Command Error\n");
1338 static int SC_ProcStartCommand(struct drxd_state *state,
1339 u16 subCmd, u16 param0, u16 param1)
1344 mutex_lock(&state->mutex);
1346 Read16(state, SC_COMM_EXEC__A, &scExec, 0);
1351 SC_WaitForReady(state);
1352 Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0);
1353 Write16(state, SC_RA_RAM_PARAM1__A, param1, 0);
1354 Write16(state, SC_RA_RAM_PARAM0__A, param0, 0);
1356 SC_SendCommand(state, SC_RA_RAM_CMD_PROC_START);
1358 mutex_unlock(&state->mutex);
1362 static int SC_SetPrefParamCommand(struct drxd_state *state,
1363 u16 subCmd, u16 param0, u16 param1)
1367 mutex_lock(&state->mutex);
1369 status = SC_WaitForReady(state);
1372 status = Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0);
1375 status = Write16(state, SC_RA_RAM_PARAM1__A, param1, 0);
1378 status = Write16(state, SC_RA_RAM_PARAM0__A, param0, 0);
1382 status = SC_SendCommand(state, SC_RA_RAM_CMD_SET_PREF_PARAM);
1386 mutex_unlock(&state->mutex);
1391 static int SC_GetOpParamCommand(struct drxd_state *state, u16 * result)
1395 mutex_lock(&state->mutex);
1397 status = SC_WaitForReady(state);
1400 status = SC_SendCommand(state, SC_RA_RAM_CMD_GET_OP_PARAM);
1403 status = Read16(state, SC_RA_RAM_PARAM0__A, result, 0);
1407 mutex_unlock(&state->mutex);
1412 static int ConfigureMPEGOutput(struct drxd_state *state, int bEnableOutput)
1417 u16 EcOcRegIprInvMpg = 0;
1418 u16 EcOcRegOcModeLop = 0;
1419 u16 EcOcRegOcModeHip = 0;
1420 u16 EcOcRegOcMpgSio = 0;
1422 /*CHK_ERROR(Read16(state, EC_OC_REG_OC_MODE_LOP__A, &EcOcRegOcModeLop, 0)); */
1424 if (state->operation_mode == OM_DVBT_Diversity_Front) {
1425 if (bEnableOutput) {
1427 B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR;
1429 EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M;
1431 EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE;
1433 EcOcRegOcModeLop = state->m_EcOcRegOcModeLop;
1436 EcOcRegOcMpgSio &= (~(EC_OC_REG_OC_MPG_SIO__M));
1438 EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M;
1440 /* Don't Insert RS Byte */
1441 if (state->insert_rs_byte) {
1443 (~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M));
1445 (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M);
1447 EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE;
1450 EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE;
1452 (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M);
1454 EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE;
1457 /* Mode = Parallel */
1458 if (state->enable_parallel)
1460 (~(EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M));
1463 EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL;
1466 /* EcOcRegIprInvMpg |= 0x00FF; */
1467 EcOcRegIprInvMpg &= (~(0x00FF));
1469 /* Invert Error ( we don't use the pin ) */
1470 /* EcOcRegIprInvMpg |= 0x0100; */
1471 EcOcRegIprInvMpg &= (~(0x0100));
1473 /* Invert Start ( we don't use the pin ) */
1474 /* EcOcRegIprInvMpg |= 0x0200; */
1475 EcOcRegIprInvMpg &= (~(0x0200));
1477 /* Invert Valid ( we don't use the pin ) */
1478 /* EcOcRegIprInvMpg |= 0x0400; */
1479 EcOcRegIprInvMpg &= (~(0x0400));
1482 /* EcOcRegIprInvMpg |= 0x0800; */
1483 EcOcRegIprInvMpg &= (~(0x0800));
1485 /* EcOcRegOcModeLop =0x05; */
1486 status = Write16(state, EC_OC_REG_IPR_INV_MPG__A, EcOcRegIprInvMpg, 0);
1489 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, EcOcRegOcModeLop, 0);
1492 status = Write16(state, EC_OC_REG_OC_MODE_HIP__A, EcOcRegOcModeHip, 0x0000);
1495 status = Write16(state, EC_OC_REG_OC_MPG_SIO__A, EcOcRegOcMpgSio, 0);
1502 static int SetDeviceTypeId(struct drxd_state *state)
1508 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0);
1511 /* TODO: why twice? */
1512 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0);
1515 printk(KERN_INFO "drxd: deviceId = %04x\n", deviceId);
1519 state->diversity = 0;
1520 if (deviceId == 0) { /* on A2 only 3975 available */
1522 printk(KERN_INFO "DRX3975D-A2\n");
1525 printk(KERN_INFO "DRX397%dD-B1\n", deviceId);
1528 state->diversity = 1;
1534 state->diversity = 1;
1548 /* Init Table selection */
1549 state->m_InitAtomicRead = DRXD_InitAtomicRead;
1550 state->m_InitSC = DRXD_InitSC;
1551 state->m_ResetECRAM = DRXD_ResetECRAM;
1552 if (state->type_A) {
1553 state->m_ResetCEFR = DRXD_ResetCEFR;
1554 state->m_InitFE_1 = DRXD_InitFEA2_1;
1555 state->m_InitFE_2 = DRXD_InitFEA2_2;
1556 state->m_InitCP = DRXD_InitCPA2;
1557 state->m_InitCE = DRXD_InitCEA2;
1558 state->m_InitEQ = DRXD_InitEQA2;
1559 state->m_InitEC = DRXD_InitECA2;
1560 if (load_firmware(state, DRX_FW_FILENAME_A2))
1563 state->m_ResetCEFR = NULL;
1564 state->m_InitFE_1 = DRXD_InitFEB1_1;
1565 state->m_InitFE_2 = DRXD_InitFEB1_2;
1566 state->m_InitCP = DRXD_InitCPB1;
1567 state->m_InitCE = DRXD_InitCEB1;
1568 state->m_InitEQ = DRXD_InitEQB1;
1569 state->m_InitEC = DRXD_InitECB1;
1570 if (load_firmware(state, DRX_FW_FILENAME_B1))
1573 if (state->diversity) {
1574 state->m_InitDiversityFront = DRXD_InitDiversityFront;
1575 state->m_InitDiversityEnd = DRXD_InitDiversityEnd;
1576 state->m_DisableDiversity = DRXD_DisableDiversity;
1577 state->m_StartDiversityFront = DRXD_StartDiversityFront;
1578 state->m_StartDiversityEnd = DRXD_StartDiversityEnd;
1579 state->m_DiversityDelay8MHZ = DRXD_DiversityDelay8MHZ;
1580 state->m_DiversityDelay6MHZ = DRXD_DiversityDelay6MHZ;
1582 state->m_InitDiversityFront = NULL;
1583 state->m_InitDiversityEnd = NULL;
1584 state->m_DisableDiversity = NULL;
1585 state->m_StartDiversityFront = NULL;
1586 state->m_StartDiversityEnd = NULL;
1587 state->m_DiversityDelay8MHZ = NULL;
1588 state->m_DiversityDelay6MHZ = NULL;
1594 static int CorrectSysClockDeviation(struct drxd_state *state)
1600 u32 sysClockInHz = 0;
1601 u32 sysClockFreq = 0; /* in kHz */
1602 s16 oscClockDeviation;
1606 /* Retrieve bandwidth and incr, sanity check */
1608 /* These accesses should be AtomicReadReg32, but that
1609 causes trouble (at least for diversity */
1610 status = Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, ((u32 *) &nomincr), 0);
1613 status = Read32(state, FE_IF_REG_INCR0__A, (u32 *) &incr, 0);
1617 if (state->type_A) {
1618 if ((nomincr - incr < -500) || (nomincr - incr > 500))
1621 if ((nomincr - incr < -2000) || (nomincr - incr > 2000))
1625 switch (state->param.u.ofdm.bandwidth) {
1626 case BANDWIDTH_8_MHZ:
1627 bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
1629 case BANDWIDTH_7_MHZ:
1630 bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
1632 case BANDWIDTH_6_MHZ:
1633 bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
1640 /* Compute new sysclock value
1641 sysClockFreq = (((incr + 2^23)*bandwidth)/2^21)/1000 */
1643 sysClockInHz = MulDiv32(incr, bandwidth, 1 << 21);
1644 sysClockFreq = (u32) (sysClockInHz / 1000);
1646 if ((sysClockInHz % 1000) > 500)
1649 /* Compute clock deviation in ppm */
1650 oscClockDeviation = (u16) ((((s32) (sysClockFreq) -
1652 (state->expected_sys_clock_freq)) *
1655 (state->expected_sys_clock_freq));
1657 Diff = oscClockDeviation - state->osc_clock_deviation;
1658 /*printk(KERN_INFO "sysclockdiff=%d\n", Diff); */
1659 if (Diff >= -200 && Diff <= 200) {
1660 state->sys_clock_freq = (u16) sysClockFreq;
1661 if (oscClockDeviation != state->osc_clock_deviation) {
1662 if (state->config.osc_deviation) {
1663 state->config.osc_deviation(state->priv,
1666 state->osc_clock_deviation =
1670 /* switch OFF SRMM scan in SC */
1671 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DONT_SCAN, 0);
1674 /* overrule FE_IF internal value for
1675 proper re-locking */
1676 status = Write16(state, SC_RA_RAM_IF_SAVE__AX, state->current_fe_if_incr, 0);
1679 state->cscd_state = CSCD_SAVED;
1686 static int DRX_Stop(struct drxd_state *state)
1690 if (state->drxd_state != DRXD_STARTED)
1694 if (state->cscd_state != CSCD_SAVED) {
1696 status = DRX_GetLockStatus(state, &lock);
1701 status = StopOC(state);
1705 state->drxd_state = DRXD_STOPPED;
1707 status = ConfigureMPEGOutput(state, 0);
1711 if (state->type_A) {
1712 /* Stop relevant processors off the device */
1713 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0x0000);
1717 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1720 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1724 /* Stop all processors except HI & CC & FE */
1725 status = Write16(state, B_SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1728 status = Write16(state, B_LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1731 status = Write16(state, B_FT_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1734 status = Write16(state, B_CP_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1737 status = Write16(state, B_CE_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1740 status = Write16(state, B_EQ_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1743 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0);
1752 int SetOperationMode(struct drxd_state *state, int oMode)
1757 if (state->drxd_state != DRXD_STOPPED) {
1762 if (oMode == state->operation_mode) {
1767 if (oMode != OM_Default && !state->diversity) {
1773 case OM_DVBT_Diversity_Front:
1774 status = WriteTable(state, state->m_InitDiversityFront);
1776 case OM_DVBT_Diversity_End:
1777 status = WriteTable(state, state->m_InitDiversityEnd);
1780 /* We need to check how to
1781 get DRXD out of diversity */
1783 status = WriteTable(state, state->m_DisableDiversity);
1789 state->operation_mode = oMode;
1793 static int StartDiversity(struct drxd_state *state)
1799 if (state->operation_mode == OM_DVBT_Diversity_Front) {
1800 status = WriteTable(state, state->m_StartDiversityFront);
1803 } else if (state->operation_mode == OM_DVBT_Diversity_End) {
1804 status = WriteTable(state, state->m_StartDiversityEnd);
1807 if (state->param.u.ofdm.bandwidth == BANDWIDTH_8_MHZ) {
1808 status = WriteTable(state, state->m_DiversityDelay8MHZ);
1812 status = WriteTable(state, state->m_DiversityDelay6MHZ);
1817 status = Read16(state, B_EQ_REG_RC_SEL_CAR__A, &rcControl, 0);
1820 rcControl &= ~(B_EQ_REG_RC_SEL_CAR_FFTMODE__M);
1821 rcControl |= B_EQ_REG_RC_SEL_CAR_DIV_ON |
1822 /* combining enabled */
1823 B_EQ_REG_RC_SEL_CAR_MEAS_A_CC |
1824 B_EQ_REG_RC_SEL_CAR_PASS_A_CC |
1825 B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC;
1826 status = Write16(state, B_EQ_REG_RC_SEL_CAR__A, rcControl, 0);
1834 static int SetFrequencyShift(struct drxd_state *state,
1835 u32 offsetFreq, int channelMirrored)
1837 int negativeShift = (state->tuner_mirrors == channelMirrored);
1839 /* Handle all mirroring
1841 * Note: ADC mirroring (aliasing) is implictly handled by limiting
1842 * feFsRegAddInc to 28 bits below
1843 * (if the result before masking is more than 28 bits, this means
1844 * that the ADC is mirroring.
1845 * The masking is in fact the aliasing of the ADC)
1849 /* Compute register value, unsigned computation */
1850 state->fe_fs_add_incr = MulDiv32(state->intermediate_freq +
1852 1 << 28, state->sys_clock_freq);
1853 /* Remove integer part */
1854 state->fe_fs_add_incr &= 0x0FFFFFFFL;
1856 state->fe_fs_add_incr = ((1 << 28) - state->fe_fs_add_incr);
1858 /* Save the frequency shift without tunerOffset compensation
1859 for CtrlGetChannel. */
1860 state->org_fe_fs_add_incr = MulDiv32(state->intermediate_freq,
1861 1 << 28, state->sys_clock_freq);
1862 /* Remove integer part */
1863 state->org_fe_fs_add_incr &= 0x0FFFFFFFL;
1865 state->org_fe_fs_add_incr = ((1L << 28) -
1866 state->org_fe_fs_add_incr);
1868 return Write32(state, FE_FS_REG_ADD_INC_LOP__A,
1869 state->fe_fs_add_incr, 0);
1872 static int SetCfgNoiseCalibration(struct drxd_state *state,
1873 struct SNoiseCal *noiseCal)
1879 status = Read16(state, SC_RA_RAM_BE_OPT_ENA__A, &beOptEna, 0);
1882 if (noiseCal->cpOpt) {
1883 beOptEna |= (1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
1885 beOptEna &= ~(1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
1886 status = Write16(state, CP_REG_AC_NEXP_OFFS__A, noiseCal->cpNexpOfs, 0);
1890 status = Write16(state, SC_RA_RAM_BE_OPT_ENA__A, beOptEna, 0);
1894 if (!state->type_A) {
1895 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_2K__A, noiseCal->tdCal2k, 0);
1898 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_8K__A, noiseCal->tdCal8k, 0);
1907 static int DRX_Start(struct drxd_state *state, s32 off)
1909 struct dvb_ofdm_parameters *p = &state->param.u.ofdm;
1912 u16 transmissionParams = 0;
1913 u16 operationMode = 0;
1914 u16 qpskTdTpsPwr = 0;
1915 u16 qam16TdTpsPwr = 0;
1916 u16 qam64TdTpsPwr = 0;
1919 int mirrorFreqSpect;
1921 u16 qpskSnCeGain = 0;
1922 u16 qam16SnCeGain = 0;
1923 u16 qam64SnCeGain = 0;
1924 u16 qpskIsGainMan = 0;
1925 u16 qam16IsGainMan = 0;
1926 u16 qam64IsGainMan = 0;
1927 u16 qpskIsGainExp = 0;
1928 u16 qam16IsGainExp = 0;
1929 u16 qam64IsGainExp = 0;
1930 u16 bandwidthParam = 0;
1933 off = (off - 500) / 1000;
1935 off = (off + 500) / 1000;
1938 if (state->drxd_state != DRXD_STOPPED)
1940 status = ResetECOD(state);
1943 if (state->type_A) {
1944 status = InitSC(state);
1948 status = InitFT(state);
1951 status = InitCP(state);
1954 status = InitCE(state);
1957 status = InitEQ(state);
1960 status = InitSC(state);
1965 /* Restore current IF & RF AGC settings */
1967 status = SetCfgIfAgc(state, &state->if_agc_cfg);
1970 status = SetCfgRfAgc(state, &state->rf_agc_cfg);
1974 mirrorFreqSpect = (state->param.inversion == INVERSION_ON);
1976 switch (p->transmission_mode) {
1977 default: /* Not set, detect it automatically */
1978 operationMode |= SC_RA_RAM_OP_AUTO_MODE__M;
1979 /* fall through , try first guess DRX_FFTMODE_8K */
1980 case TRANSMISSION_MODE_8K:
1981 transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_8K;
1982 if (state->type_A) {
1983 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_8K, 0x0000);
1991 case TRANSMISSION_MODE_2K:
1992 transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_2K;
1993 if (state->type_A) {
1994 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_2K, 0x0000);
2004 switch (p->guard_interval) {
2005 case GUARD_INTERVAL_1_4:
2006 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4;
2008 case GUARD_INTERVAL_1_8:
2009 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_8;
2011 case GUARD_INTERVAL_1_16:
2012 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_16;
2014 case GUARD_INTERVAL_1_32:
2015 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_32;
2017 default: /* Not set, detect it automatically */
2018 operationMode |= SC_RA_RAM_OP_AUTO_GUARD__M;
2019 /* try first guess 1/4 */
2020 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4;
2024 switch (p->hierarchy_information) {
2026 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A1;
2027 if (state->type_A) {
2028 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0001, 0x0000);
2031 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0001, 0x0000);
2035 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
2036 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA1;
2037 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA1;
2040 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
2042 SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE;
2044 SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE;
2047 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
2049 SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE;
2051 SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE;
2056 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A2;
2057 if (state->type_A) {
2058 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0002, 0x0000);
2061 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0002, 0x0000);
2065 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
2066 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA2;
2067 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA2;
2070 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
2072 SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE;
2074 SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE;
2077 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
2079 SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE;
2081 SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE;
2085 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A4;
2086 if (state->type_A) {
2087 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0003, 0x0000);
2090 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0003, 0x0000);
2094 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
2095 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA4;
2096 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA4;
2099 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
2101 SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE;
2103 SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE;
2106 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
2108 SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE;
2110 SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE;
2113 case HIERARCHY_AUTO:
2115 /* Not set, detect it automatically, start with none */
2116 operationMode |= SC_RA_RAM_OP_AUTO_HIER__M;
2117 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_NO;
2118 if (state->type_A) {
2119 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0000, 0x0000);
2122 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0000, 0x0000);
2126 qpskTdTpsPwr = EQ_TD_TPS_PWR_QPSK;
2127 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHAN;
2128 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHAN;
2131 SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE;
2133 SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE;
2135 SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE;
2138 SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE;
2140 SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE;
2142 SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE;
2150 switch (p->constellation) {
2152 operationMode |= SC_RA_RAM_OP_AUTO_CONST__M;
2153 /* fall through , try first guess
2154 DRX_CONSTELLATION_QAM64 */
2156 transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM64;
2157 if (state->type_A) {
2158 status = Write16(state, EQ_REG_OT_CONST__A, 0x0002, 0x0000);
2161 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_64QAM, 0x0000);
2164 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0020, 0x0000);
2167 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0008, 0x0000);
2170 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0002, 0x0000);
2174 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam64TdTpsPwr, 0x0000);
2177 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam64SnCeGain, 0x0000);
2180 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam64IsGainMan, 0x0000);
2183 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam64IsGainExp, 0x0000);
2189 transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QPSK;
2190 if (state->type_A) {
2191 status = Write16(state, EQ_REG_OT_CONST__A, 0x0000, 0x0000);
2194 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_QPSK, 0x0000);
2197 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000);
2200 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0000, 0x0000);
2203 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000);
2207 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qpskTdTpsPwr, 0x0000);
2210 status = Write16(state, EQ_REG_SN_CEGAIN__A, qpskSnCeGain, 0x0000);
2213 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qpskIsGainMan, 0x0000);
2216 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qpskIsGainExp, 0x0000);
2223 transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM16;
2224 if (state->type_A) {
2225 status = Write16(state, EQ_REG_OT_CONST__A, 0x0001, 0x0000);
2228 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_16QAM, 0x0000);
2231 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000);
2234 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0004, 0x0000);
2237 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000);
2241 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam16TdTpsPwr, 0x0000);
2244 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam16SnCeGain, 0x0000);
2247 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam16IsGainMan, 0x0000);
2250 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam16IsGainExp, 0x0000);
2261 switch (DRX_CHANNEL_HIGH) {
2263 case DRX_CHANNEL_AUTO:
2264 case DRX_CHANNEL_LOW:
2265 transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_LO;
2266 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_LO, 0x0000);
2270 case DRX_CHANNEL_HIGH:
2271 transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_HI;
2272 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_HI, 0x0000);
2279 switch (p->code_rate_HP) {
2281 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_1_2;
2282 if (state->type_A) {
2283 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C1_2, 0x0000);
2289 operationMode |= SC_RA_RAM_OP_AUTO_RATE__M;
2291 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_2_3;
2292 if (state->type_A) {
2293 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C2_3, 0x0000);
2299 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_3_4;
2300 if (state->type_A) {
2301 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C3_4, 0x0000);
2307 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_5_6;
2308 if (state->type_A) {
2309 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C5_6, 0x0000);
2315 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_7_8;
2316 if (state->type_A) {
2317 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C7_8, 0x0000);
2327 /* First determine real bandwidth (Hz) */
2328 /* Also set delay for impulse noise cruncher (only A2) */
2329 /* Also set parameters for EC_OC fix, note
2330 EC_OC_REG_TMD_HIL_MAR is changed
2331 by SC for fix for some 8K,1/8 guard but is restored by
2334 switch (p->bandwidth) {
2335 case BANDWIDTH_AUTO:
2336 case BANDWIDTH_8_MHZ:
2337 /* (64/7)*(8/8)*1000000 */
2338 bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
2341 status = Write16(state,
2342 FE_AG_REG_IND_DEL__A, 50, 0x0000);
2344 case BANDWIDTH_7_MHZ:
2345 /* (64/7)*(7/8)*1000000 */
2346 bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
2347 bandwidthParam = 0x4807; /*binary:0100 1000 0000 0111 */
2348 status = Write16(state,
2349 FE_AG_REG_IND_DEL__A, 59, 0x0000);
2351 case BANDWIDTH_6_MHZ:
2352 /* (64/7)*(6/8)*1000000 */
2353 bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
2354 bandwidthParam = 0x0F07; /*binary: 0000 1111 0000 0111 */
2355 status = Write16(state,
2356 FE_AG_REG_IND_DEL__A, 71, 0x0000);
2364 status = Write16(state, SC_RA_RAM_BAND__A, bandwidthParam, 0x0000);
2370 status = Read16(state, SC_RA_RAM_CONFIG__A, &sc_config, 0);
2374 /* enable SLAVE mode in 2k 1/32 to
2375 prevent timing change glitches */
2376 if ((p->transmission_mode == TRANSMISSION_MODE_2K) &&
2377 (p->guard_interval == GUARD_INTERVAL_1_32)) {
2379 sc_config |= SC_RA_RAM_CONFIG_SLAVE__M;
2382 sc_config &= ~SC_RA_RAM_CONFIG_SLAVE__M;
2384 status = Write16(state, SC_RA_RAM_CONFIG__A, sc_config, 0);
2389 status = SetCfgNoiseCalibration(state, &state->noise_cal);
2393 if (state->cscd_state == CSCD_INIT) {
2394 /* switch on SRMM scan in SC */
2395 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DO_SCAN, 0x0000);
2398 /* CHK_ERROR(Write16(SC_RA_RAM_SAMPLE_RATE_STEP__A, DRXD_OSCDEV_STEP, 0x0000));*/
2399 state->cscd_state = CSCD_SET;
2402 /* Now compute FE_IF_REG_INCR */
2403 /*((( SysFreq/BandWidth)/2)/2) -1) * 2^23) =>
2404 ((SysFreq / BandWidth) * (2^21) ) - (2^23) */
2405 feIfIncr = MulDiv32(state->sys_clock_freq * 1000,
2406 (1ULL << 21), bandwidth) - (1 << 23);
2407 status = Write16(state, FE_IF_REG_INCR0__A, (u16) (feIfIncr & FE_IF_REG_INCR0__M), 0x0000);
2410 status = Write16(state, FE_IF_REG_INCR1__A, (u16) ((feIfIncr >> FE_IF_REG_INCR0__W) & FE_IF_REG_INCR1__M), 0x0000);
2413 /* Bandwidth setting done */
2415 /* Mirror & frequency offset */
2416 SetFrequencyShift(state, off, mirrorFreqSpect);
2418 /* Start SC, write channel settings to SC */
2420 /* Enable SC after setting all other parameters */
2421 status = Write16(state, SC_COMM_STATE__A, 0, 0x0000);
2424 status = Write16(state, SC_COMM_EXEC__A, 1, 0x0000);
2428 /* Write SC parameter registers, operation mode */
2430 operationMode = (SC_RA_RAM_OP_AUTO_MODE__M |
2431 SC_RA_RAM_OP_AUTO_GUARD__M |
2432 SC_RA_RAM_OP_AUTO_CONST__M |
2433 SC_RA_RAM_OP_AUTO_HIER__M |
2434 SC_RA_RAM_OP_AUTO_RATE__M);
2436 status = SC_SetPrefParamCommand(state, 0x0000, transmissionParams, operationMode);
2440 /* Start correct processes to get in lock */
2441 status = SC_ProcStartCommand(state, SC_RA_RAM_PROC_LOCKTRACK, SC_RA_RAM_SW_EVENT_RUN_NMASK__M, SC_RA_RAM_LOCKTRACK_MIN);
2445 status = StartOC(state);
2449 if (state->operation_mode != OM_Default) {
2450 status = StartDiversity(state);
2455 state->drxd_state = DRXD_STARTED;
2461 static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency)
2463 u32 ulRfAgcOutputLevel = 0xffffffff;
2464 u32 ulRfAgcSettleLevel = 528; /* Optimum value for MT2060 */
2465 u32 ulRfAgcMinLevel = 0; /* Currently unused */
2466 u32 ulRfAgcMaxLevel = DRXD_FE_CTRL_MAX; /* Currently unused */
2467 u32 ulRfAgcSpeed = 0; /* Currently unused */
2468 u32 ulRfAgcMode = 0; /*2; Off */
2469 u32 ulRfAgcR1 = 820;
2470 u32 ulRfAgcR2 = 2200;
2471 u32 ulRfAgcR3 = 150;
2472 u32 ulIfAgcMode = 0; /* Auto */
2473 u32 ulIfAgcOutputLevel = 0xffffffff;
2474 u32 ulIfAgcSettleLevel = 0xffffffff;
2475 u32 ulIfAgcMinLevel = 0xffffffff;
2476 u32 ulIfAgcMaxLevel = 0xffffffff;
2477 u32 ulIfAgcSpeed = 0xffffffff;
2478 u32 ulIfAgcR1 = 820;
2479 u32 ulIfAgcR2 = 2200;
2480 u32 ulIfAgcR3 = 150;
2481 u32 ulClock = state->config.clock;
2482 u32 ulSerialMode = 0;
2483 u32 ulEcOcRegOcModeLop = 4; /* Dynamic DTO source */
2484 u32 ulHiI2cDelay = HI_I2C_DELAY;
2485 u32 ulHiI2cBridgeDelay = HI_I2C_BRIDGE_DELAY;
2486 u32 ulHiI2cPatch = 0;
2487 u32 ulEnvironment = APPENV_PORTABLE;
2488 u32 ulEnvironmentDiversity = APPENV_MOBILE;
2489 u32 ulIFFilter = IFFILTER_SAW;
2491 state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2492 state->if_agc_cfg.outputLevel = 0;
2493 state->if_agc_cfg.settleLevel = 140;
2494 state->if_agc_cfg.minOutputLevel = 0;
2495 state->if_agc_cfg.maxOutputLevel = 1023;
2496 state->if_agc_cfg.speed = 904;
2498 if (ulIfAgcMode == 1 && ulIfAgcOutputLevel <= DRXD_FE_CTRL_MAX) {
2499 state->if_agc_cfg.ctrlMode = AGC_CTRL_USER;
2500 state->if_agc_cfg.outputLevel = (u16) (ulIfAgcOutputLevel);
2503 if (ulIfAgcMode == 0 &&
2504 ulIfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&
2505 ulIfAgcMinLevel <= DRXD_FE_CTRL_MAX &&
2506 ulIfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&
2507 ulIfAgcSpeed <= DRXD_FE_CTRL_MAX) {
2508 state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2509 state->if_agc_cfg.settleLevel = (u16) (ulIfAgcSettleLevel);
2510 state->if_agc_cfg.minOutputLevel = (u16) (ulIfAgcMinLevel);
2511 state->if_agc_cfg.maxOutputLevel = (u16) (ulIfAgcMaxLevel);
2512 state->if_agc_cfg.speed = (u16) (ulIfAgcSpeed);
2515 state->if_agc_cfg.R1 = (u16) (ulIfAgcR1);
2516 state->if_agc_cfg.R2 = (u16) (ulIfAgcR2);
2517 state->if_agc_cfg.R3 = (u16) (ulIfAgcR3);
2519 state->rf_agc_cfg.R1 = (u16) (ulRfAgcR1);
2520 state->rf_agc_cfg.R2 = (u16) (ulRfAgcR2);
2521 state->rf_agc_cfg.R3 = (u16) (ulRfAgcR3);
2523 state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2524 /* rest of the RFAgcCfg structure currently unused */
2525 if (ulRfAgcMode == 1 && ulRfAgcOutputLevel <= DRXD_FE_CTRL_MAX) {
2526 state->rf_agc_cfg.ctrlMode = AGC_CTRL_USER;
2527 state->rf_agc_cfg.outputLevel = (u16) (ulRfAgcOutputLevel);
2530 if (ulRfAgcMode == 0 &&
2531 ulRfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&
2532 ulRfAgcMinLevel <= DRXD_FE_CTRL_MAX &&
2533 ulRfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&
2534 ulRfAgcSpeed <= DRXD_FE_CTRL_MAX) {
2535 state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2536 state->rf_agc_cfg.settleLevel = (u16) (ulRfAgcSettleLevel);
2537 state->rf_agc_cfg.minOutputLevel = (u16) (ulRfAgcMinLevel);
2538 state->rf_agc_cfg.maxOutputLevel = (u16) (ulRfAgcMaxLevel);
2539 state->rf_agc_cfg.speed = (u16) (ulRfAgcSpeed);
2542 if (ulRfAgcMode == 2)
2543 state->rf_agc_cfg.ctrlMode = AGC_CTRL_OFF;
2545 if (ulEnvironment <= 2)
2546 state->app_env_default = (enum app_env)
2548 if (ulEnvironmentDiversity <= 2)
2549 state->app_env_diversity = (enum app_env)
2550 (ulEnvironmentDiversity);
2552 if (ulIFFilter == IFFILTER_DISCRETE) {
2553 /* discrete filter */
2554 state->noise_cal.cpOpt = 0;
2555 state->noise_cal.cpNexpOfs = 40;
2556 state->noise_cal.tdCal2k = -40;
2557 state->noise_cal.tdCal8k = -24;
2560 state->noise_cal.cpOpt = 1;
2561 state->noise_cal.cpNexpOfs = 0;
2562 state->noise_cal.tdCal2k = -21;
2563 state->noise_cal.tdCal8k = -24;
2565 state->m_EcOcRegOcModeLop = (u16) (ulEcOcRegOcModeLop);
2567 state->chip_adr = (state->config.demod_address << 1) | 1;
2568 switch (ulHiI2cPatch) {
2570 state->m_HiI2cPatch = DRXD_HiI2cPatch_1;
2573 state->m_HiI2cPatch = DRXD_HiI2cPatch_3;
2576 state->m_HiI2cPatch = NULL;
2579 /* modify tuner and clock attributes */
2580 state->intermediate_freq = (u16) (IntermediateFrequency / 1000);
2581 /* expected system clock frequency in kHz */
2582 state->expected_sys_clock_freq = 48000;
2583 /* real system clock frequency in kHz */
2584 state->sys_clock_freq = 48000;
2585 state->osc_clock_freq = (u16) ulClock;
2586 state->osc_clock_deviation = 0;
2587 state->cscd_state = CSCD_INIT;
2588 state->drxd_state = DRXD_UNINITIALIZED;
2592 state->tuner_mirrors = 0;
2594 /* modify MPEG output attributes */
2595 state->insert_rs_byte = state->config.insert_rs_byte;
2596 state->enable_parallel = (ulSerialMode != 1);
2598 /* Timing div, 250ns/Psys */
2599 /* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */
2601 state->hi_cfg_timing_div = (u16) ((state->sys_clock_freq / 1000) *
2602 ulHiI2cDelay) / 1000;
2603 /* Bridge delay, uses oscilator clock */
2604 /* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */
2605 state->hi_cfg_bridge_delay = (u16) ((state->osc_clock_freq / 1000) *
2606 ulHiI2cBridgeDelay) / 1000;
2608 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER;
2609 /* state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO; */
2610 state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO;
2614 int DRXD_init(struct drxd_state *state, const u8 * fw, u32 fw_size)
2619 if (state->init_done)
2622 CDRXD(state, state->config.IF ? state->config.IF : 36000000);
2625 state->operation_mode = OM_Default;
2627 status = SetDeviceTypeId(state);
2631 /* Apply I2c address patch to B1 */
2632 if (!state->type_A && state->m_HiI2cPatch != NULL)
2633 status = WriteTable(state, state->m_HiI2cPatch);
2637 if (state->type_A) {
2638 /* HI firmware patch for UIO readout,
2639 avoid clearing of result register */
2640 status = Write16(state, 0x43012D, 0x047f, 0);
2645 status = HI_ResetCommand(state);
2649 status = StopAllProcessors(state);
2652 status = InitCC(state);
2656 state->osc_clock_deviation = 0;
2658 if (state->config.osc_deviation)
2659 state->osc_clock_deviation =
2660 state->config.osc_deviation(state->priv, 0, 0);
2662 /* Handle clock deviation */
2664 s32 devA = (s32) (state->osc_clock_deviation) *
2665 (s32) (state->expected_sys_clock_freq);
2666 /* deviation in kHz */
2667 s32 deviation = (devA / (1000000L));
2668 /* rounding, signed */
2673 if ((devB * (devA % 1000000L) > 1000000L)) {
2675 deviation += (devB / 2);
2678 state->sys_clock_freq =
2679 (u16) ((state->expected_sys_clock_freq) +
2682 status = InitHI(state);
2685 status = InitAtomicRead(state);
2689 status = EnableAndResetMB(state);
2693 status = ResetCEFR(state);
2698 status = DownloadMicrocode(state, fw, fw_size);
2702 status = DownloadMicrocode(state, state->microcode, state->microcode_length);
2708 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO;
2709 SetCfgPga(state, 0); /* PGA = 0 dB */
2711 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER;
2714 state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO;
2716 status = InitFE(state);
2719 status = InitFT(state);
2722 status = InitCP(state);
2725 status = InitCE(state);
2728 status = InitEQ(state);
2731 status = InitEC(state);
2734 status = InitSC(state);
2738 status = SetCfgIfAgc(state, &state->if_agc_cfg);
2741 status = SetCfgRfAgc(state, &state->rf_agc_cfg);
2745 state->cscd_state = CSCD_INIT;
2746 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
2749 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
2753 driverVersion = (((VERSION_MAJOR / 10) << 4) +
2754 (VERSION_MAJOR % 10)) << 24;
2755 driverVersion += (((VERSION_MINOR / 10) << 4) +
2756 (VERSION_MINOR % 10)) << 16;
2757 driverVersion += ((VERSION_PATCH / 1000) << 12) +
2758 ((VERSION_PATCH / 100) << 8) +
2759 ((VERSION_PATCH / 10) << 4) + (VERSION_PATCH % 10);
2761 status = Write32(state, SC_RA_RAM_DRIVER_VERSION__AX, driverVersion, 0);
2765 status = StopOC(state);
2769 state->drxd_state = DRXD_STOPPED;
2770 state->init_done = 1;
2776 int DRXD_status(struct drxd_state *state, u32 * pLockStatus)
2778 DRX_GetLockStatus(state, pLockStatus);
2780 /*if (*pLockStatus&DRX_LOCK_MPEG) */
2781 if (*pLockStatus & DRX_LOCK_FEC) {
2782 ConfigureMPEGOutput(state, 1);
2783 /* Get status again, in case we have MPEG lock now */
2784 /*DRX_GetLockStatus(state, pLockStatus); */
2790 /****************************************************************************/
2791 /****************************************************************************/
2792 /****************************************************************************/
2794 static int drxd_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
2796 struct drxd_state *state = fe->demodulator_priv;
2800 res = ReadIFAgc(state, &value);
2804 *strength = 0xffff - (value << 4);
2808 static int drxd_read_status(struct dvb_frontend *fe, fe_status_t * status)
2810 struct drxd_state *state = fe->demodulator_priv;
2813 DRXD_status(state, &lock);
2815 /* No MPEG lock in V255 firmware, bug ? */
2817 if (lock & DRX_LOCK_MPEG)
2818 *status |= FE_HAS_LOCK;
2820 if (lock & DRX_LOCK_FEC)
2821 *status |= FE_HAS_LOCK;
2823 if (lock & DRX_LOCK_FEC)
2824 *status |= FE_HAS_VITERBI | FE_HAS_SYNC;
2825 if (lock & DRX_LOCK_DEMOD)
2826 *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
2831 static int drxd_init(struct dvb_frontend *fe)
2833 struct drxd_state *state = fe->demodulator_priv;
2836 /* if (request_firmware(&state->fw, "drxd.fw", state->dev)<0) */
2837 return DRXD_init(state, 0, 0);
2839 err = DRXD_init(state, state->fw->data, state->fw->size);
2840 release_firmware(state->fw);
2844 int drxd_config_i2c(struct dvb_frontend *fe, int onoff)
2846 struct drxd_state *state = fe->demodulator_priv;
2848 if (state->config.disable_i2c_gate_ctrl == 1)
2851 return DRX_ConfigureI2CBridge(state, onoff);
2853 EXPORT_SYMBOL(drxd_config_i2c);
2855 static int drxd_get_tune_settings(struct dvb_frontend *fe,
2856 struct dvb_frontend_tune_settings *sets)
2858 sets->min_delay_ms = 10000;
2859 sets->max_drift = 0;
2860 sets->step_size = 0;
2864 static int drxd_read_ber(struct dvb_frontend *fe, u32 * ber)
2870 static int drxd_read_snr(struct dvb_frontend *fe, u16 * snr)
2876 static int drxd_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
2882 static int drxd_sleep(struct dvb_frontend *fe)
2884 struct drxd_state *state = fe->demodulator_priv;
2886 ConfigureMPEGOutput(state, 0);
2890 static int drxd_get_frontend(struct dvb_frontend *fe,
2891 struct dvb_frontend_parameters *param)
2896 static int drxd_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
2898 return drxd_config_i2c(fe, enable);
2901 static int drxd_set_frontend(struct dvb_frontend *fe,
2902 struct dvb_frontend_parameters *param)
2904 struct drxd_state *state = fe->demodulator_priv;
2907 state->param = *param;
2910 if (fe->ops.tuner_ops.set_params) {
2911 fe->ops.tuner_ops.set_params(fe, param);
2912 if (fe->ops.i2c_gate_ctrl)
2913 fe->ops.i2c_gate_ctrl(fe, 0);
2916 /* FIXME: move PLL drivers */
2917 if (state->config.pll_set &&
2918 state->config.pll_set(state->priv, param,
2919 state->config.pll_address,
2920 state->config.demoda_address, &off) < 0) {
2921 printk(KERN_ERR "Error in pll_set\n");
2927 return DRX_Start(state, off);
2930 static void drxd_release(struct dvb_frontend *fe)
2932 struct drxd_state *state = fe->demodulator_priv;
2937 static struct dvb_frontend_ops drxd_ops = {
2940 .name = "Micronas DRXD DVB-T",
2942 .frequency_min = 47125000,
2943 .frequency_max = 855250000,
2944 .frequency_stepsize = 166667,
2945 .frequency_tolerance = 0,
2946 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
2947 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
2949 FE_CAN_QAM_16 | FE_CAN_QAM_64 |
2951 FE_CAN_TRANSMISSION_MODE_AUTO |
2952 FE_CAN_GUARD_INTERVAL_AUTO |
2953 FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | FE_CAN_MUTE_TS},
2955 .release = drxd_release,
2957 .sleep = drxd_sleep,
2958 .i2c_gate_ctrl = drxd_i2c_gate_ctrl,
2960 .set_frontend = drxd_set_frontend,
2961 .get_frontend = drxd_get_frontend,
2962 .get_tune_settings = drxd_get_tune_settings,
2964 .read_status = drxd_read_status,
2965 .read_ber = drxd_read_ber,
2966 .read_signal_strength = drxd_read_signal_strength,
2967 .read_snr = drxd_read_snr,
2968 .read_ucblocks = drxd_read_ucblocks,
2971 struct dvb_frontend *drxd_attach(const struct drxd_config *config,
2972 void *priv, struct i2c_adapter *i2c,
2975 struct drxd_state *state = NULL;
2977 state = kmalloc(sizeof(struct drxd_state), GFP_KERNEL);
2980 memset(state, 0, sizeof(*state));
2982 memcpy(&state->ops, &drxd_ops, sizeof(struct dvb_frontend_ops));
2984 state->config = *config;
2988 mutex_init(&state->mutex);
2990 if (Read16(state, 0, 0, 0) < 0)
2993 memcpy(&state->frontend.ops, &drxd_ops,
2994 sizeof(struct dvb_frontend_ops));
2995 state->frontend.demodulator_priv = state;
2996 ConfigureMPEGOutput(state, 0);
2997 return &state->frontend;
3000 printk(KERN_ERR "drxd: not found\n");
3004 EXPORT_SYMBOL(drxd_attach);
3006 MODULE_DESCRIPTION("DRXD driver");
3007 MODULE_AUTHOR("Micronas");
3008 MODULE_LICENSE("GPL");