drivers/media/common/tuners/mxl5005s.c

   1 /*
   2     MaxLinear MXL5005S VSB/QAM/DVBT tuner driver
   3
   4     Copyright (C) 2008 MaxLinear
   5     Copyright (C) 2006 Steven Toth <stoth@linuxtv.org>
   6       Functions:
   7         mxl5005s_reset()
   8         mxl5005s_writereg()
   9         mxl5005s_writeregs()
  10         mxl5005s_init()
  11         mxl5005s_reconfigure()
  12         mxl5005s_AssignTunerMode()
  13         mxl5005s_set_params()
  14         mxl5005s_get_frequency()
  15         mxl5005s_get_bandwidth()
  16         mxl5005s_release()
  17         mxl5005s_attach()
  18
  19     Copyright (C) 2008 Realtek
  20     Copyright (C) 2008 Jan Hoogenraad
  21       Functions:
  22         mxl5005s_SetRfFreqHz()
  23
  24     This program is free software; you can redistribute it and/or modify
  25     it under the terms of the GNU General Public License as published by
  26     the Free Software Foundation; either version 2 of the License, or
  27     (at your option) any later version.
  28
  29     This program is distributed in the hope that it will be useful,
  30     but WITHOUT ANY WARRANTY; without even the implied warranty of
  31     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  32     GNU General Public License for more details.
  33
  34     You should have received a copy of the GNU General Public License
  35     along with this program; if not, write to the Free Software
  36     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  37
  38 */
  39
  40 /*
  41     History of this driver (Steven Toth):
  42       I was given a public release of a linux driver that included
  43       support for the MaxLinear MXL5005S silicon tuner. Analysis of
  44       the tuner driver showed clearly three things.
  45
  46       1. The tuner driver didn't support the LinuxTV tuner API
  47          so the code Realtek added had to be removed.
  48
  49       2. A significant amount of the driver is reference driver code
  50          from MaxLinear, I felt it was important to identify and
  51          preserve this.
  52
  53       3. New code has to be added to interface correctly with the
  54          LinuxTV API, as a regular kernel module.
  55
  56       Other than the reference driver enum's, I've clearly marked
  57       sections of the code and retained the copyright of the
  58       respective owners.
  59 */
  60 #include <linux/kernel.h>
  61 #include <linux/init.h>
  62 #include <linux/module.h>
  63 #include <linux/string.h>
  64 #include <linux/slab.h>
  65 #include <linux/delay.h>
  66 #include "dvb_frontend.h"
  67 #include "mxl5005s.h"
  68
  69 static int debug;
  70
  71 #define dprintk(level, arg...) do {    \
  72         if (level <= debug)            \
  73                 printk(arg);    \
  74         } while (0)
  75
  76 #define TUNER_REGS_NUM          104
  77 #define INITCTRL_NUM            40
  78
  79 #ifdef _MXL_PRODUCTION
  80 #define CHCTRL_NUM              39
  81 #else
  82 #define CHCTRL_NUM              36
  83 #endif
  84
  85 #define MXLCTRL_NUM             189
  86 #define MASTER_CONTROL_ADDR     9
  87
  88 /* Enumeration of Master Control Register State */
  89 enum master_control_state {
  90         MC_LOAD_START = 1,
  91         MC_POWER_DOWN,
  92         MC_SYNTH_RESET,
  93         MC_SEQ_OFF
  94 };
  95
  96 /* Enumeration of MXL5005 Tuner Modulation Type */
  97 enum {
  98         MXL_DEFAULT_MODULATION = 0,
  99         MXL_DVBT,
 100         MXL_ATSC,
 101         MXL_QAM,
 102         MXL_ANALOG_CABLE,
 103         MXL_ANALOG_OTA
 104 };
 105
 106 /* MXL5005 Tuner Register Struct */
 107 struct TunerReg {
 108         u16 Reg_Num;    /* Tuner Register Address */
 109         u16 Reg_Val;    /* Current sw programmed value waiting to be written */
 110 };
 111
 112 enum {
 113         /* Initialization Control Names */
 114         DN_IQTN_AMP_CUT = 1,       /* 1 */
 115         BB_MODE,                   /* 2 */
 116         BB_BUF,                    /* 3 */
 117         BB_BUF_OA,                 /* 4 */
 118         BB_ALPF_BANDSELECT,        /* 5 */
 119         BB_IQSWAP,                 /* 6 */
 120         BB_DLPF_BANDSEL,           /* 7 */
 121         RFSYN_CHP_GAIN,            /* 8 */
 122         RFSYN_EN_CHP_HIGAIN,       /* 9 */
 123         AGC_IF,                    /* 10 */
 124         AGC_RF,                    /* 11 */
 125         IF_DIVVAL,                 /* 12 */
 126         IF_VCO_BIAS,               /* 13 */
 127         CHCAL_INT_MOD_IF,          /* 14 */
 128         CHCAL_FRAC_MOD_IF,         /* 15 */
 129         DRV_RES_SEL,               /* 16 */
 130         I_DRIVER,                  /* 17 */
 131         EN_AAF,                    /* 18 */
 132         EN_3P,                     /* 19 */
 133         EN_AUX_3P,                 /* 20 */
 134         SEL_AAF_BAND,              /* 21 */
 135         SEQ_ENCLK16_CLK_OUT,       /* 22 */
 136         SEQ_SEL4_16B,              /* 23 */
 137         XTAL_CAPSELECT,            /* 24 */
 138         IF_SEL_DBL,                /* 25 */
 139         RFSYN_R_DIV,               /* 26 */
 140         SEQ_EXTSYNTHCALIF,         /* 27 */
 141         SEQ_EXTDCCAL,              /* 28 */
 142         AGC_EN_RSSI,               /* 29 */
 143         RFA_ENCLKRFAGC,            /* 30 */
 144         RFA_RSSI_REFH,             /* 31 */
 145         RFA_RSSI_REF,              /* 32 */
 146         RFA_RSSI_REFL,             /* 33 */
 147         RFA_FLR,                   /* 34 */
 148         RFA_CEIL,                  /* 35 */
 149         SEQ_EXTIQFSMPULSE,         /* 36 */
 150         OVERRIDE_1,                /* 37 */
 151         BB_INITSTATE_DLPF_TUNE,    /* 38 */
 152         TG_R_DIV,                  /* 39 */
 153         EN_CHP_LIN_B,              /* 40 */
 154
 155         /* Channel Change Control Names */
 156         DN_POLY = 51,              /* 51 */
 157         DN_RFGAIN,                 /* 52 */
 158         DN_CAP_RFLPF,              /* 53 */
 159         DN_EN_VHFUHFBAR,           /* 54 */
 160         DN_GAIN_ADJUST,            /* 55 */
 161         DN_IQTNBUF_AMP,            /* 56 */
 162         DN_IQTNGNBFBIAS_BST,       /* 57 */
 163         RFSYN_EN_OUTMUX,           /* 58 */
 164         RFSYN_SEL_VCO_OUT,         /* 59 */
 165         RFSYN_SEL_VCO_HI,          /* 60 */
 166         RFSYN_SEL_DIVM,            /* 61 */
 167         RFSYN_RF_DIV_BIAS,         /* 62 */
 168         DN_SEL_FREQ,               /* 63 */
 169         RFSYN_VCO_BIAS,            /* 64 */
 170         CHCAL_INT_MOD_RF,          /* 65 */
 171         CHCAL_FRAC_MOD_RF,         /* 66 */
 172         RFSYN_LPF_R,               /* 67 */
 173         CHCAL_EN_INT_RF,           /* 68 */
 174         TG_LO_DIVVAL,              /* 69 */
 175         TG_LO_SELVAL,              /* 70 */
 176         TG_DIV_VAL,                /* 71 */
 177         TG_VCO_BIAS,               /* 72 */
 178         SEQ_EXTPOWERUP,            /* 73 */
 179         OVERRIDE_2,                /* 74 */
 180         OVERRIDE_3,                /* 75 */
 181         OVERRIDE_4,                /* 76 */
 182         SEQ_FSM_PULSE,             /* 77 */
 183         GPIO_4B,                   /* 78 */
 184         GPIO_3B,                   /* 79 */
 185         GPIO_4,                    /* 80 */
 186         GPIO_3,                    /* 81 */
 187         GPIO_1B,                   /* 82 */
 188         DAC_A_ENABLE,              /* 83 */
 189         DAC_B_ENABLE,              /* 84 */
 190         DAC_DIN_A,                 /* 85 */
 191         DAC_DIN_B,                 /* 86 */
 192 #ifdef _MXL_PRODUCTION
 193         RFSYN_EN_DIV,              /* 87 */
 194         RFSYN_DIVM,                /* 88 */
 195         DN_BYPASS_AGC_I2C          /* 89 */
 196 #endif
 197 };
 198
 199 /*
 200  * The following context is source code provided by MaxLinear.
 201  * MaxLinear source code - Common_MXL.h (?)
 202  */
 203
 204 /* Constants */
 205 #define MXL5005S_REG_WRITING_TABLE_LEN_MAX      104
 206 #define MXL5005S_LATCH_BYTE                     0xfe
 207
 208 /* Register address, MSB, and LSB */
 209 #define MXL5005S_BB_IQSWAP_ADDR                 59
 210 #define MXL5005S_BB_IQSWAP_MSB                  0
 211 #define MXL5005S_BB_IQSWAP_LSB                  0
 212
 213 #define MXL5005S_BB_DLPF_BANDSEL_ADDR           53
 214 #define MXL5005S_BB_DLPF_BANDSEL_MSB            4
 215 #define MXL5005S_BB_DLPF_BANDSEL_LSB            3
 216
 217 /* Standard modes */
 218 enum {
 219         MXL5005S_STANDARD_DVBT,
 220         MXL5005S_STANDARD_ATSC,
 221 };
 222 #define MXL5005S_STANDARD_MODE_NUM              2
 223
 224 /* Bandwidth modes */
 225 enum {
 226         MXL5005S_BANDWIDTH_6MHZ = 6000000,
 227         MXL5005S_BANDWIDTH_7MHZ = 7000000,
 228         MXL5005S_BANDWIDTH_8MHZ = 8000000,
 229 };
 230 #define MXL5005S_BANDWIDTH_MODE_NUM             3
 231
 232 /* MXL5005 Tuner Control Struct */
 233 struct TunerControl {
 234         u16 Ctrl_Num;   /* Control Number */
 235         u16 size;       /* Number of bits to represent Value */
 236         u16 addr[25];   /* Array of Tuner Register Address for each bit pos */
 237         u16 bit[25];    /* Array of bit pos in Reg Addr for each bit pos */
 238         u16 val[25];    /* Binary representation of Value */
 239 };
 240
 241 /* MXL5005 Tuner Struct */
 242 struct mxl5005s_state {
 243         u8      Mode;           /* 0: Analog Mode ; 1: Digital Mode */
 244         u8      IF_Mode;        /* for Analog Mode, 0: zero IF; 1: low IF */
 245         u32     Chan_Bandwidth; /* filter  channel bandwidth (6, 7, 8) */
 246         u32     IF_OUT;         /* Desired IF Out Frequency */
 247         u16     IF_OUT_LOAD;    /* IF Out Load Resistor (200/300 Ohms) */
 248         u32     RF_IN;          /* RF Input Frequency */
 249         u32     Fxtal;          /* XTAL Frequency */
 250         u8      AGC_Mode;       /* AGC Mode 0: Dual AGC; 1: Single AGC */
 251         u16     TOP;            /* Value: take over point */
 252         u8      CLOCK_OUT;      /* 0: turn off clk out; 1: turn on clock out */
 253         u8      DIV_OUT;        /* 4MHz or 16MHz */
 254         u8      CAPSELECT;      /* 0: disable On-Chip pulling cap; 1: enable */
 255         u8      EN_RSSI;        /* 0: disable RSSI; 1: enable RSSI */
 256
 257         /* Modulation Type; */
 258         /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */
 259         u8      Mod_Type;
 260
 261         /* Tracking Filter Type */
 262         /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */
 263         u8      TF_Type;
 264
 265         /* Calculated Settings */
 266         u32     RF_LO;          /* Synth RF LO Frequency */
 267         u32     IF_LO;          /* Synth IF LO Frequency */
 268         u32     TG_LO;          /* Synth TG_LO Frequency */
 269
 270         /* Pointers to ControlName Arrays */
 271         u16     Init_Ctrl_Num;          /* Number of INIT Control Names */
 272         struct TunerControl
 273                 Init_Ctrl[INITCTRL_NUM]; /* INIT Control Names Array Pointer */
 274
 275         u16     CH_Ctrl_Num;            /* Number of CH Control Names */
 276         struct TunerControl
 277                 CH_Ctrl[CHCTRL_NUM];    /* CH Control Name Array Pointer */
 278
 279         u16     MXL_Ctrl_Num;           /* Number of MXL Control Names */
 280         struct TunerControl
 281                 MXL_Ctrl[MXLCTRL_NUM];  /* MXL Control Name Array Pointer */
 282
 283         /* Pointer to Tuner Register Array */
 284         u16     TunerRegs_Num;          /* Number of Tuner Registers */
 285         struct TunerReg
 286                 TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */
 287
 288         /* Linux driver framework specific */
 289         struct mxl5005s_config *config;
 290         struct dvb_frontend *frontend;
 291         struct i2c_adapter *i2c;
 292
 293         /* Cache values */
 294         u32 current_mode;
 295
 296 };
 297
 298 static u16 MXL_GetMasterControl(u8 *MasterReg, int state);
 299 static u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value);
 300 static u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value);
 301 static void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit,
 302         u8 bitVal);
 303 static u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum,
 304         u8 *RegVal, int *count);
 305 static u32 MXL_Ceiling(u32 value, u32 resolution);
 306 static u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal);
 307 static u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum,
 308         u32 value, u16 controlGroup);
 309 static u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val);
 310 static u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum,
 311         u8 *RegVal, int *count);
 312 static u32 MXL_GetXtalInt(u32 Xtal_Freq);
 313 static u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq);
 314 static void MXL_SynthIFLO_Calc(struct dvb_frontend *fe);
 315 static void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe);
 316 static u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum,
 317         u8 *RegVal, int *count);
 318 static int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable,
 319         u8 *datatable, u8 len);
 320 static u16 MXL_IFSynthInit(struct dvb_frontend *fe);
 321 static int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type,
 322         u32 bandwidth);
 323 static int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type,
 324         u32 bandwidth);
 325
 326 /* ----------------------------------------------------------------
 327  * Begin: Custom code salvaged from the Realtek driver.
 328  * Copyright (C) 2008 Realtek
 329  * Copyright (C) 2008 Jan Hoogenraad
 330  * This code is placed under the terms of the GNU General Public License
 331  *
 332  * Released by Realtek under GPLv2.
 333  * Thanks to Realtek for a lot of support we received !
 334  *
 335  *  Revision: 080314 - original version
 336  */
 337
 338 static int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz)
 339 {
 340         struct mxl5005s_state *state = fe->tuner_priv;
 341         unsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
 342         unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
 343         int TableLen;
 344
 345         u32 IfDivval = 0;
 346         unsigned char MasterControlByte;
 347
 348         dprintk(1, "%s() freq=%ld\n", __func__, RfFreqHz);
 349
 350         /* Set MxL5005S tuner RF frequency according to example code. */
 351
 352         /* Tuner RF frequency setting stage 0 */
 353         MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET);
 354         AddrTable[0] = MASTER_CONTROL_ADDR;
 355         ByteTable[0] |= state->config->AgcMasterByte;
 356
 357         mxl5005s_writeregs(fe, AddrTable, ByteTable, 1);
 358
 359         /* Tuner RF frequency setting stage 1 */
 360         MXL_TuneRF(fe, RfFreqHz);
 361
 362         MXL_ControlRead(fe, IF_DIVVAL, &IfDivval);
 363
 364         MXL_ControlWrite(fe, SEQ_FSM_PULSE, 0);
 365         MXL_ControlWrite(fe, SEQ_EXTPOWERUP, 1);
 366         MXL_ControlWrite(fe, IF_DIVVAL, 8);
 367         MXL_GetCHRegister(fe, AddrTable, ByteTable, &TableLen);
 368
 369         MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START);
 370         AddrTable[TableLen] = MASTER_CONTROL_ADDR ;
 371         ByteTable[TableLen] = MasterControlByte |
 372                 state->config->AgcMasterByte;
 373         TableLen += 1;
 374
 375         mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen);
 376
 377         /* Wait 30 ms. */
 378         msleep(150);
 379
 380         /* Tuner RF frequency setting stage 2 */
 381         MXL_ControlWrite(fe, SEQ_FSM_PULSE, 1);
 382         MXL_ControlWrite(fe, IF_DIVVAL, IfDivval);
 383         MXL_GetCHRegister_ZeroIF(fe, AddrTable, ByteTable, &TableLen);
 384
 385         MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START);
 386         AddrTable[TableLen] = MASTER_CONTROL_ADDR ;
 387         ByteTable[TableLen] = MasterControlByte |
 388                 state->config->AgcMasterByte ;
 389         TableLen += 1;
 390
 391         mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen);
 392
 393         msleep(100);
 394
 395         return 0;
 396 }
 397 /* End: Custom code taken from the Realtek driver */
 398
 399 /* ----------------------------------------------------------------
 400  * Begin: Reference driver code found in the Realtek driver.
 401  * Copyright (C) 2008 MaxLinear
 402  */
 403 static u16 MXL5005_RegisterInit(struct dvb_frontend *fe)
 404 {
 405         struct mxl5005s_state *state = fe->tuner_priv;
 406         state->TunerRegs_Num = TUNER_REGS_NUM ;
 407
 408         state->TunerRegs[0].Reg_Num = 9 ;
 409         state->TunerRegs[0].Reg_Val = 0x40 ;
 410
 411         state->TunerRegs[1].Reg_Num = 11 ;
 412         state->TunerRegs[1].Reg_Val = 0x19 ;
 413
 414         state->TunerRegs[2].Reg_Num = 12 ;
 415         state->TunerRegs[2].Reg_Val = 0x60 ;
 416
 417         state->TunerRegs[3].Reg_Num = 13 ;
 418         state->TunerRegs[3].Reg_Val = 0x00 ;
 419
 420         state->TunerRegs[4].Reg_Num = 14 ;
 421         state->TunerRegs[4].Reg_Val = 0x00 ;
 422
 423         state->TunerRegs[5].Reg_Num = 15 ;
 424         state->TunerRegs[5].Reg_Val = 0xC0 ;
 425
 426         state->TunerRegs[6].Reg_Num = 16 ;
 427         state->TunerRegs[6].Reg_Val = 0x00 ;
 428
 429         state->TunerRegs[7].Reg_Num = 17 ;
 430         state->TunerRegs[7].Reg_Val = 0x00 ;
 431
 432         state->TunerRegs[8].Reg_Num = 18 ;
 433         state->TunerRegs[8].Reg_Val = 0x00 ;
 434
 435         state->TunerRegs[9].Reg_Num = 19 ;
 436         state->TunerRegs[9].Reg_Val = 0x34 ;
 437
 438         state->TunerRegs[10].Reg_Num = 21 ;
 439         state->TunerRegs[10].Reg_Val = 0x00 ;
 440
 441         state->TunerRegs[11].Reg_Num = 22 ;
 442         state->TunerRegs[11].Reg_Val = 0x6B ;
 443
 444         state->TunerRegs[12].Reg_Num = 23 ;
 445         state->TunerRegs[12].Reg_Val = 0x35 ;
 446
 447         state->TunerRegs[13].Reg_Num = 24 ;
 448         state->TunerRegs[13].Reg_Val = 0x70 ;
 449
 450         state->TunerRegs[14].Reg_Num = 25 ;
 451         state->TunerRegs[14].Reg_Val = 0x3E ;
 452
 453         state->TunerRegs[15].Reg_Num = 26 ;
 454         state->TunerRegs[15].Reg_Val = 0x82 ;
 455
 456         state->TunerRegs[16].Reg_Num = 31 ;
 457         state->TunerRegs[16].Reg_Val = 0x00 ;
 458
 459         state->TunerRegs[17].Reg_Num = 32 ;
 460         state->TunerRegs[17].Reg_Val = 0x40 ;
 461
 462         state->TunerRegs[18].Reg_Num = 33 ;
 463         state->TunerRegs[18].Reg_Val = 0x53 ;
 464
 465         state->TunerRegs[19].Reg_Num = 34 ;
 466         state->TunerRegs[19].Reg_Val = 0x81 ;
 467
 468         state->TunerRegs[20].Reg_Num = 35 ;
 469         state->TunerRegs[20].Reg_Val = 0xC9 ;
 470
 471         state->TunerRegs[21].Reg_Num = 36 ;
 472         state->TunerRegs[21].Reg_Val = 0x01 ;
 473
 474         state->TunerRegs[22].Reg_Num = 37 ;
 475         state->TunerRegs[22].Reg_Val = 0x00 ;
 476
 477         state->TunerRegs[23].Reg_Num = 41 ;
 478         state->TunerRegs[23].Reg_Val = 0x00 ;
 479
 480         state->TunerRegs[24].Reg_Num = 42 ;
 481         state->TunerRegs[24].Reg_Val = 0xF8 ;
 482
 483         state->TunerRegs[25].Reg_Num = 43 ;
 484         state->TunerRegs[25].Reg_Val = 0x43 ;
 485
 486         state->TunerRegs[26].Reg_Num = 44 ;
 487         state->TunerRegs[26].Reg_Val = 0x20 ;
 488
 489         state->TunerRegs[27].Reg_Num = 45 ;
 490         state->TunerRegs[27].Reg_Val = 0x80 ;
 491
 492         state->TunerRegs[28].Reg_Num = 46 ;
 493         state->TunerRegs[28].Reg_Val = 0x88 ;
 494
 495         state->TunerRegs[29].Reg_Num = 47 ;
 496         state->TunerRegs[29].Reg_Val = 0x86 ;
 497
 498         state->TunerRegs[30].Reg_Num = 48 ;
 499         state->TunerRegs[30].Reg_Val = 0x00 ;
 500
 501         state->TunerRegs[31].Reg_Num = 49 ;
 502         state->TunerRegs[31].Reg_Val = 0x00 ;
 503
 504         state->TunerRegs[32].Reg_Num = 53 ;
 505         state->TunerRegs[32].Reg_Val = 0x94 ;
 506
 507         state->TunerRegs[33].Reg_Num = 54 ;
 508         state->TunerRegs[33].Reg_Val = 0xFA ;
 509
 510         state->TunerRegs[34].Reg_Num = 55 ;
 511         state->TunerRegs[34].Reg_Val = 0x92 ;
 512
 513         state->TunerRegs[35].Reg_Num = 56 ;
 514         state->TunerRegs[35].Reg_Val = 0x80 ;
 515
 516         state->TunerRegs[36].Reg_Num = 57 ;
 517         state->TunerRegs[36].Reg_Val = 0x41 ;
 518
 519         state->TunerRegs[37].Reg_Num = 58 ;
 520         state->TunerRegs[37].Reg_Val = 0xDB ;
 521
 522         state->TunerRegs[38].Reg_Num = 59 ;
 523         state->TunerRegs[38].Reg_Val = 0x00 ;
 524
 525         state->TunerRegs[39].Reg_Num = 60 ;
 526         state->TunerRegs[39].Reg_Val = 0x00 ;
 527
 528         state->TunerRegs[40].Reg_Num = 61 ;
 529         state->TunerRegs[40].Reg_Val = 0x00 ;
 530
 531         state->TunerRegs[41].Reg_Num = 62 ;
 532         state->TunerRegs[41].Reg_Val = 0x00 ;
 533
 534         state->TunerRegs[42].Reg_Num = 65 ;
 535         state->TunerRegs[42].Reg_Val = 0xF8 ;
 536
 537         state->TunerRegs[43].Reg_Num = 66 ;
 538         state->TunerRegs[43].Reg_Val = 0xE4 ;
 539
 540         state->TunerRegs[44].Reg_Num = 67 ;
 541         state->TunerRegs[44].Reg_Val = 0x90 ;
 542
 543         state->TunerRegs[45].Reg_Num = 68 ;
 544         state->TunerRegs[45].Reg_Val = 0xC0 ;
 545
 546         state->TunerRegs[46].Reg_Num = 69 ;
 547         state->TunerRegs[46].Reg_Val = 0x01 ;
 548
 549         state->TunerRegs[47].Reg_Num = 70 ;
 550         state->TunerRegs[47].Reg_Val = 0x50 ;
 551
 552         state->TunerRegs[48].Reg_Num = 71 ;
 553         state->TunerRegs[48].Reg_Val = 0x06 ;
 554
 555         state->TunerRegs[49].Reg_Num = 72 ;
 556         state->TunerRegs[49].Reg_Val = 0x00 ;
 557
 558         state->TunerRegs[50].Reg_Num = 73 ;
 559         state->TunerRegs[50].Reg_Val = 0x20 ;
 560
 561         state->TunerRegs[51].Reg_Num = 76 ;
 562         state->TunerRegs[51].Reg_Val = 0xBB ;
 563
 564         state->TunerRegs[52].Reg_Num = 77 ;
 565         state->TunerRegs[52].Reg_Val = 0x13 ;
 566
 567         state->TunerRegs[53].Reg_Num = 81 ;
 568         state->TunerRegs[53].Reg_Val = 0x04 ;
 569
 570         state->TunerRegs[54].Reg_Num = 82 ;
 571         state->TunerRegs[54].Reg_Val = 0x75 ;
 572
 573         state->TunerRegs[55].Reg_Num = 83 ;
 574         state->TunerRegs[55].Reg_Val = 0x00 ;
 575
 576         state->TunerRegs[56].Reg_Num = 84 ;
 577         state->TunerRegs[56].Reg_Val = 0x00 ;
 578
 579         state->TunerRegs[57].Reg_Num = 85 ;
 580         state->TunerRegs[57].Reg_Val = 0x00 ;
 581
 582         state->TunerRegs[58].Reg_Num = 91 ;
 583         state->TunerRegs[58].Reg_Val = 0x70 ;
 584
 585         state->TunerRegs[59].Reg_Num = 92 ;
 586         state->TunerRegs[59].Reg_Val = 0x00 ;
 587
 588         state->TunerRegs[60].Reg_Num = 93 ;
 589         state->TunerRegs[60].Reg_Val = 0x00 ;
 590
 591         state->TunerRegs[61].Reg_Num = 94 ;
 592         state->TunerRegs[61].Reg_Val = 0x00 ;
 593
 594         state->TunerRegs[62].Reg_Num = 95 ;
 595         state->TunerRegs[62].Reg_Val = 0x0C ;
 596
 597         state->TunerRegs[63].Reg_Num = 96 ;
 598         state->TunerRegs[63].Reg_Val = 0x00 ;
 599
 600         state->TunerRegs[64].Reg_Num = 97 ;
 601         state->TunerRegs[64].Reg_Val = 0x00 ;
 602
 603         state->TunerRegs[65].Reg_Num = 98 ;
 604         state->TunerRegs[65].Reg_Val = 0xE2 ;
 605
 606         state->TunerRegs[66].Reg_Num = 99 ;
 607         state->TunerRegs[66].Reg_Val = 0x00 ;
 608
 609         state->TunerRegs[67].Reg_Num = 100 ;
 610         state->TunerRegs[67].Reg_Val = 0x00 ;
 611
 612         state->TunerRegs[68].Reg_Num = 101 ;
 613         state->TunerRegs[68].Reg_Val = 0x12 ;
 614
 615         state->TunerRegs[69].Reg_Num = 102 ;
 616         state->TunerRegs[69].Reg_Val = 0x80 ;
 617
 618         state->TunerRegs[70].Reg_Num = 103 ;
 619         state->TunerRegs[70].Reg_Val = 0x32 ;
 620
 621         state->TunerRegs[71].Reg_Num = 104 ;
 622         state->TunerRegs[71].Reg_Val = 0xB4 ;
 623
 624         state->TunerRegs[72].Reg_Num = 105 ;
 625         state->TunerRegs[72].Reg_Val = 0x60 ;
 626
 627         state->TunerRegs[73].Reg_Num = 106 ;
 628         state->TunerRegs[73].Reg_Val = 0x83 ;
 629
 630         state->TunerRegs[74].Reg_Num = 107 ;
 631         state->TunerRegs[74].Reg_Val = 0x84 ;
 632
 633         state->TunerRegs[75].Reg_Num = 108 ;
 634         state->TunerRegs[75].Reg_Val = 0x9C ;
 635
 636         state->TunerRegs[76].Reg_Num = 109 ;
 637         state->TunerRegs[76].Reg_Val = 0x02 ;
 638
 639         state->TunerRegs[77].Reg_Num = 110 ;
 640         state->TunerRegs[77].Reg_Val = 0x81 ;
 641
 642         state->TunerRegs[78].Reg_Num = 111 ;
 643         state->TunerRegs[78].Reg_Val = 0xC0 ;
 644
 645         state->TunerRegs[79].Reg_Num = 112 ;
 646         state->TunerRegs[79].Reg_Val = 0x10 ;
 647
 648         state->TunerRegs[80].Reg_Num = 131 ;
 649         state->TunerRegs[80].Reg_Val = 0x8A ;
 650
 651         state->TunerRegs[81].Reg_Num = 132 ;
 652         state->TunerRegs[81].Reg_Val = 0x10 ;
 653
 654         state->TunerRegs[82].Reg_Num = 133 ;
 655         state->TunerRegs[82].Reg_Val = 0x24 ;
 656
 657         state->TunerRegs[83].Reg_Num = 134 ;
 658         state->TunerRegs[83].Reg_Val = 0x00 ;
 659
 660         state->TunerRegs[84].Reg_Num = 135 ;
 661         state->TunerRegs[84].Reg_Val = 0x00 ;
 662
 663         state->TunerRegs[85].Reg_Num = 136 ;
 664         state->TunerRegs[85].Reg_Val = 0x7E ;
 665
 666         state->TunerRegs[86].Reg_Num = 137 ;
 667         state->TunerRegs[86].Reg_Val = 0x40 ;
 668
 669         state->TunerRegs[87].Reg_Num = 138 ;
 670         state->TunerRegs[87].Reg_Val = 0x38 ;
 671
 672         state->TunerRegs[88].Reg_Num = 146 ;
 673         state->TunerRegs[88].Reg_Val = 0xF6 ;
 674
 675         state->TunerRegs[89].Reg_Num = 147 ;
 676         state->TunerRegs[89].Reg_Val = 0x1A ;
 677
 678         state->TunerRegs[90].Reg_Num = 148 ;
 679         state->TunerRegs[90].Reg_Val = 0x62 ;
 680
 681         state->TunerRegs[91].Reg_Num = 149 ;
 682         state->TunerRegs[91].Reg_Val = 0x33 ;
 683
 684         state->TunerRegs[92].Reg_Num = 150 ;
 685         state->TunerRegs[92].Reg_Val = 0x80 ;
 686
 687         state->TunerRegs[93].Reg_Num = 156 ;
 688         state->TunerRegs[93].Reg_Val = 0x56 ;
 689
 690         state->TunerRegs[94].Reg_Num = 157 ;
 691         state->TunerRegs[94].Reg_Val = 0x17 ;
 692
 693         state->TunerRegs[95].Reg_Num = 158 ;
 694         state->TunerRegs[95].Reg_Val = 0xA9 ;
 695
 696         state->TunerRegs[96].Reg_Num = 159 ;
 697         state->TunerRegs[96].Reg_Val = 0x00 ;
 698
 699         state->TunerRegs[97].Reg_Num = 160 ;
 700         state->TunerRegs[97].Reg_Val = 0x00 ;
 701
 702         state->TunerRegs[98].Reg_Num = 161 ;
 703         state->TunerRegs[98].Reg_Val = 0x00 ;
 704
 705         state->TunerRegs[99].Reg_Num = 162 ;
 706         state->TunerRegs[99].Reg_Val = 0x40 ;
 707
 708         state->TunerRegs[100].Reg_Num = 166 ;
 709         state->TunerRegs[100].Reg_Val = 0xAE ;
 710
 711         state->TunerRegs[101].Reg_Num = 167 ;
 712         state->TunerRegs[101].Reg_Val = 0x1B ;
 713
 714         state->TunerRegs[102].Reg_Num = 168 ;
 715         state->TunerRegs[102].Reg_Val = 0xF2 ;
 716
 717         state->TunerRegs[103].Reg_Num = 195 ;
 718         state->TunerRegs[103].Reg_Val = 0x00 ;
 719
 720         return 0 ;
 721 }
 722
 723 static u16 MXL5005_ControlInit(struct dvb_frontend *fe)
 724 {
 725         struct mxl5005s_state *state = fe->tuner_priv;
 726         state->Init_Ctrl_Num = INITCTRL_NUM;
 727
 728         state->Init_Ctrl[0].Ctrl_Num = DN_IQTN_AMP_CUT ;
 729         state->Init_Ctrl[0].size = 1 ;
 730         state->Init_Ctrl[0].addr[0] = 73;
 731         state->Init_Ctrl[0].bit[0] = 7;
 732         state->Init_Ctrl[0].val[0] = 0;
 733
 734         state->Init_Ctrl[1].Ctrl_Num = BB_MODE ;
 735         state->Init_Ctrl[1].size = 1 ;
 736         state->Init_Ctrl[1].addr[0] = 53;
 737         state->Init_Ctrl[1].bit[0] = 2;
 738         state->Init_Ctrl[1].val[0] = 1;
 739
 740         state->Init_Ctrl[2].Ctrl_Num = BB_BUF ;
 741         state->Init_Ctrl[2].size = 2 ;
 742         state->Init_Ctrl[2].addr[0] = 53;
 743         state->Init_Ctrl[2].bit[0] = 1;
 744         state->Init_Ctrl[2].val[0] = 0;
 745         state->Init_Ctrl[2].addr[1] = 57;
 746         state->Init_Ctrl[2].bit[1] = 0;
 747         state->Init_Ctrl[2].val[1] = 1;
 748
 749         state->Init_Ctrl[3].Ctrl_Num = BB_BUF_OA ;
 750         state->Init_Ctrl[3].size = 1 ;
 751         state->Init_Ctrl[3].addr[0] = 53;
 752         state->Init_Ctrl[3].bit[0] = 0;
 753         state->Init_Ctrl[3].val[0] = 0;
 754
 755         state->Init_Ctrl[4].Ctrl_Num = BB_ALPF_BANDSELECT ;
 756         state->Init_Ctrl[4].size = 3 ;
 757         state->Init_Ctrl[4].addr[0] = 53;
 758         state->Init_Ctrl[4].bit[0] = 5;
 759         state->Init_Ctrl[4].val[0] = 0;
 760         state->Init_Ctrl[4].addr[1] = 53;
 761         state->Init_Ctrl[4].bit[1] = 6;
 762         state->Init_Ctrl[4].val[1] = 0;
 763         state->Init_Ctrl[4].addr[2] = 53;
 764         state->Init_Ctrl[4].bit[2] = 7;
 765         state->Init_Ctrl[4].val[2] = 1;
 766
 767         state->Init_Ctrl[5].Ctrl_Num = BB_IQSWAP ;
 768         state->Init_Ctrl[5].size = 1 ;
 769         state->Init_Ctrl[5].addr[0] = 59;
 770         state->Init_Ctrl[5].bit[0] = 0;
 771         state->Init_Ctrl[5].val[0] = 0;
 772
 773         state->Init_Ctrl[6].Ctrl_Num = BB_DLPF_BANDSEL ;
 774         state->Init_Ctrl[6].size = 2 ;
 775         state->Init_Ctrl[6].addr[0] = 53;
 776         state->Init_Ctrl[6].bit[0] = 3;
 777         state->Init_Ctrl[6].val[0] = 0;
 778         state->Init_Ctrl[6].addr[1] = 53;
 779         state->Init_Ctrl[6].bit[1] = 4;
 780         state->Init_Ctrl[6].val[1] = 1;
 781
 782         state->Init_Ctrl[7].Ctrl_Num = RFSYN_CHP_GAIN ;
 783         state->Init_Ctrl[7].size = 4 ;
 784         state->Init_Ctrl[7].addr[0] = 22;
 785         state->Init_Ctrl[7].bit[0] = 4;
 786         state->Init_Ctrl[7].val[0] = 0;
 787         state->Init_Ctrl[7].addr[1] = 22;
 788         state->Init_Ctrl[7].bit[1] = 5;
 789         state->Init_Ctrl[7].val[1] = 1;
 790         state->Init_Ctrl[7].addr[2] = 22;
 791         state->Init_Ctrl[7].bit[2] = 6;
 792         state->Init_Ctrl[7].val[2] = 1;
 793         state->Init_Ctrl[7].addr[3] = 22;
 794         state->Init_Ctrl[7].bit[3] = 7;
 795         state->Init_Ctrl[7].val[3] = 0;
 796
 797         state->Init_Ctrl[8].Ctrl_Num = RFSYN_EN_CHP_HIGAIN ;
 798         state->Init_Ctrl[8].size = 1 ;
 799         state->Init_Ctrl[8].addr[0] = 22;
 800         state->Init_Ctrl[8].bit[0] = 2;
 801         state->Init_Ctrl[8].val[0] = 0;
 802
 803         state->Init_Ctrl[9].Ctrl_Num = AGC_IF ;
 804         state->Init_Ctrl[9].size = 4 ;
 805         state->Init_Ctrl[9].addr[0] = 76;
 806         state->Init_Ctrl[9].bit[0] = 0;
 807         state->Init_Ctrl[9].val[0] = 1;
 808         state->Init_Ctrl[9].addr[1] = 76;
 809         state->Init_Ctrl[9].bit[1] = 1;
 810         state->Init_Ctrl[9].val[1] = 1;
 811         state->Init_Ctrl[9].addr[2] = 76;
 812         state->Init_Ctrl[9].bit[2] = 2;
 813         state->Init_Ctrl[9].val[2] = 0;
 814         state->Init_Ctrl[9].addr[3] = 76;
 815         state->Init_Ctrl[9].bit[3] = 3;
 816         state->Init_Ctrl[9].val[3] = 1;
 817
 818         state->Init_Ctrl[10].Ctrl_Num = AGC_RF ;
 819         state->Init_Ctrl[10].size = 4 ;
 820         state->Init_Ctrl[10].addr[0] = 76;
 821         state->Init_Ctrl[10].bit[0] = 4;
 822         state->Init_Ctrl[10].val[0] = 1;
 823         state->Init_Ctrl[10].addr[1] = 76;
 824         state->Init_Ctrl[10].bit[1] = 5;
 825         state->Init_Ctrl[10].val[1] = 1;
 826         state->Init_Ctrl[10].addr[2] = 76;
 827         state->Init_Ctrl[10].bit[2] = 6;
 828         state->Init_Ctrl[10].val[2] = 0;
 829         state->Init_Ctrl[10].addr[3] = 76;
 830         state->Init_Ctrl[10].bit[3] = 7;
 831         state->Init_Ctrl[10].val[3] = 1;
 832
 833         state->Init_Ctrl[11].Ctrl_Num = IF_DIVVAL ;
 834         state->Init_Ctrl[11].size = 5 ;
 835         state->Init_Ctrl[11].addr[0] = 43;
 836         state->Init_Ctrl[11].bit[0] = 3;
 837         state->Init_Ctrl[11].val[0] = 0;
 838         state->Init_Ctrl[11].addr[1] = 43;
 839         state->Init_Ctrl[11].bit[1] = 4;
 840         state->Init_Ctrl[11].val[1] = 0;
 841         state->Init_Ctrl[11].addr[2] = 43;
 842         state->Init_Ctrl[11].bit[2] = 5;
 843         state->Init_Ctrl[11].val[2] = 0;
 844         state->Init_Ctrl[11].addr[3] = 43;
 845         state->Init_Ctrl[11].bit[3] = 6;
 846         state->Init_Ctrl[11].val[3] = 1;
 847         state->Init_Ctrl[11].addr[4] = 43;
 848         state->Init_Ctrl[11].bit[4] = 7;
 849         state->Init_Ctrl[11].val[4] = 0;
 850
 851         state->Init_Ctrl[12].Ctrl_Num = IF_VCO_BIAS ;
 852         state->Init_Ctrl[12].size = 6 ;
 853         state->Init_Ctrl[12].addr[0] = 44;
 854         state->Init_Ctrl[12].bit[0] = 2;
 855         state->Init_Ctrl[12].val[0] = 0;
 856         state->Init_Ctrl[12].addr[1] = 44;
 857         state->Init_Ctrl[12].bit[1] = 3;
 858         state->Init_Ctrl[12].val[1] = 0;
 859         state->Init_Ctrl[12].addr[2] = 44;
 860         state->Init_Ctrl[12].bit[2] = 4;
 861         state->Init_Ctrl[12].val[2] = 0;
 862         state->Init_Ctrl[12].addr[3] = 44;
 863         state->Init_Ctrl[12].bit[3] = 5;
 864         state->Init_Ctrl[12].val[3] = 1;
 865         state->Init_Ctrl[12].addr[4] = 44;
 866         state->Init_Ctrl[12].bit[4] = 6;
 867         state->Init_Ctrl[12].val[4] = 0;
 868         state->Init_Ctrl[12].addr[5] = 44;
 869         state->Init_Ctrl[12].bit[5] = 7;
 870         state->Init_Ctrl[12].val[5] = 0;
 871
 872         state->Init_Ctrl[13].Ctrl_Num = CHCAL_INT_MOD_IF ;
 873         state->Init_Ctrl[13].size = 7 ;
 874         state->Init_Ctrl[13].addr[0] = 11;
 875         state->Init_Ctrl[13].bit[0] = 0;
 876         state->Init_Ctrl[13].val[0] = 1;
 877         state->Init_Ctrl[13].addr[1] = 11;
 878         state->Init_Ctrl[13].bit[1] = 1;
 879         state->Init_Ctrl[13].val[1] = 0;
 880         state->Init_Ctrl[13].addr[2] = 11;
 881         state->Init_Ctrl[13].bit[2] = 2;
 882         state->Init_Ctrl[13].val[2] = 0;
 883         state->Init_Ctrl[13].addr[3] = 11;
 884         state->Init_Ctrl[13].bit[3] = 3;
 885         state->Init_Ctrl[13].val[3] = 1;
 886         state->Init_Ctrl[13].addr[4] = 11;
 887         state->Init_Ctrl[13].bit[4] = 4;
 888         state->Init_Ctrl[13].val[4] = 1;
 889         state->Init_Ctrl[13].addr[5] = 11;
 890         state->Init_Ctrl[13].bit[5] = 5;
 891         state->Init_Ctrl[13].val[5] = 0;
 892         state->Init_Ctrl[13].addr[6] = 11;
 893         state->Init_Ctrl[13].bit[6] = 6;
 894         state->Init_Ctrl[13].val[6] = 0;
 895
 896         state->Init_Ctrl[14].Ctrl_Num = CHCAL_FRAC_MOD_IF ;
 897         state->Init_Ctrl[14].size = 16 ;
 898         state->Init_Ctrl[14].addr[0] = 13;
 899         state->Init_Ctrl[14].bit[0] = 0;
 900         state->Init_Ctrl[14].val[0] = 0;
 901         state->Init_Ctrl[14].addr[1] = 13;
 902         state->Init_Ctrl[14].bit[1] = 1;
 903         state->Init_Ctrl[14].val[1] = 0;
 904         state->Init_Ctrl[14].addr[2] = 13;
 905         state->Init_Ctrl[14].bit[2] = 2;
 906         state->Init_Ctrl[14].val[2] = 0;
 907         state->Init_Ctrl[14].addr[3] = 13;
 908         state->Init_Ctrl[14].bit[3] = 3;
 909         state->Init_Ctrl[14].val[3] = 0;
 910         state->Init_Ctrl[14].addr[4] = 13;
 911         state->Init_Ctrl[14].bit[4] = 4;
 912         state->Init_Ctrl[14].val[4] = 0;
 913         state->Init_Ctrl[14].addr[5] = 13;
 914         state->Init_Ctrl[14].bit[5] = 5;
 915         state->Init_Ctrl[14].val[5] = 0;
 916         state->Init_Ctrl[14].addr[6] = 13;
 917         state->Init_Ctrl[14].bit[6] = 6;
 918         state->Init_Ctrl[14].val[6] = 0;
 919         state->Init_Ctrl[14].addr[7] = 13;
 920         state->Init_Ctrl[14].bit[7] = 7;
 921         state->Init_Ctrl[14].val[7] = 0;
 922         state->Init_Ctrl[14].addr[8] = 12;
 923         state->Init_Ctrl[14].bit[8] = 0;
 924         state->Init_Ctrl[14].val[8] = 0;
 925         state->Init_Ctrl[14].addr[9] = 12;
 926         state->Init_Ctrl[14].bit[9] = 1;
 927         state->Init_Ctrl[14].val[9] = 0;
 928         state->Init_Ctrl[14].addr[10] = 12;
 929         state->Init_Ctrl[14].bit[10] = 2;
 930         state->Init_Ctrl[14].val[10] = 0;
 931         state->Init_Ctrl[14].addr[11] = 12;
 932         state->Init_Ctrl[14].bit[11] = 3;
 933         state->Init_Ctrl[14].val[11] = 0;
 934         state->Init_Ctrl[14].addr[12] = 12;
 935         state->Init_Ctrl[14].bit[12] = 4;
 936         state->Init_Ctrl[14].val[12] = 0;
 937         state->Init_Ctrl[14].addr[13] = 12;
 938         state->Init_Ctrl[14].bit[13] = 5;
 939         state->Init_Ctrl[14].val[13] = 1;
 940         state->Init_Ctrl[14].addr[14] = 12;
 941         state->Init_Ctrl[14].bit[14] = 6;
 942         state->Init_Ctrl[14].val[14] = 1;
 943         state->Init_Ctrl[14].addr[15] = 12;
 944         state->Init_Ctrl[14].bit[15] = 7;
 945         state->Init_Ctrl[14].val[15] = 0;
 946
 947         state->Init_Ctrl[15].Ctrl_Num = DRV_RES_SEL ;
 948         state->Init_Ctrl[15].size = 3 ;
 949         state->Init_Ctrl[15].addr[0] = 147;
 950         state->Init_Ctrl[15].bit[0] = 2;
 951         state->Init_Ctrl[15].val[0] = 0;
 952         state->Init_Ctrl[15].addr[1] = 147;
 953         state->Init_Ctrl[15].bit[1] = 3;
 954         state->Init_Ctrl[15].val[1] = 1;
 955         state->Init_Ctrl[15].addr[2] = 147;
 956         state->Init_Ctrl[15].bit[2] = 4;
 957         state->Init_Ctrl[15].val[2] = 1;
 958
 959         state->Init_Ctrl[16].Ctrl_Num = I_DRIVER ;
 960         state->Init_Ctrl[16].size = 2 ;
 961         state->Init_Ctrl[16].addr[0] = 147;
 962         state->Init_Ctrl[16].bit[0] = 0;
 963         state->Init_Ctrl[16].val[0] = 0;
 964         state->Init_Ctrl[16].addr[1] = 147;
 965         state->Init_Ctrl[16].bit[1] = 1;
 966         state->Init_Ctrl[16].val[1] = 1;
 967
 968         state->Init_Ctrl[17].Ctrl_Num = EN_AAF ;
 969         state->Init_Ctrl[17].size = 1 ;
 970         state->Init_Ctrl[17].addr[0] = 147;
 971         state->Init_Ctrl[17].bit[0] = 7;
 972         state->Init_Ctrl[17].val[0] = 0;
 973
 974         state->Init_Ctrl[18].Ctrl_Num = EN_3P ;
 975         state->Init_Ctrl[18].size = 1 ;
 976         state->Init_Ctrl[18].addr[0] = 147;
 977         state->Init_Ctrl[18].bit[0] = 6;
 978         state->Init_Ctrl[18].val[0] = 0;
 979
 980         state->Init_Ctrl[19].Ctrl_Num = EN_AUX_3P ;
 981         state->Init_Ctrl[19].size = 1 ;
 982         state->Init_Ctrl[19].addr[0] = 156;
 983         state->Init_Ctrl[19].bit[0] = 0;
 984         state->Init_Ctrl[19].val[0] = 0;
 985
 986         state->Init_Ctrl[20].Ctrl_Num = SEL_AAF_BAND ;
 987         state->Init_Ctrl[20].size = 1 ;
 988         state->Init_Ctrl[20].addr[0] = 147;
 989         state->Init_Ctrl[20].bit[0] = 5;
 990         state->Init_Ctrl[20].val[0] = 0;
 991
 992         state->Init_Ctrl[21].Ctrl_Num = SEQ_ENCLK16_CLK_OUT ;
 993         state->Init_Ctrl[21].size = 1 ;
 994         state->Init_Ctrl[21].addr[0] = 137;
 995         state->Init_Ctrl[21].bit[0] = 4;
 996         state->Init_Ctrl[21].val[0] = 0;
 997
 998         state->Init_Ctrl[22].Ctrl_Num = SEQ_SEL4_16B ;
 999         state->Init_Ctrl[22].size = 1 ;
1000         state->Init_Ctrl[22].addr[0] = 137;
1001         state->Init_Ctrl[22].bit[0] = 7;
1002         state->Init_Ctrl[22].val[0] = 0;
1003
1004         state->Init_Ctrl[23].Ctrl_Num = XTAL_CAPSELECT ;
1005         state->Init_Ctrl[23].size = 1 ;
1006         state->Init_Ctrl[23].addr[0] = 91;
1007         state->Init_Ctrl[23].bit[0] = 5;
1008         state->Init_Ctrl[23].val[0] = 1;
1009
1010         state->Init_Ctrl[24].Ctrl_Num = IF_SEL_DBL ;
1011         state->Init_Ctrl[24].size = 1 ;
1012         state->Init_Ctrl[24].addr[0] = 43;
1013         state->Init_Ctrl[24].bit[0] = 0;
1014         state->Init_Ctrl[24].val[0] = 1;
1015
1016         state->Init_Ctrl[25].Ctrl_Num = RFSYN_R_DIV ;
1017         state->Init_Ctrl[25].size = 2 ;
1018         state->Init_Ctrl[25].addr[0] = 22;
1019         state->Init_Ctrl[25].bit[0] = 0;
1020         state->Init_Ctrl[25].val[0] = 1;
1021         state->Init_Ctrl[25].addr[1] = 22;
1022         state->Init_Ctrl[25].bit[1] = 1;
1023         state->Init_Ctrl[25].val[1] = 1;
1024
1025         state->Init_Ctrl[26].Ctrl_Num = SEQ_EXTSYNTHCALIF ;
1026         state->Init_Ctrl[26].size = 1 ;
1027         state->Init_Ctrl[26].addr[0] = 134;
1028         state->Init_Ctrl[26].bit[0] = 2;
1029         state->Init_Ctrl[26].val[0] = 0;
1030
1031         state->Init_Ctrl[27].Ctrl_Num = SEQ_EXTDCCAL ;
1032         state->Init_Ctrl[27].size = 1 ;
1033         state->Init_Ctrl[27].addr[0] = 137;
1034         state->Init_Ctrl[27].bit[0] = 3;
1035         state->Init_Ctrl[27].val[0] = 0;
1036
1037         state->Init_Ctrl[28].Ctrl_Num = AGC_EN_RSSI ;
1038         state->Init_Ctrl[28].size = 1 ;
1039         state->Init_Ctrl[28].addr[0] = 77;
1040         state->Init_Ctrl[28].bit[0] = 7;
1041         state->Init_Ctrl[28].val[0] = 0;
1042
1043         state->Init_Ctrl[29].Ctrl_Num = RFA_ENCLKRFAGC ;
1044         state->Init_Ctrl[29].size = 1 ;
1045         state->Init_Ctrl[29].addr[0] = 166;
1046         state->Init_Ctrl[29].bit[0] = 7;
1047         state->Init_Ctrl[29].val[0] = 1;
1048
1049         state->Init_Ctrl[30].Ctrl_Num = RFA_RSSI_REFH ;
1050         state->Init_Ctrl[30].size = 3 ;
1051         state->Init_Ctrl[30].addr[0] = 166;
1052         state->Init_Ctrl[30].bit[0] = 0;
1053         state->Init_Ctrl[30].val[0] = 0;
1054         state->Init_Ctrl[30].addr[1] = 166;
1055         state->Init_Ctrl[30].bit[1] = 1;
1056         state->Init_Ctrl[30].val[1] = 1;
1057         state->Init_Ctrl[30].addr[2] = 166;
1058         state->Init_Ctrl[30].bit[2] = 2;
1059         state->Init_Ctrl[30].val[2] = 1;
1060
1061         state->Init_Ctrl[31].Ctrl_Num = RFA_RSSI_REF ;
1062         state->Init_Ctrl[31].size = 3 ;
1063         state->Init_Ctrl[31].addr[0] = 166;
1064         state->Init_Ctrl[31].bit[0] = 3;
1065         state->Init_Ctrl[31].val[0] = 1;
1066         state->Init_Ctrl[31].addr[1] = 166;
1067         state->Init_Ctrl[31].bit[1] = 4;
1068         state->Init_Ctrl[31].val[1] = 0;
1069         state->Init_Ctrl[31].addr[2] = 166;
1070         state->Init_Ctrl[31].bit[2] = 5;
1071         state->Init_Ctrl[31].val[2] = 1;
1072
1073         state->Init_Ctrl[32].Ctrl_Num = RFA_RSSI_REFL ;
1074         state->Init_Ctrl[32].size = 3 ;
1075         state->Init_Ctrl[32].addr[0] = 167;
1076         state->Init_Ctrl[32].bit[0] = 0;
1077         state->Init_Ctrl[32].val[0] = 1;
1078         state->Init_Ctrl[32].addr[1] = 167;
1079         state->Init_Ctrl[32].bit[1] = 1;
1080         state->Init_Ctrl[32].val[1] = 1;
1081         state->Init_Ctrl[32].addr[2] = 167;
1082         state->Init_Ctrl[32].bit[2] = 2;
1083         state->Init_Ctrl[32].val[2] = 0;
1084
1085         state->Init_Ctrl[33].Ctrl_Num = RFA_FLR ;
1086         state->Init_Ctrl[33].size = 4 ;
1087         state->Init_Ctrl[33].addr[0] = 168;
1088         state->Init_Ctrl[33].bit[0] = 0;
1089         state->Init_Ctrl[33].val[0] = 0;
1090         state->Init_Ctrl[33].addr[1] = 168;
1091         state->Init_Ctrl[33].bit[1] = 1;
1092         state->Init_Ctrl[33].val[1] = 1;
1093         state->Init_Ctrl[33].addr[2] = 168;
1094         state->Init_Ctrl[33].bit[2] = 2;
1095         state->Init_Ctrl[33].val[2] = 0;
1096         state->Init_Ctrl[33].addr[3] = 168;
1097         state->Init_Ctrl[33].bit[3] = 3;
1098         state->Init_Ctrl[33].val[3] = 0;
1099
1100         state->Init_Ctrl[34].Ctrl_Num = RFA_CEIL ;
1101         state->Init_Ctrl[34].size = 4 ;
1102         state->Init_Ctrl[34].addr[0] = 168;
1103         state->Init_Ctrl[34].bit[0] = 4;
1104         state->Init_Ctrl[34].val[0] = 1;
1105         state->Init_Ctrl[34].addr[1] = 168;
1106         state->Init_Ctrl[34].bit[1] = 5;
1107         state->Init_Ctrl[34].val[1] = 1;
1108         state->Init_Ctrl[34].addr[2] = 168;
1109         state->Init_Ctrl[34].bit[2] = 6;
1110         state->Init_Ctrl[34].val[2] = 1;
1111         state->Init_Ctrl[34].addr[3] = 168;
1112         state->Init_Ctrl[34].bit[3] = 7;
1113         state->Init_Ctrl[34].val[3] = 1;
1114
1115         state->Init_Ctrl[35].Ctrl_Num = SEQ_EXTIQFSMPULSE ;
1116         state->Init_Ctrl[35].size = 1 ;
1117         state->Init_Ctrl[35].addr[0] = 135;
1118         state->Init_Ctrl[35].bit[0] = 0;
1119         state->Init_Ctrl[35].val[0] = 0;
1120
1121         state->Init_Ctrl[36].Ctrl_Num = OVERRIDE_1 ;
1122         state->Init_Ctrl[36].size = 1 ;
1123         state->Init_Ctrl[36].addr[0] = 56;
1124         state->Init_Ctrl[36].bit[0] = 3;
1125         state->Init_Ctrl[36].val[0] = 0;
1126
1127         state->Init_Ctrl[37].Ctrl_Num = BB_INITSTATE_DLPF_TUNE ;
1128         state->Init_Ctrl[37].size = 7 ;
1129         state->Init_Ctrl[37].addr[0] = 59;
1130         state->Init_Ctrl[37].bit[0] = 1;
1131         state->Init_Ctrl[37].val[0] = 0;
1132         state->Init_Ctrl[37].addr[1] = 59;
1133         state->Init_Ctrl[37].bit[1] = 2;
1134         state->Init_Ctrl[37].val[1] = 0;
1135         state->Init_Ctrl[37].addr[2] = 59;
1136         state->Init_Ctrl[37].bit[2] = 3;
1137         state->Init_Ctrl[37].val[2] = 0;
1138         state->Init_Ctrl[37].addr[3] = 59;
1139         state->Init_Ctrl[37].bit[3] = 4;
1140         state->Init_Ctrl[37].val[3] = 0;
1141         state->Init_Ctrl[37].addr[4] = 59;
1142         state->Init_Ctrl[37].bit[4] = 5;
1143         state->Init_Ctrl[37].val[4] = 0;
1144         state->Init_Ctrl[37].addr[5] = 59;
1145         state->Init_Ctrl[37].bit[5] = 6;
1146         state->Init_Ctrl[37].val[5] = 0;
1147         state->Init_Ctrl[37].addr[6] = 59;
1148         state->Init_Ctrl[37].bit[6] = 7;
1149         state->Init_Ctrl[37].val[6] = 0;
1150
1151         state->Init_Ctrl[38].Ctrl_Num = TG_R_DIV ;
1152         state->Init_Ctrl[38].size = 6 ;
1153         state->Init_Ctrl[38].addr[0] = 32;
1154         state->Init_Ctrl[38].bit[0] = 2;
1155         state->Init_Ctrl[38].val[0] = 0;
1156         state->Init_Ctrl[38].addr[1] = 32;
1157         state->Init_Ctrl[38].bit[1] = 3;
1158         state->Init_Ctrl[38].val[1] = 0;
1159         state->Init_Ctrl[38].addr[2] = 32;
1160         state->Init_Ctrl[38].bit[2] = 4;
1161         state->Init_Ctrl[38].val[2] = 0;
1162         state->Init_Ctrl[38].addr[3] = 32;
1163         state->Init_Ctrl[38].bit[3] = 5;
1164         state->Init_Ctrl[38].val[3] = 0;
1165         state->Init_Ctrl[38].addr[4] = 32;
1166         state->Init_Ctrl[38].bit[4] = 6;
1167         state->Init_Ctrl[38].val[4] = 1;
1168         state->Init_Ctrl[38].addr[5] = 32;
1169         state->Init_Ctrl[38].bit[5] = 7;
1170         state->Init_Ctrl[38].val[5] = 0;
1171
1172         state->Init_Ctrl[39].Ctrl_Num = EN_CHP_LIN_B ;
1173         state->Init_Ctrl[39].size = 1 ;
1174         state->Init_Ctrl[39].addr[0] = 25;
1175         state->Init_Ctrl[39].bit[0] = 3;
1176         state->Init_Ctrl[39].val[0] = 1;
1177
1178
1179         state->CH_Ctrl_Num = CHCTRL_NUM ;
1180
1181         state->CH_Ctrl[0].Ctrl_Num = DN_POLY ;
1182         state->CH_Ctrl[0].size = 2 ;
1183         state->CH_Ctrl[0].addr[0] = 68;
1184         state->CH_Ctrl[0].bit[0] = 6;
1185         state->CH_Ctrl[0].val[0] = 1;
1186         state->CH_Ctrl[0].addr[1] = 68;
1187         state->CH_Ctrl[0].bit[1] = 7;
1188         state->CH_Ctrl[0].val[1] = 1;
1189
1190         state->CH_Ctrl[1].Ctrl_Num = DN_RFGAIN ;
1191         state->CH_Ctrl[1].size = 2 ;
1192         state->CH_Ctrl[1].addr[0] = 70;
1193         state->CH_Ctrl[1].bit[0] = 6;
1194         state->CH_Ctrl[1].val[0] = 1;
1195         state->CH_Ctrl[1].addr[1] = 70;
1196         state->CH_Ctrl[1].bit[1] = 7;
1197         state->CH_Ctrl[1].val[1] = 0;
1198
1199         state->CH_Ctrl[2].Ctrl_Num = DN_CAP_RFLPF ;
1200         state->CH_Ctrl[2].size = 9 ;
1201         state->CH_Ctrl[2].addr[0] = 69;
1202         state->CH_Ctrl[2].bit[0] = 5;
1203         state->CH_Ctrl[2].val[0] = 0;
1204         state->CH_Ctrl[2].addr[1] = 69;
1205         state->CH_Ctrl[2].bit[1] = 6;
1206         state->CH_Ctrl[2].val[1] = 0;
1207         state->CH_Ctrl[2].addr[2] = 69;
1208         state->CH_Ctrl[2].bit[2] = 7;
1209         state->CH_Ctrl[2].val[2] = 0;
1210         state->CH_Ctrl[2].addr[3] = 68;
1211         state->CH_Ctrl[2].bit[3] = 0;
1212         state->CH_Ctrl[2].val[3] = 0;
1213         state->CH_Ctrl[2].addr[4] = 68;
1214         state->CH_Ctrl[2].bit[4] = 1;
1215         state->CH_Ctrl[2].val[4] = 0;
1216         state->CH_Ctrl[2].addr[5] = 68;
1217         state->CH_Ctrl[2].bit[5] = 2;
1218         state->CH_Ctrl[2].val[5] = 0;
1219         state->CH_Ctrl[2].addr[6] = 68;
1220         state->CH_Ctrl[2].bit[6] = 3;
1221         state->CH_Ctrl[2].val[6] = 0;
1222         state->CH_Ctrl[2].addr[7] = 68;
1223         state->CH_Ctrl[2].bit[7] = 4;
1224         state->CH_Ctrl[2].val[7] = 0;
1225         state->CH_Ctrl[2].addr[8] = 68;
1226         state->CH_Ctrl[2].bit[8] = 5;
1227         state->CH_Ctrl[2].val[8] = 0;
1228
1229         state->CH_Ctrl[3].Ctrl_Num = DN_EN_VHFUHFBAR ;
1230         state->CH_Ctrl[3].size = 1 ;
1231         state->CH_Ctrl[3].addr[0] = 70;
1232         state->CH_Ctrl[3].bit[0] = 5;
1233         state->CH_Ctrl[3].val[0] = 0;
1234
1235         state->CH_Ctrl[4].Ctrl_Num = DN_GAIN_ADJUST ;
1236         state->CH_Ctrl[4].size = 3 ;
1237         state->CH_Ctrl[4].addr[0] = 73;
1238         state->CH_Ctrl[4].bit[0] = 4;
1239         state->CH_Ctrl[4].val[0] = 0;
1240         state->CH_Ctrl[4].addr[1] = 73;
1241         state->CH_Ctrl[4].bit[1] = 5;
1242         state->CH_Ctrl[4].val[1] = 1;
1243         state->CH_Ctrl[4].addr[2] = 73;
1244         state->CH_Ctrl[4].bit[2] = 6;
1245         state->CH_Ctrl[4].val[2] = 0;
1246
1247         state->CH_Ctrl[5].Ctrl_Num = DN_IQTNBUF_AMP ;
1248         state->CH_Ctrl[5].size = 4 ;
1249         state->CH_Ctrl[5].addr[0] = 70;
1250         state->CH_Ctrl[5].bit[0] = 0;
1251         state->CH_Ctrl[5].val[0] = 0;
1252         state->CH_Ctrl[5].addr[1] = 70;
1253         state->CH_Ctrl[5].bit[1] = 1;
1254         state->CH_Ctrl[5].val[1] = 0;
1255         state->CH_Ctrl[5].addr[2] = 70;
1256         state->CH_Ctrl[5].bit[2] = 2;
1257         state->CH_Ctrl[5].val[2] = 0;
1258         state->CH_Ctrl[5].addr[3] = 70;
1259         state->CH_Ctrl[5].bit[3] = 3;
1260         state->CH_Ctrl[5].val[3] = 0;
1261
1262         state->CH_Ctrl[6].Ctrl_Num = DN_IQTNGNBFBIAS_BST ;
1263         state->CH_Ctrl[6].size = 1 ;
1264         state->CH_Ctrl[6].addr[0] = 70;
1265         state->CH_Ctrl[6].bit[0] = 4;
1266         state->CH_Ctrl[6].val[0] = 1;
1267
1268         state->CH_Ctrl[7].Ctrl_Num = RFSYN_EN_OUTMUX ;
1269         state->CH_Ctrl[7].size = 1 ;
1270         state->CH_Ctrl[7].addr[0] = 111;
1271         state->CH_Ctrl[7].bit[0] = 4;
1272         state->CH_Ctrl[7].val[0] = 0;
1273
1274         state->CH_Ctrl[8].Ctrl_Num = RFSYN_SEL_VCO_OUT ;
1275         state->CH_Ctrl[8].size = 1 ;
1276         state->CH_Ctrl[8].addr[0] = 111;
1277         state->CH_Ctrl[8].bit[0] = 7;
1278         state->CH_Ctrl[8].val[0] = 1;
1279
1280         state->CH_Ctrl[9].Ctrl_Num = RFSYN_SEL_VCO_HI ;
1281         state->CH_Ctrl[9].size = 1 ;
1282         state->CH_Ctrl[9].addr[0] = 111;
1283         state->CH_Ctrl[9].bit[0] = 6;
1284         state->CH_Ctrl[9].val[0] = 1;
1285
1286         state->CH_Ctrl[10].Ctrl_Num = RFSYN_SEL_DIVM ;
1287         state->CH_Ctrl[10].size = 1 ;
1288         state->CH_Ctrl[10].addr[0] = 111;
1289         state->CH_Ctrl[10].bit[0] = 5;
1290         state->CH_Ctrl[10].val[0] = 0;
1291
1292         state->CH_Ctrl[11].Ctrl_Num = RFSYN_RF_DIV_BIAS ;
1293         state->CH_Ctrl[11].size = 2 ;
1294         state->CH_Ctrl[11].addr[0] = 110;
1295         state->CH_Ctrl[11].bit[0] = 0;
1296         state->CH_Ctrl[11].val[0] = 1;
1297         state->CH_Ctrl[11].addr[1] = 110;
1298         state->CH_Ctrl[11].bit[1] = 1;
1299         state->CH_Ctrl[11].val[1] = 0;
1300
1301         state->CH_Ctrl[12].Ctrl_Num = DN_SEL_FREQ ;
1302         state->CH_Ctrl[12].size = 3 ;
1303         state->CH_Ctrl[12].addr[0] = 69;
1304         state->CH_Ctrl[12].bit[0] = 2;
1305         state->CH_Ctrl[12].val[0] = 0;
1306         state->CH_Ctrl[12].addr[1] = 69;
1307         state->CH_Ctrl[12].bit[1] = 3;
1308         state->CH_Ctrl[12].val[1] = 0;
1309         state->CH_Ctrl[12].addr[2] = 69;
1310         state->CH_Ctrl[12].bit[2] = 4;
1311         state->CH_Ctrl[12].val[2] = 0;
1312
1313         state->CH_Ctrl[13].Ctrl_Num = RFSYN_VCO_BIAS ;
1314         state->CH_Ctrl[13].size = 6 ;
1315         state->CH_Ctrl[13].addr[0] = 110;
1316         state->CH_Ctrl[13].bit[0] = 2;
1317         state->CH_Ctrl[13].val[0] = 0;
1318         state->CH_Ctrl[13].addr[1] = 110;
1319         state->CH_Ctrl[13].bit[1] = 3;
1320         state->CH_Ctrl[13].val[1] = 0;
1321         state->CH_Ctrl[13].addr[2] = 110;
1322         state->CH_Ctrl[13].bit[2] = 4;
1323         state->CH_Ctrl[13].val[2] = 0;
1324         state->CH_Ctrl[13].addr[3] = 110;
1325         state->CH_Ctrl[13].bit[3] = 5;
1326         state->CH_Ctrl[13].val[3] = 0;
1327         state->CH_Ctrl[13].addr[4] = 110;
1328         state->CH_Ctrl[13].bit[4] = 6;
1329         state->CH_Ctrl[13].val[4] = 0;
1330         state->CH_Ctrl[13].addr[5] = 110;
1331         state->CH_Ctrl[13].bit[5] = 7;
1332         state->CH_Ctrl[13].val[5] = 1;
1333
1334         state->CH_Ctrl[14].Ctrl_Num = CHCAL_INT_MOD_RF ;
1335         state->CH_Ctrl[14].size = 7 ;
1336         state->CH_Ctrl[14].addr[0] = 14;
1337         state->CH_Ctrl[14].bit[0] = 0;
1338         state->CH_Ctrl[14].val[0] = 0;
1339         state->CH_Ctrl[14].addr[1] = 14;
1340         state->CH_Ctrl[14].bit[1] = 1;
1341         state->CH_Ctrl[14].val[1] = 0;
1342         state->CH_Ctrl[14].addr[2] = 14;
1343         state->CH_Ctrl[14].bit[2] = 2;
1344         state->CH_Ctrl[14].val[2] = 0;
1345         state->CH_Ctrl[14].addr[3] = 14;
1346         state->CH_Ctrl[14].bit[3] = 3;
1347         state->CH_Ctrl[14].val[3] = 0;
1348         state->CH_Ctrl[14].addr[4] = 14;
1349         state->CH_Ctrl[14].bit[4] = 4;
1350         state->CH_Ctrl[14].val[4] = 0;
1351         state->CH_Ctrl[14].addr[5] = 14;
1352         state->CH_Ctrl[14].bit[5] = 5;
1353         state->CH_Ctrl[14].val[5] = 0;
1354         state->CH_Ctrl[14].addr[6] = 14;
1355         state->CH_Ctrl[14].bit[6] = 6;
1356         state->CH_Ctrl[14].val[6] = 0;
1357
1358         state->CH_Ctrl[15].Ctrl_Num = CHCAL_FRAC_MOD_RF ;
1359         state->CH_Ctrl[15].size = 18 ;
1360         state->CH_Ctrl[15].addr[0] = 17;
1361         state->CH_Ctrl[15].bit[0] = 6;
1362         state->CH_Ctrl[15].val[0] = 0;
1363         state->CH_Ctrl[15].addr[1] = 17;
1364         state->CH_Ctrl[15].bit[1] = 7;
1365         state->CH_Ctrl[15].val[1] = 0;
1366         state->CH_Ctrl[15].addr[2] = 16;
1367         state->CH_Ctrl[15].bit[2] = 0;
1368         state->CH_Ctrl[15].val[2] = 0;
1369         state->CH_Ctrl[15].addr[3] = 16;
1370         state->CH_Ctrl[15].bit[3] = 1;
1371         state->CH_Ctrl[15].val[3] = 0;
1372         state->CH_Ctrl[15].addr[4] = 16;
1373         state->CH_Ctrl[15].bit[4] = 2;
1374         state->CH_Ctrl[15].val[4] = 0;
1375         state->CH_Ctrl[15].addr[5] = 16;
1376         state->CH_Ctrl[15].bit[5] = 3;
1377         state->CH_Ctrl[15].val[5] = 0;
1378         state->CH_Ctrl[15].addr[6] = 16;
1379         state->CH_Ctrl[15].bit[6] = 4;
1380         state->CH_Ctrl[15].val[6] = 0;
1381         state->CH_Ctrl[15].addr[7] = 16;
1382         state->CH_Ctrl[15].bit[7] = 5;
1383         state->CH_Ctrl[15].val[7] = 0;
1384         state->CH_Ctrl[15].addr[8] = 16;
1385         state->CH_Ctrl[15].bit[8] = 6;
1386         state->CH_Ctrl[15].val[8] = 0;
1387         state->CH_Ctrl[15].addr[9] = 16;
1388         state->CH_Ctrl[15].bit[9] = 7;
1389         state->CH_Ctrl[15].val[9] = 0;
1390         state->CH_Ctrl[15].addr[10] = 15;
1391         state->CH_Ctrl[15].bit[10] = 0;
1392         state->CH_Ctrl[15].val[10] = 0;
1393         state->CH_Ctrl[15].addr[11] = 15;
1394         state->CH_Ctrl[15].bit[11] = 1;
1395         state->CH_Ctrl[15].val[11] = 0;
1396         state->CH_Ctrl[15].addr[12] = 15;
1397         state->CH_Ctrl[15].bit[12] = 2;
1398         state->CH_Ctrl[15].val[12] = 0;
1399         state->CH_Ctrl[15].addr[13] = 15;
1400         state->CH_Ctrl[15].bit[13] = 3;
1401         state->CH_Ctrl[15].val[13] = 0;
1402         state->CH_Ctrl[15].addr[14] = 15;
1403         state->CH_Ctrl[15].bit[14] = 4;
1404         state->CH_Ctrl[15].val[14] = 0;
1405         state->CH_Ctrl[15].addr[15] = 15;
1406         state->CH_Ctrl[15].bit[15] = 5;
1407         state->CH_Ctrl[15].val[15] = 0;
1408         state->CH_Ctrl[15].addr[16] = 15;
1409         state->CH_Ctrl[15].bit[16] = 6;
1410         state->CH_Ctrl[15].val[16] = 1;
1411         state->CH_Ctrl[15].addr[17] = 15;
1412         state->CH_Ctrl[15].bit[17] = 7;
1413         state->CH_Ctrl[15].val[17] = 1;
1414
1415         state->CH_Ctrl[16].Ctrl_Num = RFSYN_LPF_R ;
1416         state->CH_Ctrl[16].size = 5 ;
1417         state->CH_Ctrl[16].addr[0] = 112;
1418         state->CH_Ctrl[16].bit[0] = 0;
1419         state->CH_Ctrl[16].val[0] = 0;
1420         state->CH_Ctrl[16].addr[1] = 112;
1421         state->CH_Ctrl[16].bit[1] = 1;
1422         state->CH_Ctrl[16].val[1] = 0;
1423         state->CH_Ctrl[16].addr[2] = 112;
1424         state->CH_Ctrl[16].bit[2] = 2;
1425         state->CH_Ctrl[16].val[2] = 0;
1426         state->CH_Ctrl[16].addr[3] = 112;
1427         state->CH_Ctrl[16].bit[3] = 3;
1428         state->CH_Ctrl[16].val[3] = 0;
1429         state->CH_Ctrl[16].addr[4] = 112;
1430         state->CH_Ctrl[16].bit[4] = 4;
1431         state->CH_Ctrl[16].val[4] = 1;
1432
1433         state->CH_Ctrl[17].Ctrl_Num = CHCAL_EN_INT_RF ;
1434         state->CH_Ctrl[17].size = 1 ;
1435         state->CH_Ctrl[17].addr[0] = 14;
1436         state->CH_Ctrl[17].bit[0] = 7;
1437         state->CH_Ctrl[17].val[0] = 0;
1438
1439         state->CH_Ctrl[18].Ctrl_Num = TG_LO_DIVVAL ;
1440         state->CH_Ctrl[18].size = 4 ;
1441         state->CH_Ctrl[18].addr[0] = 107;
1442         state->CH_Ctrl[18].bit[0] = 3;
1443         state->CH_Ctrl[18].val[0] = 0;
1444         state->CH_Ctrl[18].addr[1] = 107;
1445         state->CH_Ctrl[18].bit[1] = 4;
1446         state->CH_Ctrl[18].val[1] = 0;
1447         state->CH_Ctrl[18].addr[2] = 107;
1448         state->CH_Ctrl[18].bit[2] = 5;
1449         state->CH_Ctrl[18].val[2] = 0;
1450         state->CH_Ctrl[18].addr[3] = 107;
1451         state->CH_Ctrl[18].bit[3] = 6;
1452         state->CH_Ctrl[18].val[3] = 0;
1453
1454         state->CH_Ctrl[19].Ctrl_Num = TG_LO_SELVAL ;
1455         state->CH_Ctrl[19].size = 3 ;
1456         state->CH_Ctrl[19].addr[0] = 107;
1457         state->CH_Ctrl[19].bit[0] = 7;
1458         state->CH_Ctrl[19].val[0] = 1;
1459         state->CH_Ctrl[19].addr[1] = 106;
1460         state->CH_Ctrl[19].bit[1] = 0;
1461         state->CH_Ctrl[19].val[1] = 1;
1462         state->CH_Ctrl[19].addr[2] = 106;
1463         state->CH_Ctrl[19].bit[2] = 1;
1464         state->CH_Ctrl[19].val[2] = 1;
1465
1466         state->CH_Ctrl[20].Ctrl_Num = TG_DIV_VAL ;
1467         state->CH_Ctrl[20].size = 11 ;
1468         state->CH_Ctrl[20].addr[0] = 109;
1469         state->CH_Ctrl[20].bit[0] = 2;
1470         state->CH_Ctrl[20].val[0] = 0;
1471         state->CH_Ctrl[20].addr[1] = 109;
1472         state->CH_Ctrl[20].bit[1] = 3;
1473         state->CH_Ctrl[20].val[1] = 0;
1474         state->CH_Ctrl[20].addr[2] = 109;
1475         state->CH_Ctrl[20].bit[2] = 4;
1476         state->CH_Ctrl[20].val[2] = 0;
1477         state->CH_Ctrl[20].addr[3] = 109;
1478         state->CH_Ctrl[20].bit[3] = 5;
1479         state->CH_Ctrl[20].val[3] = 0;
1480         state->CH_Ctrl[20].addr[4] = 109;
1481         state->CH_Ctrl[20].bit[4] = 6;
1482         state->CH_Ctrl[20].val[4] = 0;
1483         state->CH_Ctrl[20].addr[5] = 109;
1484         state->CH_Ctrl[20].bit[5] = 7;
1485         state->CH_Ctrl[20].val[5] = 0;
1486         state->CH_Ctrl[20].addr[6] = 108;
1487         state->CH_Ctrl[20].bit[6] = 0;
1488         state->CH_Ctrl[20].val[6] = 0;
1489         state->CH_Ctrl[20].addr[7] = 108;
1490         state->CH_Ctrl[20].bit[7] = 1;
1491         state->CH_Ctrl[20].val[7] = 0;
1492         state->CH_Ctrl[20].addr[8] = 108;
1493         state->CH_Ctrl[20].bit[8] = 2;
1494         state->CH_Ctrl[20].val[8] = 1;
1495         state->CH_Ctrl[20].addr[9] = 108;
1496         state->CH_Ctrl[20].bit[9] = 3;
1497         state->CH_Ctrl[20].val[9] = 1;
1498         state->CH_Ctrl[20].addr[10] = 108;
1499         state->CH_Ctrl[20].bit[10] = 4;
1500         state->CH_Ctrl[20].val[10] = 1;
1501
1502         state->CH_Ctrl[21].Ctrl_Num = TG_VCO_BIAS ;
1503         state->CH_Ctrl[21].size = 6 ;
1504         state->CH_Ctrl[21].addr[0] = 106;
1505         state->CH_Ctrl[21].bit[0] = 2;
1506         state->CH_Ctrl[21].val[0] = 0;
1507         state->CH_Ctrl[21].addr[1] = 106;
1508         state->CH_Ctrl[21].bit[1] = 3;
1509         state->CH_Ctrl[21].val[1] = 0;
1510         state->CH_Ctrl[21].addr[2] = 106;
1511         state->CH_Ctrl[21].bit[2] = 4;
1512         state->CH_Ctrl[21].val[2] = 0;
1513         state->CH_Ctrl[21].addr[3] = 106;
1514         state->CH_Ctrl[21].bit[3] = 5;
1515         state->CH_Ctrl[21].val[3] = 0;
1516         state->CH_Ctrl[21].addr[4] = 106;
1517         state->CH_Ctrl[21].bit[4] = 6;
1518         state->CH_Ctrl[21].val[4] = 0;
1519         state->CH_Ctrl[21].addr[5] = 106;
1520         state->CH_Ctrl[21].bit[5] = 7;
1521         state->CH_Ctrl[21].val[5] = 1;
1522
1523         state->CH_Ctrl[22].Ctrl_Num = SEQ_EXTPOWERUP ;
1524         state->CH_Ctrl[22].size = 1 ;
1525         state->CH_Ctrl[22].addr[0] = 138;
1526         state->CH_Ctrl[22].bit[0] = 4;
1527         state->CH_Ctrl[22].val[0] = 1;
1528
1529         state->CH_Ctrl[23].Ctrl_Num = OVERRIDE_2 ;
1530         state->CH_Ctrl[23].size = 1 ;
1531         state->CH_Ctrl[23].addr[0] = 17;
1532         state->CH_Ctrl[23].bit[0] = 5;
1533         state->CH_Ctrl[23].val[0] = 0;
1534
1535         state->CH_Ctrl[24].Ctrl_Num = OVERRIDE_3 ;
1536         state->CH_Ctrl[24].size = 1 ;
1537         state->CH_Ctrl[24].addr[0] = 111;
1538         state->CH_Ctrl[24].bit[0] = 3;
1539         state->CH_Ctrl[24].val[0] = 0;
1540
1541         state->CH_Ctrl[25].Ctrl_Num = OVERRIDE_4 ;
1542         state->CH_Ctrl[25].size = 1 ;
1543         state->CH_Ctrl[25].addr[0] = 112;
1544         state->CH_Ctrl[25].bit[0] = 7;
1545         state->CH_Ctrl[25].val[0] = 0;
1546
1547         state->CH_Ctrl[26].Ctrl_Num = SEQ_FSM_PULSE ;
1548         state->CH_Ctrl[26].size = 1 ;
1549         state->CH_Ctrl[26].addr[0] = 136;
1550         state->CH_Ctrl[26].bit[0] = 7;
1551         state->CH_Ctrl[26].val[0] = 0;
1552
1553         state->CH_Ctrl[27].Ctrl_Num = GPIO_4B ;
1554         state->CH_Ctrl[27].size = 1 ;
1555         state->CH_Ctrl[27].addr[0] = 149;
1556         state->CH_Ctrl[27].bit[0] = 7;
1557         state->CH_Ctrl[27].val[0] = 0;
1558
1559         state->CH_Ctrl[28].Ctrl_Num = GPIO_3B ;
1560         state->CH_Ctrl[28].size = 1 ;
1561         state->CH_Ctrl[28].addr[0] = 149;
1562         state->CH_Ctrl[28].bit[0] = 6;
1563         state->CH_Ctrl[28].val[0] = 0;
1564
1565         state->CH_Ctrl[29].Ctrl_Num = GPIO_4 ;
1566         state->CH_Ctrl[29].size = 1 ;
1567         state->CH_Ctrl[29].addr[0] = 149;
1568         state->CH_Ctrl[29].bit[0] = 5;
1569         state->CH_Ctrl[29].val[0] = 1;
1570
1571         state->CH_Ctrl[30].Ctrl_Num = GPIO_3 ;
1572         state->CH_Ctrl[30].size = 1 ;
1573         state->CH_Ctrl[30].addr[0] = 149;
1574         state->CH_Ctrl[30].bit[0] = 4;
1575         state->CH_Ctrl[30].val[0] = 1;
1576
1577         state->CH_Ctrl[31].Ctrl_Num = GPIO_1B ;
1578         state->CH_Ctrl[31].size = 1 ;
1579         state->CH_Ctrl[31].addr[0] = 149;
1580         state->CH_Ctrl[31].bit[0] = 3;
1581         state->CH_Ctrl[31].val[0] = 0;
1582
1583         state->CH_Ctrl[32].Ctrl_Num = DAC_A_ENABLE ;
1584         state->CH_Ctrl[32].size = 1 ;
1585         state->CH_Ctrl[32].addr[0] = 93;
1586         state->CH_Ctrl[32].bit[0] = 1;
1587         state->CH_Ctrl[32].val[0] = 0;
1588
1589         state->CH_Ctrl[33].Ctrl_Num = DAC_B_ENABLE ;
1590         state->CH_Ctrl[33].size = 1 ;
1591         state->CH_Ctrl[33].addr[0] = 93;
1592         state->CH_Ctrl[33].bit[0] = 0;
1593         state->CH_Ctrl[33].val[0] = 0;
1594
1595         state->CH_Ctrl[34].Ctrl_Num = DAC_DIN_A ;
1596         state->CH_Ctrl[34].size = 6 ;
1597         state->CH_Ctrl[34].addr[0] = 92;
1598         state->CH_Ctrl[34].bit[0] = 2;
1599         state->CH_Ctrl[34].val[0] = 0;
1600         state->CH_Ctrl[34].addr[1] = 92;
1601         state->CH_Ctrl[34].bit[1] = 3;
1602         state->CH_Ctrl[34].val[1] = 0;
1603         state->CH_Ctrl[34].addr[2] = 92;
1604         state->CH_Ctrl[34].bit[2] = 4;
1605         state->CH_Ctrl[34].val[2] = 0;
1606         state->CH_Ctrl[34].addr[3] = 92;
1607         state->CH_Ctrl[34].bit[3] = 5;
1608         state->CH_Ctrl[34].val[3] = 0;
1609         state->CH_Ctrl[34].addr[4] = 92;
1610         state->CH_Ctrl[34].bit[4] = 6;
1611         state->CH_Ctrl[34].val[4] = 0;
1612         state->CH_Ctrl[34].addr[5] = 92;
1613         state->CH_Ctrl[34].bit[5] = 7;
1614         state->CH_Ctrl[34].val[5] = 0;
1615
1616         state->CH_Ctrl[35].Ctrl_Num = DAC_DIN_B ;
1617         state->CH_Ctrl[35].size = 6 ;
1618         state->CH_Ctrl[35].addr[0] = 93;
1619         state->CH_Ctrl[35].bit[0] = 2;
1620         state->CH_Ctrl[35].val[0] = 0;
1621         state->CH_Ctrl[35].addr[1] = 93;
1622         state->CH_Ctrl[35].bit[1] = 3;
1623         state->CH_Ctrl[35].val[1] = 0;
1624         state->CH_Ctrl[35].addr[2] = 93;
1625         state->CH_Ctrl[35].bit[2] = 4;
1626         state->CH_Ctrl[35].val[2] = 0;
1627         state->CH_Ctrl[35].addr[3] = 93;
1628         state->CH_Ctrl[35].bit[3] = 5;
1629         state->CH_Ctrl[35].val[3] = 0;
1630         state->CH_Ctrl[35].addr[4] = 93;
1631         state->CH_Ctrl[35].bit[4] = 6;
1632         state->CH_Ctrl[35].val[4] = 0;
1633         state->CH_Ctrl[35].addr[5] = 93;
1634         state->CH_Ctrl[35].bit[5] = 7;
1635         state->CH_Ctrl[35].val[5] = 0;
1636
1637 #ifdef _MXL_PRODUCTION
1638         state->CH_Ctrl[36].Ctrl_Num = RFSYN_EN_DIV ;
1639         state->CH_Ctrl[36].size = 1 ;
1640         state->CH_Ctrl[36].addr[0] = 109;
1641         state->CH_Ctrl[36].bit[0] = 1;
1642         state->CH_Ctrl[36].val[0] = 1;
1643
1644         state->CH_Ctrl[37].Ctrl_Num = RFSYN_DIVM ;
1645         state->CH_Ctrl[37].size = 2 ;
1646         state->CH_Ctrl[37].addr[0] = 112;
1647         state->CH_Ctrl[37].bit[0] = 5;
1648         state->CH_Ctrl[37].val[0] = 0;
1649         state->CH_Ctrl[37].addr[1] = 112;
1650         state->CH_Ctrl[37].bit[1] = 6;
1651         state->CH_Ctrl[37].val[1] = 0;
1652
1653         state->CH_Ctrl[38].Ctrl_Num = DN_BYPASS_AGC_I2C ;
1654         state->CH_Ctrl[38].size = 1 ;
1655         state->CH_Ctrl[38].addr[0] = 65;
1656         state->CH_Ctrl[38].bit[0] = 1;
1657         state->CH_Ctrl[38].val[0] = 0;
1658 #endif
1659
1660         return 0 ;
1661 }
1662
1663 static void InitTunerControls(struct dvb_frontend *fe)
1664 {
1665         MXL5005_RegisterInit(fe);
1666         MXL5005_ControlInit(fe);
1667 #ifdef _MXL_INTERNAL
1668         MXL5005_MXLControlInit(fe);
1669 #endif
1670 }
1671
1672 static u16 MXL5005_TunerConfig(struct dvb_frontend *fe,
1673         u8      Mode,           /* 0: Analog Mode ; 1: Digital Mode */
1674         u8      IF_mode,        /* for Analog Mode, 0: zero IF; 1: low IF */
1675         u32     Bandwidth,      /* filter  channel bandwidth (6, 7, 8) */
1676         u32     IF_out,         /* Desired IF Out Frequency */
1677         u32     Fxtal,          /* XTAL Frequency */
1678         u8      AGC_Mode,       /* AGC Mode - Dual AGC: 0, Single AGC: 1 */
1679         u16     TOP,            /* 0: Dual AGC; Value: take over point */
1680         u16     IF_OUT_LOAD,    /* IF Out Load Resistor (200 / 300 Ohms) */
1681         u8      CLOCK_OUT,      /* 0: turn off clk out; 1: turn on clock out */
1682         u8      DIV_OUT,        /* 0: Div-1; 1: Div-4 */
1683         u8      CAPSELECT,      /* 0: disable On-Chip pulling cap; 1: enable */
1684         u8      EN_RSSI,        /* 0: disable RSSI; 1: enable RSSI */
1685
1686         /* Modulation Type; */
1687         /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */
1688         u8      Mod_Type,
1689
1690         /* Tracking Filter */
1691         /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */
1692         u8      TF_Type
1693         )
1694 {
1695         struct mxl5005s_state *state = fe->tuner_priv;
1696         u16 status = 0;
1697
1698         state->Mode = Mode;
1699         state->IF_Mode = IF_mode;
1700         state->Chan_Bandwidth = Bandwidth;
1701         state->IF_OUT = IF_out;
1702         state->Fxtal = Fxtal;
1703         state->AGC_Mode = AGC_Mode;
1704         state->TOP = TOP;
1705         state->IF_OUT_LOAD = IF_OUT_LOAD;
1706         state->CLOCK_OUT = CLOCK_OUT;
1707         state->DIV_OUT = DIV_OUT;
1708         state->CAPSELECT = CAPSELECT;
1709         state->EN_RSSI = EN_RSSI;
1710         state->Mod_Type = Mod_Type;
1711         state->TF_Type = TF_Type;
1712
1713         /* Initialize all the controls and registers */
1714         InitTunerControls(fe);
1715
1716         /* Synthesizer LO frequency calculation */
1717         MXL_SynthIFLO_Calc(fe);
1718
1719         return status;
1720 }
1721
1722 static void MXL_SynthIFLO_Calc(struct dvb_frontend *fe)
1723 {
1724         struct mxl5005s_state *state = fe->tuner_priv;
1725         if (state->Mode == 1) /* Digital Mode */
1726                 state->IF_LO = state->IF_OUT;
1727         else /* Analog Mode */ {
1728                 if (state->IF_Mode == 0) /* Analog Zero IF mode */
1729                         state->IF_LO = state->IF_OUT + 400000;
1730                 else /* Analog Low IF mode */
1731                         state->IF_LO = state->IF_OUT + state->Chan_Bandwidth/2;
1732         }
1733 }
1734
1735 static void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe)
1736 {
1737         struct mxl5005s_state *state = fe->tuner_priv;
1738
1739         if (state->Mode == 1) /* Digital Mode */ {
1740                         /* remove 20.48MHz setting for 2.6.10 */
1741                         state->RF_LO = state->RF_IN;
1742                         /* change for 2.6.6 */
1743                         state->TG_LO = state->RF_IN - 750000;
1744         } else /* Analog Mode */ {
1745                 if (state->IF_Mode == 0) /* Analog Zero IF mode */ {
1746                         state->RF_LO = state->RF_IN - 400000;
1747                         state->TG_LO = state->RF_IN - 1750000;
1748                 } else /* Analog Low IF mode */ {
1749                         state->RF_LO = state->RF_IN - state->Chan_Bandwidth/2;
1750                         state->TG_LO = state->RF_IN -
1751                                 state->Chan_Bandwidth + 500000;
1752                 }
1753         }
1754 }
1755
1756 static u16 MXL_OverwriteICDefault(struct dvb_frontend *fe)
1757 {
1758         u16 status = 0;
1759
1760         status += MXL_ControlWrite(fe, OVERRIDE_1, 1);
1761         status += MXL_ControlWrite(fe, OVERRIDE_2, 1);
1762         status += MXL_ControlWrite(fe, OVERRIDE_3, 1);
1763         status += MXL_ControlWrite(fe, OVERRIDE_4, 1);
1764
1765         return status;
1766 }
1767
1768 static u16 MXL_BlockInit(struct dvb_frontend *fe)
1769 {
1770         struct mxl5005s_state *state = fe->tuner_priv;
1771         u16 status = 0;
1772
1773         status += MXL_OverwriteICDefault(fe);
1774
1775         /* Downconverter Control Dig Ana */
1776         status += MXL_ControlWrite(fe, DN_IQTN_AMP_CUT, state->Mode ? 1 : 0);
1777
1778         /* Filter Control  Dig  Ana */
1779         status += MXL_ControlWrite(fe, BB_MODE, state->Mode ? 0 : 1);
1780         status += MXL_ControlWrite(fe, BB_BUF, state->Mode ? 3 : 2);
1781         status += MXL_ControlWrite(fe, BB_BUF_OA, state->Mode ? 1 : 0);
1782         status += MXL_ControlWrite(fe, BB_IQSWAP, state->Mode ? 0 : 1);
1783         status += MXL_ControlWrite(fe, BB_INITSTATE_DLPF_TUNE, 0);
1784
1785         /* Initialize Low-Pass Filter */
1786         if (state->Mode) { /* Digital Mode */
1787                 switch (state->Chan_Bandwidth) {
1788                 case 8000000:
1789                         status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 0);
1790                         break;
1791                 case 7000000:
1792                         status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 2);
1793                         break;
1794                 case 6000000:
1795                         status += MXL_ControlWrite(fe,
1796                                         BB_DLPF_BANDSEL, 3);
1797                         break;
1798                 }
1799         } else { /* Analog Mode */
1800                 switch (state->Chan_Bandwidth) {
1801                 case 8000000:   /* Low Zero */
1802                         status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT,
1803                                         (state->IF_Mode ? 0 : 3));
1804                         break;
1805                 case 7000000:
1806                         status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT,
1807                                         (state->IF_Mode ? 1 : 4));
1808                         break;
1809                 case 6000000:
1810                         status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT,
1811                                         (state->IF_Mode ? 2 : 5));
1812                         break;
1813                 }
1814         }
1815
1816         /* Charge Pump Control Dig  Ana */
1817         status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, state->Mode ? 5 : 8);
1818         status += MXL_ControlWrite(fe,
1819                 RFSYN_EN_CHP_HIGAIN, state->Mode ? 1 : 1);
1820         status += MXL_ControlWrite(fe, EN_CHP_LIN_B, state->Mode ? 0 : 0);
1821
1822         /* AGC TOP Control */
1823         if (state->AGC_Mode == 0) /* Dual AGC */ {
1824                 status += MXL_ControlWrite(fe, AGC_IF, 15);
1825                 status += MXL_ControlWrite(fe, AGC_RF, 15);
1826         } else /*  Single AGC Mode Dig  Ana */
1827                 status += MXL_ControlWrite(fe, AGC_RF, state->Mode ? 15 : 12);
1828
1829         if (state->TOP == 55) /* TOP == 5.5 */
1830                 status += MXL_ControlWrite(fe, AGC_IF, 0x0);
1831
1832         if (state->TOP == 72) /* TOP == 7.2 */
1833                 status += MXL_ControlWrite(fe, AGC_IF, 0x1);
1834
1835         if (state->TOP == 92) /* TOP == 9.2 */
1836                 status += MXL_ControlWrite(fe, AGC_IF, 0x2);
1837
1838         if (state->TOP == 110) /* TOP == 11.0 */
1839                 status += MXL_ControlWrite(fe, AGC_IF, 0x3);
1840
1841         if (state->TOP == 129) /* TOP == 12.9 */
1842                 status += MXL_ControlWrite(fe, AGC_IF, 0x4);
1843
1844         if (state->TOP == 147) /* TOP == 14.7 */
1845                 status += MXL_ControlWrite(fe, AGC_IF, 0x5);
1846
1847         if (state->TOP == 168) /* TOP == 16.8 */
1848                 status += MXL_ControlWrite(fe, AGC_IF, 0x6);
1849
1850         if (state->TOP == 194) /* TOP == 19.4 */
1851                 status += MXL_ControlWrite(fe, AGC_IF, 0x7);
1852
1853         if (state->TOP == 212) /* TOP == 21.2 */
1854                 status += MXL_ControlWrite(fe, AGC_IF, 0x9);
1855
1856         if (state->TOP == 232) /* TOP == 23.2 */
1857                 status += MXL_ControlWrite(fe, AGC_IF, 0xA);
1858
1859         if (state->TOP == 252) /* TOP == 25.2 */
1860                 status += MXL_ControlWrite(fe, AGC_IF, 0xB);
1861
1862         if (state->TOP == 271) /* TOP == 27.1 */
1863                 status += MXL_ControlWrite(fe, AGC_IF, 0xC);
1864
1865         if (state->TOP == 292) /* TOP == 29.2 */
1866                 status += MXL_ControlWrite(fe, AGC_IF, 0xD);
1867
1868         if (state->TOP == 317) /* TOP == 31.7 */
1869                 status += MXL_ControlWrite(fe, AGC_IF, 0xE);
1870
1871         if (state->TOP == 349) /* TOP == 34.9 */
1872                 status += MXL_ControlWrite(fe, AGC_IF, 0xF);
1873
1874         /* IF Synthesizer Control */
1875         status += MXL_IFSynthInit(fe);
1876
1877         /* IF UpConverter Control */
1878         if (state->IF_OUT_LOAD == 200) {
1879                 status += MXL_ControlWrite(fe, DRV_RES_SEL, 6);
1880                 status += MXL_ControlWrite(fe, I_DRIVER, 2);
1881         }
1882         if (state->IF_OUT_LOAD == 300) {
1883                 status += MXL_ControlWrite(fe, DRV_RES_SEL, 4);
1884                 status += MXL_ControlWrite(fe, I_DRIVER, 1);
1885         }
1886
1887         /* Anti-Alias Filtering Control
1888          * initialise Anti-Aliasing Filter
1889          */
1890         if (state->Mode) { /* Digital Mode */
1891                 if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 6280000UL) {
1892                         status += MXL_ControlWrite(fe, EN_AAF, 1);
1893                         status += MXL_ControlWrite(fe, EN_3P, 1);
1894                         status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
1895                         status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0);
1896                 }
1897                 if ((state->IF_OUT == 36125000UL) ||
1898                         (state->IF_OUT == 36150000UL)) {
1899                         status += MXL_ControlWrite(fe, EN_AAF, 1);
1900                         status += MXL_ControlWrite(fe, EN_3P, 1);
1901                         status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
1902                         status += MXL_ControlWrite(fe, SEL_AAF_BAND, 1);
1903                 }
1904                 if (state->IF_OUT > 36150000UL) {
1905                         status += MXL_ControlWrite(fe, EN_AAF, 0);
1906                         status += MXL_ControlWrite(fe, EN_3P, 1);
1907                         status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
1908                         status += MXL_ControlWrite(fe, SEL_AAF_BAND, 1);
1909                 }
1910         } else { /* Analog Mode */
1911                 if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 5000000UL) {
1912                         status += MXL_ControlWrite(fe, EN_AAF, 1);
1913                         status += MXL_ControlWrite(fe, EN_3P, 1);
1914                         status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
1915                         status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0);
1916                 }
1917                 if (state->IF_OUT > 5000000UL) {
1918                         status += MXL_ControlWrite(fe, EN_AAF, 0);
1919                         status += MXL_ControlWrite(fe, EN_3P, 0);
1920                         status += MXL_ControlWrite(fe, EN_AUX_3P, 0);
1921                         status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0);
1922                 }
1923         }
1924
1925         /* Demod Clock Out */
1926         if (state->CLOCK_OUT)
1927                 status += MXL_ControlWrite(fe, SEQ_ENCLK16_CLK_OUT, 1);
1928         else
1929                 status += MXL_ControlWrite(fe, SEQ_ENCLK16_CLK_OUT, 0);
1930
1931         if (state->DIV_OUT == 1)
1932                 status += MXL_ControlWrite(fe, SEQ_SEL4_16B, 1);
1933         if (state->DIV_OUT == 0)
1934                 status += MXL_ControlWrite(fe, SEQ_SEL4_16B, 0);
1935
1936         /* Crystal Control */
1937         if (state->CAPSELECT)
1938                 status += MXL_ControlWrite(fe, XTAL_CAPSELECT, 1);
1939         else
1940                 status += MXL_ControlWrite(fe, XTAL_CAPSELECT, 0);
1941
1942         if (state->Fxtal >= 12000000UL && state->Fxtal <= 16000000UL)
1943                 status += MXL_ControlWrite(fe, IF_SEL_DBL, 1);
1944         if (state->Fxtal > 16000000UL && state->Fxtal <= 32000000UL)
1945                 status += MXL_ControlWrite(fe, IF_SEL_DBL, 0);
1946
1947         if (state->Fxtal >= 12000000UL && state->Fxtal <= 22000000UL)
1948                 status += MXL_ControlWrite(fe, RFSYN_R_DIV, 3);
1949         if (state->Fxtal > 22000000UL && state->Fxtal <= 32000000UL)
1950                 status += MXL_ControlWrite(fe, RFSYN_R_DIV, 0);
1951
1952         /* Misc Controls */
1953         if (state->Mode == 0 && state->IF_Mode == 1) /* Analog LowIF mode */
1954                 status += MXL_ControlWrite(fe, SEQ_EXTIQFSMPULSE, 0);
1955         else
1956                 status += MXL_ControlWrite(fe, SEQ_EXTIQFSMPULSE, 1);
1957
1958         /* status += MXL_ControlRead(fe, IF_DIVVAL, &IF_DIVVAL_Val); */
1959
1960         /* Set TG_R_DIV */
1961         status += MXL_ControlWrite(fe, TG_R_DIV,
1962                 MXL_Ceiling(state->Fxtal, 1000000));
1963
1964         /* Apply Default value to BB_INITSTATE_DLPF_TUNE */
1965
1966         /* RSSI Control */
1967         if (state->EN_RSSI) {
1968                 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
1969                 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
1970                 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
1971                 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
1972
1973                 /* RSSI reference point */
1974                 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 2);
1975                 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 3);
1976                 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1);
1977
1978                 /* TOP point */
1979                 status += MXL_ControlWrite(fe, RFA_FLR, 0);
1980                 status += MXL_ControlWrite(fe, RFA_CEIL, 12);
1981         }
1982
1983         /* Modulation type bit settings
1984          * Override the control values preset
1985          */
1986         if (state->Mod_Type == MXL_DVBT) /* DVB-T Mode */ {
1987                 state->AGC_Mode = 1; /* Single AGC Mode */
1988
1989                 /* Enable RSSI */
1990                 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
1991                 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
1992                 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
1993                 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
1994
1995                 /* RSSI reference point */
1996                 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3);
1997                 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5);
1998                 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1);
1999
2000                 /* TOP point */
2001                 status += MXL_ControlWrite(fe, RFA_FLR, 2);
2002                 status += MXL_ControlWrite(fe, RFA_CEIL, 13);
2003                 if (state->IF_OUT <= 6280000UL) /* Low IF */
2004                         status += MXL_ControlWrite(fe, BB_IQSWAP, 0);
2005                 else /* High IF */
2006                         status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
2007
2008         }
2009         if (state->Mod_Type == MXL_ATSC) /* ATSC Mode */ {
2010                 state->AGC_Mode = 1;    /* Single AGC Mode */
2011
2012                 /* Enable RSSI */
2013                 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2014                 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2015                 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
2016                 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2017
2018                 /* RSSI reference point */
2019                 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 2);
2020                 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 4);
2021                 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1);
2022
2023                 /* TOP point */
2024                 status += MXL_ControlWrite(fe, RFA_FLR, 2);
2025                 status += MXL_ControlWrite(fe, RFA_CEIL, 13);
2026                 status += MXL_ControlWrite(fe, BB_INITSTATE_DLPF_TUNE, 1);
2027                 /* Low Zero */
2028                 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5);
2029
2030                 if (state->IF_OUT <= 6280000UL) /* Low IF */
2031                         status += MXL_ControlWrite(fe, BB_IQSWAP, 0);
2032                 else /* High IF */
2033                         status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
2034         }
2035         if (state->Mod_Type == MXL_QAM) /* QAM Mode */ {
2036                 state->Mode = MXL_DIGITAL_MODE;
2037
2038                 /* state->AGC_Mode = 1; */ /* Single AGC Mode */
2039
2040                 /* Disable RSSI */      /* change here for v2.6.5 */
2041                 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2042                 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2043                 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
2044                 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2045
2046                 /* RSSI reference point */
2047                 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5);
2048                 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3);
2049                 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2);
2050                 /* change here for v2.6.5 */
2051                 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3);
2052
2053                 if (state->IF_OUT <= 6280000UL) /* Low IF */
2054                         status += MXL_ControlWrite(fe, BB_IQSWAP, 0);
2055                 else /* High IF */
2056                         status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
2057                 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2);
2058
2059         }
2060         if (state->Mod_Type == MXL_ANALOG_CABLE) {
2061                 /* Analog Cable Mode */
2062                 /* state->Mode = MXL_DIGITAL_MODE; */
2063
2064                 state->AGC_Mode = 1; /* Single AGC Mode */
2065
2066                 /* Disable RSSI */
2067                 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2068                 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2069                 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
2070                 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2071                 /* change for 2.6.3 */
2072                 status += MXL_ControlWrite(fe, AGC_IF, 1);
2073                 status += MXL_ControlWrite(fe, AGC_RF, 15);
2074                 status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
2075         }
2076
2077         if (state->Mod_Type == MXL_ANALOG_OTA) {
2078                 /* Analog OTA Terrestrial mode add for 2.6.7 */
2079                 /* state->Mode = MXL_ANALOG_MODE; */
2080
2081                 /* Enable RSSI */
2082                 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2083                 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2084                 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
2085                 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2086
2087                 /* RSSI reference point */
2088                 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5);
2089                 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3);
2090                 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2);
2091                 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3);
2092                 status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
2093         }
2094
2095         /* RSSI disable */
2096         if (state->EN_RSSI == 0) {
2097                 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2098                 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2099                 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
2100                 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2101         }
2102
2103         return status;
2104 }
2105
2106 static u16 MXL_IFSynthInit(struct dvb_frontend *fe)
2107 {
2108         struct mxl5005s_state *state = fe->tuner_priv;
2109         u16 status = 0 ;
2110         u32     Fref = 0 ;
2111         u32     Kdbl, intModVal ;
2112         u32     fracModVal ;
2113         Kdbl = 2 ;
2114
2115         if (state->Fxtal >= 12000000UL && state->Fxtal <= 16000000UL)
2116                 Kdbl = 2 ;
2117         if (state->Fxtal > 16000000UL && state->Fxtal <= 32000000UL)
2118                 Kdbl = 1 ;
2119
2120         /* IF Synthesizer Control */
2121         if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF mode */ {
2122                 if (state->IF_LO == 41000000UL) {
2123                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08);
2124                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2125                         Fref = 328000000UL ;
2126                 }
2127                 if (state->IF_LO == 47000000UL) {
2128                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08);
2129                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2130                         Fref = 376000000UL ;
2131                 }
2132                 if (state->IF_LO == 54000000UL) {
2133                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x10);
2134                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2135                         Fref = 324000000UL ;
2136                 }
2137                 if (state->IF_LO == 60000000UL) {
2138                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x10);
2139                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2140                         Fref = 360000000UL ;
2141                 }
2142                 if (state->IF_LO == 39250000UL) {
2143                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08);
2144                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2145                         Fref = 314000000UL ;
2146                 }
2147                 if (state->IF_LO == 39650000UL) {
2148                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08);
2149                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2150                         Fref = 317200000UL ;
2151                 }
2152                 if (state->IF_LO == 40150000UL) {
2153                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08);
2154                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2155                         Fref = 321200000UL ;
2156                 }
2157                 if (state->IF_LO == 40650000UL) {
2158                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08);
2159                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2160                         Fref = 325200000UL ;
2161                 }
2162         }
2163
2164         if (state->Mode || (state->Mode == 0 && state->IF_Mode == 0)) {
2165                 if (state->IF_LO == 57000000UL) {
2166                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x10);
2167                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2168                         Fref = 342000000UL ;
2169                 }
2170                 if (state->IF_LO == 44000000UL) {
2171                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08);
2172                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2173                         Fref = 352000000UL ;
2174                 }
2175                 if (state->IF_LO == 43750000UL) {
2176                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08);
2177                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2178                         Fref = 350000000UL ;
2179                 }
2180                 if (state->IF_LO == 36650000UL) {
2181                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x04);
2182                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2183                         Fref = 366500000UL ;
2184                 }
2185                 if (state->IF_LO == 36150000UL) {
2186                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x04);
2187                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2188                         Fref = 361500000UL ;
2189                 }
2190                 if (state->IF_LO == 36000000UL) {
2191                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x04);
2192                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2193                         Fref = 360000000UL ;
2194                 }
2195                 if (state->IF_LO == 35250000UL) {
2196                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x04);
2197                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2198                         Fref = 352500000UL ;
2199                 }
2200                 if (state->IF_LO == 34750000UL) {
2201                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x04);
2202                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2203                         Fref = 347500000UL ;
2204                 }
2205                 if (state->IF_LO == 6280000UL) {
2206                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x07);
2207                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2208                         Fref = 376800000UL ;
2209                 }
2210                 if (state->IF_LO == 5000000UL) {
2211                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x09);
2212                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2213                         Fref = 360000000UL ;
2214                 }
2215                 if (state->IF_LO == 4500000UL) {
2216                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x06);
2217                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2218                         Fref = 360000000UL ;
2219                 }
2220                 if (state->IF_LO == 4570000UL) {
2221                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x06);
2222                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2223                         Fref = 365600000UL ;
2224                 }
2225                 if (state->IF_LO == 4000000UL) {
2226                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x05);
2227                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2228                         Fref = 360000000UL ;
2229                 }
2230                 if (state->IF_LO == 57400000UL) {
2231                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x10);
2232                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2233                         Fref = 344400000UL ;
2234                 }
2235                 if (state->IF_LO == 44400000UL) {
2236                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08);
2237                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2238                         Fref = 355200000UL ;
2239                 }
2240                 if (state->IF_LO == 44150000UL) {
2241                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08);
2242                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2243                         Fref = 353200000UL ;
2244                 }
2245                 if (state->IF_LO == 37050000UL) {
2246                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x04);
2247                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2248                         Fref = 370500000UL ;
2249                 }
2250                 if (state->IF_LO == 36550000UL) {
2251                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x04);
2252                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2253                         Fref = 365500000UL ;
2254                 }
2255                 if (state->IF_LO == 36125000UL) {
2256                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x04);
2257                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2258                         Fref = 361250000UL ;
2259                 }
2260                 if (state->IF_LO == 6000000UL) {
2261                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x07);
2262                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2263                         Fref = 360000000UL ;
2264                 }
2265                 if (state->IF_LO == 5400000UL) {
2266                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x07);
2267                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2268                         Fref = 324000000UL ;
2269                 }
2270                 if (state->IF_LO == 5380000UL) {
2271                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x07);
2272                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2273                         Fref = 322800000UL ;
2274                 }
2275                 if (state->IF_LO == 5200000UL) {
2276                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x09);
2277                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2278                         Fref = 374400000UL ;
2279                 }
2280                 if (state->IF_LO == 4900000UL) {
2281                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x09);
2282                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2283                         Fref = 352800000UL ;
2284                 }
2285                 if (state->IF_LO == 4400000UL) {
2286                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x06);
2287                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2288                         Fref = 352000000UL ;
2289                 }
2290                 if (state->IF_LO == 4063000UL)  /* add for 2.6.8 */ {
2291                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x05);
2292                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2293                         Fref = 365670000UL ;
2294                 }
2295         }
2296         /* CHCAL_INT_MOD_IF */
2297         /* CHCAL_FRAC_MOD_IF */
2298         intModVal = Fref / (state->Fxtal * Kdbl/2);
2299         status += MXL_ControlWrite(fe, CHCAL_INT_MOD_IF, intModVal);
2300
2301         fracModVal = (2<<15)*(Fref/1000 - (state->Fxtal/1000 * Kdbl/2) *
2302                 intModVal);
2303
2304         fracModVal = fracModVal / ((state->Fxtal * Kdbl/2)/1000);
2305         status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_IF, fracModVal);
2306
2307         return status ;
2308 }
2309
2310 static u32 MXL_GetXtalInt(u32 Xtal_Freq)
2311 {
2312         if ((Xtal_Freq % 1000000) == 0)
2313                 return (Xtal_Freq / 10000);
2314         else
2315                 return (((Xtal_Freq / 1000000) + 1)*100);
2316 }
2317
2318 static u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
2319 {
2320         struct mxl5005s_state *state = fe->tuner_priv;
2321         u16 status = 0;
2322         u32 divider_val, E3, E4, E5, E5A;
2323         u32 Fmax, Fmin, FmaxBin, FminBin;
2324         u32 Kdbl_RF = 2;
2325         u32 tg_divval;
2326         u32 tg_lo;
2327         u32 Xtal_Int;
2328
2329         u32 Fref_TG;
2330         u32 Fvco;
2331
2332         Xtal_Int = MXL_GetXtalInt(state->Fxtal);
2333
2334         state->RF_IN = RF_Freq;
2335
2336         MXL_SynthRFTGLO_Calc(fe);
2337
2338         if (state->Fxtal >= 12000000UL && state->Fxtal <= 22000000UL)
2339                 Kdbl_RF = 2;
2340         if (state->Fxtal > 22000000 && state->Fxtal <= 32000000)
2341                 Kdbl_RF = 1;
2342
2343         /* Downconverter Controls
2344          * Look-Up Table Implementation for:
2345          *      DN_POLY
2346          *      DN_RFGAIN
2347          *      DN_CAP_RFLPF
2348          *      DN_EN_VHFUHFBAR
2349          *      DN_GAIN_ADJUST
2350          *  Change the boundary reference from RF_IN to RF_LO
2351          */
2352         if (state->RF_LO < 40000000UL)
2353                 return -1;
2354
2355         if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) {
2356                 status += MXL_ControlWrite(fe, DN_POLY,              2);
2357                 status += MXL_ControlWrite(fe, DN_RFGAIN,            3);
2358                 status += MXL_ControlWrite(fe, DN_CAP_RFLPF,         423);
2359                 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR,      1);
2360                 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST,       1);
2361         }
2362         if (state->RF_LO > 75000000UL && state->RF_LO <= 100000000UL) {
2363                 status += MXL_ControlWrite(fe, DN_POLY,              3);
2364                 status += MXL_ControlWrite(fe, DN_RFGAIN,            3);
2365                 status += MXL_ControlWrite(fe, DN_CAP_RFLPF,         222);
2366                 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR,      1);
2367                 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST,       1);
2368         }
2369         if (state->RF_LO > 100000000UL && state->RF_LO <= 150000000UL) {
2370                 status += MXL_ControlWrite(fe, DN_POLY,              3);
2371                 status += MXL_ControlWrite(fe, DN_RFGAIN,            3);
2372                 status += MXL_ControlWrite(fe, DN_CAP_RFLPF,         147);
2373                 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR,      1);
2374                 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST,       2);
2375         }
2376         if (state->RF_LO > 150000000UL && state->RF_LO <= 200000000UL) {
2377                 status += MXL_ControlWrite(fe, DN_POLY,              3);
2378                 status += MXL_ControlWrite(fe, DN_RFGAIN,            3);
2379                 status += MXL_ControlWrite(fe, DN_CAP_RFLPF,         9);
2380                 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR,      1);
2381                 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST,       2);
2382         }
2383         if (state->RF_LO > 200000000UL && state->RF_LO <= 300000000UL) {
2384                 status += MXL_ControlWrite(fe, DN_POLY,              3);
2385                 status += MXL_ControlWrite(fe, DN_RFGAIN,            3);
2386                 status += MXL_ControlWrite(fe, DN_CAP_RFLPF,         0);
2387                 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR,      1);
2388                 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST,       3);
2389         }
2390         if (state->RF_LO > 300000000UL && state->RF_LO <= 650000000UL) {
2391                 status += MXL_ControlWrite(fe, DN_POLY,              3);
2392                 status += MXL_ControlWrite(fe, DN_RFGAIN,            1);
2393                 status += MXL_ControlWrite(fe, DN_CAP_RFLPF,         0);
2394                 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR,      0);
2395                 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST,       3);
2396         }
2397         if (state->RF_LO > 650000000UL && state->RF_LO <= 900000000UL) {
2398                 status += MXL_ControlWrite(fe, DN_POLY,              3);
2399                 status += MXL_ControlWrite(fe, DN_RFGAIN,            2);
2400                 status += MXL_ControlWrite(fe, DN_CAP_RFLPF,         0);
2401                 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR,      0);
2402                 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST,       3);
2403         }
2404         if (state->RF_LO > 900000000UL)
2405                 return -1;
2406
2407         /*      DN_IQTNBUF_AMP */
2408         /*      DN_IQTNGNBFBIAS_BST */
2409         if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) {
2410                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       1);
2411                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  0);
2412         }
2413         if (state->RF_LO > 75000000UL && state->RF_LO <= 100000000UL) {
2414                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       1);
2415                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  0);
2416         }
2417         if (state->RF_LO > 100000000UL && state->RF_LO <= 150000000UL) {
2418                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       1);
2419                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  0);
2420         }
2421         if (state->RF_LO > 150000000UL && state->RF_LO <= 200000000UL) {
2422                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       1);
2423                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  0);
2424         }
2425         if (state->RF_LO > 200000000UL && state->RF_LO <= 300000000UL) {
2426                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       1);
2427                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  0);
2428         }
2429         if (state->RF_LO > 300000000UL && state->RF_LO <= 400000000UL) {
2430                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       1);
2431                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  0);
2432         }
2433         if (state->RF_LO > 400000000UL && state->RF_LO <= 450000000UL) {
2434                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       1);
2435                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  0);
2436         }
2437         if (state->RF_LO > 450000000UL && state->RF_LO <= 500000000UL) {
2438                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       1);
2439                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  0);
2440         }
2441         if (state->RF_LO > 500000000UL && state->RF_LO <= 550000000UL) {
2442                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       1);
2443                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  0);
2444         }
2445         if (state->RF_LO > 550000000UL && state->RF_LO <= 600000000UL) {
2446                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       1);
2447                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  0);
2448         }
2449         if (state->RF_LO > 600000000UL && state->RF_LO <= 650000000UL) {
2450                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       1);
2451                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  0);
2452         }
2453         if (state->RF_LO > 650000000UL && state->RF_LO <= 700000000UL) {
2454                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       1);
2455                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  0);
2456         }
2457         if (state->RF_LO > 700000000UL && state->RF_LO <= 750000000UL) {
2458                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       1);
2459                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  0);
2460         }
2461         if (state->RF_LO > 750000000UL && state->RF_LO <= 800000000UL) {
2462                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       1);
2463                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  0);
2464         }
2465         if (state->RF_LO > 800000000UL && state->RF_LO <= 850000000UL) {
2466                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       10);
2467                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  1);
2468         }
2469         if (state->RF_LO > 850000000UL && state->RF_LO <= 900000000UL) {
2470                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       10);
2471                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  1);
2472         }
2473
2474         /*
2475          * Set RF Synth and LO Path Control
2476          *
2477          * Look-Up table implementation for:
2478          *      RFSYN_EN_OUTMUX
2479          *      RFSYN_SEL_VCO_OUT
2480          *      RFSYN_SEL_VCO_HI
2481          *  RFSYN_SEL_DIVM
2482          *      RFSYN_RF_DIV_BIAS
2483          *      DN_SEL_FREQ
2484          *
2485          * Set divider_val, Fmax, Fmix to use in Equations
2486          */
2487         FminBin = 28000000UL ;
2488         FmaxBin = 42500000UL ;
2489         if (state->RF_LO >= 40000000UL && state->RF_LO <= FmaxBin) {
2490                 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX,     1);
2491                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT,   0);
2492                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI,    0);
2493                 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM,      0);
2494                 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS,   1);
2495                 status += MXL_ControlWrite(fe, DN_SEL_FREQ,         1);
2496                 divider_val = 64 ;
2497                 Fmax = FmaxBin ;
2498                 Fmin = FminBin ;
2499         }
2500         FminBin = 42500000UL ;
2501         FmaxBin = 56000000UL ;
2502         if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2503                 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX,     1);
2504                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT,   0);
2505                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI,    1);
2506                 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM,      0);
2507                 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS,   1);
2508                 status += MXL_ControlWrite(fe, DN_SEL_FREQ,         1);
2509                 divider_val = 64 ;
2510                 Fmax = FmaxBin ;
2511                 Fmin = FminBin ;
2512         }
2513         FminBin = 56000000UL ;
2514         FmaxBin = 85000000UL ;
2515         if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2516                 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX,     0);
2517                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT,   1);
2518                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI,    0);
2519                 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM,      0);
2520                 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS,   1);
2521                 status += MXL_ControlWrite(fe, DN_SEL_FREQ,         1);
2522                 divider_val = 32 ;
2523                 Fmax = FmaxBin ;
2524                 Fmin = FminBin ;
2525         }
2526         FminBin = 85000000UL ;
2527         FmaxBin = 112000000UL ;
2528         if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2529                 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX,     0);
2530                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT,   1);
2531                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI,    1);
2532                 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM,      0);
2533                 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS,   1);
2534                 status += MXL_ControlWrite(fe, DN_SEL_FREQ,         1);
2535                 divider_val = 32 ;
2536                 Fmax = FmaxBin ;
2537                 Fmin = FminBin ;
2538         }
2539         FminBin = 112000000UL ;
2540         FmaxBin = 170000000UL ;
2541         if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2542                 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX,     0);
2543                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT,   1);
2544                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI,    0);
2545                 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM,      0);
2546                 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS,   1);
2547                 status += MXL_ControlWrite(fe, DN_SEL_FREQ,         2);
2548                 divider_val = 16 ;
2549                 Fmax = FmaxBin ;
2550                 Fmin = FminBin ;
2551         }
2552         FminBin = 170000000UL ;
2553         FmaxBin = 225000000UL ;
2554         if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2555                 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX,     0);
2556                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT,   1);
2557                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI,    1);
2558                 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM,      0);
2559                 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS,   1);
2560                 status += MXL_ControlWrite(fe, DN_SEL_FREQ,         2);
2561                 divider_val = 16 ;
2562                 Fmax = FmaxBin ;
2563                 Fmin = FminBin ;
2564         }
2565         FminBin = 225000000UL ;
2566         FmaxBin = 300000000UL ;
2567         if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2568                 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX,     0);
2569                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT,   1);
2570                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI,    0);
2571                 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM,      0);
2572                 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS,   1);
2573                 status += MXL_ControlWrite(fe, DN_SEL_FREQ,         4);
2574                 divider_val = 8 ;
2575                 Fmax = 340000000UL ;
2576                 Fmin = FminBin ;
2577         }
2578         FminBin = 300000000UL ;
2579         FmaxBin = 340000000UL ;
2580         if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2581                 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX,     1);
2582                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT,   0);
2583                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI,    0);
2584                 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM,      0);
2585                 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS,   1);
2586                 status += MXL_ControlWrite(fe, DN_SEL_FREQ,         0);
2587                 divider_val = 8 ;
2588                 Fmax = FmaxBin ;
2589                 Fmin = 225000000UL ;
2590         }
2591         FminBin = 340000000UL ;
2592         FmaxBin = 450000000UL ;
2593         if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2594                 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX,     1);
2595                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT,   0);
2596                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI,    1);
2597                 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM,      0);
2598                 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS,   2);
2599                 status += MXL_ControlWrite(fe, DN_SEL_FREQ,         0);
2600                 divider_val = 8 ;
2601                 Fmax = FmaxBin ;
2602                 Fmin = FminBin ;
2603         }
2604         FminBin = 450000000UL ;
2605         FmaxBin = 680000000UL ;
2606         if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2607                 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX,     0);
2608                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT,   1);
2609                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI,    0);
2610                 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM,      1);
2611                 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS,   1);
2612                 status += MXL_ControlWrite(fe, DN_SEL_FREQ,         0);
2613                 divider_val = 4 ;
2614                 Fmax = FmaxBin ;
2615                 Fmin = FminBin ;
2616         }
2617         FminBin = 680000000UL ;
2618         FmaxBin = 900000000UL ;
2619         if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2620                 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX,     0);
2621                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT,   1);
2622                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI,    1);
2623                 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM,      1);
2624                 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS,   1);
2625                 status += MXL_ControlWrite(fe, DN_SEL_FREQ,         0);
2626                 divider_val = 4 ;
2627                 Fmax = FmaxBin ;
2628                 Fmin = FminBin ;
2629         }
2630
2631         /*      CHCAL_INT_MOD_RF
2632          *      CHCAL_FRAC_MOD_RF
2633          *      RFSYN_LPF_R
2634          *      CHCAL_EN_INT_RF
2635          */
2636         /* Equation E3 RFSYN_VCO_BIAS */
2637         E3 = (((Fmax-state->RF_LO)/1000)*32)/((Fmax-Fmin)/1000) + 8 ;
2638         status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, E3);
2639
2640         /* Equation E4 CHCAL_INT_MOD_RF */
2641         E4 = (state->RF_LO*divider_val/1000)/(2*state->Fxtal*Kdbl_RF/1000);
2642         MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, E4);
2643
2644         /* Equation E5 CHCAL_FRAC_MOD_RF CHCAL_EN_INT_RF */
2645         E5 = ((2<<17)*(state->RF_LO/10000*divider_val -
2646                 (E4*(2*state->Fxtal*Kdbl_RF)/10000))) /
2647                 (2*state->Fxtal*Kdbl_RF/10000);
2648
2649         status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5);
2650
2651         /* Equation E5A RFSYN_LPF_R */
2652         E5A = (((Fmax - state->RF_LO)/1000)*4/((Fmax-Fmin)/1000)) + 1 ;
2653         status += MXL_ControlWrite(fe, RFSYN_LPF_R, E5A);
2654
2655         /* Euqation E5B CHCAL_EN_INIT_RF */
2656         status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, ((E5 == 0) ? 1 : 0));
2657         /*if (E5 == 0)
2658          *      status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, 1);
2659          *else
2660          *      status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5);
2661          */
2662
2663         /*
2664          * Set TG Synth
2665          *
2666          * Look-Up table implementation for:
2667          *      TG_LO_DIVVAL
2668          *      TG_LO_SELVAL
2669          *
2670          * Set divider_val, Fmax, Fmix to use in Equations
2671          */
2672         if (state->TG_LO < 33000000UL)
2673                 return -1;
2674
2675         FminBin = 33000000UL ;
2676         FmaxBin = 50000000UL ;
2677         if (state->TG_LO >= FminBin && state->TG_LO <= FmaxBin) {
2678                 status += MXL_ControlWrite(fe, TG_LO_DIVVAL,    0x6);
2679                 status += MXL_ControlWrite(fe, TG_LO_SELVAL,    0x0);
2680                 divider_val = 36 ;
2681                 Fmax = FmaxBin ;
2682                 Fmin = FminBin ;
2683         }
2684         FminBin = 50000000UL ;
2685         FmaxBin = 67000000UL ;
2686         if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2687                 status += MXL_ControlWrite(fe, TG_LO_DIVVAL,    0x1);
2688                 status += MXL_ControlWrite(fe, TG_LO_SELVAL,    0x0);
2689                 divider_val = 24 ;
2690                 Fmax = FmaxBin ;
2691                 Fmin = FminBin ;
2692         }
2693         FminBin = 67000000UL ;
2694         FmaxBin = 100000000UL ;
2695         if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2696                 status += MXL_ControlWrite(fe, TG_LO_DIVVAL,    0xC);
2697                 status += MXL_ControlWrite(fe, TG_LO_SELVAL,    0x2);
2698                 divider_val = 18 ;
2699                 Fmax = FmaxBin ;
2700                 Fmin = FminBin ;
2701         }
2702         FminBin = 100000000UL ;
2703         FmaxBin = 150000000UL ;
2704         if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2705                 status += MXL_ControlWrite(fe, TG_LO_DIVVAL,    0x8);
2706                 status += MXL_ControlWrite(fe, TG_LO_SELVAL,    0x2);
2707                 divider_val = 12 ;
2708                 Fmax = FmaxBin ;
2709                 Fmin = FminBin ;
2710         }
2711         FminBin = 150000000UL ;
2712         FmaxBin = 200000000UL ;
2713         if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2714                 status += MXL_ControlWrite(fe, TG_LO_DIVVAL,    0x0);
2715                 status += MXL_ControlWrite(fe, TG_LO_SELVAL,    0x2);
2716                 divider_val = 8 ;
2717                 Fmax = FmaxBin ;
2718                 Fmin = FminBin ;
2719         }
2720         FminBin = 200000000UL ;
2721         FmaxBin = 300000000UL ;
2722         if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2723                 status += MXL_ControlWrite(fe, TG_LO_DIVVAL,    0x8);
2724                 status += MXL_ControlWrite(fe, TG_LO_SELVAL,    0x3);
2725                 divider_val = 6 ;
2726                 Fmax = FmaxBin ;
2727                 Fmin = FminBin ;
2728         }
2729         FminBin = 300000000UL ;
2730         FmaxBin = 400000000UL ;
2731         if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2732                 status += MXL_ControlWrite(fe, TG_LO_DIVVAL,    0x0);
2733                 status += MXL_ControlWrite(fe, TG_LO_SELVAL,    0x3);
2734                 divider_val = 4 ;
2735                 Fmax = FmaxBin ;
2736                 Fmin = FminBin ;
2737         }
2738         FminBin = 400000000UL ;
2739         FmaxBin = 600000000UL ;
2740         if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2741                 status += MXL_ControlWrite(fe, TG_LO_DIVVAL,    0x8);
2742                 status += MXL_ControlWrite(fe, TG_LO_SELVAL,    0x7);
2743                 divider_val = 3 ;
2744                 Fmax = FmaxBin ;
2745                 Fmin = FminBin ;
2746         }
2747         FminBin = 600000000UL ;
2748         FmaxBin = 900000000UL ;
2749         if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2750                 status += MXL_ControlWrite(fe, TG_LO_DIVVAL,    0x0);
2751                 status += MXL_ControlWrite(fe, TG_LO_SELVAL,    0x7);
2752                 divider_val = 2 ;
2753                 Fmax = FmaxBin ;
2754                 Fmin = FminBin ;
2755         }
2756
2757         /* TG_DIV_VAL */
2758         tg_divval = (state->TG_LO*divider_val/100000) *
2759                 (MXL_Ceiling(state->Fxtal, 1000000) * 100) /
2760                 (state->Fxtal/1000);
2761
2762         status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval);
2763
2764         if (state->TG_LO > 600000000UL)
2765                 status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval + 1);
2766
2767         Fmax = 1800000000UL ;
2768         Fmin = 1200000000UL ;
2769
2770         /* prevent overflow of 32 bit unsigned integer, use
2771          * following equation. Edit for v2.6.4
2772          */
2773         /* Fref_TF = Fref_TG * 1000 */
2774         Fref_TG = (state->Fxtal/1000) / MXL_Ceiling(state->Fxtal, 1000000);
2775
2776         /* Fvco = Fvco/10 */
2777         Fvco = (state->TG_LO/10000) * divider_val * Fref_TG;
2778
2779         tg_lo = (((Fmax/10 - Fvco)/100)*32) / ((Fmax-Fmin)/1000)+8;
2780
2781         /* below equation is same as above but much harder to debug.
2782          * tg_lo = ( ((Fmax/10000 * Xtal_Int)/100) -
2783          * ((state->TG_LO/10000)*divider_val *
2784          * (state->Fxtal/10000)/100) )*32/((Fmax-Fmin)/10000 *
2785          * Xtal_Int/100) + 8;
2786          */
2787
2788         status += MXL_ControlWrite(fe, TG_VCO_BIAS , tg_lo);
2789
2790         /* add for 2.6.5 Special setting for QAM */
2791         if (state->Mod_Type == MXL_QAM) {
2792                 if (state->config->qam_gain != 0)
2793                         status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN,
2794                                                    state->config->qam_gain);
2795                 else if (state->RF_IN < 680000000)
2796                         status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3);
2797                 else
2798                         status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2);
2799         }
2800
2801         /* Off Chip Tracking Filter Control */
2802         if (state->TF_Type == MXL_TF_OFF) {
2803                 /* Tracking Filter Off State; turn off all the banks */
2804                 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2805                 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
2806                 status += MXL_SetGPIO(fe, 3, 1); /* Bank1 Off */
2807                 status += MXL_SetGPIO(fe, 1, 1); /* Bank2 Off */
2808                 status += MXL_SetGPIO(fe, 4, 1); /* Bank3 Off */
2809         }
2810
2811         if (state->TF_Type == MXL_TF_C) /* Tracking Filter type C */ {
2812                 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
2813                 status += MXL_ControlWrite(fe, DAC_DIN_A, 0);
2814
2815                 if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) {
2816                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2817                         status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
2818                         status += MXL_SetGPIO(fe, 3, 0);
2819                         status += MXL_SetGPIO(fe, 1, 1);
2820                         status += MXL_SetGPIO(fe, 4, 1);
2821                 }
2822                 if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) {
2823                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2824                         status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
2825                         status += MXL_SetGPIO(fe, 3, 1);
2826                         status += MXL_SetGPIO(fe, 1, 0);
2827                         status += MXL_SetGPIO(fe, 4, 1);
2828                 }
2829                 if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) {
2830                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2831                         status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
2832                         status += MXL_SetGPIO(fe, 3, 1);
2833                         status += MXL_SetGPIO(fe, 1, 0);
2834                         status += MXL_SetGPIO(fe, 4, 0);
2835                 }
2836                 if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) {
2837                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2838                         status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
2839                         status += MXL_SetGPIO(fe, 3, 1);
2840                         status += MXL_SetGPIO(fe, 1, 1);
2841                         status += MXL_SetGPIO(fe, 4, 0);
2842                 }
2843                 if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) {
2844                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2845                         status += MXL_ControlWrite(fe, DAC_DIN_B, 29);
2846                         status += MXL_SetGPIO(fe, 3, 1);
2847                         status += MXL_SetGPIO(fe, 1, 1);
2848                         status += MXL_SetGPIO(fe, 4, 0);
2849                 }
2850                 if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) {
2851                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2852                         status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
2853                         status += MXL_SetGPIO(fe, 3, 1);
2854                         status += MXL_SetGPIO(fe, 1, 1);
2855                         status += MXL_SetGPIO(fe, 4, 0);
2856                 }
2857                 if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) {
2858                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2859                         status += MXL_ControlWrite(fe, DAC_DIN_B, 16);
2860                         status += MXL_SetGPIO(fe, 3, 1);
2861                         status += MXL_SetGPIO(fe, 1, 1);
2862                         status += MXL_SetGPIO(fe, 4, 1);
2863                 }
2864                 if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) {
2865                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2866                         status += MXL_ControlWrite(fe, DAC_DIN_B, 7);
2867                         status += MXL_SetGPIO(fe, 3, 1);
2868                         status += MXL_SetGPIO(fe, 1, 1);
2869                         status += MXL_SetGPIO(fe, 4, 1);
2870                 }
2871                 if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) {
2872                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2873                         status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
2874                         status += MXL_SetGPIO(fe, 3, 1);
2875                         status += MXL_SetGPIO(fe, 1, 1);
2876                         status += MXL_SetGPIO(fe, 4, 1);
2877                 }
2878         }
2879
2880         if (state->TF_Type == MXL_TF_C_H) {
2881
2882                 /* Tracking Filter type C-H for Hauppauge only */
2883                 status += MXL_ControlWrite(fe, DAC_DIN_A, 0);
2884
2885                 if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) {
2886                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2887                         status += MXL_SetGPIO(fe, 4, 0);
2888                         status += MXL_SetGPIO(fe, 3, 1);
2889                         status += MXL_SetGPIO(fe, 1, 1);
2890                 }
2891                 if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) {
2892                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2893                         status += MXL_SetGPIO(fe, 4, 1);
2894                         status += MXL_SetGPIO(fe, 3, 0);
2895                         status += MXL_SetGPIO(fe, 1, 1);
2896                 }
2897                 if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) {
2898                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2899                         status += MXL_SetGPIO(fe, 4, 1);
2900                         status += MXL_SetGPIO(fe, 3, 0);
2901                         status += MXL_SetGPIO(fe, 1, 0);
2902                 }
2903                 if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) {
2904                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2905                         status += MXL_SetGPIO(fe, 4, 1);
2906                         status += MXL_SetGPIO(fe, 3, 1);
2907                         status += MXL_SetGPIO(fe, 1, 0);
2908                 }
2909                 if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) {
2910                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2911                         status += MXL_SetGPIO(fe, 4, 1);
2912                         status += MXL_SetGPIO(fe, 3, 1);
2913                         status += MXL_SetGPIO(fe, 1, 0);
2914                 }
2915                 if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) {
2916                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2917                         status += MXL_SetGPIO(fe, 4, 1);
2918                         status += MXL_SetGPIO(fe, 3, 1);
2919                         status += MXL_SetGPIO(fe, 1, 0);
2920                 }
2921                 if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) {
2922                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2923                         status += MXL_SetGPIO(fe, 4, 1);
2924                         status += MXL_SetGPIO(fe, 3, 1);
2925                         status += MXL_SetGPIO(fe, 1, 1);
2926                 }
2927                 if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) {
2928                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2929                         status += MXL_SetGPIO(fe, 4, 1);
2930                         status += MXL_SetGPIO(fe, 3, 1);
2931                         status += MXL_SetGPIO(fe, 1, 1);
2932                 }
2933                 if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) {
2934                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2935                         status += MXL_SetGPIO(fe, 4, 1);
2936                         status += MXL_SetGPIO(fe, 3, 1);
2937                         status += MXL_SetGPIO(fe, 1, 1);
2938                 }
2939         }
2940
2941         if (state->TF_Type == MXL_TF_D) { /* Tracking Filter type D */
2942
2943                 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
2944
2945                 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) {
2946                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
2947                         status += MXL_SetGPIO(fe, 4, 0);
2948                         status += MXL_SetGPIO(fe, 1, 1);
2949                         status += MXL_SetGPIO(fe, 3, 1);
2950                 }
2951                 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) {
2952                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
2953                         status += MXL_SetGPIO(fe, 4, 0);
2954                         status += MXL_SetGPIO(fe, 1, 0);
2955                         status += MXL_SetGPIO(fe, 3, 1);
2956                 }
2957                 if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) {
2958                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
2959                         status += MXL_SetGPIO(fe, 4, 1);
2960                         status += MXL_SetGPIO(fe, 1, 0);
2961                         status += MXL_SetGPIO(fe, 3, 1);
2962                 }
2963                 if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) {
2964                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
2965                         status += MXL_SetGPIO(fe, 4, 1);
2966                         status += MXL_SetGPIO(fe, 1, 0);
2967                         status += MXL_SetGPIO(fe, 3, 0);
2968                 }
2969                 if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) {
2970                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
2971                         status += MXL_SetGPIO(fe, 4, 1);
2972                         status += MXL_SetGPIO(fe, 1, 1);
2973                         status += MXL_SetGPIO(fe, 3, 0);
2974                 }
2975                 if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) {
2976                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
2977                         status += MXL_SetGPIO(fe, 4, 1);
2978                         status += MXL_SetGPIO(fe, 1, 1);
2979                         status += MXL_SetGPIO(fe, 3, 0);
2980                 }
2981                 if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000) {
2982                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
2983                         status += MXL_SetGPIO(fe, 4, 1);
2984                         status += MXL_SetGPIO(fe, 1, 1);
2985                         status += MXL_SetGPIO(fe, 3, 1);
2986                 }
2987         }
2988
2989         if (state->TF_Type == MXL_TF_D_L) {
2990
2991                 /* Tracking Filter type D-L for Lumanate ONLY change 2.6.3 */
2992                 status += MXL_ControlWrite(fe, DAC_DIN_A, 0);
2993
2994                 /* if UHF and terrestrial => Turn off Tracking Filter */
2995                 if (state->RF_IN >= 471000000 &&
2996                         (state->RF_IN - 471000000)%6000000 != 0) {
2997                         /* Turn off all the banks */
2998                         status += MXL_SetGPIO(fe, 3, 1);
2999                         status += MXL_SetGPIO(fe, 1, 1);
3000                         status += MXL_SetGPIO(fe, 4, 1);
3001                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3002                         status += MXL_ControlWrite(fe, AGC_IF, 10);
3003                 } else {
3004                         /* if VHF or cable => Turn on Tracking Filter */
3005                         if (state->RF_IN >= 43000000 &&
3006                                 state->RF_IN < 140000000) {
3007
3008                                 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3009                                 status += MXL_SetGPIO(fe, 4, 1);
3010                                 status += MXL_SetGPIO(fe, 1, 1);
3011                                 status += MXL_SetGPIO(fe, 3, 0);
3012                         }
3013                         if (state->RF_IN >= 140000000 &&
3014                                 state->RF_IN < 240000000) {
3015                                 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3016                                 status += MXL_SetGPIO(fe, 4, 1);
3017                                 status += MXL_SetGPIO(fe, 1, 0);
3018                                 status += MXL_SetGPIO(fe, 3, 0);
3019                         }
3020                         if (state->RF_IN >= 240000000 &&
3021                                 state->RF_IN < 340000000) {
3022                                 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3023                                 status += MXL_SetGPIO(fe, 4, 0);
3024                                 status += MXL_SetGPIO(fe, 1, 1);
3025                                 status += MXL_SetGPIO(fe, 3, 0);
3026                         }
3027                         if (state->RF_IN >= 340000000 &&
3028                                 state->RF_IN < 430000000) {
3029                                 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3030                                 status += MXL_SetGPIO(fe, 4, 0);
3031                                 status += MXL_SetGPIO(fe, 1, 0);
3032                                 status += MXL_SetGPIO(fe, 3, 1);
3033                         }
3034                         if (state->RF_IN >= 430000000 &&
3035                                 state->RF_IN < 470000000) {
3036                                 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
3037                                 status += MXL_SetGPIO(fe, 4, 1);
3038                                 status += MXL_SetGPIO(fe, 1, 0);
3039                                 status += MXL_SetGPIO(fe, 3, 1);
3040                         }
3041                         if (state->RF_IN >= 470000000 &&
3042                                 state->RF_IN < 570000000) {
3043                                 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
3044                                 status += MXL_SetGPIO(fe, 4, 0);
3045                                 status += MXL_SetGPIO(fe, 1, 0);
3046                                 status += MXL_SetGPIO(fe, 3, 1);
3047                         }
3048                         if (state->RF_IN >= 570000000 &&
3049                                 state->RF_IN < 620000000) {
3050                                 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3051                                 status += MXL_SetGPIO(fe, 4, 0);
3052                                 status += MXL_SetGPIO(fe, 1, 1);
3053                                 status += MXL_SetGPIO(fe, 3, 1);
3054                         }
3055                         if (state->RF_IN >= 620000000 &&
3056                                 state->RF_IN < 760000000) {
3057                                 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
3058                                 status += MXL_SetGPIO(fe, 4, 0);
3059                                 status += MXL_SetGPIO(fe, 1, 1);
3060                                 status += MXL_SetGPIO(fe, 3, 1);
3061                         }
3062                         if (state->RF_IN >= 760000000 &&
3063                                 state->RF_IN <= 900000000) {
3064                                 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
3065                                 status += MXL_SetGPIO(fe, 4, 1);
3066                                 status += MXL_SetGPIO(fe, 1, 1);
3067                                 status += MXL_SetGPIO(fe, 3, 1);
3068                         }
3069                 }
3070         }
3071
3072         if (state->TF_Type == MXL_TF_E) /* Tracking Filter type E */ {
3073
3074                 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
3075
3076                 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) {
3077                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3078                         status += MXL_SetGPIO(fe, 4, 0);
3079                         status += MXL_SetGPIO(fe, 1, 1);
3080                         status += MXL_SetGPIO(fe, 3, 1);
3081                 }
3082                 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) {
3083                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3084                         status += MXL_SetGPIO(fe, 4, 0);
3085                         status += MXL_SetGPIO(fe, 1, 0);
3086                         status += MXL_SetGPIO(fe, 3, 1);
3087                 }
3088                 if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) {
3089                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3090                         status += MXL_SetGPIO(fe, 4, 1);
3091                         status += MXL_SetGPIO(fe, 1, 0);
3092                         status += MXL_SetGPIO(fe, 3, 1);
3093                 }
3094                 if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) {
3095                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3096                         status += MXL_SetGPIO(fe, 4, 1);
3097                         status += MXL_SetGPIO(fe, 1, 0);
3098                         status += MXL_SetGPIO(fe, 3, 0);
3099                 }
3100                 if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) {
3101                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3102                         status += MXL_SetGPIO(fe, 4, 1);
3103                         status += MXL_SetGPIO(fe, 1, 1);
3104                         status += MXL_SetGPIO(fe, 3, 0);
3105                 }
3106                 if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) {
3107                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3108                         status += MXL_SetGPIO(fe, 4, 1);
3109                         status += MXL_SetGPIO(fe, 1, 1);
3110                         status += MXL_SetGPIO(fe, 3, 0);
3111                 }
3112                 if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000) {
3113                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3114                         status += MXL_SetGPIO(fe, 4, 1);
3115                         status += MXL_SetGPIO(fe, 1, 1);
3116                         status += MXL_SetGPIO(fe, 3, 1);
3117                 }
3118         }
3119
3120         if (state->TF_Type == MXL_TF_F) {
3121
3122                 /* Tracking Filter type F */
3123                 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
3124
3125                 if (state->RF_IN >= 43000000 && state->RF_IN < 160000000) {
3126                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3127                         status += MXL_SetGPIO(fe, 4, 0);
3128                         status += MXL_SetGPIO(fe, 1, 1);
3129                         status += MXL_SetGPIO(fe, 3, 1);
3130                 }
3131                 if (state->RF_IN >= 160000000 && state->RF_IN < 210000000) {
3132                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3133                         status += MXL_SetGPIO(fe, 4, 0);
3134                         status += MXL_SetGPIO(fe, 1, 0);
3135                         status += MXL_SetGPIO(fe, 3, 1);
3136                 }
3137                 if (state->RF_IN >= 210000000 && state->RF_IN < 300000000) {
3138                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3139                         status += MXL_SetGPIO(fe, 4, 1);
3140                         status += MXL_SetGPIO(fe, 1, 0);
3141                         status += MXL_SetGPIO(fe, 3, 1);
3142                 }
3143                 if (state->RF_IN >= 300000000 && state->RF_IN < 390000000) {
3144                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3145                         status += MXL_SetGPIO(fe, 4, 1);
3146                         status += MXL_SetGPIO(fe, 1, 0);
3147                         status += MXL_SetGPIO(fe, 3, 0);
3148                 }
3149                 if (state->RF_IN >= 390000000 && state->RF_IN < 515000000) {
3150                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3151                         status += MXL_SetGPIO(fe, 4, 1);
3152                         status += MXL_SetGPIO(fe, 1, 1);
3153                         status += MXL_SetGPIO(fe, 3, 0);
3154                 }
3155                 if (state->RF_IN >= 515000000 && state->RF_IN < 650000000) {
3156                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3157                         status += MXL_SetGPIO(fe, 4, 1);
3158                         status += MXL_SetGPIO(fe, 1, 1);
3159                         status += MXL_SetGPIO(fe, 3, 0);
3160                 }
3161                 if (state->RF_IN >= 650000000 && state->RF_IN <= 900000000) {
3162                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3163                         status += MXL_SetGPIO(fe, 4, 1);
3164                         status += MXL_SetGPIO(fe, 1, 1);
3165                         status += MXL_SetGPIO(fe, 3, 1);
3166                 }
3167         }
3168
3169         if (state->TF_Type == MXL_TF_E_2) {
3170
3171                 /* Tracking Filter type E_2 */
3172                 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
3173
3174                 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) {
3175                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3176                         status += MXL_SetGPIO(fe, 4, 0);
3177                         status += MXL_SetGPIO(fe, 1, 1);
3178                         status += MXL_SetGPIO(fe, 3, 1);
3179                 }
3180                 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) {
3181                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3182                         status += MXL_SetGPIO(fe, 4, 0);
3183                         status += MXL_SetGPIO(fe, 1, 0);
3184                         status += MXL_SetGPIO(fe, 3, 1);
3185                 }
3186                 if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) {
3187                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3188                         status += MXL_SetGPIO(fe, 4, 1);
3189                         status += MXL_SetGPIO(fe, 1, 0);
3190                         status += MXL_SetGPIO(fe, 3, 1);
3191                 }
3192                 if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) {
3193                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3194                         status += MXL_SetGPIO(fe, 4, 1);
3195                         status += MXL_SetGPIO(fe, 1, 0);
3196                         status += MXL_SetGPIO(fe, 3, 0);
3197                 }
3198                 if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) {
3199                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3200                         status += MXL_SetGPIO(fe, 4, 1);
3201                         status += MXL_SetGPIO(fe, 1, 1);
3202                         status += MXL_SetGPIO(fe, 3, 0);
3203                 }
3204                 if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) {
3205                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3206                         status += MXL_SetGPIO(fe, 4, 1);
3207                         status += MXL_SetGPIO(fe, 1, 1);
3208                         status += MXL_SetGPIO(fe, 3, 0);
3209                 }
3210                 if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000) {
3211                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3212                         status += MXL_SetGPIO(fe, 4, 1);
3213                         status += MXL_SetGPIO(fe, 1, 1);
3214                         status += MXL_SetGPIO(fe, 3, 1);
3215                 }
3216         }
3217
3218         if (state->TF_Type == MXL_TF_G) {
3219
3220                 /* Tracking Filter type G add for v2.6.8 */
3221                 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
3222
3223                 if (state->RF_IN >= 50000000 && state->RF_IN < 190000000) {
3224
3225                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3226                         status += MXL_SetGPIO(fe, 4, 0);
3227                         status += MXL_SetGPIO(fe, 1, 1);
3228                         status += MXL_SetGPIO(fe, 3, 1);
3229                 }
3230                 if (state->RF_IN >= 190000000 && state->RF_IN < 280000000) {
3231                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3232                         status += MXL_SetGPIO(fe, 4, 0);
3233                         status += MXL_SetGPIO(fe, 1, 0);
3234                         status += MXL_SetGPIO(fe, 3, 1);
3235                 }
3236                 if (state->RF_IN >= 280000000 && state->RF_IN < 350000000) {
3237                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3238                         status += MXL_SetGPIO(fe, 4, 1);
3239                         status += MXL_SetGPIO(fe, 1, 0);
3240                         status += MXL_SetGPIO(fe, 3, 1);
3241                 }
3242                 if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) {
3243                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3244                         status += MXL_SetGPIO(fe, 4, 1);
3245                         status += MXL_SetGPIO(fe, 1, 0);
3246                         status += MXL_SetGPIO(fe, 3, 0);
3247                 }
3248                 if (state->RF_IN >= 400000000 && state->RF_IN < 470000000) {
3249                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3250                         status += MXL_SetGPIO(fe, 4, 1);
3251                         status += MXL_SetGPIO(fe, 1, 0);
3252                         status += MXL_SetGPIO(fe, 3, 1);
3253                 }
3254                 if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) {
3255                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3256                         status += MXL_SetGPIO(fe, 4, 1);
3257                         status += MXL_SetGPIO(fe, 1, 1);
3258                         status += MXL_SetGPIO(fe, 3, 0);
3259                 }
3260                 if (state->RF_IN >= 640000000 && state->RF_IN < 820000000) {
3261                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3262                         status += MXL_SetGPIO(fe, 4, 1);
3263                         status += MXL_SetGPIO(fe, 1, 1);
3264                         status += MXL_SetGPIO(fe, 3, 0);
3265                 }
3266                 if (state->RF_IN >= 820000000 && state->RF_IN <= 900000000) {
3267                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3268                         status += MXL_SetGPIO(fe, 4, 1);
3269                         status += MXL_SetGPIO(fe, 1, 1);
3270                         status += MXL_SetGPIO(fe, 3, 1);
3271                 }
3272         }
3273
3274         if (state->TF_Type == MXL_TF_E_NA) {
3275
3276                 /* Tracking Filter type E-NA for Empia ONLY change for 2.6.8 */
3277                 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
3278
3279                 /* if UHF and terrestrial=> Turn off Tracking Filter */
3280                 if (state->RF_IN >= 471000000 &&
3281                         (state->RF_IN - 471000000)%6000000 != 0) {
3282
3283                         /* Turn off all the banks */
3284                         status += MXL_SetGPIO(fe, 3, 1);
3285                         status += MXL_SetGPIO(fe, 1, 1);
3286                         status += MXL_SetGPIO(fe, 4, 1);
3287                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3288
3289                         /* 2.6.12 Turn on RSSI */
3290                         status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
3291                         status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
3292                         status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
3293                         status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
3294
3295                         /* RSSI reference point */
3296                         status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5);
3297                         status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3);
3298                         status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2);
3299
3300                         /* following parameter is from analog OTA mode,
3301                          * can be change to seek better performance */
3302                         status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3);
3303                 } else {
3304                 /* if VHF or Cable =>  Turn on Tracking Filter */
3305
3306                 /* 2.6.12 Turn off RSSI */
3307                 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
3308
3309                 /* change back from above condition */
3310                 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5);
3311
3312
3313                 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) {
3314
3315                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3316                         status += MXL_SetGPIO(fe, 4, 0);
3317                         status += MXL_SetGPIO(fe, 1, 1);
3318                         status += MXL_SetGPIO(fe, 3, 1);
3319                 }
3320                 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) {
3321                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3322                         status += MXL_SetGPIO(fe, 4, 0);
3323                         status += MXL_SetGPIO(fe, 1, 0);
3324                         status += MXL_SetGPIO(fe, 3, 1);
3325                 }
3326                 if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) {
3327                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3328                         status += MXL_SetGPIO(fe, 4, 1);
3329                         status += MXL_SetGPIO(fe, 1, 0);
3330                         status += MXL_SetGPIO(fe, 3, 1);
3331                 }
3332                 if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) {
3333                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3334                         status += MXL_SetGPIO(fe, 4, 1);
3335                         status += MXL_SetGPIO(fe, 1, 0);
3336                         status += MXL_SetGPIO(fe, 3, 0);
3337                 }
3338                 if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) {
3339                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3340                         status += MXL_SetGPIO(fe, 4, 1);
3341                         status += MXL_SetGPIO(fe, 1, 1);
3342                         status += MXL_SetGPIO(fe, 3, 0);
3343                 }
3344                 if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) {
3345                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3346                         status += MXL_SetGPIO(fe, 4, 1);
3347                         status += MXL_SetGPIO(fe, 1, 1);
3348                         status += MXL_SetGPIO(fe, 3, 0);
3349                 }
3350                 if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000) {
3351                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3352                         status += MXL_SetGPIO(fe, 4, 1);
3353                         status += MXL_SetGPIO(fe, 1, 1);
3354                         status += MXL_SetGPIO(fe, 3, 1);
3355                 }
3356                 }
3357         }
3358         return status ;
3359 }
3360
3361 static u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val)
3362 {
3363         u16 status = 0;
3364
3365         if (GPIO_Num == 1)
3366                 status += MXL_ControlWrite(fe, GPIO_1B, GPIO_Val ? 0 : 1);
3367
3368         /* GPIO2 is not available */
3369
3370         if (GPIO_Num == 3) {
3371                 if (GPIO_Val == 1) {
3372                         status += MXL_ControlWrite(fe, GPIO_3, 0);
3373                         status += MXL_ControlWrite(fe, GPIO_3B, 0);
3374                 }
3375                 if (GPIO_Val == 0) {
3376                         status += MXL_ControlWrite(fe, GPIO_3, 1);
3377                         status += MXL_ControlWrite(fe, GPIO_3B, 1);
3378                 }
3379                 if (GPIO_Val == 3) { /* tri-state */
3380                         status += MXL_ControlWrite(fe, GPIO_3, 0);
3381                         status += MXL_ControlWrite(fe, GPIO_3B, 1);
3382                 }
3383         }
3384         if (GPIO_Num == 4) {
3385                 if (GPIO_Val == 1) {
3386                         status += MXL_ControlWrite(fe, GPIO_4, 0);
3387                         status += MXL_ControlWrite(fe, GPIO_4B, 0);
3388                 }
3389                 if (GPIO_Val == 0) {
3390                         status += MXL_ControlWrite(fe, GPIO_4, 1);
3391                         status += MXL_ControlWrite(fe, GPIO_4B, 1);
3392                 }
3393                 if (GPIO_Val == 3) { /* tri-state */
3394                         status += MXL_ControlWrite(fe, GPIO_4, 0);
3395                         status += MXL_ControlWrite(fe, GPIO_4B, 1);
3396                 }
3397         }
3398
3399         return status;
3400 }
3401
3402 static u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value)
3403 {
3404         u16 status = 0;
3405
3406         /* Will write ALL Matching Control Name */
3407         /* Write Matching INIT Control */
3408         status += MXL_ControlWrite_Group(fe, ControlNum, value, 1);
3409         /* Write Matching CH Control */
3410         status += MXL_ControlWrite_Group(fe, ControlNum, value, 2);
3411 #ifdef _MXL_INTERNAL
3412         /* Write Matching MXL Control */
3413         status += MXL_ControlWrite_Group(fe, ControlNum, value, 3);
3414 #endif
3415         return status;
3416 }
3417
3418 static u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum,
3419         u32 value, u16 controlGroup)
3420 {
3421         struct mxl5005s_state *state = fe->tuner_priv;
3422         u16 i, j, k;
3423         u32 highLimit;
3424         u32 ctrlVal;
3425
3426         if (controlGroup == 1) /* Initial Control */ {
3427
3428                 for (i = 0; i < state->Init_Ctrl_Num; i++) {
3429
3430                         if (controlNum == state->Init_Ctrl[i].Ctrl_Num) {
3431
3432                                 highLimit = 1 << state->Init_Ctrl[i].size;
3433                                 if (value < highLimit) {
3434                                         for (j = 0; j < state->Init_Ctrl[i].size; j++) {
3435                                                 state->Init_Ctrl[i].val[j] = (u8)((value >> j) & 0x01);
3436                                                 MXL_RegWriteBit(fe, (u8)(state->Init_Ctrl[i].addr[j]),
3437                                                         (u8)(state->Init_Ctrl[i].bit[j]),
3438                                                         (u8)((value>>j) & 0x01));
3439                                         }
3440                                         ctrlVal = 0;
3441                                         for (k = 0; k < state->Init_Ctrl[i].size; k++)
3442                                                 ctrlVal += state->Init_Ctrl[i].val[k] * (1 << k);
3443                                 } else
3444                                         return -1;
3445                         }
3446                 }
3447         }
3448         if (controlGroup == 2) /* Chan change Control */ {
3449
3450                 for (i = 0; i < state->CH_Ctrl_Num; i++) {
3451
3452                         if (controlNum == state->CH_Ctrl[i].Ctrl_Num) {
3453
3454                                 highLimit = 1 << state->CH_Ctrl[i].size;
3455                                 if (value < highLimit) {
3456                                         for (j = 0; j < state->CH_Ctrl[i].size; j++) {
3457                                                 state->CH_Ctrl[i].val[j] = (u8)((value >> j) & 0x01);
3458                                                 MXL_RegWriteBit(fe, (u8)(state->CH_Ctrl[i].addr[j]),
3459                                                         (u8)(state->CH_Ctrl[i].bit[j]),
3460                                                         (u8)((value>>j) & 0x01));
3461                                         }
3462                                         ctrlVal = 0;
3463                                         for (k = 0; k < state->CH_Ctrl[i].size; k++)
3464                                                 ctrlVal += state->CH_Ctrl[i].val[k] * (1 << k);
3465                                 } else
3466                                         return -1;
3467                         }
3468                 }
3469         }
3470 #ifdef _MXL_INTERNAL
3471         if (controlGroup == 3) /* Maxlinear Control */ {
3472
3473                 for (i = 0; i < state->MXL_Ctrl_Num; i++) {
3474
3475                         if (controlNum == state->MXL_Ctrl[i].Ctrl_Num) {
3476
3477                                 highLimit = (1 << state->MXL_Ctrl[i].size);
3478                                 if (value < highLimit) {
3479                                         for (j = 0; j < state->MXL_Ctrl[i].size; j++) {
3480                                                 state->MXL_Ctrl[i].val[j] = (u8)((value >> j) & 0x01);
3481                                                 MXL_RegWriteBit(fe, (u8)(state->MXL_Ctrl[i].addr[j]),
3482                                                         (u8)(state->MXL_Ctrl[i].bit[j]),
3483                                                         (u8)((value>>j) & 0x01));
3484                                         }
3485                                         ctrlVal = 0;
3486                                         for (k = 0; k < state->MXL_Ctrl[i].size; k++)
3487                                                 ctrlVal += state->
3488                                                         MXL_Ctrl[i].val[k] *
3489                                                         (1 << k);
3490                                 } else
3491                                         return -1;
3492                         }
3493                 }
3494         }
3495 #endif
3496         return 0 ; /* successful return */
3497 }
3498
3499 static u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal)
3500 {
3501         struct mxl5005s_state *state = fe->tuner_priv;
3502         int i ;
3503
3504         for (i = 0; i < 104; i++) {
3505                 if (RegNum == state->TunerRegs[i].Reg_Num) {
3506                         *RegVal = (u8)(state->TunerRegs[i].Reg_Val);
3507                         return 0;
3508                 }
3509         }
3510
3511         return 1;
3512 }
3513
3514 static u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value)
3515 {
3516         struct mxl5005s_state *state = fe->tuner_priv;
3517         u32 ctrlVal ;
3518         u16 i, k ;
3519
3520         for (i = 0; i < state->Init_Ctrl_Num ; i++) {
3521
3522                 if (controlNum == state->Init_Ctrl[i].Ctrl_Num) {
3523
3524                         ctrlVal = 0;
3525                         for (k = 0; k < state->Init_Ctrl[i].size; k++)
3526                                 ctrlVal += state->Init_Ctrl[i].val[k] * (1<<k);
3527                         *value = ctrlVal;
3528                         return 0;
3529                 }
3530         }
3531
3532         for (i = 0; i < state->CH_Ctrl_Num ; i++) {
3533
3534                 if (controlNum == state->CH_Ctrl[i].Ctrl_Num) {
3535
3536                         ctrlVal = 0;
3537                         for (k = 0; k < state->CH_Ctrl[i].size; k++)
3538                                 ctrlVal += state->CH_Ctrl[i].val[k] * (1 << k);
3539                         *value = ctrlVal;
3540                         return 0;
3541
3542                 }
3543         }
3544
3545 #ifdef _MXL_INTERNAL
3546         for (i = 0; i < state->MXL_Ctrl_Num ; i++) {
3547
3548                 if (controlNum == state->MXL_Ctrl[i].Ctrl_Num) {
3549
3550                         ctrlVal = 0;
3551                         for (k = 0; k < state->MXL_Ctrl[i].size; k++)
3552                                 ctrlVal += state->MXL_Ctrl[i].val[k] * (1<<k);
3553                         *value = ctrlVal;
3554                         return 0;
3555
3556                 }
3557         }
3558 #endif
3559         return 1;
3560 }
3561
3562 static void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit,
3563         u8 bitVal)
3564 {
3565         struct mxl5005s_state *state = fe->tuner_priv;
3566         int i ;
3567
3568         const u8 AND_MAP[8] = {
3569                 0xFE, 0xFD, 0xFB, 0xF7,
3570                 0xEF, 0xDF, 0xBF, 0x7F } ;
3571
3572         const u8 OR_MAP[8] = {
3573                 0x01, 0x02, 0x04, 0x08,
3574                 0x10, 0x20, 0x40, 0x80 } ;
3575
3576         for (i = 0; i < state->TunerRegs_Num; i++) {
3577                 if (state->TunerRegs[i].Reg_Num == address) {
3578                         if (bitVal)
3579                                 state->TunerRegs[i].Reg_Val |= OR_MAP[bit];
3580                         else
3581                                 state->TunerRegs[i].Reg_Val &= AND_MAP[bit];
3582                         break ;
3583                 }
3584         }
3585 }
3586
3587 static u32 MXL_Ceiling(u32 value, u32 resolution)
3588 {
3589         return value / resolution + (value % resolution > 0 ? 1 : 0);
3590 }
3591
3592 /* Retrieve the Initialzation Registers */
3593 static u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum,
3594         u8 *RegVal, int *count)
3595 {
3596         u16 status = 0;
3597         int i ;
3598
3599         u8 RegAddr[] = {
3600                 11, 12, 13, 22, 32, 43, 44, 53, 56, 59, 73,
3601                 76, 77, 91, 134, 135, 137, 147,
3602                 156, 166, 167, 168, 25 };
3603
3604         *count = ARRAY_SIZE(RegAddr);
3605
3606         status += MXL_BlockInit(fe);
3607
3608         for (i = 0 ; i < *count; i++) {
3609                 RegNum[i] = RegAddr[i];
3610                 status += MXL_RegRead(fe, RegNum[i], &RegVal[i]);
3611         }
3612
3613         return status;
3614 }
3615
3616 static u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal,
3617         int *count)
3618 {
3619         u16 status = 0;
3620         int i ;
3621
3622 /* add 77, 166, 167, 168 register for 2.6.12 */
3623 #ifdef _MXL_PRODUCTION
3624         u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 65, 68, 69, 70, 73, 92, 93, 106,
3625            107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ;
3626 #else
3627         u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 68, 69, 70, 73, 92, 93, 106,
3628            107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ;
3629         /*
3630         u8 RegAddr[171];
3631         for (i = 0; i <= 170; i++)
3632                 RegAddr[i] = i;
3633         */
3634 #endif
3635
3636         *count = ARRAY_SIZE(RegAddr);
3637
3638         for (i = 0 ; i < *count; i++) {
3639                 RegNum[i] = RegAddr[i];
3640                 status += MXL_RegRead(fe, RegNum[i], &RegVal[i]);
3641         }
3642
3643         return status;
3644 }
3645
3646 static u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum,
3647         u8 *RegVal, int *count)
3648 {
3649         u16 status = 0;
3650         int i;
3651
3652         u8 RegAddr[] = {43, 136};
3653
3654         *count = ARRAY_SIZE(RegAddr);
3655
3656         for (i = 0; i < *count; i++) {
3657                 RegNum[i] = RegAddr[i];
3658                 status += MXL_RegRead(fe, RegNum[i], &RegVal[i]);
3659         }
3660
3661         return status;
3662 }
3663
3664 static u16 MXL_GetMasterControl(u8 *MasterReg, int state)
3665 {
3666         if (state == 1) /* Load_Start */
3667                 *MasterReg = 0xF3;
3668         if (state == 2) /* Power_Down */
3669                 *MasterReg = 0x41;
3670         if (state == 3) /* Synth_Reset */
3671                 *MasterReg = 0xB1;
3672         if (state == 4) /* Seq_Off */
3673                 *MasterReg = 0xF1;
3674
3675         return 0;
3676 }
3677
3678 #ifdef _MXL_PRODUCTION
3679 static u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range)
3680 {
3681         struct mxl5005s_state *state = fe->tuner_priv;
3682         u16 status = 0 ;
3683
3684         if (VCO_Range == 1) {
3685                 status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1);
3686                 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
3687                 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
3688                 status += MXL_ControlWrite(fe, RFSYN_DIVM, 1);
3689                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
3690                 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
3691                 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
3692                 if (state->Mode == 0 && state->IF_Mode == 1) {
3693                         /* Analog Low IF Mode */
3694                         status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
3695                         status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
3696                         status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56);
3697                         status += MXL_ControlWrite(fe,
3698                                 CHCAL_FRAC_MOD_RF, 180224);
3699                 }
3700                 if (state->Mode == 0 && state->IF_Mode == 0) {
3701                         /* Analog Zero IF Mode */
3702                         status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
3703                         status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
3704                         status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56);
3705                         status += MXL_ControlWrite(fe,
3706                                 CHCAL_FRAC_MOD_RF, 222822);
3707                 }
3708                 if (state->Mode == 1) /* Digital Mode */ {
3709                         status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
3710                         status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
3711                         status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56);
3712                         status += MXL_ControlWrite(fe,
3713                                 CHCAL_FRAC_MOD_RF, 229376);
3714                 }
3715         }
3716
3717         if (VCO_Range == 2) {
3718                 status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1);
3719                 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
3720                 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
3721                 status += MXL_ControlWrite(fe, RFSYN_DIVM, 1);
3722                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
3723                 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
3724                 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
3725                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
3726                 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3727                 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41);
3728                 if (state->Mode == 0 && state->IF_Mode == 1) {
3729                         /* Analog Low IF Mode */
3730                         status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
3731                         status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3732                         status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
3733                         status += MXL_ControlWrite(fe,
3734                                 CHCAL_FRAC_MOD_RF, 206438);
3735                 }
3736                 if (state->Mode == 0 && state->IF_Mode == 0) {
3737                         /* Analog Zero IF Mode */
3738                         status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
3739                         status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3740                         status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
3741                         status += MXL_ControlWrite(fe,
3742                                 CHCAL_FRAC_MOD_RF, 206438);
3743                 }
3744                 if (state->Mode == 1) /* Digital Mode */ {
3745                         status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
3746                         status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3747                         status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41);
3748                         status += MXL_ControlWrite(fe,
3749                                 CHCAL_FRAC_MOD_RF, 16384);
3750                 }
3751         }
3752
3753         if (VCO_Range == 3) {
3754                 status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1);
3755                 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
3756                 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
3757                 status += MXL_ControlWrite(fe, RFSYN_DIVM, 1);
3758                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
3759                 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
3760                 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
3761                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3762                 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
3763                 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
3764                 if (state->Mode == 0 && state->IF_Mode == 1) {
3765                         /* Analog Low IF Mode */
3766                         status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3767                         status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
3768                         status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44);
3769                         status += MXL_ControlWrite(fe,
3770                                 CHCAL_FRAC_MOD_RF, 173670);
3771                 }
3772                 if (state->Mode == 0 && state->IF_Mode == 0) {
3773                         /* Analog Zero IF Mode */
3774                         status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3775                         status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
3776                         status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44);
3777                         status += MXL_ControlWrite(fe,
3778                                 CHCAL_FRAC_MOD_RF, 173670);
3779                 }
3780                 if (state->Mode == 1) /* Digital Mode */ {
3781                         status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3782                         status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
3783                         status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
3784                         status += MXL_ControlWrite(fe,
3785                                 CHCAL_FRAC_MOD_RF, 245760);
3786                 }
3787         }
3788
3789         if (VCO_Range == 4) {
3790                 status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1);
3791                 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
3792                 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
3793                 status += MXL_ControlWrite(fe, RFSYN_DIVM, 1);
3794                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
3795                 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
3796                 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
3797                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3798                 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3799                 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
3800                 if (state->Mode == 0 && state->IF_Mode == 1) {
3801                         /* Analog Low IF Mode */
3802                         status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3803                         status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3804                         status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
3805                         status += MXL_ControlWrite(fe,
3806                                 CHCAL_FRAC_MOD_RF, 206438);
3807                 }
3808                 if (state->Mode == 0 && state->IF_Mode == 0) {
3809                         /* Analog Zero IF Mode */
3810                         status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3811                         status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3812                         status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
3813                         status += MXL_ControlWrite(fe,
3814                                 CHCAL_FRAC_MOD_RF, 206438);
3815                 }
3816                 if (state->Mode == 1) /* Digital Mode */ {
3817                         status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3818                         status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3819                         status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
3820                         status += MXL_ControlWrite(fe,
3821                                 CHCAL_FRAC_MOD_RF, 212992);
3822                 }
3823         }
3824
3825         return status;
3826 }
3827
3828 static u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis)
3829 {
3830         struct mxl5005s_state *state = fe->tuner_priv;
3831         u16 status = 0;
3832
3833         if (Hystersis == 1)
3834                 status += MXL_ControlWrite(fe, DN_BYPASS_AGC_I2C, 1);
3835
3836         return status;
3837 }
3838 #endif
3839 /* End: Reference driver code found in the Realtek driver that
3840  * is copyright MaxLinear */
3841
3842 /* ----------------------------------------------------------------
3843  * Begin: Everything after here is new code to adapt the
3844  * proprietary Realtek driver into a Linux API tuner.
3845  * Copyright (C) 2008 Steven Toth <stoth@linuxtv.org>
3846  */
3847 static int mxl5005s_reset(struct dvb_frontend *fe)
3848 {
3849         struct mxl5005s_state *state = fe->tuner_priv;
3850         int ret = 0;
3851
3852         u8 buf[2] = { 0xff, 0x00 };
3853         struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0,
3854                                .buf = buf, .len = 2 };
3855
3856         dprintk(2, "%s()\n", __func__);
3857
3858         if (fe->ops.i2c_gate_ctrl)
3859                 fe->ops.i2c_gate_ctrl(fe, 1);
3860
3861         if (i2c_transfer(state->i2c, &msg, 1) != 1) {
3862                 printk(KERN_WARNING "mxl5005s I2C reset failed\n");
3863                 ret = -EREMOTEIO;
3864         }
3865
3866         if (fe->ops.i2c_gate_ctrl)
3867                 fe->ops.i2c_gate_ctrl(fe, 0);
3868
3869         return ret;
3870 }
3871
3872 /* Write a single byte to a single reg, latch the value if required by
3873  * following the transaction with the latch byte.
3874  */
3875 static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val, int latch)
3876 {
3877         struct mxl5005s_state *state = fe->tuner_priv;
3878         u8 buf[3] = { reg, val, MXL5005S_LATCH_BYTE };
3879         struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0,
3880                                .buf = buf, .len = 3 };
3881
3882         if (latch == 0)
3883                 msg.len = 2;
3884
3885         dprintk(2, "%s(0x%x, 0x%x, 0x%x)\n", __func__, reg, val, msg.addr);
3886
3887         if (i2c_transfer(state->i2c, &msg, 1) != 1) {
3888                 printk(KERN_WARNING "mxl5005s I2C write failed\n");
3889                 return -EREMOTEIO;
3890         }
3891         return 0;
3892 }
3893
3894 static int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable,
3895         u8 *datatable, u8 len)
3896 {
3897         int ret = 0, i;
3898
3899         if (fe->ops.i2c_gate_ctrl)
3900                 fe->ops.i2c_gate_ctrl(fe, 1);
3901
3902         for (i = 0 ; i < len-1; i++) {
3903                 ret = mxl5005s_writereg(fe, addrtable[i], datatable[i], 0);
3904                 if (ret < 0)
3905                         break;
3906         }
3907
3908         ret = mxl5005s_writereg(fe, addrtable[i], datatable[i], 1);
3909
3910         if (fe->ops.i2c_gate_ctrl)
3911                 fe->ops.i2c_gate_ctrl(fe, 0);
3912
3913         return ret;
3914 }
3915
3916 static int mxl5005s_init(struct dvb_frontend *fe)
3917 {
3918         struct mxl5005s_state *state = fe->tuner_priv;
3919
3920         dprintk(1, "%s()\n", __func__);
3921         state->current_mode = MXL_QAM;
3922         return mxl5005s_reconfigure(fe, MXL_QAM, MXL5005S_BANDWIDTH_6MHZ);
3923 }
3924
3925 static int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type,
3926         u32 bandwidth)
3927 {
3928         struct mxl5005s_state *state = fe->tuner_priv;
3929
3930         u8 AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
3931         u8 ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
3932         int TableLen;
3933
3934         dprintk(1, "%s(type=%d, bw=%d)\n", __func__, mod_type, bandwidth);
3935
3936         mxl5005s_reset(fe);
3937
3938         /* Tuner initialization stage 0 */
3939         MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET);
3940         AddrTable[0] = MASTER_CONTROL_ADDR;
3941         ByteTable[0] |= state->config->AgcMasterByte;
3942
3943         mxl5005s_writeregs(fe, AddrTable, ByteTable, 1);
3944
3945         mxl5005s_AssignTunerMode(fe, mod_type, bandwidth);
3946
3947         /* Tuner initialization stage 1 */
3948         MXL_GetInitRegister(fe, AddrTable, ByteTable, &TableLen);
3949
3950         mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen);
3951
3952         return 0;
3953 }
3954
3955 static int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type,
3956         u32 bandwidth)
3957 {
3958         struct mxl5005s_state *state = fe->tuner_priv;
3959         struct mxl5005s_config *c = state->config;
3960
3961         InitTunerControls(fe);
3962
3963         /* Set MxL5005S parameters. */
3964         MXL5005_TunerConfig(
3965                 fe,
3966                 c->mod_mode,
3967                 c->if_mode,
3968                 bandwidth,
3969                 c->if_freq,
3970                 c->xtal_freq,
3971                 c->agc_mode,
3972                 c->top,
3973                 c->output_load,
3974                 c->clock_out,
3975                 c->div_out,
3976                 c->cap_select,
3977                 c->rssi_enable,
3978                 mod_type,
3979                 c->tracking_filter);
3980
3981         return 0;
3982 }
3983
3984 static int mxl5005s_set_params(struct dvb_frontend *fe,
3985                                struct dvb_frontend_parameters *params)
3986 {
3987         struct mxl5005s_state *state = fe->tuner_priv;
3988         u32 req_mode, req_bw = 0;
3989         int ret;
3990
3991         dprintk(1, "%s()\n", __func__);
3992
3993         if (fe->ops.info.type == FE_ATSC) {
3994                 switch (params->u.vsb.modulation) {
3995                 case VSB_8:
3996                         req_mode = MXL_ATSC; break;
3997                 default:
3998                 case QAM_64:
3999                 case QAM_256:
4000                 case QAM_AUTO:
4001                         req_mode = MXL_QAM; break;
4002                 }
4003         } else
4004                 req_mode = MXL_DVBT;
4005
4006         /* Change tuner for new modulation type if reqd */
4007         if (req_mode != state->current_mode) {
4008                 switch (req_mode) {
4009                 case MXL_ATSC:
4010                 case MXL_QAM:
4011                         req_bw  = MXL5005S_BANDWIDTH_6MHZ;
4012                         break;
4013                 case MXL_DVBT:
4014                 default:
4015                         /* Assume DVB-T */
4016                         switch (params->u.ofdm.bandwidth) {
4017                         case BANDWIDTH_6_MHZ:
4018                                 req_bw  = MXL5005S_BANDWIDTH_6MHZ;
4019                                 break;
4020                         case BANDWIDTH_7_MHZ:
4021                                 req_bw  = MXL5005S_BANDWIDTH_7MHZ;
4022                                 break;
4023                         case BANDWIDTH_AUTO:
4024                         case BANDWIDTH_8_MHZ:
4025                                 req_bw  = MXL5005S_BANDWIDTH_8MHZ;
4026                                 break;
4027                         }
4028                 }
4029
4030                 state->current_mode = req_mode;
4031                 ret = mxl5005s_reconfigure(fe, req_mode, req_bw);
4032
4033         } else
4034                 ret = 0;
4035
4036         if (ret == 0) {
4037                 dprintk(1, "%s() freq=%d\n", __func__, params->frequency);
4038                 ret = mxl5005s_SetRfFreqHz(fe, params->frequency);
4039         }
4040
4041         return ret;
4042 }
4043
4044 static int mxl5005s_get_frequency(struct dvb_frontend *fe, u32 *frequency)
4045 {
4046         struct mxl5005s_state *state = fe->tuner_priv;
4047         dprintk(1, "%s()\n", __func__);
4048
4049         *frequency = state->RF_IN;
4050
4051         return 0;
4052 }
4053
4054 static int mxl5005s_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
4055 {
4056         struct mxl5005s_state *state = fe->tuner_priv;
4057         dprintk(1, "%s()\n", __func__);
4058
4059         *bandwidth = state->Chan_Bandwidth;
4060
4061         return 0;
4062 }
4063
4064 static int mxl5005s_release(struct dvb_frontend *fe)
4065 {
4066         dprintk(1, "%s()\n", __func__);
4067         kfree(fe->tuner_priv);
4068         fe->tuner_priv = NULL;
4069         return 0;
4070 }
4071
4072 static const struct dvb_tuner_ops mxl5005s_tuner_ops = {
4073         .info = {
4074                 .name           = "MaxLinear MXL5005S",
4075                 .frequency_min  =  48000000,
4076                 .frequency_max  = 860000000,
4077                 .frequency_step =     50000,
4078         },
4079
4080         .release       = mxl5005s_release,
4081         .init          = mxl5005s_init,
4082
4083         .set_params    = mxl5005s_set_params,
4084         .get_frequency = mxl5005s_get_frequency,
4085         .get_bandwidth = mxl5005s_get_bandwidth,
4086 };
4087
4088 struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe,
4089                                      struct i2c_adapter *i2c,
4090                                      struct mxl5005s_config *config)
4091 {
4092         struct mxl5005s_state *state = NULL;
4093         dprintk(1, "%s()\n", __func__);
4094
4095         state = kzalloc(sizeof(struct mxl5005s_state), GFP_KERNEL);
4096         if (state == NULL)
4097                 return NULL;
4098
4099         state->frontend = fe;
4100         state->config = config;
4101         state->i2c = i2c;
4102
4103         printk(KERN_INFO "MXL5005S: Attached at address 0x%02x\n",
4104                 config->i2c_address);
4105
4106         memcpy(&fe->ops.tuner_ops, &mxl5005s_tuner_ops,
4107                 sizeof(struct dvb_tuner_ops));
4108
4109         fe->tuner_priv = state;
4110         return fe;
4111 }
4112 EXPORT_SYMBOL(mxl5005s_attach);
4113
4114 MODULE_DESCRIPTION("MaxLinear MXL5005S silicon tuner driver");
4115 MODULE_AUTHOR("Steven Toth");
4116 MODULE_LICENSE("GPL");