drivers/isdn/hardware/mISDN/ipac.h

   1 /*
   2  *
   3  * ipac.h       Defines for the Infineon (former Siemens) ISDN
   4  *              chip series
   5  *
   6  * Author       Karsten Keil <keil@isdn4linux.de>
   7  *
   8  * Copyright 2009  by Karsten Keil <keil@isdn4linux.de>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22  *
  23  */
  24
  25 #include "iohelper.h"
  26
  27 struct isac_hw {
  28         struct dchannel         dch;
  29         u32                     type;
  30         u32                     off;            /* offset to isac regs */
  31         char                    *name;
  32         spinlock_t              *hwlock;        /* lock HW access */
  33         read_reg_func           *read_reg;
  34         write_reg_func          *write_reg;
  35         fifo_func               *read_fifo;
  36         fifo_func               *write_fifo;
  37         int                     (*monitor)(void *, u32, u8 *, int);
  38         void                    (*release)(struct isac_hw *);
  39         int                     (*init)(struct isac_hw *);
  40         int                     (*ctrl)(struct isac_hw *, u32, u_long);
  41         int                     (*open)(struct isac_hw *, struct channel_req *);
  42         u8                      *mon_tx;
  43         u8                      *mon_rx;
  44         int                     mon_txp;
  45         int                     mon_txc;
  46         int                     mon_rxp;
  47         struct arcofi_msg       *arcofi_list;
  48         struct timer_list       arcofitimer;
  49         wait_queue_head_t       arcofi_wait;
  50         u8                      arcofi_bc;
  51         u8                      arcofi_state;
  52         u8                      mocr;
  53         u8                      adf2;
  54         u8                      state;
  55 };
  56
  57 struct ipac_hw;
  58
  59 struct hscx_hw {
  60         struct bchannel         bch;
  61         struct ipac_hw          *ip;
  62         u8                      fifo_size;
  63         u8                      off;    /* offset to ICA or ICB */
  64         u8                      slot;
  65         char                    log[64];
  66 };
  67
  68 struct ipac_hw {
  69         struct isac_hw          isac;
  70         struct hscx_hw          hscx[2];
  71         char                    *name;
  72         void                    *hw;
  73         spinlock_t              *hwlock;        /* lock HW access */
  74         struct module           *owner;
  75         u32                     type;
  76         read_reg_func           *read_reg;
  77         write_reg_func          *write_reg;
  78         fifo_func               *read_fifo;
  79         fifo_func               *write_fifo;
  80         void                    (*release)(struct ipac_hw *);
  81         int                     (*init)(struct ipac_hw *);
  82         int                     (*ctrl)(struct ipac_hw *, u32, u_long);
  83         u8                      conf;
  84 };
  85
  86 #define IPAC_TYPE_ISAC          0x0010
  87 #define IPAC_TYPE_IPAC          0x0020
  88 #define IPAC_TYPE_ISACX         0x0040
  89 #define IPAC_TYPE_IPACX         0x0080
  90 #define IPAC_TYPE_HSCX          0x0100
  91
  92 #define ISAC_USE_ARCOFI         0x1000
  93
  94 /* Monitor functions */
  95 #define MONITOR_RX_0            0x1000
  96 #define MONITOR_RX_1            0x1001
  97 #define MONITOR_TX_0            0x2000
  98 #define MONITOR_TX_1            0x2001
  99
 100 /* All registers original Siemens Spec  */
 101 /* IPAC/ISAC registers */
 102 #define ISAC_MASK               0x20
 103 #define ISAC_ISTA               0x20
 104 #define ISAC_STAR               0x21
 105 #define ISAC_CMDR               0x21
 106 #define ISAC_EXIR               0x24
 107 #define ISAC_ADF2               0x39
 108 #define ISAC_SPCR               0x30
 109 #define ISAC_ADF1               0x38
 110 #define ISAC_CIR0               0x31
 111 #define ISAC_CIX0               0x31
 112 #define ISAC_CIR1               0x33
 113 #define ISAC_CIX1               0x33
 114 #define ISAC_STCR               0x37
 115 #define ISAC_MODE               0x22
 116 #define ISAC_RSTA               0x27
 117 #define ISAC_RBCL               0x25
 118 #define ISAC_RBCH               0x2A
 119 #define ISAC_TIMR               0x23
 120 #define ISAC_SQXR               0x3b
 121 #define ISAC_SQRR               0x3b
 122 #define ISAC_MOSR               0x3a
 123 #define ISAC_MOCR               0x3a
 124 #define ISAC_MOR0               0x32
 125 #define ISAC_MOX0               0x32
 126 #define ISAC_MOR1               0x34
 127 #define ISAC_MOX1               0x34
 128
 129 #define ISAC_RBCH_XAC           0x80
 130
 131 #define IPAC_D_TIN2             0x01
 132
 133 /* IPAC/HSCX */
 134 #define IPAC_ISTAB              0x20    /* RD   */
 135 #define IPAC_MASKB              0x20    /* WR   */
 136 #define IPAC_STARB              0x21    /* RD   */
 137 #define IPAC_CMDRB              0x21    /* WR   */
 138 #define IPAC_MODEB              0x22    /* R/W  */
 139 #define IPAC_EXIRB              0x24    /* RD   */
 140 #define IPAC_RBCLB              0x25    /* RD   */
 141 #define IPAC_RAH1               0x26    /* WR   */
 142 #define IPAC_RAH2               0x27    /* WR   */
 143 #define IPAC_RSTAB              0x27    /* RD   */
 144 #define IPAC_RAL1               0x28    /* R/W  */
 145 #define IPAC_RAL2               0x29    /* WR   */
 146 #define IPAC_RHCRB              0x29    /* RD   */
 147 #define IPAC_XBCL               0x2A    /* WR   */
 148 #define IPAC_CCR2               0x2C    /* R/W  */
 149 #define IPAC_RBCHB              0x2D    /* RD   */
 150 #define IPAC_XBCH               0x2D    /* WR   */
 151 #define HSCX_VSTR               0x2E    /* RD   */
 152 #define IPAC_RLCR               0x2E    /* WR   */
 153 #define IPAC_CCR1               0x2F    /* R/W  */
 154 #define IPAC_TSAX               0x30    /* WR   */
 155 #define IPAC_TSAR               0x31    /* WR   */
 156 #define IPAC_XCCR               0x32    /* WR   */
 157 #define IPAC_RCCR               0x33    /* WR   */
 158
 159 /* IPAC_ISTAB/IPAC_MASKB bits */
 160 #define IPAC_B_XPR              0x10
 161 #define IPAC_B_RPF              0x40
 162 #define IPAC_B_RME              0x80
 163 #define IPAC_B_ON               0x2F
 164
 165 /* IPAC_EXIRB bits */
 166 #define IPAC_B_RFS              0x04
 167 #define IPAC_B_RFO              0x10
 168 #define IPAC_B_XDU              0x40
 169 #define IPAC_B_XMR              0x80
 170
 171 /* IPAC special registers */
 172 #define IPAC_CONF               0xC0    /* R/W  */
 173 #define IPAC_ISTA               0xC1    /* RD   */
 174 #define IPAC_MASK               0xC1    /* WR   */
 175 #define IPAC_ID                 0xC2    /* RD   */
 176 #define IPAC_ACFG               0xC3    /* R/W  */
 177 #define IPAC_AOE                0xC4    /* R/W  */
 178 #define IPAC_ARX                0xC5    /* RD   */
 179 #define IPAC_ATX                0xC5    /* WR   */
 180 #define IPAC_PITA1              0xC6    /* R/W  */
 181 #define IPAC_PITA2              0xC7    /* R/W  */
 182 #define IPAC_POTA1              0xC8    /* R/W  */
 183 #define IPAC_POTA2              0xC9    /* R/W  */
 184 #define IPAC_PCFG               0xCA    /* R/W  */
 185 #define IPAC_SCFG               0xCB    /* R/W  */
 186 #define IPAC_TIMR2              0xCC    /* R/W  */
 187
 188 /* IPAC_ISTA/_MASK bits */
 189 #define IPAC__EXB               0x01
 190 #define IPAC__ICB               0x02
 191 #define IPAC__EXA               0x04
 192 #define IPAC__ICA               0x08
 193 #define IPAC__EXD               0x10
 194 #define IPAC__ICD               0x20
 195 #define IPAC__INT0              0x40
 196 #define IPAC__INT1              0x80
 197 #define IPAC__ON                0xC0
 198
 199 /* HSCX ISTA/MASK bits */
 200 #define HSCX__EXB               0x01
 201 #define HSCX__EXA               0x02
 202 #define HSCX__ICA               0x04
 203
 204 /* ISAC/ISACX/IPAC/IPACX L1 commands */
 205 #define ISAC_CMD_TIM            0x0
 206 #define ISAC_CMD_RS             0x1
 207 #define ISAC_CMD_SCZ            0x4
 208 #define ISAC_CMD_SSZ            0x2
 209 #define ISAC_CMD_AR8            0x8
 210 #define ISAC_CMD_AR10           0x9
 211 #define ISAC_CMD_ARL            0xA
 212 #define ISAC_CMD_DUI            0xF
 213
 214 /* ISAC/ISACX/IPAC/IPACX L1 indications */
 215 #define ISAC_IND_RS             0x1
 216 #define ISAC_IND_PU             0x7
 217 #define ISAC_IND_DR             0x0
 218 #define ISAC_IND_SD             0x2
 219 #define ISAC_IND_DIS            0x3
 220 #define ISAC_IND_EI             0x6
 221 #define ISAC_IND_RSY            0x4
 222 #define ISAC_IND_ARD            0x8
 223 #define ISAC_IND_TI             0xA
 224 #define ISAC_IND_ATI            0xB
 225 #define ISAC_IND_AI8            0xC
 226 #define ISAC_IND_AI10           0xD
 227 #define ISAC_IND_DID            0xF
 228
 229 /* the new ISACX / IPACX */
 230 /* D-channel registers   */
 231 #define ISACX_RFIFOD            0x00    /* RD   */
 232 #define ISACX_XFIFOD            0x00    /* WR   */
 233 #define ISACX_ISTAD             0x20    /* RD   */
 234 #define ISACX_MASKD             0x20    /* WR   */
 235 #define ISACX_STARD             0x21    /* RD   */
 236 #define ISACX_CMDRD             0x21    /* WR   */
 237 #define ISACX_MODED             0x22    /* R/W  */
 238 #define ISACX_EXMD1             0x23    /* R/W  */
 239 #define ISACX_TIMR1             0x24    /* R/W  */
 240 #define ISACX_SAP1              0x25    /* WR   */
 241 #define ISACX_SAP2              0x26    /* WR   */
 242 #define ISACX_RBCLD             0x26    /* RD   */
 243 #define ISACX_RBCHD             0x27    /* RD   */
 244 #define ISACX_TEI1              0x27    /* WR   */
 245 #define ISACX_TEI2              0x28    /* WR   */
 246 #define ISACX_RSTAD             0x28    /* RD   */
 247 #define ISACX_TMD               0x29    /* R/W  */
 248 #define ISACX_CIR0              0x2E    /* RD   */
 249 #define ISACX_CIX0              0x2E    /* WR   */
 250 #define ISACX_CIR1              0x2F    /* RD   */
 251 #define ISACX_CIX1              0x2F    /* WR   */
 252
 253 /* Transceiver registers  */
 254 #define ISACX_TR_CONF0          0x30    /* R/W  */
 255 #define ISACX_TR_CONF1          0x31    /* R/W  */
 256 #define ISACX_TR_CONF2          0x32    /* R/W  */
 257 #define ISACX_TR_STA            0x33    /* RD   */
 258 #define ISACX_TR_CMD            0x34    /* R/W  */
 259 #define ISACX_SQRR1             0x35    /* RD   */
 260 #define ISACX_SQXR1             0x35    /* WR   */
 261 #define ISACX_SQRR2             0x36    /* RD   */
 262 #define ISACX_SQXR2             0x36    /* WR   */
 263 #define ISACX_SQRR3             0x37    /* RD   */
 264 #define ISACX_SQXR3             0x37    /* WR   */
 265 #define ISACX_ISTATR            0x38    /* RD   */
 266 #define ISACX_MASKTR            0x39    /* R/W  */
 267 #define ISACX_TR_MODE           0x3A    /* R/W  */
 268 #define ISACX_ACFG1             0x3C    /* R/W  */
 269 #define ISACX_ACFG2             0x3D    /* R/W  */
 270 #define ISACX_AOE               0x3E    /* R/W  */
 271 #define ISACX_ARX               0x3F    /* RD   */
 272 #define ISACX_ATX               0x3F    /* WR   */
 273
 274 /* IOM: Timeslot, DPS, CDA  */
 275 #define ISACX_CDA10             0x40    /* R/W  */
 276 #define ISACX_CDA11             0x41    /* R/W  */
 277 #define ISACX_CDA20             0x42    /* R/W  */
 278 #define ISACX_CDA21             0x43    /* R/W  */
 279 #define ISACX_CDA_TSDP10        0x44    /* R/W  */
 280 #define ISACX_CDA_TSDP11        0x45    /* R/W  */
 281 #define ISACX_CDA_TSDP20        0x46    /* R/W  */
 282 #define ISACX_CDA_TSDP21        0x47    /* R/W  */
 283 #define ISACX_BCHA_TSDP_BC1     0x48    /* R/W  */
 284 #define ISACX_BCHA_TSDP_BC2     0x49    /* R/W  */
 285 #define ISACX_BCHB_TSDP_BC1     0x4A    /* R/W  */
 286 #define ISACX_BCHB_TSDP_BC2     0x4B    /* R/W  */
 287 #define ISACX_TR_TSDP_BC1       0x4C    /* R/W  */
 288 #define ISACX_TR_TSDP_BC2       0x4D    /* R/W  */
 289 #define ISACX_CDA1_CR           0x4E    /* R/W  */
 290 #define ISACX_CDA2_CR           0x4F    /* R/W  */
 291
 292 /* IOM: Contol, Sync transfer, Monitor    */
 293 #define ISACX_TR_CR             0x50    /* R/W  */
 294 #define ISACX_TRC_CR            0x50    /* R/W  */
 295 #define ISACX_BCHA_CR           0x51    /* R/W  */
 296 #define ISACX_BCHB_CR           0x52    /* R/W  */
 297 #define ISACX_DCI_CR            0x53    /* R/W  */
 298 #define ISACX_DCIC_CR           0x53    /* R/W  */
 299 #define ISACX_MON_CR            0x54    /* R/W  */
 300 #define ISACX_SDS1_CR           0x55    /* R/W  */
 301 #define ISACX_SDS2_CR           0x56    /* R/W  */
 302 #define ISACX_IOM_CR            0x57    /* R/W  */
 303 #define ISACX_STI               0x58    /* RD   */
 304 #define ISACX_ASTI              0x58    /* WR   */
 305 #define ISACX_MSTI              0x59    /* R/W  */
 306 #define ISACX_SDS_CONF          0x5A    /* R/W  */
 307 #define ISACX_MCDA              0x5B    /* RD   */
 308 #define ISACX_MOR               0x5C    /* RD   */
 309 #define ISACX_MOX               0x5C    /* WR   */
 310 #define ISACX_MOSR              0x5D    /* RD   */
 311 #define ISACX_MOCR              0x5E    /* R/W  */
 312 #define ISACX_MSTA              0x5F    /* RD   */
 313 #define ISACX_MCONF             0x5F    /* WR   */
 314
 315 /* Interrupt and general registers */
 316 #define ISACX_ISTA              0x60    /* RD   */
 317 #define ISACX_MASK              0x60    /* WR   */
 318 #define ISACX_AUXI              0x61    /* RD   */
 319 #define ISACX_AUXM              0x61    /* WR   */
 320 #define ISACX_MODE1             0x62    /* R/W  */
 321 #define ISACX_MODE2             0x63    /* R/W  */
 322 #define ISACX_ID                0x64    /* RD   */
 323 #define ISACX_SRES              0x64    /* WR   */
 324 #define ISACX_TIMR2             0x65    /* R/W  */
 325
 326 /* Register Bits */
 327 /* ISACX/IPACX _ISTAD (R) and _MASKD (W) */
 328 #define ISACX_D_XDU             0x04
 329 #define ISACX_D_XMR             0x08
 330 #define ISACX_D_XPR             0x10
 331 #define ISACX_D_RFO             0x20
 332 #define ISACX_D_RPF             0x40
 333 #define ISACX_D_RME             0x80
 334
 335 /* ISACX/IPACX _ISTA (R) and _MASK (W) */
 336 #define ISACX__ICD              0x01
 337 #define ISACX__MOS              0x02
 338 #define ISACX__TRAN             0x04
 339 #define ISACX__AUX              0x08
 340 #define ISACX__CIC              0x10
 341 #define ISACX__ST               0x20
 342 #define IPACX__ICB              0x40
 343 #define IPACX__ICA              0x80
 344 #define IPACX__ON               0x2C
 345
 346 /* ISACX/IPACX _CMDRD (W) */
 347 #define ISACX_CMDRD_XRES        0x01
 348 #define ISACX_CMDRD_XME         0x02
 349 #define ISACX_CMDRD_XTF         0x08
 350 #define ISACX_CMDRD_STI         0x10
 351 #define ISACX_CMDRD_RRES        0x40
 352 #define ISACX_CMDRD_RMC         0x80
 353
 354 /* ISACX/IPACX _RSTAD (R) */
 355 #define ISACX_RSTAD_TA          0x01
 356 #define ISACX_RSTAD_CR          0x02
 357 #define ISACX_RSTAD_SA0         0x04
 358 #define ISACX_RSTAD_SA1         0x08
 359 #define ISACX_RSTAD_RAB         0x10
 360 #define ISACX_RSTAD_CRC         0x20
 361 #define ISACX_RSTAD_RDO         0x40
 362 #define ISACX_RSTAD_VFR         0x80
 363
 364 /* ISACX/IPACX _CIR0 (R) */
 365 #define ISACX_CIR0_BAS          0x01
 366 #define ISACX_CIR0_SG           0x08
 367 #define ISACX_CIR0_CIC1         0x08
 368 #define ISACX_CIR0_CIC0         0x08
 369
 370 /* B-channel registers */
 371 #define IPACX_OFF_ICA           0x70
 372 #define IPACX_OFF_ICB           0x80
 373
 374 /* ICA: IPACX_OFF_ICA + Reg ICB: IPACX_OFF_ICB + Reg */
 375
 376 #define IPACX_ISTAB             0x00    /* RD   */
 377 #define IPACX_MASKB             0x00    /* WR   */
 378 #define IPACX_STARB             0x01    /* RD   */
 379 #define IPACX_CMDRB             0x01    /* WR   */
 380 #define IPACX_MODEB             0x02    /* R/W  */
 381 #define IPACX_EXMB              0x03    /* R/W  */
 382 #define IPACX_RAH1              0x05    /* WR   */
 383 #define IPACX_RAH2              0x06    /* WR   */
 384 #define IPACX_RBCLB             0x06    /* RD   */
 385 #define IPACX_RBCHB             0x07    /* RD   */
 386 #define IPACX_RAL1              0x07    /* WR   */
 387 #define IPACX_RAL2              0x08    /* WR   */
 388 #define IPACX_RSTAB             0x08    /* RD   */
 389 #define IPACX_TMB               0x09    /* R/W  */
 390 #define IPACX_RFIFOB            0x0A    /* RD   */
 391 #define IPACX_XFIFOB            0x0A    /* WR   */
 392
 393 /* IPACX_ISTAB / IPACX_MASKB bits */
 394 #define IPACX_B_XDU             0x04
 395 #define IPACX_B_XPR             0x10
 396 #define IPACX_B_RFO             0x20
 397 #define IPACX_B_RPF             0x40
 398 #define IPACX_B_RME             0x80
 399
 400 #define IPACX_B_ON              0x0B
 401
 402 extern int mISDNisac_init(struct isac_hw *, void *);
 403 extern irqreturn_t mISDNisac_irq(struct isac_hw *, u8);
 404 extern u32 mISDNipac_init(struct ipac_hw *, void *);
 405 extern irqreturn_t mISDNipac_irq(struct ipac_hw *, int);