drivers/isdn/hardware/mISDN/hfcpci.c

   1 /*
   2  *
   3  * hfcpci.c     low level driver for CCD's hfc-pci based cards
   4  *
   5  * Author     Werner Cornelius (werner@isdn4linux.de)
   6  *            based on existing driver for CCD hfc ISA cards
   7  *            type approval valid for HFC-S PCI A based card
   8  *
   9  * Copyright 1999  by Werner Cornelius (werner@isdn-development.de)
  10  * Copyright 2008  by Karsten Keil <kkeil@novell.com>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2, or (at your option)
  15  * any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25  *
  26  * Module options:
  27  *
  28  * debug:
  29  *      NOTE: only one poll value must be given for all cards
  30  *      See hfc_pci.h for debug flags.
  31  *
  32  * poll:
  33  *      NOTE: only one poll value must be given for all cards
  34  *      Give the number of samples for each fifo process.
  35  *      By default 128 is used. Decrease to reduce delay, increase to
  36  *      reduce cpu load. If unsure, don't mess with it!
  37  *      A value of 128 will use controller's interrupt. Other values will
  38  *      use kernel timer, because the controller will not allow lower values
  39  *      than 128.
  40  *      Also note that the value depends on the kernel timer frequency.
  41  *      If kernel uses a frequency of 1000 Hz, steps of 8 samples are possible.
  42  *      If the kernel uses 100 Hz, steps of 80 samples are possible.
  43  *      If the kernel uses 300 Hz, steps of about 26 samples are possible.
  44  *
  45  */
  46
  47 #include <linux/module.h>
  48 #include <linux/pci.h>
  49 #include <linux/delay.h>
  50 #include <linux/mISDNhw.h>
  51 #include <linux/slab.h>
  52
  53 #include "hfc_pci.h"
  54
  55 static const char *hfcpci_revision = "2.0";
  56
  57 static int HFC_cnt;
  58 static uint debug;
  59 static uint poll, tics;
  60 static struct timer_list hfc_tl;
  61 static unsigned long hfc_jiffies;
  62
  63 MODULE_AUTHOR("Karsten Keil");
  64 MODULE_LICENSE("GPL");
  65 module_param(debug, uint, S_IRUGO | S_IWUSR);
  66 module_param(poll, uint, S_IRUGO | S_IWUSR);
  67
  68 enum {
  69         HFC_CCD_2BD0,
  70         HFC_CCD_B000,
  71         HFC_CCD_B006,
  72         HFC_CCD_B007,
  73         HFC_CCD_B008,
  74         HFC_CCD_B009,
  75         HFC_CCD_B00A,
  76         HFC_CCD_B00B,
  77         HFC_CCD_B00C,
  78         HFC_CCD_B100,
  79         HFC_CCD_B700,
  80         HFC_CCD_B701,
  81         HFC_ASUS_0675,
  82         HFC_BERKOM_A1T,
  83         HFC_BERKOM_TCONCEPT,
  84         HFC_ANIGMA_MC145575,
  85         HFC_ZOLTRIX_2BD0,
  86         HFC_DIGI_DF_M_IOM2_E,
  87         HFC_DIGI_DF_M_E,
  88         HFC_DIGI_DF_M_IOM2_A,
  89         HFC_DIGI_DF_M_A,
  90         HFC_ABOCOM_2BD1,
  91         HFC_SITECOM_DC105V2,
  92 };
  93
  94 struct hfcPCI_hw {
  95         unsigned char           cirm;
  96         unsigned char           ctmt;
  97         unsigned char           clkdel;
  98         unsigned char           states;
  99         unsigned char           conn;
 100         unsigned char           mst_m;
 101         unsigned char           int_m1;
 102         unsigned char           int_m2;
 103         unsigned char           sctrl;
 104         unsigned char           sctrl_r;
 105         unsigned char           sctrl_e;
 106         unsigned char           trm;
 107         unsigned char           fifo_en;
 108         unsigned char           bswapped;
 109         unsigned char           protocol;
 110         int                     nt_timer;
 111         unsigned char __iomem   *pci_io; /* start of PCI IO memory */
 112         dma_addr_t              dmahandle;
 113         void                    *fifos; /* FIFO memory */
 114         int                     last_bfifo_cnt[2];
 115             /* marker saving last b-fifo frame count */
 116         struct timer_list       timer;
 117 };
 118
 119 #define HFC_CFG_MASTER          1
 120 #define HFC_CFG_SLAVE           2
 121 #define HFC_CFG_PCM             3
 122 #define HFC_CFG_2HFC            4
 123 #define HFC_CFG_SLAVEHFC        5
 124 #define HFC_CFG_NEG_F0          6
 125 #define HFC_CFG_SW_DD_DU        7
 126
 127 #define FLG_HFC_TIMER_T1        16
 128 #define FLG_HFC_TIMER_T3        17
 129
 130 #define NT_T1_COUNT     1120    /* number of 3.125ms interrupts (3.5s) */
 131 #define NT_T3_COUNT     31      /* number of 3.125ms interrupts (97 ms) */
 132 #define CLKDEL_TE       0x0e    /* CLKDEL in TE mode */
 133 #define CLKDEL_NT       0x6c    /* CLKDEL in NT mode */
 134
 135
 136 struct hfc_pci {
 137         u_char                  subtype;
 138         u_char                  chanlimit;
 139         u_char                  initdone;
 140         u_long                  cfg;
 141         u_int                   irq;
 142         u_int                   irqcnt;
 143         struct pci_dev          *pdev;
 144         struct hfcPCI_hw        hw;
 145         spinlock_t              lock;   /* card lock */
 146         struct dchannel         dch;
 147         struct bchannel         bch[2];
 148 };
 149
 150 /* Interface functions */
 151 static void
 152 enable_hwirq(struct hfc_pci *hc)
 153 {
 154         hc->hw.int_m2 |= HFCPCI_IRQ_ENABLE;
 155         Write_hfc(hc, HFCPCI_INT_M2, hc->hw.int_m2);
 156 }
 157
 158 static void
 159 disable_hwirq(struct hfc_pci *hc)
 160 {
 161         hc->hw.int_m2 &= ~((u_char)HFCPCI_IRQ_ENABLE);
 162         Write_hfc(hc, HFCPCI_INT_M2, hc->hw.int_m2);
 163 }
 164
 165 /*
 166  * free hardware resources used by driver
 167  */
 168 static void
 169 release_io_hfcpci(struct hfc_pci *hc)
 170 {
 171         /* disable memory mapped ports + busmaster */
 172         pci_write_config_word(hc->pdev, PCI_COMMAND, 0);
 173         del_timer(&hc->hw.timer);
 174         pci_free_consistent(hc->pdev, 0x8000, hc->hw.fifos, hc->hw.dmahandle);
 175         iounmap(hc->hw.pci_io);
 176 }
 177
 178 /*
 179  * set mode (NT or TE)
 180  */
 181 static void
 182 hfcpci_setmode(struct hfc_pci *hc)
 183 {
 184         if (hc->hw.protocol == ISDN_P_NT_S0) {
 185                 hc->hw.clkdel = CLKDEL_NT;      /* ST-Bit delay for NT-Mode */
 186                 hc->hw.sctrl |= SCTRL_MODE_NT;  /* NT-MODE */
 187                 hc->hw.states = 1;              /* G1 */
 188         } else {
 189                 hc->hw.clkdel = CLKDEL_TE;      /* ST-Bit delay for TE-Mode */
 190                 hc->hw.sctrl &= ~SCTRL_MODE_NT; /* TE-MODE */
 191                 hc->hw.states = 2;              /* F2 */
 192         }
 193         Write_hfc(hc, HFCPCI_CLKDEL, hc->hw.clkdel);
 194         Write_hfc(hc, HFCPCI_STATES, HFCPCI_LOAD_STATE | hc->hw.states);
 195         udelay(10);
 196         Write_hfc(hc, HFCPCI_STATES, hc->hw.states | 0x40); /* Deactivate */
 197         Write_hfc(hc, HFCPCI_SCTRL, hc->hw.sctrl);
 198 }
 199
 200 /*
 201  * function called to reset the HFC PCI chip. A complete software reset of chip
 202  * and fifos is done.
 203  */
 204 static void
 205 reset_hfcpci(struct hfc_pci *hc)
 206 {
 207         u_char  val;
 208         int     cnt = 0;
 209
 210         printk(KERN_DEBUG "reset_hfcpci: entered\n");
 211         val = Read_hfc(hc, HFCPCI_CHIP_ID);
 212         printk(KERN_INFO "HFC_PCI: resetting HFC ChipId(%x)\n", val);
 213         /* enable memory mapped ports, disable busmaster */
 214         pci_write_config_word(hc->pdev, PCI_COMMAND, PCI_ENA_MEMIO);
 215         disable_hwirq(hc);
 216         /* enable memory ports + busmaster */
 217         pci_write_config_word(hc->pdev, PCI_COMMAND,
 218             PCI_ENA_MEMIO + PCI_ENA_MASTER);
 219         val = Read_hfc(hc, HFCPCI_STATUS);
 220         printk(KERN_DEBUG "HFC-PCI status(%x) before reset\n", val);
 221         hc->hw.cirm = HFCPCI_RESET;     /* Reset On */
 222         Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
 223         set_current_state(TASK_UNINTERRUPTIBLE);
 224         mdelay(10);                     /* Timeout 10ms */
 225         hc->hw.cirm = 0;                /* Reset Off */
 226         Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
 227         val = Read_hfc(hc, HFCPCI_STATUS);
 228         printk(KERN_DEBUG "HFC-PCI status(%x) after reset\n", val);
 229         while (cnt < 50000) { /* max 50000 us */
 230                 udelay(5);
 231                 cnt += 5;
 232                 val = Read_hfc(hc, HFCPCI_STATUS);
 233                 if (!(val & 2))
 234                         break;
 235         }
 236         printk(KERN_DEBUG "HFC-PCI status(%x) after %dus\n", val, cnt);
 237
 238         hc->hw.fifo_en = 0x30;  /* only D fifos enabled */
 239
 240         hc->hw.bswapped = 0;    /* no exchange */
 241         hc->hw.ctmt = HFCPCI_TIM3_125 | HFCPCI_AUTO_TIMER;
 242         hc->hw.trm = HFCPCI_BTRANS_THRESMASK; /* no echo connect , threshold */
 243         hc->hw.sctrl = 0x40;    /* set tx_lo mode, error in datasheet ! */
 244         hc->hw.sctrl_r = 0;
 245         hc->hw.sctrl_e = HFCPCI_AUTO_AWAKE;     /* S/T Auto awake */
 246         hc->hw.mst_m = 0;
 247         if (test_bit(HFC_CFG_MASTER, &hc->cfg))
 248                 hc->hw.mst_m |= HFCPCI_MASTER;  /* HFC Master Mode */
 249         if (test_bit(HFC_CFG_NEG_F0, &hc->cfg))
 250                 hc->hw.mst_m |= HFCPCI_F0_NEGATIV;
 251         Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
 252         Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
 253         Write_hfc(hc, HFCPCI_SCTRL_E, hc->hw.sctrl_e);
 254         Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
 255
 256         hc->hw.int_m1 = HFCPCI_INTS_DTRANS | HFCPCI_INTS_DREC |
 257             HFCPCI_INTS_L1STATE | HFCPCI_INTS_TIMER;
 258         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
 259
 260         /* Clear already pending ints */
 261         val = Read_hfc(hc, HFCPCI_INT_S1);
 262
 263         /* set NT/TE mode */
 264         hfcpci_setmode(hc);
 265
 266         Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
 267         Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
 268
 269         /*
 270          * Init GCI/IOM2 in master mode
 271          * Slots 0 and 1 are set for B-chan 1 and 2
 272          * D- and monitor/CI channel are not enabled
 273          * STIO1 is used as output for data, B1+B2 from ST->IOM+HFC
 274          * STIO2 is used as data input, B1+B2 from IOM->ST
 275          * ST B-channel send disabled -> continuous 1s
 276          * The IOM slots are always enabled
 277          */
 278         if (test_bit(HFC_CFG_PCM, &hc->cfg)) {
 279                 /* set data flow directions: connect B1,B2: HFC to/from PCM */
 280                 hc->hw.conn = 0x09;
 281         } else {
 282                 hc->hw.conn = 0x36;     /* set data flow directions */
 283                 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg)) {
 284                         Write_hfc(hc, HFCPCI_B1_SSL, 0xC0);
 285                         Write_hfc(hc, HFCPCI_B2_SSL, 0xC1);
 286                         Write_hfc(hc, HFCPCI_B1_RSL, 0xC0);
 287                         Write_hfc(hc, HFCPCI_B2_RSL, 0xC1);
 288                 } else {
 289                         Write_hfc(hc, HFCPCI_B1_SSL, 0x80);
 290                         Write_hfc(hc, HFCPCI_B2_SSL, 0x81);
 291                         Write_hfc(hc, HFCPCI_B1_RSL, 0x80);
 292                         Write_hfc(hc, HFCPCI_B2_RSL, 0x81);
 293                 }
 294         }
 295         Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
 296         val = Read_hfc(hc, HFCPCI_INT_S2);
 297 }
 298
 299 /*
 300  * Timer function called when kernel timer expires
 301  */
 302 static void
 303 hfcpci_Timer(struct hfc_pci *hc)
 304 {
 305         hc->hw.timer.expires = jiffies + 75;
 306         /* WD RESET */
 307 /*
 308  *      WriteReg(hc, HFCD_DATA, HFCD_CTMT, hc->hw.ctmt | 0x80);
 309  *      add_timer(&hc->hw.timer);
 310  */
 311 }
 312
 313
 314 /*
 315  * select a b-channel entry matching and active
 316  */
 317 static struct bchannel *
 318 Sel_BCS(struct hfc_pci *hc, int channel)
 319 {
 320         if (test_bit(FLG_ACTIVE, &hc->bch[0].Flags) &&
 321                 (hc->bch[0].nr & channel))
 322                 return &hc->bch[0];
 323         else if (test_bit(FLG_ACTIVE, &hc->bch[1].Flags) &&
 324                 (hc->bch[1].nr & channel))
 325                 return &hc->bch[1];
 326         else
 327                 return NULL;
 328 }
 329
 330 /*
 331  * clear the desired B-channel rx fifo
 332  */
 333 static void
 334 hfcpci_clear_fifo_rx(struct hfc_pci *hc, int fifo)
 335 {
 336         u_char          fifo_state;
 337         struct bzfifo   *bzr;
 338
 339         if (fifo) {
 340                 bzr = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b2;
 341                 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B2RX;
 342         } else {
 343                 bzr = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b1;
 344                 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B1RX;
 345         }
 346         if (fifo_state)
 347                 hc->hw.fifo_en ^= fifo_state;
 348         Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
 349         hc->hw.last_bfifo_cnt[fifo] = 0;
 350         bzr->f1 = MAX_B_FRAMES;
 351         bzr->f2 = bzr->f1;      /* init F pointers to remain constant */
 352         bzr->za[MAX_B_FRAMES].z1 = cpu_to_le16(B_FIFO_SIZE + B_SUB_VAL - 1);
 353         bzr->za[MAX_B_FRAMES].z2 = cpu_to_le16(
 354             le16_to_cpu(bzr->za[MAX_B_FRAMES].z1));
 355         if (fifo_state)
 356                 hc->hw.fifo_en |= fifo_state;
 357         Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
 358 }
 359
 360 /*
 361  * clear the desired B-channel tx fifo
 362  */
 363 static void hfcpci_clear_fifo_tx(struct hfc_pci *hc, int fifo)
 364 {
 365         u_char          fifo_state;
 366         struct bzfifo   *bzt;
 367
 368         if (fifo) {
 369                 bzt = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2;
 370                 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B2TX;
 371         } else {
 372                 bzt = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1;
 373                 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B1TX;
 374         }
 375         if (fifo_state)
 376                 hc->hw.fifo_en ^= fifo_state;
 377         Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
 378         if (hc->bch[fifo].debug & DEBUG_HW_BCHANNEL)
 379                 printk(KERN_DEBUG "hfcpci_clear_fifo_tx%d f1(%x) f2(%x) "
 380                     "z1(%x) z2(%x) state(%x)\n",
 381                     fifo, bzt->f1, bzt->f2,
 382                     le16_to_cpu(bzt->za[MAX_B_FRAMES].z1),
 383                     le16_to_cpu(bzt->za[MAX_B_FRAMES].z2),
 384                     fifo_state);
 385         bzt->f2 = MAX_B_FRAMES;
 386         bzt->f1 = bzt->f2;      /* init F pointers to remain constant */
 387         bzt->za[MAX_B_FRAMES].z1 = cpu_to_le16(B_FIFO_SIZE + B_SUB_VAL - 1);
 388         bzt->za[MAX_B_FRAMES].z2 = cpu_to_le16(B_FIFO_SIZE + B_SUB_VAL - 2);
 389         if (fifo_state)
 390                 hc->hw.fifo_en |= fifo_state;
 391         Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
 392         if (hc->bch[fifo].debug & DEBUG_HW_BCHANNEL)
 393                 printk(KERN_DEBUG
 394                     "hfcpci_clear_fifo_tx%d f1(%x) f2(%x) z1(%x) z2(%x)\n",
 395                     fifo, bzt->f1, bzt->f2,
 396                     le16_to_cpu(bzt->za[MAX_B_FRAMES].z1),
 397                     le16_to_cpu(bzt->za[MAX_B_FRAMES].z2));
 398 }
 399
 400 /*
 401  * read a complete B-frame out of the buffer
 402  */
 403 static void
 404 hfcpci_empty_bfifo(struct bchannel *bch, struct bzfifo *bz,
 405     u_char *bdata, int count)
 406 {
 407         u_char          *ptr, *ptr1, new_f2;
 408         int             total, maxlen, new_z2;
 409         struct zt       *zp;
 410
 411         if ((bch->debug & DEBUG_HW_BCHANNEL) && !(bch->debug & DEBUG_HW_BFIFO))
 412                 printk(KERN_DEBUG "hfcpci_empty_fifo\n");
 413         zp = &bz->za[bz->f2];   /* point to Z-Regs */
 414         new_z2 = le16_to_cpu(zp->z2) + count;   /* new position in fifo */
 415         if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
 416                 new_z2 -= B_FIFO_SIZE;  /* buffer wrap */
 417         new_f2 = (bz->f2 + 1) & MAX_B_FRAMES;
 418         if ((count > MAX_DATA_SIZE + 3) || (count < 4) ||
 419             (*(bdata + (le16_to_cpu(zp->z1) - B_SUB_VAL)))) {
 420                 if (bch->debug & DEBUG_HW)
 421                         printk(KERN_DEBUG "hfcpci_empty_fifo: incoming packet "
 422                             "invalid length %d or crc\n", count);
 423 #ifdef ERROR_STATISTIC
 424                 bch->err_inv++;
 425 #endif
 426                 bz->za[new_f2].z2 = cpu_to_le16(new_z2);
 427                 bz->f2 = new_f2;        /* next buffer */
 428         } else {
 429                 bch->rx_skb = mI_alloc_skb(count - 3, GFP_ATOMIC);
 430                 if (!bch->rx_skb) {
 431                         printk(KERN_WARNING "HFCPCI: receive out of memory\n");
 432                         return;
 433                 }
 434                 total = count;
 435                 count -= 3;
 436                 ptr = skb_put(bch->rx_skb, count);
 437
 438                 if (le16_to_cpu(zp->z2) + count <= B_FIFO_SIZE + B_SUB_VAL)
 439                         maxlen = count;         /* complete transfer */
 440                 else
 441                         maxlen = B_FIFO_SIZE + B_SUB_VAL -
 442                             le16_to_cpu(zp->z2);        /* maximum */
 443
 444                 ptr1 = bdata + (le16_to_cpu(zp->z2) - B_SUB_VAL);
 445                     /* start of data */
 446                 memcpy(ptr, ptr1, maxlen);      /* copy data */
 447                 count -= maxlen;
 448
 449                 if (count) {    /* rest remaining */
 450                         ptr += maxlen;
 451                         ptr1 = bdata;   /* start of buffer */
 452                         memcpy(ptr, ptr1, count);       /* rest */
 453                 }
 454                 bz->za[new_f2].z2 = cpu_to_le16(new_z2);
 455                 bz->f2 = new_f2;        /* next buffer */
 456                 recv_Bchannel(bch, MISDN_ID_ANY);
 457         }
 458 }
 459
 460 /*
 461  * D-channel receive procedure
 462  */
 463 static int
 464 receive_dmsg(struct hfc_pci *hc)
 465 {
 466         struct dchannel *dch = &hc->dch;
 467         int             maxlen;
 468         int             rcnt, total;
 469         int             count = 5;
 470         u_char          *ptr, *ptr1;
 471         struct dfifo    *df;
 472         struct zt       *zp;
 473
 474         df = &((union fifo_area *)(hc->hw.fifos))->d_chan.d_rx;
 475         while (((df->f1 & D_FREG_MASK) != (df->f2 & D_FREG_MASK)) && count--) {
 476                 zp = &df->za[df->f2 & D_FREG_MASK];
 477                 rcnt = le16_to_cpu(zp->z1) - le16_to_cpu(zp->z2);
 478                 if (rcnt < 0)
 479                         rcnt += D_FIFO_SIZE;
 480                 rcnt++;
 481                 if (dch->debug & DEBUG_HW_DCHANNEL)
 482                         printk(KERN_DEBUG
 483                             "hfcpci recd f1(%d) f2(%d) z1(%x) z2(%x) cnt(%d)\n",
 484                                 df->f1, df->f2,
 485                                 le16_to_cpu(zp->z1),
 486                                 le16_to_cpu(zp->z2),
 487                                 rcnt);
 488
 489                 if ((rcnt > MAX_DFRAME_LEN + 3) || (rcnt < 4) ||
 490                     (df->data[le16_to_cpu(zp->z1)])) {
 491                         if (dch->debug & DEBUG_HW)
 492                                 printk(KERN_DEBUG
 493                                     "empty_fifo hfcpci paket inv. len "
 494                                     "%d or crc %d\n",
 495                                     rcnt,
 496                                     df->data[le16_to_cpu(zp->z1)]);
 497 #ifdef ERROR_STATISTIC
 498                         cs->err_rx++;
 499 #endif
 500                         df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) |
 501                             (MAX_D_FRAMES + 1); /* next buffer */
 502                         df->za[df->f2 & D_FREG_MASK].z2 =
 503                             cpu_to_le16((le16_to_cpu(zp->z2) + rcnt) &
 504                             (D_FIFO_SIZE - 1));
 505                 } else {
 506                         dch->rx_skb = mI_alloc_skb(rcnt - 3, GFP_ATOMIC);
 507                         if (!dch->rx_skb) {
 508                                 printk(KERN_WARNING
 509                                     "HFC-PCI: D receive out of memory\n");
 510                                 break;
 511                         }
 512                         total = rcnt;
 513                         rcnt -= 3;
 514                         ptr = skb_put(dch->rx_skb, rcnt);
 515
 516                         if (le16_to_cpu(zp->z2) + rcnt <= D_FIFO_SIZE)
 517                                 maxlen = rcnt;  /* complete transfer */
 518                         else
 519                                 maxlen = D_FIFO_SIZE - le16_to_cpu(zp->z2);
 520                                     /* maximum */
 521
 522                         ptr1 = df->data + le16_to_cpu(zp->z2);
 523                             /* start of data */
 524                         memcpy(ptr, ptr1, maxlen);      /* copy data */
 525                         rcnt -= maxlen;
 526
 527                         if (rcnt) {     /* rest remaining */
 528                                 ptr += maxlen;
 529                                 ptr1 = df->data;        /* start of buffer */
 530                                 memcpy(ptr, ptr1, rcnt);        /* rest */
 531                         }
 532                         df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) |
 533                             (MAX_D_FRAMES + 1); /* next buffer */
 534                         df->za[df->f2 & D_FREG_MASK].z2 = cpu_to_le16((
 535                             le16_to_cpu(zp->z2) + total) & (D_FIFO_SIZE - 1));
 536                         recv_Dchannel(dch);
 537                 }
 538         }
 539         return 1;
 540 }
 541
 542 /*
 543  * check for transparent receive data and read max one 'poll' size if avail
 544  */
 545 static void
 546 hfcpci_empty_fifo_trans(struct bchannel *bch, struct bzfifo *rxbz,
 547         struct bzfifo *txbz, u_char *bdata)
 548 {
 549          __le16 *z1r, *z2r, *z1t, *z2t;
 550         int     new_z2, fcnt_rx, fcnt_tx, maxlen;
 551         u_char  *ptr, *ptr1;
 552
 553         z1r = &rxbz->za[MAX_B_FRAMES].z1;       /* pointer to z reg */
 554         z2r = z1r + 1;
 555         z1t = &txbz->za[MAX_B_FRAMES].z1;
 556         z2t = z1t + 1;
 557
 558         fcnt_rx = le16_to_cpu(*z1r) - le16_to_cpu(*z2r);
 559         if (!fcnt_rx)
 560                 return; /* no data avail */
 561
 562         if (fcnt_rx <= 0)
 563                 fcnt_rx += B_FIFO_SIZE; /* bytes actually buffered */
 564         new_z2 = le16_to_cpu(*z2r) + fcnt_rx;   /* new position in fifo */
 565         if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
 566                 new_z2 -= B_FIFO_SIZE;  /* buffer wrap */
 567
 568         if (fcnt_rx > MAX_DATA_SIZE) {  /* flush, if oversized */
 569                 *z2r = cpu_to_le16(new_z2);             /* new position */
 570                 return;
 571         }
 572
 573         fcnt_tx = le16_to_cpu(*z2t) - le16_to_cpu(*z1t);
 574         if (fcnt_tx <= 0)
 575                 fcnt_tx += B_FIFO_SIZE;
 576                     /* fcnt_tx contains available bytes in tx-fifo */
 577         fcnt_tx = B_FIFO_SIZE - fcnt_tx;
 578                     /* remaining bytes to send (bytes in tx-fifo) */
 579
 580         bch->rx_skb = mI_alloc_skb(fcnt_rx, GFP_ATOMIC);
 581         if (bch->rx_skb) {
 582                 ptr = skb_put(bch->rx_skb, fcnt_rx);
 583                 if (le16_to_cpu(*z2r) + fcnt_rx <= B_FIFO_SIZE + B_SUB_VAL)
 584                         maxlen = fcnt_rx;       /* complete transfer */
 585                 else
 586                         maxlen = B_FIFO_SIZE + B_SUB_VAL - le16_to_cpu(*z2r);
 587                             /* maximum */
 588
 589                 ptr1 = bdata + (le16_to_cpu(*z2r) - B_SUB_VAL);
 590                     /* start of data */
 591                 memcpy(ptr, ptr1, maxlen);      /* copy data */
 592                 fcnt_rx -= maxlen;
 593
 594                 if (fcnt_rx) {  /* rest remaining */
 595                         ptr += maxlen;
 596                         ptr1 = bdata;   /* start of buffer */
 597                         memcpy(ptr, ptr1, fcnt_rx);     /* rest */
 598                 }
 599                 recv_Bchannel(bch, fcnt_tx); /* bch, id */
 600         } else
 601                 printk(KERN_WARNING "HFCPCI: receive out of memory\n");
 602
 603         *z2r = cpu_to_le16(new_z2);             /* new position */
 604 }
 605
 606 /*
 607  * B-channel main receive routine
 608  */
 609 static void
 610 main_rec_hfcpci(struct bchannel *bch)
 611 {
 612         struct hfc_pci  *hc = bch->hw;
 613         int             rcnt, real_fifo;
 614         int             receive = 0, count = 5;
 615         struct bzfifo   *txbz, *rxbz;
 616         u_char          *bdata;
 617         struct zt       *zp;
 618
 619         if ((bch->nr & 2) && (!hc->hw.bswapped)) {
 620                 rxbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b2;
 621                 txbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2;
 622                 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.rxdat_b2;
 623                 real_fifo = 1;
 624         } else {
 625                 rxbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b1;
 626                 txbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1;
 627                 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.rxdat_b1;
 628                 real_fifo = 0;
 629         }
 630 Begin:
 631         count--;
 632         if (rxbz->f1 != rxbz->f2) {
 633                 if (bch->debug & DEBUG_HW_BCHANNEL)
 634                         printk(KERN_DEBUG "hfcpci rec ch(%x) f1(%d) f2(%d)\n",
 635                             bch->nr, rxbz->f1, rxbz->f2);
 636                 zp = &rxbz->za[rxbz->f2];
 637
 638                 rcnt = le16_to_cpu(zp->z1) - le16_to_cpu(zp->z2);
 639                 if (rcnt < 0)
 640                         rcnt += B_FIFO_SIZE;
 641                 rcnt++;
 642                 if (bch->debug & DEBUG_HW_BCHANNEL)
 643                         printk(KERN_DEBUG
 644                             "hfcpci rec ch(%x) z1(%x) z2(%x) cnt(%d)\n",
 645                             bch->nr, le16_to_cpu(zp->z1),
 646                             le16_to_cpu(zp->z2), rcnt);
 647                 hfcpci_empty_bfifo(bch, rxbz, bdata, rcnt);
 648                 rcnt = rxbz->f1 - rxbz->f2;
 649                 if (rcnt < 0)
 650                         rcnt += MAX_B_FRAMES + 1;
 651                 if (hc->hw.last_bfifo_cnt[real_fifo] > rcnt + 1) {
 652                         rcnt = 0;
 653                         hfcpci_clear_fifo_rx(hc, real_fifo);
 654                 }
 655                 hc->hw.last_bfifo_cnt[real_fifo] = rcnt;
 656                 if (rcnt > 1)
 657                         receive = 1;
 658                 else
 659                         receive = 0;
 660         } else if (test_bit(FLG_TRANSPARENT, &bch->Flags)) {
 661                 hfcpci_empty_fifo_trans(bch, rxbz, txbz, bdata);
 662                 return;
 663         } else
 664                 receive = 0;
 665         if (count && receive)
 666                 goto Begin;
 667
 668 }
 669
 670 /*
 671  * D-channel send routine
 672  */
 673 static void
 674 hfcpci_fill_dfifo(struct hfc_pci *hc)
 675 {
 676         struct dchannel *dch = &hc->dch;
 677         int             fcnt;
 678         int             count, new_z1, maxlen;
 679         struct dfifo    *df;
 680         u_char          *src, *dst, new_f1;
 681
 682         if ((dch->debug & DEBUG_HW_DCHANNEL) && !(dch->debug & DEBUG_HW_DFIFO))
 683                 printk(KERN_DEBUG "%s\n", __func__);
 684
 685         if (!dch->tx_skb)
 686                 return;
 687         count = dch->tx_skb->len - dch->tx_idx;
 688         if (count <= 0)
 689                 return;
 690         df = &((union fifo_area *) (hc->hw.fifos))->d_chan.d_tx;
 691
 692         if (dch->debug & DEBUG_HW_DFIFO)
 693                 printk(KERN_DEBUG "%s:f1(%d) f2(%d) z1(f1)(%x)\n", __func__,
 694                     df->f1, df->f2,
 695                     le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1));
 696         fcnt = df->f1 - df->f2; /* frame count actually buffered */
 697         if (fcnt < 0)
 698                 fcnt += (MAX_D_FRAMES + 1);     /* if wrap around */
 699         if (fcnt > (MAX_D_FRAMES - 1)) {
 700                 if (dch->debug & DEBUG_HW_DCHANNEL)
 701                         printk(KERN_DEBUG
 702                             "hfcpci_fill_Dfifo more as 14 frames\n");
 703 #ifdef ERROR_STATISTIC
 704                 cs->err_tx++;
 705 #endif
 706                 return;
 707         }
 708         /* now determine free bytes in FIFO buffer */
 709         maxlen = le16_to_cpu(df->za[df->f2 & D_FREG_MASK].z2) -
 710             le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1) - 1;
 711         if (maxlen <= 0)
 712                 maxlen += D_FIFO_SIZE;  /* count now contains available bytes */
 713
 714         if (dch->debug & DEBUG_HW_DCHANNEL)
 715                 printk(KERN_DEBUG "hfcpci_fill_Dfifo count(%d/%d)\n",
 716                         count, maxlen);
 717         if (count > maxlen) {
 718                 if (dch->debug & DEBUG_HW_DCHANNEL)
 719                         printk(KERN_DEBUG "hfcpci_fill_Dfifo no fifo mem\n");
 720                 return;
 721         }
 722         new_z1 = (le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1) + count) &
 723             (D_FIFO_SIZE - 1);
 724         new_f1 = ((df->f1 + 1) & D_FREG_MASK) | (D_FREG_MASK + 1);
 725         src = dch->tx_skb->data + dch->tx_idx;  /* source pointer */
 726         dst = df->data + le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1);
 727         maxlen = D_FIFO_SIZE - le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1);
 728             /* end fifo */
 729         if (maxlen > count)
 730                 maxlen = count; /* limit size */
 731         memcpy(dst, src, maxlen);       /* first copy */
 732
 733         count -= maxlen;        /* remaining bytes */
 734         if (count) {
 735                 dst = df->data; /* start of buffer */
 736                 src += maxlen;  /* new position */
 737                 memcpy(dst, src, count);
 738         }
 739         df->za[new_f1 & D_FREG_MASK].z1 = cpu_to_le16(new_z1);
 740             /* for next buffer */
 741         df->za[df->f1 & D_FREG_MASK].z1 = cpu_to_le16(new_z1);
 742             /* new pos actual buffer */
 743         df->f1 = new_f1;        /* next frame */
 744         dch->tx_idx = dch->tx_skb->len;
 745 }
 746
 747 /*
 748  * B-channel send routine
 749  */
 750 static void
 751 hfcpci_fill_fifo(struct bchannel *bch)
 752 {
 753         struct hfc_pci  *hc = bch->hw;
 754         int             maxlen, fcnt;
 755         int             count, new_z1;
 756         struct bzfifo   *bz;
 757         u_char          *bdata;
 758         u_char          new_f1, *src, *dst;
 759         __le16 *z1t, *z2t;
 760
 761         if ((bch->debug & DEBUG_HW_BCHANNEL) && !(bch->debug & DEBUG_HW_BFIFO))
 762                 printk(KERN_DEBUG "%s\n", __func__);
 763         if ((!bch->tx_skb) || bch->tx_skb->len <= 0)
 764                 return;
 765         count = bch->tx_skb->len - bch->tx_idx;
 766         if ((bch->nr & 2) && (!hc->hw.bswapped)) {
 767                 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2;
 768                 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.txdat_b2;
 769         } else {
 770                 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1;
 771                 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.txdat_b1;
 772         }
 773
 774         if (test_bit(FLG_TRANSPARENT, &bch->Flags)) {
 775                 z1t = &bz->za[MAX_B_FRAMES].z1;
 776                 z2t = z1t + 1;
 777                 if (bch->debug & DEBUG_HW_BCHANNEL)
 778                         printk(KERN_DEBUG "hfcpci_fill_fifo_trans ch(%x) "
 779                             "cnt(%d) z1(%x) z2(%x)\n", bch->nr, count,
 780                             le16_to_cpu(*z1t), le16_to_cpu(*z2t));
 781                 fcnt = le16_to_cpu(*z2t) - le16_to_cpu(*z1t);
 782                 if (fcnt <= 0)
 783                         fcnt += B_FIFO_SIZE;
 784                             /* fcnt contains available bytes in fifo */
 785                 fcnt = B_FIFO_SIZE - fcnt;
 786                     /* remaining bytes to send (bytes in fifo) */
 787
 788                 /* "fill fifo if empty" feature */
 789                 if (test_bit(FLG_FILLEMPTY, &bch->Flags) && !fcnt) {
 790                         /* printk(KERN_DEBUG "%s: buffer empty, so we have "
 791                                 "underrun\n", __func__); */
 792                         /* fill buffer, to prevent future underrun */
 793                         count = HFCPCI_FILLEMPTY;
 794                         new_z1 = le16_to_cpu(*z1t) + count;
 795                            /* new buffer Position */
 796                         if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
 797                                 new_z1 -= B_FIFO_SIZE;  /* buffer wrap */
 798                         dst = bdata + (le16_to_cpu(*z1t) - B_SUB_VAL);
 799                         maxlen = (B_FIFO_SIZE + B_SUB_VAL) - le16_to_cpu(*z1t);
 800                             /* end of fifo */
 801                         if (bch->debug & DEBUG_HW_BFIFO)
 802                                 printk(KERN_DEBUG "hfcpci_FFt fillempty "
 803                                     "fcnt(%d) maxl(%d) nz1(%x) dst(%p)\n",
 804                                     fcnt, maxlen, new_z1, dst);
 805                         fcnt += count;
 806                         if (maxlen > count)
 807                                 maxlen = count;         /* limit size */
 808                         memset(dst, 0x2a, maxlen);      /* first copy */
 809                         count -= maxlen;                /* remaining bytes */
 810                         if (count) {
 811                                 dst = bdata;            /* start of buffer */
 812                                 memset(dst, 0x2a, count);
 813                         }
 814                         *z1t = cpu_to_le16(new_z1);     /* now send data */
 815                 }
 816
 817 next_t_frame:
 818                 count = bch->tx_skb->len - bch->tx_idx;
 819                 /* maximum fill shall be poll*2 */
 820                 if (count > (poll << 1) - fcnt)
 821                         count = (poll << 1) - fcnt;
 822                 if (count <= 0)
 823                         return;
 824                 /* data is suitable for fifo */
 825                 new_z1 = le16_to_cpu(*z1t) + count;
 826                     /* new buffer Position */
 827                 if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
 828                         new_z1 -= B_FIFO_SIZE;  /* buffer wrap */
 829                 src = bch->tx_skb->data + bch->tx_idx;
 830                     /* source pointer */
 831                 dst = bdata + (le16_to_cpu(*z1t) - B_SUB_VAL);
 832                 maxlen = (B_FIFO_SIZE + B_SUB_VAL) - le16_to_cpu(*z1t);
 833                     /* end of fifo */
 834                 if (bch->debug & DEBUG_HW_BFIFO)
 835                         printk(KERN_DEBUG "hfcpci_FFt fcnt(%d) "
 836                             "maxl(%d) nz1(%x) dst(%p)\n",
 837                             fcnt, maxlen, new_z1, dst);
 838                 fcnt += count;
 839                 bch->tx_idx += count;
 840                 if (maxlen > count)
 841                         maxlen = count;         /* limit size */
 842                 memcpy(dst, src, maxlen);       /* first copy */
 843                 count -= maxlen;        /* remaining bytes */
 844                 if (count) {
 845                         dst = bdata;    /* start of buffer */
 846                         src += maxlen;  /* new position */
 847                         memcpy(dst, src, count);
 848                 }
 849                 *z1t = cpu_to_le16(new_z1);     /* now send data */
 850                 if (bch->tx_idx < bch->tx_skb->len)
 851                         return;
 852                 /* send confirm, on trans, free on hdlc. */
 853                 if (test_bit(FLG_TRANSPARENT, &bch->Flags))
 854                         confirm_Bsend(bch);
 855                 dev_kfree_skb(bch->tx_skb);
 856                 if (get_next_bframe(bch))
 857                         goto next_t_frame;
 858                 return;
 859         }
 860         if (bch->debug & DEBUG_HW_BCHANNEL)
 861                 printk(KERN_DEBUG
 862                     "%s: ch(%x) f1(%d) f2(%d) z1(f1)(%x)\n",
 863                     __func__, bch->nr, bz->f1, bz->f2,
 864                     bz->za[bz->f1].z1);
 865         fcnt = bz->f1 - bz->f2; /* frame count actually buffered */
 866         if (fcnt < 0)
 867                 fcnt += (MAX_B_FRAMES + 1);     /* if wrap around */
 868         if (fcnt > (MAX_B_FRAMES - 1)) {
 869                 if (bch->debug & DEBUG_HW_BCHANNEL)
 870                         printk(KERN_DEBUG
 871                             "hfcpci_fill_Bfifo more as 14 frames\n");
 872                 return;
 873         }
 874         /* now determine free bytes in FIFO buffer */
 875         maxlen = le16_to_cpu(bz->za[bz->f2].z2) -
 876             le16_to_cpu(bz->za[bz->f1].z1) - 1;
 877         if (maxlen <= 0)
 878                 maxlen += B_FIFO_SIZE;  /* count now contains available bytes */
 879
 880         if (bch->debug & DEBUG_HW_BCHANNEL)
 881                 printk(KERN_DEBUG "hfcpci_fill_fifo ch(%x) count(%d/%d)\n",
 882                         bch->nr, count, maxlen);
 883
 884         if (maxlen < count) {
 885                 if (bch->debug & DEBUG_HW_BCHANNEL)
 886                         printk(KERN_DEBUG "hfcpci_fill_fifo no fifo mem\n");
 887                 return;
 888         }
 889         new_z1 = le16_to_cpu(bz->za[bz->f1].z1) + count;
 890             /* new buffer Position */
 891         if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
 892                 new_z1 -= B_FIFO_SIZE;  /* buffer wrap */
 893
 894         new_f1 = ((bz->f1 + 1) & MAX_B_FRAMES);
 895         src = bch->tx_skb->data + bch->tx_idx;  /* source pointer */
 896         dst = bdata + (le16_to_cpu(bz->za[bz->f1].z1) - B_SUB_VAL);
 897         maxlen = (B_FIFO_SIZE + B_SUB_VAL) - le16_to_cpu(bz->za[bz->f1].z1);
 898             /* end fifo */
 899         if (maxlen > count)
 900                 maxlen = count; /* limit size */
 901         memcpy(dst, src, maxlen);       /* first copy */
 902
 903         count -= maxlen;        /* remaining bytes */
 904         if (count) {
 905                 dst = bdata;    /* start of buffer */
 906                 src += maxlen;  /* new position */
 907                 memcpy(dst, src, count);
 908         }
 909         bz->za[new_f1].z1 = cpu_to_le16(new_z1);        /* for next buffer */
 910         bz->f1 = new_f1;        /* next frame */
 911         dev_kfree_skb(bch->tx_skb);
 912         get_next_bframe(bch);
 913 }
 914
 915
 916
 917 /*
 918  * handle L1 state changes TE
 919  */
 920
 921 static void
 922 ph_state_te(struct dchannel *dch)
 923 {
 924         if (dch->debug)
 925                 printk(KERN_DEBUG "%s: TE newstate %x\n",
 926                         __func__, dch->state);
 927         switch (dch->state) {
 928         case 0:
 929                 l1_event(dch->l1, HW_RESET_IND);
 930                 break;
 931         case 3:
 932                 l1_event(dch->l1, HW_DEACT_IND);
 933                 break;
 934         case 5:
 935         case 8:
 936                 l1_event(dch->l1, ANYSIGNAL);
 937                 break;
 938         case 6:
 939                 l1_event(dch->l1, INFO2);
 940                 break;
 941         case 7:
 942                 l1_event(dch->l1, INFO4_P8);
 943                 break;
 944         }
 945 }
 946
 947 /*
 948  * handle L1 state changes NT
 949  */
 950
 951 static void
 952 handle_nt_timer3(struct dchannel *dch) {
 953         struct hfc_pci  *hc = dch->hw;
 954
 955         test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
 956         hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
 957         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
 958         hc->hw.nt_timer = 0;
 959         test_and_set_bit(FLG_ACTIVE, &dch->Flags);
 960         if (test_bit(HFC_CFG_MASTER, &hc->cfg))
 961                 hc->hw.mst_m |= HFCPCI_MASTER;
 962         Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
 963         _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
 964             MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
 965 }
 966
 967 static void
 968 ph_state_nt(struct dchannel *dch)
 969 {
 970         struct hfc_pci  *hc = dch->hw;
 971         u_char  val;
 972
 973         if (dch->debug)
 974                 printk(KERN_DEBUG "%s: NT newstate %x\n",
 975                         __func__, dch->state);
 976         switch (dch->state) {
 977         case 2:
 978                 if (hc->hw.nt_timer < 0) {
 979                         hc->hw.nt_timer = 0;
 980                         test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
 981                         test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
 982                         hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
 983                         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
 984                         /* Clear already pending ints */
 985                         val = Read_hfc(hc, HFCPCI_INT_S1);
 986                         Write_hfc(hc, HFCPCI_STATES, 4 | HFCPCI_LOAD_STATE);
 987                         udelay(10);
 988                         Write_hfc(hc, HFCPCI_STATES, 4);
 989                         dch->state = 4;
 990                 } else if (hc->hw.nt_timer == 0) {
 991                         hc->hw.int_m1 |= HFCPCI_INTS_TIMER;
 992                         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
 993                         hc->hw.nt_timer = NT_T1_COUNT;
 994                         hc->hw.ctmt &= ~HFCPCI_AUTO_TIMER;
 995                         hc->hw.ctmt |= HFCPCI_TIM3_125;
 996                         Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt |
 997                                 HFCPCI_CLTIMER);
 998                         test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
 999                         test_and_set_bit(FLG_HFC_TIMER_T1, &dch->Flags);
1000                         /* allow G2 -> G3 transition */
1001                         Write_hfc(hc, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3);
1002                 } else {
1003                         Write_hfc(hc, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3);
1004                 }
1005                 break;
1006         case 1:
1007                 hc->hw.nt_timer = 0;
1008                 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
1009                 test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
1010                 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
1011                 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1012                 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
1013                 hc->hw.mst_m &= ~HFCPCI_MASTER;
1014                 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1015                 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
1016                 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
1017                     MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
1018                 break;
1019         case 4:
1020                 hc->hw.nt_timer = 0;
1021                 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
1022                 test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
1023                 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
1024                 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1025                 break;
1026         case 3:
1027                 if (!test_and_set_bit(FLG_HFC_TIMER_T3, &dch->Flags)) {
1028                         if (!test_and_clear_bit(FLG_L2_ACTIVATED,
1029                             &dch->Flags)) {
1030                                 handle_nt_timer3(dch);
1031                                 break;
1032                         }
1033                         test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
1034                         hc->hw.int_m1 |= HFCPCI_INTS_TIMER;
1035                         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1036                         hc->hw.nt_timer = NT_T3_COUNT;
1037                         hc->hw.ctmt &= ~HFCPCI_AUTO_TIMER;
1038                         hc->hw.ctmt |= HFCPCI_TIM3_125;
1039                         Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt |
1040                                 HFCPCI_CLTIMER);
1041                 }
1042                 break;
1043         }
1044 }
1045
1046 static void
1047 ph_state(struct dchannel *dch)
1048 {
1049         struct hfc_pci  *hc = dch->hw;
1050
1051         if (hc->hw.protocol == ISDN_P_NT_S0) {
1052                 if (test_bit(FLG_HFC_TIMER_T3, &dch->Flags) &&
1053                     hc->hw.nt_timer < 0)
1054                         handle_nt_timer3(dch);
1055                 else
1056                         ph_state_nt(dch);
1057         } else
1058                 ph_state_te(dch);
1059 }
1060
1061 /*
1062  * Layer 1 callback function
1063  */
1064 static int
1065 hfc_l1callback(struct dchannel *dch, u_int cmd)
1066 {
1067         struct hfc_pci          *hc = dch->hw;
1068
1069         switch (cmd) {
1070         case INFO3_P8:
1071         case INFO3_P10:
1072                 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
1073                         hc->hw.mst_m |= HFCPCI_MASTER;
1074                 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1075                 break;
1076         case HW_RESET_REQ:
1077                 Write_hfc(hc, HFCPCI_STATES, HFCPCI_LOAD_STATE | 3);
1078                 /* HFC ST 3 */
1079                 udelay(6);
1080                 Write_hfc(hc, HFCPCI_STATES, 3);        /* HFC ST 2 */
1081                 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
1082                         hc->hw.mst_m |= HFCPCI_MASTER;
1083                 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1084                 Write_hfc(hc, HFCPCI_STATES, HFCPCI_ACTIVATE |
1085                    HFCPCI_DO_ACTION);
1086                 l1_event(dch->l1, HW_POWERUP_IND);
1087                 break;
1088         case HW_DEACT_REQ:
1089                 hc->hw.mst_m &= ~HFCPCI_MASTER;
1090                 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1091                 skb_queue_purge(&dch->squeue);
1092                 if (dch->tx_skb) {
1093                         dev_kfree_skb(dch->tx_skb);
1094                         dch->tx_skb = NULL;
1095                 }
1096                 dch->tx_idx = 0;
1097                 if (dch->rx_skb) {
1098                         dev_kfree_skb(dch->rx_skb);
1099                         dch->rx_skb = NULL;
1100                 }
1101                 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
1102                 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
1103                         del_timer(&dch->timer);
1104                 break;
1105         case HW_POWERUP_REQ:
1106                 Write_hfc(hc, HFCPCI_STATES, HFCPCI_DO_ACTION);
1107                 break;
1108         case PH_ACTIVATE_IND:
1109                 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
1110                 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
1111                         GFP_ATOMIC);
1112                 break;
1113         case PH_DEACTIVATE_IND:
1114                 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
1115                 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
1116                         GFP_ATOMIC);
1117                 break;
1118         default:
1119                 if (dch->debug & DEBUG_HW)
1120                         printk(KERN_DEBUG "%s: unknown command %x\n",
1121                             __func__, cmd);
1122                 return -1;
1123         }
1124         return 0;
1125 }
1126
1127 /*
1128  * Interrupt handler
1129  */
1130 static inline void
1131 tx_birq(struct bchannel *bch)
1132 {
1133         if (bch->tx_skb && bch->tx_idx < bch->tx_skb->len)
1134                 hfcpci_fill_fifo(bch);
1135         else {
1136                 if (bch->tx_skb)
1137                         dev_kfree_skb(bch->tx_skb);
1138                 if (get_next_bframe(bch))
1139                         hfcpci_fill_fifo(bch);
1140         }
1141 }
1142
1143 static inline void
1144 tx_dirq(struct dchannel *dch)
1145 {
1146         if (dch->tx_skb && dch->tx_idx < dch->tx_skb->len)
1147                 hfcpci_fill_dfifo(dch->hw);
1148         else {
1149                 if (dch->tx_skb)
1150                         dev_kfree_skb(dch->tx_skb);
1151                 if (get_next_dframe(dch))
1152                         hfcpci_fill_dfifo(dch->hw);
1153         }
1154 }
1155
1156 static irqreturn_t
1157 hfcpci_int(int intno, void *dev_id)
1158 {
1159         struct hfc_pci  *hc = dev_id;
1160         u_char          exval;
1161         struct bchannel *bch;
1162         u_char          val, stat;
1163
1164         spin_lock(&hc->lock);
1165         if (!(hc->hw.int_m2 & 0x08)) {
1166                 spin_unlock(&hc->lock);
1167                 return IRQ_NONE; /* not initialised */
1168         }
1169         stat = Read_hfc(hc, HFCPCI_STATUS);
1170         if (HFCPCI_ANYINT & stat) {
1171                 val = Read_hfc(hc, HFCPCI_INT_S1);
1172                 if (hc->dch.debug & DEBUG_HW_DCHANNEL)
1173                         printk(KERN_DEBUG
1174                             "HFC-PCI: stat(%02x) s1(%02x)\n", stat, val);
1175         } else {
1176                 /* shared */
1177                 spin_unlock(&hc->lock);
1178                 return IRQ_NONE;
1179         }
1180         hc->irqcnt++;
1181
1182         if (hc->dch.debug & DEBUG_HW_DCHANNEL)
1183                 printk(KERN_DEBUG "HFC-PCI irq %x\n", val);
1184         val &= hc->hw.int_m1;
1185         if (val & 0x40) {       /* state machine irq */
1186                 exval = Read_hfc(hc, HFCPCI_STATES) & 0xf;
1187                 if (hc->dch.debug & DEBUG_HW_DCHANNEL)
1188                         printk(KERN_DEBUG "ph_state chg %d->%d\n",
1189                                 hc->dch.state, exval);
1190                 hc->dch.state = exval;
1191                 schedule_event(&hc->dch, FLG_PHCHANGE);
1192                 val &= ~0x40;
1193         }
1194         if (val & 0x80) {       /* timer irq */
1195                 if (hc->hw.protocol == ISDN_P_NT_S0) {
1196                         if ((--hc->hw.nt_timer) < 0)
1197                                 schedule_event(&hc->dch, FLG_PHCHANGE);
1198                 }
1199                 val &= ~0x80;
1200                 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt | HFCPCI_CLTIMER);
1201         }
1202         if (val & 0x08) {       /* B1 rx */
1203                 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1);
1204                 if (bch)
1205                         main_rec_hfcpci(bch);
1206                 else if (hc->dch.debug)
1207                         printk(KERN_DEBUG "hfcpci spurious 0x08 IRQ\n");
1208         }
1209         if (val & 0x10) {       /* B2 rx */
1210                 bch = Sel_BCS(hc, 2);
1211                 if (bch)
1212                         main_rec_hfcpci(bch);
1213                 else if (hc->dch.debug)
1214                         printk(KERN_DEBUG "hfcpci spurious 0x10 IRQ\n");
1215         }
1216         if (val & 0x01) {       /* B1 tx */
1217                 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1);
1218                 if (bch)
1219                         tx_birq(bch);
1220                 else if (hc->dch.debug)
1221                         printk(KERN_DEBUG "hfcpci spurious 0x01 IRQ\n");
1222         }
1223         if (val & 0x02) {       /* B2 tx */
1224                 bch = Sel_BCS(hc, 2);
1225                 if (bch)
1226                         tx_birq(bch);
1227                 else if (hc->dch.debug)
1228                         printk(KERN_DEBUG "hfcpci spurious 0x02 IRQ\n");
1229         }
1230         if (val & 0x20)         /* D rx */
1231                 receive_dmsg(hc);
1232         if (val & 0x04) {       /* D tx */
1233                 if (test_and_clear_bit(FLG_BUSY_TIMER, &hc->dch.Flags))
1234                         del_timer(&hc->dch.timer);
1235                 tx_dirq(&hc->dch);
1236         }
1237         spin_unlock(&hc->lock);
1238         return IRQ_HANDLED;
1239 }
1240
1241 /*
1242  * timer callback for D-chan busy resolution. Currently no function
1243  */
1244 static void
1245 hfcpci_dbusy_timer(struct hfc_pci *hc)
1246 {
1247 }
1248
1249 /*
1250  * activate/deactivate hardware for selected channels and mode
1251  */
1252 static int
1253 mode_hfcpci(struct bchannel *bch, int bc, int protocol)
1254 {
1255         struct hfc_pci  *hc = bch->hw;
1256         int             fifo2;
1257         u_char          rx_slot = 0, tx_slot = 0, pcm_mode;
1258
1259         if (bch->debug & DEBUG_HW_BCHANNEL)
1260                 printk(KERN_DEBUG
1261                     "HFCPCI bchannel protocol %x-->%x ch %x-->%x\n",
1262                     bch->state, protocol, bch->nr, bc);
1263
1264         fifo2 = bc;
1265         pcm_mode = (bc>>24) & 0xff;
1266         if (pcm_mode) { /* PCM SLOT USE */
1267                 if (!test_bit(HFC_CFG_PCM, &hc->cfg))
1268                         printk(KERN_WARNING
1269                             "%s: pcm channel id without HFC_CFG_PCM\n",
1270                             __func__);
1271                 rx_slot = (bc>>8) & 0xff;
1272                 tx_slot = (bc>>16) & 0xff;
1273                 bc = bc & 0xff;
1274         } else if (test_bit(HFC_CFG_PCM, &hc->cfg) && (protocol > ISDN_P_NONE))
1275                 printk(KERN_WARNING "%s: no pcm channel id but HFC_CFG_PCM\n",
1276                     __func__);
1277         if (hc->chanlimit > 1) {
1278                 hc->hw.bswapped = 0;    /* B1 and B2 normal mode */
1279                 hc->hw.sctrl_e &= ~0x80;
1280         } else {
1281                 if (bc & 2) {
1282                         if (protocol != ISDN_P_NONE) {
1283                                 hc->hw.bswapped = 1; /* B1 and B2 exchanged */
1284                                 hc->hw.sctrl_e |= 0x80;
1285                         } else {
1286                                 hc->hw.bswapped = 0; /* B1 and B2 normal mode */
1287                                 hc->hw.sctrl_e &= ~0x80;
1288                         }
1289                         fifo2 = 1;
1290                 } else {
1291                         hc->hw.bswapped = 0;    /* B1 and B2 normal mode */
1292                         hc->hw.sctrl_e &= ~0x80;
1293                 }
1294         }
1295         switch (protocol) {
1296         case (-1): /* used for init */
1297                 bch->state = -1;
1298                 bch->nr = bc;
1299         case (ISDN_P_NONE):
1300                 if (bch->state == ISDN_P_NONE)
1301                         return 0;
1302                 if (bc & 2) {
1303                         hc->hw.sctrl &= ~SCTRL_B2_ENA;
1304                         hc->hw.sctrl_r &= ~SCTRL_B2_ENA;
1305                 } else {
1306                         hc->hw.sctrl &= ~SCTRL_B1_ENA;
1307                         hc->hw.sctrl_r &= ~SCTRL_B1_ENA;
1308                 }
1309                 if (fifo2 & 2) {
1310                         hc->hw.fifo_en &= ~HFCPCI_FIFOEN_B2;
1311                         hc->hw.int_m1 &= ~(HFCPCI_INTS_B2TRANS +
1312                                 HFCPCI_INTS_B2REC);
1313                 } else {
1314                         hc->hw.fifo_en &= ~HFCPCI_FIFOEN_B1;
1315                         hc->hw.int_m1 &= ~(HFCPCI_INTS_B1TRANS +
1316                                 HFCPCI_INTS_B1REC);
1317                 }
1318 #ifdef REVERSE_BITORDER
1319                 if (bch->nr & 2)
1320                         hc->hw.cirm &= 0x7f;
1321                 else
1322                         hc->hw.cirm &= 0xbf;
1323 #endif
1324                 bch->state = ISDN_P_NONE;
1325                 bch->nr = bc;
1326                 test_and_clear_bit(FLG_HDLC, &bch->Flags);
1327                 test_and_clear_bit(FLG_TRANSPARENT, &bch->Flags);
1328                 break;
1329         case (ISDN_P_B_RAW):
1330                 bch->state = protocol;
1331                 bch->nr = bc;
1332                 hfcpci_clear_fifo_rx(hc, (fifo2 & 2) ? 1 : 0);
1333                 hfcpci_clear_fifo_tx(hc, (fifo2 & 2) ? 1 : 0);
1334                 if (bc & 2) {
1335                         hc->hw.sctrl |= SCTRL_B2_ENA;
1336                         hc->hw.sctrl_r |= SCTRL_B2_ENA;
1337 #ifdef REVERSE_BITORDER
1338                         hc->hw.cirm |= 0x80;
1339 #endif
1340                 } else {
1341                         hc->hw.sctrl |= SCTRL_B1_ENA;
1342                         hc->hw.sctrl_r |= SCTRL_B1_ENA;
1343 #ifdef REVERSE_BITORDER
1344                         hc->hw.cirm |= 0x40;
1345 #endif
1346                 }
1347                 if (fifo2 & 2) {
1348                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B2;
1349                         if (!tics)
1350                                 hc->hw.int_m1 |= (HFCPCI_INTS_B2TRANS +
1351                                     HFCPCI_INTS_B2REC);
1352                         hc->hw.ctmt |= 2;
1353                         hc->hw.conn &= ~0x18;
1354                 } else {
1355                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B1;
1356                         if (!tics)
1357                                 hc->hw.int_m1 |= (HFCPCI_INTS_B1TRANS +
1358                                     HFCPCI_INTS_B1REC);
1359                         hc->hw.ctmt |= 1;
1360                         hc->hw.conn &= ~0x03;
1361                 }
1362                 test_and_set_bit(FLG_TRANSPARENT, &bch->Flags);
1363                 break;
1364         case (ISDN_P_B_HDLC):
1365                 bch->state = protocol;
1366                 bch->nr = bc;
1367                 hfcpci_clear_fifo_rx(hc, (fifo2 & 2) ? 1 : 0);
1368                 hfcpci_clear_fifo_tx(hc, (fifo2 & 2) ? 1 : 0);
1369                 if (bc & 2) {
1370                         hc->hw.sctrl |= SCTRL_B2_ENA;
1371                         hc->hw.sctrl_r |= SCTRL_B2_ENA;
1372                 } else {
1373                         hc->hw.sctrl |= SCTRL_B1_ENA;
1374                         hc->hw.sctrl_r |= SCTRL_B1_ENA;
1375                 }
1376                 if (fifo2 & 2) {
1377                         hc->hw.last_bfifo_cnt[1] = 0;
1378                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B2;
1379                         hc->hw.int_m1 |= (HFCPCI_INTS_B2TRANS +
1380                             HFCPCI_INTS_B2REC);
1381                         hc->hw.ctmt &= ~2;
1382                         hc->hw.conn &= ~0x18;
1383                 } else {
1384                         hc->hw.last_bfifo_cnt[0] = 0;
1385                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B1;
1386                         hc->hw.int_m1 |= (HFCPCI_INTS_B1TRANS +
1387                             HFCPCI_INTS_B1REC);
1388                         hc->hw.ctmt &= ~1;
1389                         hc->hw.conn &= ~0x03;
1390                 }
1391                 test_and_set_bit(FLG_HDLC, &bch->Flags);
1392                 break;
1393         default:
1394                 printk(KERN_DEBUG "prot not known %x\n", protocol);
1395                 return -ENOPROTOOPT;
1396         }
1397         if (test_bit(HFC_CFG_PCM, &hc->cfg)) {
1398                 if ((protocol == ISDN_P_NONE) ||
1399                         (protocol == -1)) {     /* init case */
1400                         rx_slot = 0;
1401                         tx_slot = 0;
1402                 } else {
1403                         if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg)) {
1404                                 rx_slot |= 0xC0;
1405                                 tx_slot |= 0xC0;
1406                         } else {
1407                                 rx_slot |= 0x80;
1408                                 tx_slot |= 0x80;
1409                         }
1410                 }
1411                 if (bc & 2) {
1412                         hc->hw.conn &= 0xc7;
1413                         hc->hw.conn |= 0x08;
1414                         printk(KERN_DEBUG "%s: Write_hfc: B2_SSL 0x%x\n",
1415                                 __func__, tx_slot);
1416                         printk(KERN_DEBUG "%s: Write_hfc: B2_RSL 0x%x\n",
1417                                 __func__, rx_slot);
1418                         Write_hfc(hc, HFCPCI_B2_SSL, tx_slot);
1419                         Write_hfc(hc, HFCPCI_B2_RSL, rx_slot);
1420                 } else {
1421                         hc->hw.conn &= 0xf8;
1422                         hc->hw.conn |= 0x01;
1423                         printk(KERN_DEBUG "%s: Write_hfc: B1_SSL 0x%x\n",
1424                                 __func__, tx_slot);
1425                         printk(KERN_DEBUG "%s: Write_hfc: B1_RSL 0x%x\n",
1426                                 __func__, rx_slot);
1427                         Write_hfc(hc, HFCPCI_B1_SSL, tx_slot);
1428                         Write_hfc(hc, HFCPCI_B1_RSL, rx_slot);
1429                 }
1430         }
1431         Write_hfc(hc, HFCPCI_SCTRL_E, hc->hw.sctrl_e);
1432         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1433         Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
1434         Write_hfc(hc, HFCPCI_SCTRL, hc->hw.sctrl);
1435         Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
1436         Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
1437         Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1438 #ifdef REVERSE_BITORDER
1439         Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
1440 #endif
1441         return 0;
1442 }
1443
1444 static int
1445 set_hfcpci_rxtest(struct bchannel *bch, int protocol, int chan)
1446 {
1447         struct hfc_pci  *hc = bch->hw;
1448
1449         if (bch->debug & DEBUG_HW_BCHANNEL)
1450                 printk(KERN_DEBUG
1451                     "HFCPCI bchannel test rx protocol %x-->%x ch %x-->%x\n",
1452                     bch->state, protocol, bch->nr, chan);
1453         if (bch->nr != chan) {
1454                 printk(KERN_DEBUG
1455                     "HFCPCI rxtest wrong channel parameter %x/%x\n",
1456                     bch->nr, chan);
1457                 return -EINVAL;
1458         }
1459         switch (protocol) {
1460         case (ISDN_P_B_RAW):
1461                 bch->state = protocol;
1462                 hfcpci_clear_fifo_rx(hc, (chan & 2) ? 1 : 0);
1463                 if (chan & 2) {
1464                         hc->hw.sctrl_r |= SCTRL_B2_ENA;
1465                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B2RX;
1466                         if (!tics)
1467                                 hc->hw.int_m1 |= HFCPCI_INTS_B2REC;
1468                         hc->hw.ctmt |= 2;
1469                         hc->hw.conn &= ~0x18;
1470 #ifdef REVERSE_BITORDER
1471                         hc->hw.cirm |= 0x80;
1472 #endif
1473                 } else {
1474                         hc->hw.sctrl_r |= SCTRL_B1_ENA;
1475                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B1RX;
1476                         if (!tics)
1477                                 hc->hw.int_m1 |= HFCPCI_INTS_B1REC;
1478                         hc->hw.ctmt |= 1;
1479                         hc->hw.conn &= ~0x03;
1480 #ifdef REVERSE_BITORDER
1481                         hc->hw.cirm |= 0x40;
1482 #endif
1483                 }
1484                 break;
1485         case (ISDN_P_B_HDLC):
1486                 bch->state = protocol;
1487                 hfcpci_clear_fifo_rx(hc, (chan & 2) ? 1 : 0);
1488                 if (chan & 2) {
1489                         hc->hw.sctrl_r |= SCTRL_B2_ENA;
1490                         hc->hw.last_bfifo_cnt[1] = 0;
1491                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B2RX;
1492                         hc->hw.int_m1 |= HFCPCI_INTS_B2REC;
1493                         hc->hw.ctmt &= ~2;
1494                         hc->hw.conn &= ~0x18;
1495                 } else {
1496                         hc->hw.sctrl_r |= SCTRL_B1_ENA;
1497                         hc->hw.last_bfifo_cnt[0] = 0;
1498                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B1RX;
1499                         hc->hw.int_m1 |= HFCPCI_INTS_B1REC;
1500                         hc->hw.ctmt &= ~1;
1501                         hc->hw.conn &= ~0x03;
1502                 }
1503                 break;
1504         default:
1505                 printk(KERN_DEBUG "prot not known %x\n", protocol);
1506                 return -ENOPROTOOPT;
1507         }
1508         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1509         Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
1510         Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
1511         Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
1512         Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1513 #ifdef REVERSE_BITORDER
1514         Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
1515 #endif
1516         return 0;
1517 }
1518
1519 static void
1520 deactivate_bchannel(struct bchannel *bch)
1521 {
1522         struct hfc_pci  *hc = bch->hw;
1523         u_long          flags;
1524
1525         spin_lock_irqsave(&hc->lock, flags);
1526         mISDN_clear_bchannel(bch);
1527         mode_hfcpci(bch, bch->nr, ISDN_P_NONE);
1528         spin_unlock_irqrestore(&hc->lock, flags);
1529 }
1530
1531 /*
1532  * Layer 1 B-channel hardware access
1533  */
1534 static int
1535 channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
1536 {
1537         int     ret = 0;
1538
1539         switch (cq->op) {
1540         case MISDN_CTRL_GETOP:
1541                 cq->op = MISDN_CTRL_FILL_EMPTY;
1542                 break;
1543         case MISDN_CTRL_FILL_EMPTY: /* fill fifo, if empty */
1544                 test_and_set_bit(FLG_FILLEMPTY, &bch->Flags);
1545                 if (debug & DEBUG_HW_OPEN)
1546                         printk(KERN_DEBUG "%s: FILL_EMPTY request (nr=%d "
1547                                 "off=%d)\n", __func__, bch->nr, !!cq->p1);
1548                 break;
1549         default:
1550                 printk(KERN_WARNING "%s: unknown Op %x\n", __func__, cq->op);
1551                 ret = -EINVAL;
1552                 break;
1553         }
1554         return ret;
1555 }
1556 static int
1557 hfc_bctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
1558 {
1559         struct bchannel *bch = container_of(ch, struct bchannel, ch);
1560         struct hfc_pci  *hc = bch->hw;
1561         int             ret = -EINVAL;
1562         u_long          flags;
1563
1564         if (bch->debug & DEBUG_HW)
1565                 printk(KERN_DEBUG "%s: cmd:%x %p\n", __func__, cmd, arg);
1566         switch (cmd) {
1567         case HW_TESTRX_RAW:
1568                 spin_lock_irqsave(&hc->lock, flags);
1569                 ret = set_hfcpci_rxtest(bch, ISDN_P_B_RAW, (int)(long)arg);
1570                 spin_unlock_irqrestore(&hc->lock, flags);
1571                 break;
1572         case HW_TESTRX_HDLC:
1573                 spin_lock_irqsave(&hc->lock, flags);
1574                 ret = set_hfcpci_rxtest(bch, ISDN_P_B_HDLC, (int)(long)arg);
1575                 spin_unlock_irqrestore(&hc->lock, flags);
1576                 break;
1577         case HW_TESTRX_OFF:
1578                 spin_lock_irqsave(&hc->lock, flags);
1579                 mode_hfcpci(bch, bch->nr, ISDN_P_NONE);
1580                 spin_unlock_irqrestore(&hc->lock, flags);
1581                 ret = 0;
1582                 break;
1583         case CLOSE_CHANNEL:
1584                 test_and_clear_bit(FLG_OPEN, &bch->Flags);
1585                 if (test_bit(FLG_ACTIVE, &bch->Flags))
1586                         deactivate_bchannel(bch);
1587                 ch->protocol = ISDN_P_NONE;
1588                 ch->peer = NULL;
1589                 module_put(THIS_MODULE);
1590                 ret = 0;
1591                 break;
1592         case CONTROL_CHANNEL:
1593                 ret = channel_bctrl(bch, arg);
1594                 break;
1595         default:
1596                 printk(KERN_WARNING "%s: unknown prim(%x)\n",
1597                         __func__, cmd);
1598         }
1599         return ret;
1600 }
1601
1602 /*
1603  * Layer2 -> Layer 1 Dchannel data
1604  */
1605 static int
1606 hfcpci_l2l1D(struct mISDNchannel *ch, struct sk_buff *skb)
1607 {
1608         struct mISDNdevice      *dev = container_of(ch, struct mISDNdevice, D);
1609         struct dchannel         *dch = container_of(dev, struct dchannel, dev);
1610         struct hfc_pci          *hc = dch->hw;
1611         int                     ret = -EINVAL;
1612         struct mISDNhead        *hh = mISDN_HEAD_P(skb);
1613         unsigned int            id;
1614         u_long                  flags;
1615
1616         switch (hh->prim) {
1617         case PH_DATA_REQ:
1618                 spin_lock_irqsave(&hc->lock, flags);
1619                 ret = dchannel_senddata(dch, skb);
1620                 if (ret > 0) { /* direct TX */
1621                         id = hh->id; /* skb can be freed */
1622                         hfcpci_fill_dfifo(dch->hw);
1623                         ret = 0;
1624                         spin_unlock_irqrestore(&hc->lock, flags);
1625                         queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
1626                 } else
1627                         spin_unlock_irqrestore(&hc->lock, flags);
1628                 return ret;
1629         case PH_ACTIVATE_REQ:
1630                 spin_lock_irqsave(&hc->lock, flags);
1631                 if (hc->hw.protocol == ISDN_P_NT_S0) {
1632                         ret = 0;
1633                         if (test_bit(HFC_CFG_MASTER, &hc->cfg))
1634                                 hc->hw.mst_m |= HFCPCI_MASTER;
1635                         Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1636                         if (test_bit(FLG_ACTIVE, &dch->Flags)) {
1637                                 spin_unlock_irqrestore(&hc->lock, flags);
1638                                 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
1639                                     MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
1640                                 break;
1641                         }
1642                         test_and_set_bit(FLG_L2_ACTIVATED, &dch->Flags);
1643                         Write_hfc(hc, HFCPCI_STATES, HFCPCI_ACTIVATE |
1644                             HFCPCI_DO_ACTION | 1);
1645                 } else
1646                         ret = l1_event(dch->l1, hh->prim);
1647                 spin_unlock_irqrestore(&hc->lock, flags);
1648                 break;
1649         case PH_DEACTIVATE_REQ:
1650                 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
1651                 spin_lock_irqsave(&hc->lock, flags);
1652                 if (hc->hw.protocol == ISDN_P_NT_S0) {
1653                         /* prepare deactivation */
1654                         Write_hfc(hc, HFCPCI_STATES, 0x40);
1655                         skb_queue_purge(&dch->squeue);
1656                         if (dch->tx_skb) {
1657                                 dev_kfree_skb(dch->tx_skb);
1658                                 dch->tx_skb = NULL;
1659                         }
1660                         dch->tx_idx = 0;
1661                         if (dch->rx_skb) {
1662                                 dev_kfree_skb(dch->rx_skb);
1663                                 dch->rx_skb = NULL;
1664                         }
1665                         test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
1666                         if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
1667                                 del_timer(&dch->timer);
1668 #ifdef FIXME
1669                         if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags))
1670                                 dchannel_sched_event(&hc->dch, D_CLEARBUSY);
1671 #endif
1672                         hc->hw.mst_m &= ~HFCPCI_MASTER;
1673                         Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1674                         ret = 0;
1675                 } else {
1676                         ret = l1_event(dch->l1, hh->prim);
1677                 }
1678                 spin_unlock_irqrestore(&hc->lock, flags);
1679                 break;
1680         }
1681         if (!ret)
1682                 dev_kfree_skb(skb);
1683         return ret;
1684 }
1685
1686 /*
1687  * Layer2 -> Layer 1 Bchannel data
1688  */
1689 static int
1690 hfcpci_l2l1B(struct mISDNchannel *ch, struct sk_buff *skb)
1691 {
1692         struct bchannel         *bch = container_of(ch, struct bchannel, ch);
1693         struct hfc_pci          *hc = bch->hw;
1694         int                     ret = -EINVAL;
1695         struct mISDNhead        *hh = mISDN_HEAD_P(skb);
1696         unsigned int            id;
1697         u_long                  flags;
1698
1699         switch (hh->prim) {
1700         case PH_DATA_REQ:
1701                 spin_lock_irqsave(&hc->lock, flags);
1702                 ret = bchannel_senddata(bch, skb);
1703                 if (ret > 0) { /* direct TX */
1704                         id = hh->id; /* skb can be freed */
1705                         hfcpci_fill_fifo(bch);
1706                         ret = 0;
1707                         spin_unlock_irqrestore(&hc->lock, flags);
1708                         if (!test_bit(FLG_TRANSPARENT, &bch->Flags))
1709                                 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
1710                 } else
1711                         spin_unlock_irqrestore(&hc->lock, flags);
1712                 return ret;
1713         case PH_ACTIVATE_REQ:
1714                 spin_lock_irqsave(&hc->lock, flags);
1715                 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags))
1716                         ret = mode_hfcpci(bch, bch->nr, ch->protocol);
1717                 else
1718                         ret = 0;
1719                 spin_unlock_irqrestore(&hc->lock, flags);
1720                 if (!ret)
1721                         _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0,
1722                                 NULL, GFP_KERNEL);
1723                 break;
1724         case PH_DEACTIVATE_REQ:
1725                 deactivate_bchannel(bch);
1726                 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0,
1727                         NULL, GFP_KERNEL);
1728                 ret = 0;
1729                 break;
1730         }
1731         if (!ret)
1732                 dev_kfree_skb(skb);
1733         return ret;
1734 }
1735
1736 /*
1737  * called for card init message
1738  */
1739
1740 static void
1741 inithfcpci(struct hfc_pci *hc)
1742 {
1743         printk(KERN_DEBUG "inithfcpci: entered\n");
1744         hc->dch.timer.function = (void *) hfcpci_dbusy_timer;
1745         hc->dch.timer.data = (long) &hc->dch;
1746         init_timer(&hc->dch.timer);
1747         hc->chanlimit = 2;
1748         mode_hfcpci(&hc->bch[0], 1, -1);
1749         mode_hfcpci(&hc->bch[1], 2, -1);
1750 }
1751
1752
1753 static int
1754 init_card(struct hfc_pci *hc)
1755 {
1756         int     cnt = 3;
1757         u_long  flags;
1758
1759         printk(KERN_DEBUG "init_card: entered\n");
1760
1761
1762         spin_lock_irqsave(&hc->lock, flags);
1763         disable_hwirq(hc);
1764         spin_unlock_irqrestore(&hc->lock, flags);
1765         if (request_irq(hc->irq, hfcpci_int, IRQF_SHARED, "HFC PCI", hc)) {
1766                 printk(KERN_WARNING
1767                     "mISDN: couldn't get interrupt %d\n", hc->irq);
1768                 return -EIO;
1769         }
1770         spin_lock_irqsave(&hc->lock, flags);
1771         reset_hfcpci(hc);
1772         while (cnt) {
1773                 inithfcpci(hc);
1774                 /*
1775                  * Finally enable IRQ output
1776                  * this is only allowed, if an IRQ routine is already
1777                  * established for this HFC, so don't do that earlier
1778                  */
1779                 enable_hwirq(hc);
1780                 spin_unlock_irqrestore(&hc->lock, flags);
1781                 /* Timeout 80ms */
1782                 current->state = TASK_UNINTERRUPTIBLE;
1783                 schedule_timeout((80*HZ)/1000);
1784                 printk(KERN_INFO "HFC PCI: IRQ %d count %d\n",
1785                         hc->irq, hc->irqcnt);
1786                 /* now switch timer interrupt off */
1787                 spin_lock_irqsave(&hc->lock, flags);
1788                 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
1789                 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1790                 /* reinit mode reg */
1791                 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1792                 if (!hc->irqcnt) {
1793                         printk(KERN_WARNING
1794                             "HFC PCI: IRQ(%d) getting no interrupts "
1795                             "during init %d\n", hc->irq, 4 - cnt);
1796                         if (cnt == 1)
1797                                 break;
1798                         else {
1799                                 reset_hfcpci(hc);
1800                                 cnt--;
1801                         }
1802                 } else {
1803                         spin_unlock_irqrestore(&hc->lock, flags);
1804                         hc->initdone = 1;
1805                         return 0;
1806                 }
1807         }
1808         disable_hwirq(hc);
1809         spin_unlock_irqrestore(&hc->lock, flags);
1810         free_irq(hc->irq, hc);
1811         return -EIO;
1812 }
1813
1814 static int
1815 channel_ctrl(struct hfc_pci *hc, struct mISDN_ctrl_req *cq)
1816 {
1817         int     ret = 0;
1818         u_char  slot;
1819
1820         switch (cq->op) {
1821         case MISDN_CTRL_GETOP:
1822                 cq->op = MISDN_CTRL_LOOP | MISDN_CTRL_CONNECT |
1823                     MISDN_CTRL_DISCONNECT;
1824                 break;
1825         case MISDN_CTRL_LOOP:
1826                 /* channel 0 disabled loop */
1827                 if (cq->channel < 0 || cq->channel > 2) {
1828                         ret = -EINVAL;
1829                         break;
1830                 }
1831                 if (cq->channel & 1) {
1832                         if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1833                                 slot = 0xC0;
1834                         else
1835                                 slot = 0x80;
1836                         printk(KERN_DEBUG "%s: Write_hfc: B1_SSL/RSL 0x%x\n",
1837                             __func__, slot);
1838                         Write_hfc(hc, HFCPCI_B1_SSL, slot);
1839                         Write_hfc(hc, HFCPCI_B1_RSL, slot);
1840                         hc->hw.conn = (hc->hw.conn & ~7) | 6;
1841                         Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1842                 }
1843                 if (cq->channel & 2) {
1844                         if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1845                                 slot = 0xC1;
1846                         else
1847                                 slot = 0x81;
1848                         printk(KERN_DEBUG "%s: Write_hfc: B2_SSL/RSL 0x%x\n",
1849                             __func__, slot);
1850                         Write_hfc(hc, HFCPCI_B2_SSL, slot);
1851                         Write_hfc(hc, HFCPCI_B2_RSL, slot);
1852                         hc->hw.conn = (hc->hw.conn & ~0x38) | 0x30;
1853                         Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1854                 }
1855                 if (cq->channel & 3)
1856                         hc->hw.trm |= 0x80;     /* enable IOM-loop */
1857                 else {
1858                         hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x09;
1859                         Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1860                         hc->hw.trm &= 0x7f;     /* disable IOM-loop */
1861                 }
1862                 Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
1863                 break;
1864         case MISDN_CTRL_CONNECT:
1865                 if (cq->channel == cq->p1) {
1866                         ret = -EINVAL;
1867                         break;
1868                 }
1869                 if (cq->channel < 1 || cq->channel > 2 ||
1870                     cq->p1 < 1 || cq->p1 > 2) {
1871                         ret = -EINVAL;
1872                         break;
1873                 }
1874                 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1875                         slot = 0xC0;
1876                 else
1877                         slot = 0x80;
1878                 printk(KERN_DEBUG "%s: Write_hfc: B1_SSL/RSL 0x%x\n",
1879                     __func__, slot);
1880                 Write_hfc(hc, HFCPCI_B1_SSL, slot);
1881                 Write_hfc(hc, HFCPCI_B2_RSL, slot);
1882                 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1883                         slot = 0xC1;
1884                 else
1885                         slot = 0x81;
1886                 printk(KERN_DEBUG "%s: Write_hfc: B2_SSL/RSL 0x%x\n",
1887                     __func__, slot);
1888                 Write_hfc(hc, HFCPCI_B2_SSL, slot);
1889                 Write_hfc(hc, HFCPCI_B1_RSL, slot);
1890                 hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x36;
1891                 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1892                 hc->hw.trm |= 0x80;
1893                 Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
1894                 break;
1895         case MISDN_CTRL_DISCONNECT:
1896                 hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x09;
1897                 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1898                 hc->hw.trm &= 0x7f;     /* disable IOM-loop */
1899                 break;
1900         default:
1901                 printk(KERN_WARNING "%s: unknown Op %x\n",
1902                     __func__, cq->op);
1903                 ret = -EINVAL;
1904                 break;
1905         }
1906         return ret;
1907 }
1908
1909 static int
1910 open_dchannel(struct hfc_pci *hc, struct mISDNchannel *ch,
1911     struct channel_req *rq)
1912 {
1913         int err = 0;
1914
1915         if (debug & DEBUG_HW_OPEN)
1916                 printk(KERN_DEBUG "%s: dev(%d) open from %p\n", __func__,
1917                     hc->dch.dev.id, __builtin_return_address(0));
1918         if (rq->protocol == ISDN_P_NONE)
1919                 return -EINVAL;
1920         if (rq->adr.channel == 1) {
1921                 /* TODO: E-Channel */
1922                 return -EINVAL;
1923         }
1924         if (!hc->initdone) {
1925                 if (rq->protocol == ISDN_P_TE_S0) {
1926                         err = create_l1(&hc->dch, hfc_l1callback);
1927                         if (err)
1928                                 return err;
1929                 }
1930                 hc->hw.protocol = rq->protocol;
1931                 ch->protocol = rq->protocol;
1932                 err = init_card(hc);
1933                 if (err)
1934                         return err;
1935         } else {
1936                 if (rq->protocol != ch->protocol) {
1937                         if (hc->hw.protocol == ISDN_P_TE_S0)
1938                                 l1_event(hc->dch.l1, CLOSE_CHANNEL);
1939                         if (rq->protocol == ISDN_P_TE_S0) {
1940                                 err = create_l1(&hc->dch, hfc_l1callback);
1941                                 if (err)
1942                                         return err;
1943                         }
1944                         hc->hw.protocol = rq->protocol;
1945                         ch->protocol = rq->protocol;
1946                         hfcpci_setmode(hc);
1947                 }
1948         }
1949
1950         if (((ch->protocol == ISDN_P_NT_S0) && (hc->dch.state == 3)) ||
1951             ((ch->protocol == ISDN_P_TE_S0) && (hc->dch.state == 7))) {
1952                 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY,
1953                     0, NULL, GFP_KERNEL);
1954         }
1955         rq->ch = ch;
1956         if (!try_module_get(THIS_MODULE))
1957                 printk(KERN_WARNING "%s:cannot get module\n", __func__);
1958         return 0;
1959 }
1960
1961 static int
1962 open_bchannel(struct hfc_pci *hc, struct channel_req *rq)
1963 {
1964         struct bchannel         *bch;
1965
1966         if (rq->adr.channel > 2)
1967                 return -EINVAL;
1968         if (rq->protocol == ISDN_P_NONE)
1969                 return -EINVAL;
1970         bch = &hc->bch[rq->adr.channel - 1];
1971         if (test_and_set_bit(FLG_OPEN, &bch->Flags))
1972                 return -EBUSY; /* b-channel can be only open once */
1973         test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags);
1974         bch->ch.protocol = rq->protocol;
1975         rq->ch = &bch->ch; /* TODO: E-channel */
1976         if (!try_module_get(THIS_MODULE))
1977                 printk(KERN_WARNING "%s:cannot get module\n", __func__);
1978         return 0;
1979 }
1980
1981 /*
1982  * device control function
1983  */
1984 static int
1985 hfc_dctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
1986 {
1987         struct mISDNdevice      *dev = container_of(ch, struct mISDNdevice, D);
1988         struct dchannel         *dch = container_of(dev, struct dchannel, dev);
1989         struct hfc_pci          *hc = dch->hw;
1990         struct channel_req      *rq;
1991         int                     err = 0;
1992
1993         if (dch->debug & DEBUG_HW)
1994                 printk(KERN_DEBUG "%s: cmd:%x %p\n",
1995                     __func__, cmd, arg);
1996         switch (cmd) {
1997         case OPEN_CHANNEL:
1998                 rq = arg;
1999                 if ((rq->protocol == ISDN_P_TE_S0) ||
2000                     (rq->protocol == ISDN_P_NT_S0))
2001                         err = open_dchannel(hc, ch, rq);
2002                 else
2003                         err = open_bchannel(hc, rq);
2004                 break;
2005         case CLOSE_CHANNEL:
2006                 if (debug & DEBUG_HW_OPEN)
2007                         printk(KERN_DEBUG "%s: dev(%d) close from %p\n",
2008                             __func__, hc->dch.dev.id,
2009                             __builtin_return_address(0));
2010                 module_put(THIS_MODULE);
2011                 break;
2012         case CONTROL_CHANNEL:
2013                 err = channel_ctrl(hc, arg);
2014                 break;
2015         default:
2016                 if (dch->debug & DEBUG_HW)
2017                         printk(KERN_DEBUG "%s: unknown command %x\n",
2018                             __func__, cmd);
2019                 return -EINVAL;
2020         }
2021         return err;
2022 }
2023
2024 static int
2025 setup_hw(struct hfc_pci *hc)
2026 {
2027         void    *buffer;
2028
2029         printk(KERN_INFO "mISDN: HFC-PCI driver %s\n", hfcpci_revision);
2030         hc->hw.cirm = 0;
2031         hc->dch.state = 0;
2032         pci_set_master(hc->pdev);
2033         if (!hc->irq) {
2034                 printk(KERN_WARNING "HFC-PCI: No IRQ for PCI card found\n");
2035                 return 1;
2036         }
2037         hc->hw.pci_io =
2038                 (char __iomem *)(unsigned long)hc->pdev->resource[1].start;
2039
2040         if (!hc->hw.pci_io) {
2041                 printk(KERN_WARNING "HFC-PCI: No IO-Mem for PCI card found\n");
2042                 return 1;
2043         }
2044         /* Allocate memory for FIFOS */
2045         /* the memory needs to be on a 32k boundary within the first 4G */
2046         pci_set_dma_mask(hc->pdev, 0xFFFF8000);
2047         buffer = pci_alloc_consistent(hc->pdev, 0x8000, &hc->hw.dmahandle);
2048         /* We silently assume the address is okay if nonzero */
2049         if (!buffer) {
2050                 printk(KERN_WARNING
2051                     "HFC-PCI: Error allocating memory for FIFO!\n");
2052                 return 1;
2053         }
2054         hc->hw.fifos = buffer;
2055         pci_write_config_dword(hc->pdev, 0x80, hc->hw.dmahandle);
2056         hc->hw.pci_io = ioremap((ulong) hc->hw.pci_io, 256);
2057         printk(KERN_INFO
2058                 "HFC-PCI: defined at mem %#lx fifo %#lx(%#lx) IRQ %d HZ %d\n",
2059                 (u_long) hc->hw.pci_io, (u_long) hc->hw.fifos,
2060                 (u_long) hc->hw.dmahandle, hc->irq, HZ);
2061         /* enable memory mapped ports, disable busmaster */
2062         pci_write_config_word(hc->pdev, PCI_COMMAND, PCI_ENA_MEMIO);
2063         hc->hw.int_m2 = 0;
2064         disable_hwirq(hc);
2065         hc->hw.int_m1 = 0;
2066         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
2067         /* At this point the needed PCI config is done */
2068         /* fifos are still not enabled */
2069         hc->hw.timer.function = (void *) hfcpci_Timer;
2070         hc->hw.timer.data = (long) hc;
2071         init_timer(&hc->hw.timer);
2072         /* default PCM master */
2073         test_and_set_bit(HFC_CFG_MASTER, &hc->cfg);
2074         return 0;
2075 }
2076
2077 static void
2078 release_card(struct hfc_pci *hc) {
2079         u_long  flags;
2080
2081         spin_lock_irqsave(&hc->lock, flags);
2082         hc->hw.int_m2 = 0; /* interrupt output off ! */
2083         disable_hwirq(hc);
2084         mode_hfcpci(&hc->bch[0], 1, ISDN_P_NONE);
2085         mode_hfcpci(&hc->bch[1], 2, ISDN_P_NONE);
2086         if (hc->dch.timer.function != NULL) {
2087                 del_timer(&hc->dch.timer);
2088                 hc->dch.timer.function = NULL;
2089         }
2090         spin_unlock_irqrestore(&hc->lock, flags);
2091         if (hc->hw.protocol == ISDN_P_TE_S0)
2092                 l1_event(hc->dch.l1, CLOSE_CHANNEL);
2093         if (hc->initdone)
2094                 free_irq(hc->irq, hc);
2095         release_io_hfcpci(hc); /* must release after free_irq! */
2096         mISDN_unregister_device(&hc->dch.dev);
2097         mISDN_freebchannel(&hc->bch[1]);
2098         mISDN_freebchannel(&hc->bch[0]);
2099         mISDN_freedchannel(&hc->dch);
2100         pci_set_drvdata(hc->pdev, NULL);
2101         kfree(hc);
2102 }
2103
2104 static int
2105 setup_card(struct hfc_pci *card)
2106 {
2107         int             err = -EINVAL;
2108         u_int           i;
2109         char            name[MISDN_MAX_IDLEN];
2110
2111         card->dch.debug = debug;
2112         spin_lock_init(&card->lock);
2113         mISDN_initdchannel(&card->dch, MAX_DFRAME_LEN_L1, ph_state);
2114         card->dch.hw = card;
2115         card->dch.dev.Dprotocols = (1 << ISDN_P_TE_S0) | (1 << ISDN_P_NT_S0);
2116         card->dch.dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
2117             (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
2118         card->dch.dev.D.send = hfcpci_l2l1D;
2119         card->dch.dev.D.ctrl = hfc_dctrl;
2120         card->dch.dev.nrbchan = 2;
2121         for (i = 0; i < 2; i++) {
2122                 card->bch[i].nr = i + 1;
2123                 set_channelmap(i + 1, card->dch.dev.channelmap);
2124                 card->bch[i].debug = debug;
2125                 mISDN_initbchannel(&card->bch[i], MAX_DATA_MEM);
2126                 card->bch[i].hw = card;
2127                 card->bch[i].ch.send = hfcpci_l2l1B;
2128                 card->bch[i].ch.ctrl = hfc_bctrl;
2129                 card->bch[i].ch.nr = i + 1;
2130                 list_add(&card->bch[i].ch.list, &card->dch.dev.bchannels);
2131         }
2132         err = setup_hw(card);
2133         if (err)
2134                 goto error;
2135         snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-pci.%d", HFC_cnt + 1);
2136         err = mISDN_register_device(&card->dch.dev, &card->pdev->dev, name);
2137         if (err)
2138                 goto error;
2139         HFC_cnt++;
2140         printk(KERN_INFO "HFC %d cards installed\n", HFC_cnt);
2141         return 0;
2142 error:
2143         mISDN_freebchannel(&card->bch[1]);
2144         mISDN_freebchannel(&card->bch[0]);
2145         mISDN_freedchannel(&card->dch);
2146         kfree(card);
2147         return err;
2148 }
2149
2150 /* private data in the PCI devices list */
2151 struct _hfc_map {
2152         u_int   subtype;
2153         u_int   flag;
2154         char    *name;
2155 };
2156
2157 static const struct _hfc_map hfc_map[] =
2158 {
2159         {HFC_CCD_2BD0, 0, "CCD/Billion/Asuscom 2BD0"},
2160         {HFC_CCD_B000, 0, "Billion B000"},
2161         {HFC_CCD_B006, 0, "Billion B006"},
2162         {HFC_CCD_B007, 0, "Billion B007"},
2163         {HFC_CCD_B008, 0, "Billion B008"},
2164         {HFC_CCD_B009, 0, "Billion B009"},
2165         {HFC_CCD_B00A, 0, "Billion B00A"},
2166         {HFC_CCD_B00B, 0, "Billion B00B"},
2167         {HFC_CCD_B00C, 0, "Billion B00C"},
2168         {HFC_CCD_B100, 0, "Seyeon B100"},
2169         {HFC_CCD_B700, 0, "Primux II S0 B700"},
2170         {HFC_CCD_B701, 0, "Primux II S0 NT B701"},
2171         {HFC_ABOCOM_2BD1, 0, "Abocom/Magitek 2BD1"},
2172         {HFC_ASUS_0675, 0, "Asuscom/Askey 675"},
2173         {HFC_BERKOM_TCONCEPT, 0, "German telekom T-Concept"},
2174         {HFC_BERKOM_A1T, 0, "German telekom A1T"},
2175         {HFC_ANIGMA_MC145575, 0, "Motorola MC145575"},
2176         {HFC_ZOLTRIX_2BD0, 0, "Zoltrix 2BD0"},
2177         {HFC_DIGI_DF_M_IOM2_E, 0,
2178             "Digi International DataFire Micro V IOM2 (Europe)"},
2179         {HFC_DIGI_DF_M_E, 0,
2180             "Digi International DataFire Micro V (Europe)"},
2181         {HFC_DIGI_DF_M_IOM2_A, 0,
2182             "Digi International DataFire Micro V IOM2 (North America)"},
2183         {HFC_DIGI_DF_M_A, 0,
2184             "Digi International DataFire Micro V (North America)"},
2185         {HFC_SITECOM_DC105V2, 0, "Sitecom Connectivity DC-105 ISDN TA"},
2186         {},
2187 };
2188
2189 static struct pci_device_id hfc_ids[] =
2190 {
2191         { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_2BD0),
2192                 (unsigned long) &hfc_map[0] },
2193         { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B000),
2194                 (unsigned long) &hfc_map[1] },
2195         { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B006),
2196                 (unsigned long) &hfc_map[2] },
2197         { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B007),
2198                 (unsigned long) &hfc_map[3] },
2199         { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B008),
2200                 (unsigned long) &hfc_map[4] },
2201         { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B009),
2202                 (unsigned long) &hfc_map[5] },
2203         { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B00A),
2204                 (unsigned long) &hfc_map[6] },
2205         { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B00B),
2206                 (unsigned long) &hfc_map[7] },
2207         { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B00C),
2208                 (unsigned long) &hfc_map[8] },
2209         { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B100),
2210                 (unsigned long) &hfc_map[9] },
2211         { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B700),
2212                 (unsigned long) &hfc_map[10] },
2213         { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B701),
2214                 (unsigned long) &hfc_map[11] },
2215         { PCI_VDEVICE(ABOCOM, PCI_DEVICE_ID_ABOCOM_2BD1),
2216                 (unsigned long) &hfc_map[12] },
2217         { PCI_VDEVICE(ASUSTEK, PCI_DEVICE_ID_ASUSTEK_0675),
2218                 (unsigned long) &hfc_map[13] },
2219         { PCI_VDEVICE(BERKOM, PCI_DEVICE_ID_BERKOM_T_CONCEPT),
2220                 (unsigned long) &hfc_map[14] },
2221         { PCI_VDEVICE(BERKOM, PCI_DEVICE_ID_BERKOM_A1T),
2222                 (unsigned long) &hfc_map[15] },
2223         { PCI_VDEVICE(ANIGMA, PCI_DEVICE_ID_ANIGMA_MC145575),
2224                 (unsigned long) &hfc_map[16] },
2225         { PCI_VDEVICE(ZOLTRIX, PCI_DEVICE_ID_ZOLTRIX_2BD0),
2226                 (unsigned long) &hfc_map[17] },
2227         { PCI_VDEVICE(DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_E),
2228                 (unsigned long) &hfc_map[18] },
2229         { PCI_VDEVICE(DIGI, PCI_DEVICE_ID_DIGI_DF_M_E),
2230                 (unsigned long) &hfc_map[19] },
2231         { PCI_VDEVICE(DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_A),
2232                 (unsigned long) &hfc_map[20] },
2233         { PCI_VDEVICE(DIGI, PCI_DEVICE_ID_DIGI_DF_M_A),
2234                 (unsigned long) &hfc_map[21] },
2235         { PCI_VDEVICE(SITECOM, PCI_DEVICE_ID_SITECOM_DC105V2),
2236                 (unsigned long) &hfc_map[22] },
2237         {},
2238 };
2239
2240 static int __devinit
2241 hfc_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2242 {
2243         int             err = -ENOMEM;
2244         struct hfc_pci  *card;
2245         struct _hfc_map *m = (struct _hfc_map *)ent->driver_data;
2246
2247         card = kzalloc(sizeof(struct hfc_pci), GFP_ATOMIC);
2248         if (!card) {
2249                 printk(KERN_ERR "No kmem for HFC card\n");
2250                 return err;
2251         }
2252         card->pdev = pdev;
2253         card->subtype = m->subtype;
2254         err = pci_enable_device(pdev);
2255         if (err) {
2256                 kfree(card);
2257                 return err;
2258         }
2259
2260         printk(KERN_INFO "mISDN_hfcpci: found adapter %s at %s\n",
2261                m->name, pci_name(pdev));
2262
2263         card->irq = pdev->irq;
2264         pci_set_drvdata(pdev, card);
2265         err = setup_card(card);
2266         if (err)
2267                 pci_set_drvdata(pdev, NULL);
2268         return err;
2269 }
2270
2271 static void __devexit
2272 hfc_remove_pci(struct pci_dev *pdev)
2273 {
2274         struct hfc_pci  *card = pci_get_drvdata(pdev);
2275
2276         if (card)
2277                 release_card(card);
2278         else
2279                 if (debug)
2280                         printk(KERN_DEBUG "%s: drvdata already removed\n",
2281                             __func__);
2282 }
2283
2284
2285 static struct pci_driver hfc_driver = {
2286         .name = "hfcpci",
2287         .probe = hfc_probe,
2288         .remove = __devexit_p(hfc_remove_pci),
2289         .id_table = hfc_ids,
2290 };
2291
2292 static int
2293 _hfcpci_softirq(struct device *dev, void *arg)
2294 {
2295         struct hfc_pci  *hc = dev_get_drvdata(dev);
2296         struct bchannel *bch;
2297         if (hc == NULL)
2298                 return 0;
2299
2300         if (hc->hw.int_m2 & HFCPCI_IRQ_ENABLE) {
2301                 spin_lock(&hc->lock);
2302                 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1);
2303                 if (bch && bch->state == ISDN_P_B_RAW) { /* B1 rx&tx */
2304                         main_rec_hfcpci(bch);
2305                         tx_birq(bch);
2306                 }
2307                 bch = Sel_BCS(hc, hc->hw.bswapped ? 1 : 2);
2308                 if (bch && bch->state == ISDN_P_B_RAW) { /* B2 rx&tx */
2309                         main_rec_hfcpci(bch);
2310                         tx_birq(bch);
2311                 }
2312                 spin_unlock(&hc->lock);
2313         }
2314         return 0;
2315 }
2316
2317 static void
2318 hfcpci_softirq(void *arg)
2319 {
2320         (void) driver_for_each_device(&hfc_driver.driver, NULL, arg,
2321                                         _hfcpci_softirq);
2322
2323         /* if next event would be in the past ... */
2324         if ((s32)(hfc_jiffies + tics - jiffies) <= 0)
2325                 hfc_jiffies = jiffies + 1;
2326         else
2327                 hfc_jiffies += tics;
2328         hfc_tl.expires = hfc_jiffies;
2329         add_timer(&hfc_tl);
2330 }
2331
2332 static int __init
2333 HFC_init(void)
2334 {
2335         int             err;
2336
2337         if (!poll)
2338                 poll = HFCPCI_BTRANS_THRESHOLD;
2339
2340         if (poll != HFCPCI_BTRANS_THRESHOLD) {
2341                 tics = (poll * HZ) / 8000;
2342                 if (tics < 1)
2343                         tics = 1;
2344                 poll = (tics * 8000) / HZ;
2345                 if (poll > 256 || poll < 8) {
2346                         printk(KERN_ERR "%s: Wrong poll value %d not in range "
2347                                 "of 8..256.\n", __func__, poll);
2348                         err = -EINVAL;
2349                         return err;
2350                 }
2351         }
2352         if (poll != HFCPCI_BTRANS_THRESHOLD) {
2353                 printk(KERN_INFO "%s: Using alternative poll value of %d\n",
2354                         __func__, poll);
2355                 hfc_tl.function = (void *)hfcpci_softirq;
2356                 hfc_tl.data = 0;
2357                 init_timer(&hfc_tl);
2358                 hfc_tl.expires = jiffies + tics;
2359                 hfc_jiffies = hfc_tl.expires;
2360                 add_timer(&hfc_tl);
2361         } else
2362                 tics = 0; /* indicate the use of controller's timer */
2363
2364         err = pci_register_driver(&hfc_driver);
2365         if (err) {
2366                 if (timer_pending(&hfc_tl))
2367                         del_timer(&hfc_tl);
2368         }
2369
2370         return err;
2371 }
2372
2373 static void __exit
2374 HFC_cleanup(void)
2375 {
2376         if (timer_pending(&hfc_tl))
2377                 del_timer(&hfc_tl);
2378
2379         pci_unregister_driver(&hfc_driver);
2380 }
2381
2382 module_init(HFC_init);
2383 module_exit(HFC_cleanup);
2384
2385 MODULE_DEVICE_TABLE(pci, hfc_ids);