drivers/isdn/hardware/mISDN/hfcmulti.c

   1 /*
   2  * hfcmulti.c  low level driver for hfc-4s/hfc-8s/hfc-e1 based cards
   3  *
   4  * Author       Andreas Eversberg (jolly@eversberg.eu)
   5  * ported to mqueue mechanism:
   6  *              Peter Sprenger (sprengermoving-bytes.de)
   7  *
   8  * inspired by existing hfc-pci driver:
   9  * Copyright 1999  by Werner Cornelius (werner@isdn-development.de)
  10  * Copyright 2008  by Karsten Keil (kkeil@suse.de)
  11  * Copyright 2008  by Andreas Eversberg (jolly@eversberg.eu)
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2, or (at your option)
  16  * any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  26  *
  27  *
  28  * Thanks to Cologne Chip AG for this great controller!
  29  */
  30
  31 /*
  32  * module parameters:
  33  * type:
  34  *      By default (0), the card is automatically detected.
  35  *      Or use the following combinations:
  36  *      Bit 0-7   = 0x00001 = HFC-E1 (1 port)
  37  * or   Bit 0-7   = 0x00004 = HFC-4S (4 ports)
  38  * or   Bit 0-7   = 0x00008 = HFC-8S (8 ports)
  39  *      Bit 8     = 0x00100 = uLaw (instead of aLaw)
  40  *      Bit 9     = 0x00200 = Disable DTMF detect on all B-channels via hardware
  41  *      Bit 10    = spare
  42  *      Bit 11    = 0x00800 = Force PCM bus into slave mode. (otherwhise auto)
  43  * or   Bit 12    = 0x01000 = Force PCM bus into master mode. (otherwhise auto)
  44  *      Bit 13    = spare
  45  *      Bit 14    = 0x04000 = Use external ram (128K)
  46  *      Bit 15    = 0x08000 = Use external ram (512K)
  47  *      Bit 16    = 0x10000 = Use 64 timeslots instead of 32
  48  * or   Bit 17    = 0x20000 = Use 128 timeslots instead of anything else
  49  *      Bit 18    = spare
  50  *      Bit 19    = 0x80000 = Send the Watchdog a Signal (Dual E1 with Watchdog)
  51  * (all other bits are reserved and shall be 0)
  52  *      example: 0x20204 one HFC-4S with dtmf detection and 128 timeslots on PCM
  53  *               bus (PCM master)
  54  *
  55  * port: (optional or required for all ports on all installed cards)
  56  *      HFC-4S/HFC-8S only bits:
  57  *      Bit 0     = 0x001 = Use master clock for this S/T interface
  58  *                          (ony once per chip).
  59  *      Bit 1     = 0x002 = transmitter line setup (non capacitive mode)
  60  *                          Don't use this unless you know what you are doing!
  61  *      Bit 2     = 0x004 = Disable E-channel. (No E-channel processing)
  62  *      example: 0x0001,0x0000,0x0000,0x0000 one HFC-4S with master clock
  63  *               received from port 1
  64  *
  65  *      HFC-E1 only bits:
  66  *      Bit 0     = 0x0001 = interface: 0=copper, 1=optical
  67  *      Bit 1     = 0x0002 = reserved (later for 32 B-channels transparent mode)
  68  *      Bit 2     = 0x0004 = Report LOS
  69  *      Bit 3     = 0x0008 = Report AIS
  70  *      Bit 4     = 0x0010 = Report SLIP
  71  *      Bit 5     = 0x0020 = Report RDI
  72  *      Bit 8     = 0x0100 = Turn off CRC-4 Multiframe Mode, use double frame
  73  *                           mode instead.
  74  *      Bit 9     = 0x0200 = Force get clock from interface, even in NT mode.
  75  * or   Bit 10    = 0x0400 = Force put clock to interface, even in TE mode.
  76  *      Bit 11    = 0x0800 = Use direct RX clock for PCM sync rather than PLL.
  77  *                           (E1 only)
  78  *      Bit 12-13 = 0xX000 = elastic jitter buffer (1-3), Set both bits to 0
  79  *                           for default.
  80  * (all other bits are reserved and shall be 0)
  81  *
  82  * debug:
  83  *      NOTE: only one debug value must be given for all cards
  84  *      enable debugging (see hfc_multi.h for debug options)
  85  *
  86  * poll:
  87  *      NOTE: only one poll value must be given for all cards
  88  *      Give the number of samples for each fifo process.
  89  *      By default 128 is used. Decrease to reduce delay, increase to
  90  *      reduce cpu load. If unsure, don't mess with it!
  91  *      Valid is 8, 16, 32, 64, 128, 256.
  92  *
  93  * pcm:
  94  *      NOTE: only one pcm value must be given for every card.
  95  *      The PCM bus id tells the mISDNdsp module about the connected PCM bus.
  96  *      By default (0), the PCM bus id is 100 for the card that is PCM master.
  97  *      If multiple cards are PCM master (because they are not interconnected),
  98  *      each card with PCM master will have increasing PCM id.
  99  *      All PCM busses with the same ID are expected to be connected and have
 100  *      common time slots slots.
 101  *      Only one chip of the PCM bus must be master, the others slave.
 102  *      -1 means no support of PCM bus not even.
 103  *      Omit this value, if all cards are interconnected or none is connected.
 104  *      If unsure, don't give this parameter.
 105  *
 106  * dslot:
 107  *      NOTE: only one poll value must be given for every card.
 108  *      Also this value must be given for non-E1 cards. If omitted, the E1
 109  *      card has D-channel on time slot 16, which is default.
 110  *      If 1..15 or 17..31, an alternate time slot is used for D-channel.
 111  *      In this case, the application must be able to handle this.
 112  *      If -1 is given, the D-channel is disabled and all 31 slots can be used
 113  *      for B-channel. (only for specific applications)
 114  *      If you don't know how to use it, you don't need it!
 115  *
 116  * iomode:
 117  *      NOTE: only one mode value must be given for every card.
 118  *      -> See hfc_multi.h for HFC_IO_MODE_* values
 119  *      By default, the IO mode is pci memory IO (MEMIO).
 120  *      Some cards requre specific IO mode, so it cannot be changed.
 121  *      It may be usefull to set IO mode to register io (REGIO) to solve
 122  *      PCI bridge problems.
 123  *      If unsure, don't give this parameter.
 124  *
 125  * clockdelay_nt:
 126  *      NOTE: only one clockdelay_nt value must be given once for all cards.
 127  *      Give the value of the clock control register (A_ST_CLK_DLY)
 128  *      of the S/T interfaces in NT mode.
 129  *      This register is needed for the TBR3 certification, so don't change it.
 130  *
 131  * clockdelay_te:
 132  *      NOTE: only one clockdelay_te value must be given once
 133  *      Give the value of the clock control register (A_ST_CLK_DLY)
 134  *      of the S/T interfaces in TE mode.
 135  *      This register is needed for the TBR3 certification, so don't change it.
 136  */
 137
 138 /*
 139  * debug register access (never use this, it will flood your system log)
 140  * #define HFC_REGISTER_DEBUG
 141  */
 142
 143 static const char *hfcmulti_revision = "2.02";
 144
 145 #include <linux/module.h>
 146 #include <linux/pci.h>
 147 #include <linux/delay.h>
 148 #include <linux/mISDNhw.h>
 149 #include <linux/mISDNdsp.h>
 150
 151 /*
 152 #define IRQCOUNT_DEBUG
 153 #define IRQ_DEBUG
 154 */
 155
 156 #include "hfc_multi.h"
 157 #ifdef ECHOPREP
 158 #include "gaintab.h"
 159 #endif
 160
 161 #define MAX_CARDS       8
 162 #define MAX_PORTS       (8 * MAX_CARDS)
 163
 164 static LIST_HEAD(HFClist);
 165 static spinlock_t HFClock; /* global hfc list lock */
 166
 167 static void ph_state_change(struct dchannel *);
 168 static void (*hfc_interrupt)(void);
 169 static void (*register_interrupt)(void);
 170 static int (*unregister_interrupt)(void);
 171 static int interrupt_registered;
 172
 173 static struct hfc_multi *syncmaster;
 174 static int plxsd_master; /* if we have a master card (yet) */
 175 static spinlock_t plx_lock; /* may not acquire other lock inside */
 176
 177 #define TYP_E1          1
 178 #define TYP_4S          4
 179 #define TYP_8S          8
 180
 181 static int poll_timer = 6;      /* default = 128 samples = 16ms */
 182 /* number of POLL_TIMER interrupts for G2 timeout (ca 1s) */
 183 static int nt_t1_count[] = { 3840, 1920, 960, 480, 240, 120, 60, 30  };
 184 #define CLKDEL_TE       0x0f    /* CLKDEL in TE mode */
 185 #define CLKDEL_NT       0x6c    /* CLKDEL in NT mode
 186                                    (0x60 MUST be included!) */
 187 static u_char silence = 0xff;   /* silence by LAW */
 188
 189 #define DIP_4S  0x1             /* DIP Switches for Beronet 1S/2S/4S cards */
 190 #define DIP_8S  0x2             /* DIP Switches for Beronet 8S+ cards */
 191 #define DIP_E1  0x3             /* DIP Switches for Beronet E1 cards */
 192
 193 /*
 194  * module stuff
 195  */
 196
 197 static uint     type[MAX_CARDS];
 198 static uint     pcm[MAX_CARDS];
 199 static uint     dslot[MAX_CARDS];
 200 static uint     iomode[MAX_CARDS];
 201 static uint     port[MAX_PORTS];
 202 static uint     debug;
 203 static uint     poll;
 204 static uint     timer;
 205 static uint     clockdelay_te = CLKDEL_TE;
 206 static uint     clockdelay_nt = CLKDEL_NT;
 207
 208 static int      HFC_cnt, Port_cnt, PCM_cnt = 99;
 209
 210 MODULE_AUTHOR("Andreas Eversberg");
 211 MODULE_LICENSE("GPL");
 212 module_param(debug, uint, S_IRUGO | S_IWUSR);
 213 module_param(poll, uint, S_IRUGO | S_IWUSR);
 214 module_param(timer, uint, S_IRUGO | S_IWUSR);
 215 module_param(clockdelay_te, uint, S_IRUGO | S_IWUSR);
 216 module_param(clockdelay_nt, uint, S_IRUGO | S_IWUSR);
 217 module_param_array(type, uint, NULL, S_IRUGO | S_IWUSR);
 218 module_param_array(pcm, uint, NULL, S_IRUGO | S_IWUSR);
 219 module_param_array(dslot, uint, NULL, S_IRUGO | S_IWUSR);
 220 module_param_array(iomode, uint, NULL, S_IRUGO | S_IWUSR);
 221 module_param_array(port, uint, NULL, S_IRUGO | S_IWUSR);
 222
 223 #ifdef HFC_REGISTER_DEBUG
 224 #define HFC_outb(hc, reg, val) \
 225         (hc->HFC_outb(hc, reg, val, __func__, __LINE__))
 226 #define HFC_outb_nodebug(hc, reg, val) \
 227         (hc->HFC_outb_nodebug(hc, reg, val, __func__, __LINE__))
 228 #define HFC_inb(hc, reg) \
 229         (hc->HFC_inb(hc, reg, __func__, __LINE__))
 230 #define HFC_inb_nodebug(hc, reg) \
 231         (hc->HFC_inb_nodebug(hc, reg, __func__, __LINE__))
 232 #define HFC_inw(hc, reg) \
 233         (hc->HFC_inw(hc, reg, __func__, __LINE__))
 234 #define HFC_inw_nodebug(hc, reg) \
 235         (hc->HFC_inw_nodebug(hc, reg, __func__, __LINE__))
 236 #define HFC_wait(hc) \
 237         (hc->HFC_wait(hc, __func__, __LINE__))
 238 #define HFC_wait_nodebug(hc) \
 239         (hc->HFC_wait_nodebug(hc, __func__, __LINE__))
 240 #else
 241 #define HFC_outb(hc, reg, val)          (hc->HFC_outb(hc, reg, val))
 242 #define HFC_outb_nodebug(hc, reg, val)  (hc->HFC_outb_nodebug(hc, reg, val))
 243 #define HFC_inb(hc, reg)                (hc->HFC_inb(hc, reg))
 244 #define HFC_inb_nodebug(hc, reg)        (hc->HFC_inb_nodebug(hc, reg))
 245 #define HFC_inw(hc, reg)                (hc->HFC_inw(hc, reg))
 246 #define HFC_inw_nodebug(hc, reg)        (hc->HFC_inw_nodebug(hc, reg))
 247 #define HFC_wait(hc)                    (hc->HFC_wait(hc))
 248 #define HFC_wait_nodebug(hc)            (hc->HFC_wait_nodebug(hc))
 249 #endif
 250
 251 /* HFC_IO_MODE_PCIMEM */
 252 static void
 253 #ifdef HFC_REGISTER_DEBUG
 254 HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val,
 255                 const char *function, int line)
 256 #else
 257 HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val)
 258 #endif
 259 {
 260         writeb(val, (hc->pci_membase)+reg);
 261 }
 262 static u_char
 263 #ifdef HFC_REGISTER_DEBUG
 264 HFC_inb_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line)
 265 #else
 266 HFC_inb_pcimem(struct hfc_multi *hc, u_char reg)
 267 #endif
 268 {
 269         return readb((hc->pci_membase)+reg);
 270 }
 271 static u_short
 272 #ifdef HFC_REGISTER_DEBUG
 273 HFC_inw_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line)
 274 #else
 275 HFC_inw_pcimem(struct hfc_multi *hc, u_char reg)
 276 #endif
 277 {
 278         return readw((hc->pci_membase)+reg);
 279 }
 280 static void
 281 #ifdef HFC_REGISTER_DEBUG
 282 HFC_wait_pcimem(struct hfc_multi *hc, const char *function, int line)
 283 #else
 284 HFC_wait_pcimem(struct hfc_multi *hc)
 285 #endif
 286 {
 287         while (readb((hc->pci_membase)+R_STATUS) & V_BUSY);
 288 }
 289
 290 /* HFC_IO_MODE_REGIO */
 291 static void
 292 #ifdef HFC_REGISTER_DEBUG
 293 HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val,
 294         const char *function, int line)
 295 #else
 296 HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val)
 297 #endif
 298 {
 299         outb(reg, (hc->pci_iobase)+4);
 300         outb(val, hc->pci_iobase);
 301 }
 302 static u_char
 303 #ifdef HFC_REGISTER_DEBUG
 304 HFC_inb_regio(struct hfc_multi *hc, u_char reg, const char *function, int line)
 305 #else
 306 HFC_inb_regio(struct hfc_multi *hc, u_char reg)
 307 #endif
 308 {
 309         outb(reg, (hc->pci_iobase)+4);
 310         return inb(hc->pci_iobase);
 311 }
 312 static u_short
 313 #ifdef HFC_REGISTER_DEBUG
 314 HFC_inw_regio(struct hfc_multi *hc, u_char reg, const char *function, int line)
 315 #else
 316 HFC_inw_regio(struct hfc_multi *hc, u_char reg)
 317 #endif
 318 {
 319         outb(reg, (hc->pci_iobase)+4);
 320         return inw(hc->pci_iobase);
 321 }
 322 static void
 323 #ifdef HFC_REGISTER_DEBUG
 324 HFC_wait_regio(struct hfc_multi *hc, const char *function, int line)
 325 #else
 326 HFC_wait_regio(struct hfc_multi *hc)
 327 #endif
 328 {
 329         outb(R_STATUS, (hc->pci_iobase)+4);
 330         while (inb(hc->pci_iobase) & V_BUSY);
 331 }
 332
 333 #ifdef HFC_REGISTER_DEBUG
 334 static void
 335 HFC_outb_debug(struct hfc_multi *hc, u_char reg, u_char val,
 336                 const char *function, int line)
 337 {
 338         char regname[256] = "", bits[9] = "xxxxxxxx";
 339         int i;
 340
 341         i = -1;
 342         while (hfc_register_names[++i].name) {
 343                 if (hfc_register_names[i].reg == reg)
 344                         strcat(regname, hfc_register_names[i].name);
 345         }
 346         if (regname[0] == '\0')
 347                 strcpy(regname, "register");
 348
 349         bits[7] = '0'+(!!(val&1));
 350         bits[6] = '0'+(!!(val&2));
 351         bits[5] = '0'+(!!(val&4));
 352         bits[4] = '0'+(!!(val&8));
 353         bits[3] = '0'+(!!(val&16));
 354         bits[2] = '0'+(!!(val&32));
 355         bits[1] = '0'+(!!(val&64));
 356         bits[0] = '0'+(!!(val&128));
 357         printk(KERN_DEBUG
 358             "HFC_outb(chip %d, %02x=%s, 0x%02x=%s); in %s() line %d\n",
 359             hc->id, reg, regname, val, bits, function, line);
 360         HFC_outb_nodebug(hc, reg, val);
 361 }
 362 static u_char
 363 HFC_inb_debug(struct hfc_multi *hc, u_char reg, const char *function, int line)
 364 {
 365         char regname[256] = "", bits[9] = "xxxxxxxx";
 366         u_char val = HFC_inb_nodebug(hc, reg);
 367         int i;
 368
 369         i = 0;
 370         while (hfc_register_names[i++].name)
 371                 ;
 372         while (hfc_register_names[++i].name) {
 373                 if (hfc_register_names[i].reg == reg)
 374                         strcat(regname, hfc_register_names[i].name);
 375         }
 376         if (regname[0] == '\0')
 377                 strcpy(regname, "register");
 378
 379         bits[7] = '0'+(!!(val&1));
 380         bits[6] = '0'+(!!(val&2));
 381         bits[5] = '0'+(!!(val&4));
 382         bits[4] = '0'+(!!(val&8));
 383         bits[3] = '0'+(!!(val&16));
 384         bits[2] = '0'+(!!(val&32));
 385         bits[1] = '0'+(!!(val&64));
 386         bits[0] = '0'+(!!(val&128));
 387         printk(KERN_DEBUG
 388             "HFC_inb(chip %d, %02x=%s) = 0x%02x=%s; in %s() line %d\n",
 389             hc->id, reg, regname, val, bits, function, line);
 390         return val;
 391 }
 392 static u_short
 393 HFC_inw_debug(struct hfc_multi *hc, u_char reg, const char *function, int line)
 394 {
 395         char regname[256] = "";
 396         u_short val = HFC_inw_nodebug(hc, reg);
 397         int i;
 398
 399         i = 0;
 400         while (hfc_register_names[i++].name)
 401                 ;
 402         while (hfc_register_names[++i].name) {
 403                 if (hfc_register_names[i].reg == reg)
 404                         strcat(regname, hfc_register_names[i].name);
 405         }
 406         if (regname[0] == '\0')
 407                 strcpy(regname, "register");
 408
 409         printk(KERN_DEBUG
 410             "HFC_inw(chip %d, %02x=%s) = 0x%04x; in %s() line %d\n",
 411             hc->id, reg, regname, val, function, line);
 412         return val;
 413 }
 414 static void
 415 HFC_wait_debug(struct hfc_multi *hc, const char *function, int line)
 416 {
 417         printk(KERN_DEBUG "HFC_wait(chip %d); in %s() line %d\n",
 418             hc->id, function, line);
 419         HFC_wait_nodebug(hc);
 420 }
 421 #endif
 422
 423 /* write fifo data (REGIO) */
 424 static void
 425 write_fifo_regio(struct hfc_multi *hc, u_char *data, int len)
 426 {
 427         outb(A_FIFO_DATA0, (hc->pci_iobase)+4);
 428         while (len>>2) {
 429                 outl(cpu_to_le32(*(u32 *)data), hc->pci_iobase);
 430                 data += 4;
 431                 len -= 4;
 432         }
 433         while (len>>1) {
 434                 outw(cpu_to_le16(*(u16 *)data), hc->pci_iobase);
 435                 data += 2;
 436                 len -= 2;
 437         }
 438         while (len) {
 439                 outb(*data, hc->pci_iobase);
 440                 data++;
 441                 len--;
 442         }
 443 }
 444 /* write fifo data (PCIMEM) */
 445 static void
 446 write_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len)
 447 {
 448         while (len>>2) {
 449                 writel(cpu_to_le32(*(u32 *)data),
 450                         hc->pci_membase + A_FIFO_DATA0);
 451                 data += 4;
 452                 len -= 4;
 453         }
 454         while (len>>1) {
 455                 writew(cpu_to_le16(*(u16 *)data),
 456                         hc->pci_membase + A_FIFO_DATA0);
 457                 data += 2;
 458                 len -= 2;
 459         }
 460         while (len) {
 461                 writeb(*data, hc->pci_membase + A_FIFO_DATA0);
 462                 data++;
 463                 len--;
 464         }
 465 }
 466 /* read fifo data (REGIO) */
 467 static void
 468 read_fifo_regio(struct hfc_multi *hc, u_char *data, int len)
 469 {
 470         outb(A_FIFO_DATA0, (hc->pci_iobase)+4);
 471         while (len>>2) {
 472                 *(u32 *)data = le32_to_cpu(inl(hc->pci_iobase));
 473                 data += 4;
 474                 len -= 4;
 475         }
 476         while (len>>1) {
 477                 *(u16 *)data = le16_to_cpu(inw(hc->pci_iobase));
 478                 data += 2;
 479                 len -= 2;
 480         }
 481         while (len) {
 482                 *data = inb(hc->pci_iobase);
 483                 data++;
 484                 len--;
 485         }
 486 }
 487
 488 /* read fifo data (PCIMEM) */
 489 static void
 490 read_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len)
 491 {
 492         while (len>>2) {
 493                 *(u32 *)data =
 494                         le32_to_cpu(readl(hc->pci_membase + A_FIFO_DATA0));
 495                 data += 4;
 496                 len -= 4;
 497         }
 498         while (len>>1) {
 499                 *(u16 *)data =
 500                         le16_to_cpu(readw(hc->pci_membase + A_FIFO_DATA0));
 501                 data += 2;
 502                 len -= 2;
 503         }
 504         while (len) {
 505                 *data = readb(hc->pci_membase + A_FIFO_DATA0);
 506                 data++;
 507                 len--;
 508         }
 509 }
 510
 511
 512 static void
 513 enable_hwirq(struct hfc_multi *hc)
 514 {
 515         hc->hw.r_irq_ctrl |= V_GLOB_IRQ_EN;
 516         HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl);
 517 }
 518
 519 static void
 520 disable_hwirq(struct hfc_multi *hc)
 521 {
 522         hc->hw.r_irq_ctrl &= ~((u_char)V_GLOB_IRQ_EN);
 523         HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl);
 524 }
 525
 526 #define NUM_EC 2
 527 #define MAX_TDM_CHAN 32
 528
 529
 530 inline void
 531 enablepcibridge(struct hfc_multi *c)
 532 {
 533         HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); /* was _io before */
 534 }
 535
 536 inline void
 537 disablepcibridge(struct hfc_multi *c)
 538 {
 539         HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x2); /* was _io before */
 540 }
 541
 542 inline unsigned char
 543 readpcibridge(struct hfc_multi *hc, unsigned char address)
 544 {
 545         unsigned short cipv;
 546         unsigned char data;
 547
 548         if (!hc->pci_iobase)
 549                 return 0;
 550
 551         /* slow down a PCI read access by 1 PCI clock cycle */
 552         HFC_outb(hc, R_CTRL, 0x4); /*was _io before*/
 553
 554         if (address == 0)
 555                 cipv = 0x4000;
 556         else
 557                 cipv = 0x5800;
 558
 559         /* select local bridge port address by writing to CIP port */
 560         /* data = HFC_inb(c, cipv); * was _io before */
 561         outw(cipv, hc->pci_iobase + 4);
 562         data = inb(hc->pci_iobase);
 563
 564         /* restore R_CTRL for normal PCI read cycle speed */
 565         HFC_outb(hc, R_CTRL, 0x0); /* was _io before */
 566
 567         return data;
 568 }
 569
 570 inline void
 571 writepcibridge(struct hfc_multi *hc, unsigned char address, unsigned char data)
 572 {
 573         unsigned short cipv;
 574         unsigned int datav;
 575
 576         if (!hc->pci_iobase)
 577                 return;
 578
 579         if (address == 0)
 580                 cipv = 0x4000;
 581         else
 582                 cipv = 0x5800;
 583
 584         /* select local bridge port address by writing to CIP port */
 585         outw(cipv, hc->pci_iobase + 4);
 586         /* define a 32 bit dword with 4 identical bytes for write sequence */
 587         datav = data | ((__u32) data << 8) | ((__u32) data << 16) |
 588             ((__u32) data << 24);
 589
 590         /*
 591          * write this 32 bit dword to the bridge data port
 592          * this will initiate a write sequence of up to 4 writes to the same
 593          * address on the local bus interface the number of write accesses
 594          * is undefined but >=1 and depends on the next PCI transaction
 595          * during write sequence on the local bus
 596          */
 597         outl(datav, hc->pci_iobase);
 598 }
 599
 600 inline void
 601 cpld_set_reg(struct hfc_multi *hc, unsigned char reg)
 602 {
 603         /* Do data pin read low byte */
 604         HFC_outb(hc, R_GPIO_OUT1, reg);
 605 }
 606
 607 inline void
 608 cpld_write_reg(struct hfc_multi *hc, unsigned char reg, unsigned char val)
 609 {
 610         cpld_set_reg(hc, reg);
 611
 612         enablepcibridge(hc);
 613         writepcibridge(hc, 1, val);
 614         disablepcibridge(hc);
 615
 616         return;
 617 }
 618
 619 inline unsigned char
 620 cpld_read_reg(struct hfc_multi *hc, unsigned char reg)
 621 {
 622         unsigned char bytein;
 623
 624         cpld_set_reg(hc, reg);
 625
 626         /* Do data pin read low byte */
 627         HFC_outb(hc, R_GPIO_OUT1, reg);
 628
 629         enablepcibridge(hc);
 630         bytein = readpcibridge(hc, 1);
 631         disablepcibridge(hc);
 632
 633         return bytein;
 634 }
 635
 636 inline void
 637 vpm_write_address(struct hfc_multi *hc, unsigned short addr)
 638 {
 639         cpld_write_reg(hc, 0, 0xff & addr);
 640         cpld_write_reg(hc, 1, 0x01 & (addr >> 8));
 641 }
 642
 643 inline unsigned short
 644 vpm_read_address(struct hfc_multi *c)
 645 {
 646         unsigned short addr;
 647         unsigned short highbit;
 648
 649         addr = cpld_read_reg(c, 0);
 650         highbit = cpld_read_reg(c, 1);
 651
 652         addr = addr | (highbit << 8);
 653
 654         return addr & 0x1ff;
 655 }
 656
 657 inline unsigned char
 658 vpm_in(struct hfc_multi *c, int which, unsigned short addr)
 659 {
 660         unsigned char res;
 661
 662         vpm_write_address(c, addr);
 663
 664         if (!which)
 665                 cpld_set_reg(c, 2);
 666         else
 667                 cpld_set_reg(c, 3);
 668
 669         enablepcibridge(c);
 670         res = readpcibridge(c, 1);
 671         disablepcibridge(c);
 672
 673         cpld_set_reg(c, 0);
 674
 675         return res;
 676 }
 677
 678 inline void
 679 vpm_out(struct hfc_multi *c, int which, unsigned short addr,
 680     unsigned char data)
 681 {
 682         vpm_write_address(c, addr);
 683
 684         enablepcibridge(c);
 685
 686         if (!which)
 687                 cpld_set_reg(c, 2);
 688         else
 689                 cpld_set_reg(c, 3);
 690
 691         writepcibridge(c, 1, data);
 692
 693         cpld_set_reg(c, 0);
 694
 695         disablepcibridge(c);
 696
 697         {
 698         unsigned char regin;
 699         regin = vpm_in(c, which, addr);
 700         if (regin != data)
 701                 printk(KERN_DEBUG "Wrote 0x%x to register 0x%x but got back "
 702                         "0x%x\n", data, addr, regin);
 703         }
 704
 705 }
 706
 707
 708 static void
 709 vpm_init(struct hfc_multi *wc)
 710 {
 711         unsigned char reg;
 712         unsigned int mask;
 713         unsigned int i, x, y;
 714         unsigned int ver;
 715
 716         for (x = 0; x < NUM_EC; x++) {
 717                 /* Setup GPIO's */
 718                 if (!x) {
 719                         ver = vpm_in(wc, x, 0x1a0);
 720                         printk(KERN_DEBUG "VPM: Chip %d: ver %02x\n", x, ver);
 721                 }
 722
 723                 for (y = 0; y < 4; y++) {
 724                         vpm_out(wc, x, 0x1a8 + y, 0x00); /* GPIO out */
 725                         vpm_out(wc, x, 0x1ac + y, 0x00); /* GPIO dir */
 726                         vpm_out(wc, x, 0x1b0 + y, 0x00); /* GPIO sel */
 727                 }
 728
 729                 /* Setup TDM path - sets fsync and tdm_clk as inputs */
 730                 reg = vpm_in(wc, x, 0x1a3); /* misc_con */
 731                 vpm_out(wc, x, 0x1a3, reg & ~2);
 732
 733                 /* Setup Echo length (256 taps) */
 734                 vpm_out(wc, x, 0x022, 1);
 735                 vpm_out(wc, x, 0x023, 0xff);
 736
 737                 /* Setup timeslots */
 738                 vpm_out(wc, x, 0x02f, 0x00);
 739                 mask = 0x02020202 << (x * 4);
 740
 741                 /* Setup the tdm channel masks for all chips */
 742                 for (i = 0; i < 4; i++)
 743                         vpm_out(wc, x, 0x33 - i, (mask >> (i << 3)) & 0xff);
 744
 745                 /* Setup convergence rate */
 746                 printk(KERN_DEBUG "VPM: A-law mode\n");
 747                 reg = 0x00 | 0x10 | 0x01;
 748                 vpm_out(wc, x, 0x20, reg);
 749                 printk(KERN_DEBUG "VPM reg 0x20 is %x\n", reg);
 750                 /*vpm_out(wc, x, 0x20, (0x00 | 0x08 | 0x20 | 0x10)); */
 751
 752                 vpm_out(wc, x, 0x24, 0x02);
 753                 reg = vpm_in(wc, x, 0x24);
 754                 printk(KERN_DEBUG "NLP Thresh is set to %d (0x%x)\n", reg, reg);
 755
 756                 /* Initialize echo cans */
 757                 for (i = 0; i < MAX_TDM_CHAN; i++) {
 758                         if (mask & (0x00000001 << i))
 759                                 vpm_out(wc, x, i, 0x00);
 760                 }
 761
 762                 /*
 763                  * ARM arch at least disallows a udelay of
 764                  * more than 2ms... it gives a fake "__bad_udelay"
 765                  * reference at link-time.
 766                  * long delays in kernel code are pretty sucky anyway
 767                  * for now work around it using 5 x 2ms instead of 1 x 10ms
 768                  */
 769
 770                 udelay(2000);
 771                 udelay(2000);
 772                 udelay(2000);
 773                 udelay(2000);
 774                 udelay(2000);
 775
 776                 /* Put in bypass mode */
 777                 for (i = 0; i < MAX_TDM_CHAN; i++) {
 778                         if (mask & (0x00000001 << i))
 779                                 vpm_out(wc, x, i, 0x01);
 780                 }
 781
 782                 /* Enable bypass */
 783                 for (i = 0; i < MAX_TDM_CHAN; i++) {
 784                         if (mask & (0x00000001 << i))
 785                                 vpm_out(wc, x, 0x78 + i, 0x01);
 786                 }
 787
 788         }
 789 }
 790
 791 #ifdef UNUSED
 792 static void
 793 vpm_check(struct hfc_multi *hctmp)
 794 {
 795         unsigned char gpi2;
 796
 797         gpi2 = HFC_inb(hctmp, R_GPI_IN2);
 798
 799         if ((gpi2 & 0x3) != 0x3)
 800                 printk(KERN_DEBUG "Got interrupt 0x%x from VPM!\n", gpi2);
 801 }
 802 #endif /* UNUSED */
 803
 804
 805 /*
 806  * Interface to enable/disable the HW Echocan
 807  *
 808  * these functions are called within a spin_lock_irqsave on
 809  * the channel instance lock, so we are not disturbed by irqs
 810  *
 811  * we can later easily change the interface to make  other
 812  * things configurable, for now we configure the taps
 813  *
 814  */
 815
 816 static void
 817 vpm_echocan_on(struct hfc_multi *hc, int ch, int taps)
 818 {
 819         unsigned int timeslot;
 820         unsigned int unit;
 821         struct bchannel *bch = hc->chan[ch].bch;
 822 #ifdef TXADJ
 823         int txadj = -4;
 824         struct sk_buff *skb;
 825 #endif
 826         if (hc->chan[ch].protocol != ISDN_P_B_RAW)
 827                 return;
 828
 829         if (!bch)
 830                 return;
 831
 832 #ifdef TXADJ
 833         skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX,
 834                 sizeof(int), &txadj, GFP_ATOMIC);
 835         if (skb)
 836                 recv_Bchannel_skb(bch, skb);
 837 #endif
 838
 839         timeslot = ((ch/4)*8) + ((ch%4)*4) + 1;
 840         unit = ch % 4;
 841
 842         printk(KERN_NOTICE "vpm_echocan_on called taps [%d] on timeslot %d\n",
 843             taps, timeslot);
 844
 845         vpm_out(hc, unit, timeslot, 0x7e);
 846 }
 847
 848 static void
 849 vpm_echocan_off(struct hfc_multi *hc, int ch)
 850 {
 851         unsigned int timeslot;
 852         unsigned int unit;
 853         struct bchannel *bch = hc->chan[ch].bch;
 854 #ifdef TXADJ
 855         int txadj = 0;
 856         struct sk_buff *skb;
 857 #endif
 858
 859         if (hc->chan[ch].protocol != ISDN_P_B_RAW)
 860                 return;
 861
 862         if (!bch)
 863                 return;
 864
 865 #ifdef TXADJ
 866         skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX,
 867                 sizeof(int), &txadj, GFP_ATOMIC);
 868         if (skb)
 869                 recv_Bchannel_skb(bch, skb);
 870 #endif
 871
 872         timeslot = ((ch/4)*8) + ((ch%4)*4) + 1;
 873         unit = ch % 4;
 874
 875         printk(KERN_NOTICE "vpm_echocan_off called on timeslot %d\n",
 876             timeslot);
 877         /* FILLME */
 878         vpm_out(hc, unit, timeslot, 0x01);
 879 }
 880
 881
 882 /*
 883  * Speech Design resync feature
 884  * NOTE: This is called sometimes outside interrupt handler.
 885  * We must lock irqsave, so no other interrupt (other card) will occurr!
 886  * Also multiple interrupts may nest, so must lock each access (lists, card)!
 887  */
 888 static inline void
 889 hfcmulti_resync(struct hfc_multi *locked, struct hfc_multi *newmaster, int rm)
 890 {
 891         struct hfc_multi *hc, *next, *pcmmaster = NULL;
 892         void __iomem *plx_acc_32;
 893         u_int pv;
 894         u_long flags;
 895
 896         spin_lock_irqsave(&HFClock, flags);
 897         spin_lock(&plx_lock); /* must be locked inside other locks */
 898
 899         if (debug & DEBUG_HFCMULTI_PLXSD)
 900                 printk(KERN_DEBUG "%s: RESYNC(syncmaster=0x%p)\n",
 901                         __func__, syncmaster);
 902
 903         /* select new master */
 904         if (newmaster) {
 905                 if (debug & DEBUG_HFCMULTI_PLXSD)
 906                         printk(KERN_DEBUG "using provided controller\n");
 907         } else {
 908                 list_for_each_entry_safe(hc, next, &HFClist, list) {
 909                         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
 910                                 if (hc->syncronized) {
 911                                         newmaster = hc;
 912                                         break;
 913                                 }
 914                         }
 915                 }
 916         }
 917
 918         /* Disable sync of all cards */
 919         list_for_each_entry_safe(hc, next, &HFClist, list) {
 920                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
 921                         plx_acc_32 = hc->plx_membase + PLX_GPIOC;
 922                         pv = readl(plx_acc_32);
 923                         pv &= ~PLX_SYNC_O_EN;
 924                         writel(pv, plx_acc_32);
 925                         if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
 926                                 pcmmaster = hc;
 927                                 if (hc->type == 1) {
 928                                         if (debug & DEBUG_HFCMULTI_PLXSD)
 929                                                 printk(KERN_DEBUG
 930                                                         "Schedule SYNC_I\n");
 931                                         hc->e1_resync |= 1; /* get SYNC_I */
 932                                 }
 933                         }
 934                 }
 935         }
 936
 937         if (newmaster) {
 938                 hc = newmaster;
 939                 if (debug & DEBUG_HFCMULTI_PLXSD)
 940                         printk(KERN_DEBUG "id=%d (0x%p) = syncronized with "
 941                                 "interface.\n", hc->id, hc);
 942                 /* Enable new sync master */
 943                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
 944                 pv = readl(plx_acc_32);
 945                 pv |= PLX_SYNC_O_EN;
 946                 writel(pv, plx_acc_32);
 947                 /* switch to jatt PLL, if not disabled by RX_SYNC */
 948                 if (hc->type == 1 && !test_bit(HFC_CHIP_RX_SYNC, &hc->chip)) {
 949                         if (debug & DEBUG_HFCMULTI_PLXSD)
 950                                 printk(KERN_DEBUG "Schedule jatt PLL\n");
 951                         hc->e1_resync |= 2; /* switch to jatt */
 952                 }
 953         } else {
 954                 if (pcmmaster) {
 955                         hc = pcmmaster;
 956                         if (debug & DEBUG_HFCMULTI_PLXSD)
 957                                 printk(KERN_DEBUG
 958                                         "id=%d (0x%p) = PCM master syncronized "
 959                                         "with QUARTZ\n", hc->id, hc);
 960                         if (hc->type == 1) {
 961                                 /* Use the crystal clock for the PCM
 962                                    master card */
 963                                 if (debug & DEBUG_HFCMULTI_PLXSD)
 964                                         printk(KERN_DEBUG
 965                                             "Schedule QUARTZ for HFC-E1\n");
 966                                 hc->e1_resync |= 4; /* switch quartz */
 967                         } else {
 968                                 if (debug & DEBUG_HFCMULTI_PLXSD)
 969                                         printk(KERN_DEBUG
 970                                             "QUARTZ is automatically "
 971                                             "enabled by HFC-%dS\n", hc->type);
 972                         }
 973                         plx_acc_32 = hc->plx_membase + PLX_GPIOC;
 974                         pv = readl(plx_acc_32);
 975                         pv |= PLX_SYNC_O_EN;
 976                         writel(pv, plx_acc_32);
 977                 } else
 978                         if (!rm)
 979                                 printk(KERN_ERR "%s no pcm master, this MUST "
 980                                         "not happen!\n", __func__);
 981         }
 982         syncmaster = newmaster;
 983
 984         spin_unlock(&plx_lock);
 985         spin_unlock_irqrestore(&HFClock, flags);
 986 }
 987
 988 /* This must be called AND hc must be locked irqsave!!! */
 989 inline void
 990 plxsd_checksync(struct hfc_multi *hc, int rm)
 991 {
 992         if (hc->syncronized) {
 993                 if (syncmaster == NULL) {
 994                         if (debug & DEBUG_HFCMULTI_PLXSD)
 995                                 printk(KERN_WARNING "%s: GOT sync on card %d"
 996                                         " (id=%d)\n", __func__, hc->id + 1,
 997                                         hc->id);
 998                         hfcmulti_resync(hc, hc, rm);
 999                 }
1000         } else {
1001                 if (syncmaster == hc) {
1002                         if (debug & DEBUG_HFCMULTI_PLXSD)
1003                                 printk(KERN_WARNING "%s: LOST sync on card %d"
1004                                         " (id=%d)\n", __func__, hc->id + 1,
1005                                         hc->id);
1006                         hfcmulti_resync(hc, NULL, rm);
1007                 }
1008         }
1009 }
1010
1011
1012 /*
1013  * free hardware resources used by driver
1014  */
1015 static void
1016 release_io_hfcmulti(struct hfc_multi *hc)
1017 {
1018         void __iomem *plx_acc_32;
1019         u_int   pv;
1020         u_long  plx_flags;
1021
1022         if (debug & DEBUG_HFCMULTI_INIT)
1023                 printk(KERN_DEBUG "%s: entered\n", __func__);
1024
1025         /* soft reset also masks all interrupts */
1026         hc->hw.r_cirm |= V_SRES;
1027         HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1028         udelay(1000);
1029         hc->hw.r_cirm &= ~V_SRES;
1030         HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1031         udelay(1000); /* instead of 'wait' that may cause locking */
1032
1033         /* release Speech Design card, if PLX was initialized */
1034         if (test_bit(HFC_CHIP_PLXSD, &hc->chip) && hc->plx_membase) {
1035                 if (debug & DEBUG_HFCMULTI_PLXSD)
1036                         printk(KERN_DEBUG "%s: release PLXSD card %d\n",
1037                             __func__, hc->id + 1);
1038                 spin_lock_irqsave(&plx_lock, plx_flags);
1039                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1040                 writel(PLX_GPIOC_INIT, plx_acc_32);
1041                 pv = readl(plx_acc_32);
1042                 /* Termination off */
1043                 pv &= ~PLX_TERM_ON;
1044                 /* Disconnect the PCM */
1045                 pv |= PLX_SLAVE_EN_N;
1046                 pv &= ~PLX_MASTER_EN;
1047                 pv &= ~PLX_SYNC_O_EN;
1048                 /* Put the DSP in Reset */
1049                 pv &= ~PLX_DSP_RES_N;
1050                 writel(pv, plx_acc_32);
1051                 if (debug & DEBUG_HFCMULTI_INIT)
1052                         printk(KERN_WARNING "%s: PCM off: PLX_GPIO=%x\n",
1053                                 __func__, pv);
1054                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1055         }
1056
1057         /* disable memory mapped ports / io ports */
1058         test_and_clear_bit(HFC_CHIP_PLXSD, &hc->chip); /* prevent resync */
1059         pci_write_config_word(hc->pci_dev, PCI_COMMAND, 0);
1060         if (hc->pci_membase)
1061                 iounmap(hc->pci_membase);
1062         if (hc->plx_membase)
1063                 iounmap(hc->plx_membase);
1064         if (hc->pci_iobase)
1065                 release_region(hc->pci_iobase, 8);
1066
1067         if (hc->pci_dev) {
1068                 pci_disable_device(hc->pci_dev);
1069                 pci_set_drvdata(hc->pci_dev, NULL);
1070         }
1071         if (debug & DEBUG_HFCMULTI_INIT)
1072                 printk(KERN_DEBUG "%s: done\n", __func__);
1073 }
1074
1075 /*
1076  * function called to reset the HFC chip. A complete software reset of chip
1077  * and fifos is done. All configuration of the chip is done.
1078  */
1079
1080 static int
1081 init_chip(struct hfc_multi *hc)
1082 {
1083         u_long                  flags, val, val2 = 0, rev;
1084         int                     i, err = 0;
1085         u_char                  r_conf_en, rval;
1086         void __iomem            *plx_acc_32;
1087         u_int                   pv;
1088         u_long                  plx_flags, hfc_flags;
1089         int                     plx_count;
1090         struct hfc_multi        *pos, *next, *plx_last_hc;
1091
1092         spin_lock_irqsave(&hc->lock, flags);
1093         /* reset all registers */
1094         memset(&hc->hw, 0, sizeof(struct hfcm_hw));
1095
1096         /* revision check */
1097         if (debug & DEBUG_HFCMULTI_INIT)
1098                 printk(KERN_DEBUG "%s: entered\n", __func__);
1099         val = HFC_inb(hc, R_CHIP_ID)>>4;
1100         if (val != 0x8 && val != 0xc && val != 0xe) {
1101                 printk(KERN_INFO "HFC_multi: unknown CHIP_ID:%x\n", (u_int)val);
1102                 err = -EIO;
1103                 goto out;
1104         }
1105         rev = HFC_inb(hc, R_CHIP_RV);
1106         printk(KERN_INFO
1107             "HFC_multi: detected HFC with chip ID=0x%lx revision=%ld%s\n",
1108             val, rev, (rev == 0) ? " (old FIFO handling)" : "");
1109         if (rev == 0) {
1110                 test_and_set_bit(HFC_CHIP_REVISION0, &hc->chip);
1111                 printk(KERN_WARNING
1112                     "HFC_multi: NOTE: Your chip is revision 0, "
1113                     "ask Cologne Chip for update. Newer chips "
1114                     "have a better FIFO handling. Old chips "
1115                     "still work but may have slightly lower "
1116                     "HDLC transmit performance.\n");
1117         }
1118         if (rev > 1) {
1119                 printk(KERN_WARNING "HFC_multi: WARNING: This driver doesn't "
1120                     "consider chip revision = %ld. The chip / "
1121                     "bridge may not work.\n", rev);
1122         }
1123
1124         /* set s-ram size */
1125         hc->Flen = 0x10;
1126         hc->Zmin = 0x80;
1127         hc->Zlen = 384;
1128         hc->DTMFbase = 0x1000;
1129         if (test_bit(HFC_CHIP_EXRAM_128, &hc->chip)) {
1130                 if (debug & DEBUG_HFCMULTI_INIT)
1131                         printk(KERN_DEBUG "%s: changing to 128K extenal RAM\n",
1132                             __func__);
1133                 hc->hw.r_ctrl |= V_EXT_RAM;
1134                 hc->hw.r_ram_sz = 1;
1135                 hc->Flen = 0x20;
1136                 hc->Zmin = 0xc0;
1137                 hc->Zlen = 1856;
1138                 hc->DTMFbase = 0x2000;
1139         }
1140         if (test_bit(HFC_CHIP_EXRAM_512, &hc->chip)) {
1141                 if (debug & DEBUG_HFCMULTI_INIT)
1142                         printk(KERN_DEBUG "%s: changing to 512K extenal RAM\n",
1143                             __func__);
1144                 hc->hw.r_ctrl |= V_EXT_RAM;
1145                 hc->hw.r_ram_sz = 2;
1146                 hc->Flen = 0x20;
1147                 hc->Zmin = 0xc0;
1148                 hc->Zlen = 8000;
1149                 hc->DTMFbase = 0x2000;
1150         }
1151         hc->max_trans = poll << 1;
1152         if (hc->max_trans > hc->Zlen)
1153                 hc->max_trans = hc->Zlen;
1154
1155         /* Speech Design PLX bridge */
1156         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1157                 if (debug & DEBUG_HFCMULTI_PLXSD)
1158                         printk(KERN_DEBUG "%s: initializing PLXSD card %d\n",
1159                             __func__, hc->id + 1);
1160                 spin_lock_irqsave(&plx_lock, plx_flags);
1161                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1162                 writel(PLX_GPIOC_INIT, plx_acc_32);
1163                 pv = readl(plx_acc_32);
1164                 /* The first and the last cards are terminating the PCM bus */
1165                 pv |= PLX_TERM_ON; /* hc is currently the last */
1166                 /* Disconnect the PCM */
1167                 pv |= PLX_SLAVE_EN_N;
1168                 pv &= ~PLX_MASTER_EN;
1169                 pv &= ~PLX_SYNC_O_EN;
1170                 /* Put the DSP in Reset */
1171                 pv &= ~PLX_DSP_RES_N;
1172                 writel(pv, plx_acc_32);
1173                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1174                 if (debug & DEBUG_HFCMULTI_INIT)
1175                         printk(KERN_WARNING "%s: slave/term: PLX_GPIO=%x\n",
1176                                 __func__, pv);
1177                 /*
1178                  * If we are the 3rd PLXSD card or higher, we must turn
1179                  * termination of last PLXSD card off.
1180                  */
1181                 spin_lock_irqsave(&HFClock, hfc_flags);
1182                 plx_count = 0;
1183                 plx_last_hc = NULL;
1184                 list_for_each_entry_safe(pos, next, &HFClist, list) {
1185                         if (test_bit(HFC_CHIP_PLXSD, &pos->chip)) {
1186                                 plx_count++;
1187                                 if (pos != hc)
1188                                         plx_last_hc = pos;
1189                         }
1190                 }
1191                 if (plx_count >= 3) {
1192                         if (debug & DEBUG_HFCMULTI_PLXSD)
1193                                 printk(KERN_DEBUG "%s: card %d is between, so "
1194                                         "we disable termination\n",
1195                                     __func__, plx_last_hc->id + 1);
1196                         spin_lock_irqsave(&plx_lock, plx_flags);
1197                         plx_acc_32 = plx_last_hc->plx_membase + PLX_GPIOC;
1198                         pv = readl(plx_acc_32);
1199                         pv &= ~PLX_TERM_ON;
1200                         writel(pv, plx_acc_32);
1201                         spin_unlock_irqrestore(&plx_lock, plx_flags);
1202                         if (debug & DEBUG_HFCMULTI_INIT)
1203                             printk(KERN_WARNING "%s: term off: PLX_GPIO=%x\n",
1204                                         __func__, pv);
1205                 }
1206                 spin_unlock_irqrestore(&HFClock, hfc_flags);
1207                 hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */
1208         }
1209
1210         /* we only want the real Z2 read-pointer for revision > 0 */
1211         if (!test_bit(HFC_CHIP_REVISION0, &hc->chip))
1212                 hc->hw.r_ram_sz |= V_FZ_MD;
1213
1214         /* select pcm mode */
1215         if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
1216                 if (debug & DEBUG_HFCMULTI_INIT)
1217                         printk(KERN_DEBUG "%s: setting PCM into slave mode\n",
1218                             __func__);
1219         } else
1220         if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip) && !plxsd_master) {
1221                 if (debug & DEBUG_HFCMULTI_INIT)
1222                         printk(KERN_DEBUG "%s: setting PCM into master mode\n",
1223                             __func__);
1224                 hc->hw.r_pcm_md0 |= V_PCM_MD;
1225         } else {
1226                 if (debug & DEBUG_HFCMULTI_INIT)
1227                         printk(KERN_DEBUG "%s: performing PCM auto detect\n",
1228                             __func__);
1229         }
1230
1231         /* soft reset */
1232         HFC_outb(hc, R_CTRL, hc->hw.r_ctrl);
1233         HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
1234         HFC_outb(hc, R_FIFO_MD, 0);
1235         hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES | V_RLD_EPR;
1236         HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1237         udelay(100);
1238         hc->hw.r_cirm = 0;
1239         HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1240         udelay(100);
1241         HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
1242
1243         /* Speech Design PLX bridge pcm and sync mode */
1244         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1245                 spin_lock_irqsave(&plx_lock, plx_flags);
1246                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1247                 pv = readl(plx_acc_32);
1248                 /* Connect PCM */
1249                 if (hc->hw.r_pcm_md0 & V_PCM_MD) {
1250                         pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N;
1251                         pv |= PLX_SYNC_O_EN;
1252                         if (debug & DEBUG_HFCMULTI_INIT)
1253                                 printk(KERN_WARNING "%s: master: PLX_GPIO=%x\n",
1254                                         __func__, pv);
1255                 } else {
1256                         pv &= ~(PLX_MASTER_EN | PLX_SLAVE_EN_N);
1257                         pv &= ~PLX_SYNC_O_EN;
1258                         if (debug & DEBUG_HFCMULTI_INIT)
1259                                 printk(KERN_WARNING "%s: slave: PLX_GPIO=%x\n",
1260                                         __func__, pv);
1261                 }
1262                 writel(pv, plx_acc_32);
1263                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1264         }
1265
1266         /* PCM setup */
1267         HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x90);
1268         if (hc->slots == 32)
1269                 HFC_outb(hc, R_PCM_MD1, 0x00);
1270         if (hc->slots == 64)
1271                 HFC_outb(hc, R_PCM_MD1, 0x10);
1272         if (hc->slots == 128)
1273                 HFC_outb(hc, R_PCM_MD1, 0x20);
1274         HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0xa0);
1275         if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
1276                 HFC_outb(hc, R_PCM_MD2, V_SYNC_SRC); /* sync via SYNC_I / O */
1277         else
1278                 HFC_outb(hc, R_PCM_MD2, 0x00); /* sync from interface */
1279         HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
1280         for (i = 0; i < 256; i++) {
1281                 HFC_outb_nodebug(hc, R_SLOT, i);
1282                 HFC_outb_nodebug(hc, A_SL_CFG, 0);
1283                 HFC_outb_nodebug(hc, A_CONF, 0);
1284                 hc->slot_owner[i] = -1;
1285         }
1286
1287         /* set clock speed */
1288         if (test_bit(HFC_CHIP_CLOCK2, &hc->chip)) {
1289                 if (debug & DEBUG_HFCMULTI_INIT)
1290                         printk(KERN_DEBUG
1291                             "%s: setting double clock\n", __func__);
1292                 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK);
1293         }
1294
1295         /* B410P GPIO */
1296         if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
1297                 printk(KERN_NOTICE "Setting GPIOs\n");
1298                 HFC_outb(hc, R_GPIO_SEL, 0x30);
1299                 HFC_outb(hc, R_GPIO_EN1, 0x3);
1300                 udelay(1000);
1301                 printk(KERN_NOTICE "calling vpm_init\n");
1302                 vpm_init(hc);
1303         }
1304
1305         /* check if R_F0_CNT counts (8 kHz frame count) */
1306         val = HFC_inb(hc, R_F0_CNTL);
1307         val += HFC_inb(hc, R_F0_CNTH) << 8;
1308         if (debug & DEBUG_HFCMULTI_INIT)
1309                 printk(KERN_DEBUG
1310                     "HFC_multi F0_CNT %ld after reset\n", val);
1311         spin_unlock_irqrestore(&hc->lock, flags);
1312         set_current_state(TASK_UNINTERRUPTIBLE);
1313         schedule_timeout((HZ/100)?:1); /* Timeout minimum 10ms */
1314         spin_lock_irqsave(&hc->lock, flags);
1315         val2 = HFC_inb(hc, R_F0_CNTL);
1316         val2 += HFC_inb(hc, R_F0_CNTH) << 8;
1317         if (debug & DEBUG_HFCMULTI_INIT)
1318                 printk(KERN_DEBUG
1319                         "HFC_multi F0_CNT %ld after 10 ms (1st try)\n",
1320                     val2);
1321         if (val2 >= val+8) { /* 1 ms */
1322                 /* it counts, so we keep the pcm mode */
1323                 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip))
1324                         printk(KERN_INFO "controller is PCM bus MASTER\n");
1325                 else
1326                 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip))
1327                         printk(KERN_INFO "controller is PCM bus SLAVE\n");
1328                 else {
1329                         test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
1330                         printk(KERN_INFO "controller is PCM bus SLAVE "
1331                                 "(auto detected)\n");
1332                 }
1333         } else {
1334                 /* does not count */
1335                 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
1336 controller_fail:
1337                         printk(KERN_ERR "HFC_multi ERROR, getting no 125us "
1338                             "pulse. Seems that controller fails.\n");
1339                         err = -EIO;
1340                         goto out;
1341                 }
1342                 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
1343                         printk(KERN_INFO "controller is PCM bus SLAVE "
1344                                 "(ignoring missing PCM clock)\n");
1345                 } else {
1346                         /* only one pcm master */
1347                         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)
1348                                 && plxsd_master) {
1349                                 printk(KERN_ERR "HFC_multi ERROR, no clock "
1350                                     "on another Speech Design card found. "
1351                                     "Please be sure to connect PCM cable.\n");
1352                                 err = -EIO;
1353                                 goto out;
1354                         }
1355                         /* retry with master clock */
1356                         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1357                                 spin_lock_irqsave(&plx_lock, plx_flags);
1358                                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1359                                 pv = readl(plx_acc_32);
1360                                 pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N;
1361                                 pv |= PLX_SYNC_O_EN;
1362                                 writel(pv, plx_acc_32);
1363                                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1364                                 if (debug & DEBUG_HFCMULTI_INIT)
1365                                     printk(KERN_WARNING "%s: master: PLX_GPIO"
1366                                         "=%x\n", __func__, pv);
1367                         }
1368                         hc->hw.r_pcm_md0 |= V_PCM_MD;
1369                         HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
1370                         spin_unlock_irqrestore(&hc->lock, flags);
1371                         set_current_state(TASK_UNINTERRUPTIBLE);
1372                         schedule_timeout((HZ/100)?:1); /* Timeout min. 10ms */
1373                         spin_lock_irqsave(&hc->lock, flags);
1374                         val2 = HFC_inb(hc, R_F0_CNTL);
1375                         val2 += HFC_inb(hc, R_F0_CNTH) << 8;
1376                         if (debug & DEBUG_HFCMULTI_INIT)
1377                                 printk(KERN_DEBUG "HFC_multi F0_CNT %ld after "
1378                                         "10 ms (2nd try)\n", val2);
1379                         if (val2 >= val+8) { /* 1 ms */
1380                                 test_and_set_bit(HFC_CHIP_PCM_MASTER,
1381                                         &hc->chip);
1382                                 printk(KERN_INFO "controller is PCM bus MASTER "
1383                                         "(auto detected)\n");
1384                         } else
1385                                 goto controller_fail;
1386                 }
1387         }
1388
1389         /* Release the DSP Reset */
1390         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1391                 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip))
1392                         plxsd_master = 1;
1393                 spin_lock_irqsave(&plx_lock, plx_flags);
1394                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1395                 pv = readl(plx_acc_32);
1396                 pv |=  PLX_DSP_RES_N;
1397                 writel(pv, plx_acc_32);
1398                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1399                 if (debug & DEBUG_HFCMULTI_INIT)
1400                         printk(KERN_WARNING "%s: reset off: PLX_GPIO=%x\n",
1401                                 __func__, pv);
1402         }
1403
1404         /* pcm id */
1405         if (hc->pcm)
1406                 printk(KERN_INFO "controller has given PCM BUS ID %d\n",
1407                         hc->pcm);
1408         else {
1409                 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)
1410                  || test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1411                         PCM_cnt++; /* SD has proprietary bridging */
1412                 }
1413                 hc->pcm = PCM_cnt;
1414                 printk(KERN_INFO "controller has PCM BUS ID %d "
1415                         "(auto selected)\n", hc->pcm);
1416         }
1417
1418         /* set up timer */
1419         HFC_outb(hc, R_TI_WD, poll_timer);
1420         hc->hw.r_irqmsk_misc |= V_TI_IRQMSK;
1421
1422         /*
1423          * set up 125us interrupt, only if function pointer is available
1424          * and module parameter timer is set
1425          */
1426         if (timer && hfc_interrupt && register_interrupt) {
1427                 /* only one chip should use this interrupt */
1428                 timer = 0;
1429                 interrupt_registered = 1;
1430                 hc->hw.r_irqmsk_misc |= V_PROC_IRQMSK;
1431                 /* deactivate other interrupts in ztdummy */
1432                 register_interrupt();
1433         }
1434
1435         /* set E1 state machine IRQ */
1436         if (hc->type == 1)
1437                 hc->hw.r_irqmsk_misc |= V_STA_IRQMSK;
1438
1439         /* set DTMF detection */
1440         if (test_bit(HFC_CHIP_DTMF, &hc->chip)) {
1441                 if (debug & DEBUG_HFCMULTI_INIT)
1442                         printk(KERN_DEBUG "%s: enabling DTMF detection "
1443                             "for all B-channel\n", __func__);
1444                 hc->hw.r_dtmf = V_DTMF_EN | V_DTMF_STOP;
1445                 if (test_bit(HFC_CHIP_ULAW, &hc->chip))
1446                         hc->hw.r_dtmf |= V_ULAW_SEL;
1447                 HFC_outb(hc, R_DTMF_N, 102 - 1);
1448                 hc->hw.r_irqmsk_misc |= V_DTMF_IRQMSK;
1449         }
1450
1451         /* conference engine */
1452         if (test_bit(HFC_CHIP_ULAW, &hc->chip))
1453                 r_conf_en = V_CONF_EN | V_ULAW;
1454         else
1455                 r_conf_en = V_CONF_EN;
1456         HFC_outb(hc, R_CONF_EN, r_conf_en);
1457
1458         /* setting leds */
1459         switch (hc->leds) {
1460         case 1: /* HFC-E1 OEM */
1461                 if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip))
1462                         HFC_outb(hc, R_GPIO_SEL, 0x32);
1463                 else
1464                         HFC_outb(hc, R_GPIO_SEL, 0x30);
1465
1466                 HFC_outb(hc, R_GPIO_EN1, 0x0f);
1467                 HFC_outb(hc, R_GPIO_OUT1, 0x00);
1468
1469                 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3);
1470                 break;
1471
1472         case 2: /* HFC-4S OEM */
1473         case 3:
1474                 HFC_outb(hc, R_GPIO_SEL, 0xf0);
1475                 HFC_outb(hc, R_GPIO_EN1, 0xff);
1476                 HFC_outb(hc, R_GPIO_OUT1, 0x00);
1477                 break;
1478         }
1479
1480         /* set master clock */
1481         if (hc->masterclk >= 0) {
1482                 if (debug & DEBUG_HFCMULTI_INIT)
1483                         printk(KERN_DEBUG "%s: setting ST master clock "
1484                             "to port %d (0..%d)\n",
1485                             __func__, hc->masterclk, hc->ports-1);
1486                 hc->hw.r_st_sync = hc->masterclk | V_AUTO_SYNC;
1487                 HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync);
1488         }
1489
1490         /* setting misc irq */
1491         HFC_outb(hc, R_IRQMSK_MISC, hc->hw.r_irqmsk_misc);
1492         if (debug & DEBUG_HFCMULTI_INIT)
1493                 printk(KERN_DEBUG "r_irqmsk_misc.2: 0x%x\n",
1494                     hc->hw.r_irqmsk_misc);
1495
1496         /* RAM access test */
1497         HFC_outb(hc, R_RAM_ADDR0, 0);
1498         HFC_outb(hc, R_RAM_ADDR1, 0);
1499         HFC_outb(hc, R_RAM_ADDR2, 0);
1500         for (i = 0; i < 256; i++) {
1501                 HFC_outb_nodebug(hc, R_RAM_ADDR0, i);
1502                 HFC_outb_nodebug(hc, R_RAM_DATA, ((i*3)&0xff));
1503         }
1504         for (i = 0; i < 256; i++) {
1505                 HFC_outb_nodebug(hc, R_RAM_ADDR0, i);
1506                 HFC_inb_nodebug(hc, R_RAM_DATA);
1507                 rval = HFC_inb_nodebug(hc, R_INT_DATA);
1508                 if (rval != ((i * 3) & 0xff)) {
1509                         printk(KERN_DEBUG
1510                             "addr:%x val:%x should:%x\n", i, rval,
1511                             (i * 3) & 0xff);
1512                         err++;
1513                 }
1514         }
1515         if (err) {
1516                 printk(KERN_DEBUG "aborting - %d RAM access errors\n", err);
1517                 err = -EIO;
1518                 goto out;
1519         }
1520
1521         if (debug & DEBUG_HFCMULTI_INIT)
1522                 printk(KERN_DEBUG "%s: done\n", __func__);
1523 out:
1524         spin_unlock_irqrestore(&hc->lock, flags);
1525         return err;
1526 }
1527
1528
1529 /*
1530  * control the watchdog
1531  */
1532 static void
1533 hfcmulti_watchdog(struct hfc_multi *hc)
1534 {
1535         hc->wdcount++;
1536
1537         if (hc->wdcount > 10) {
1538                 hc->wdcount = 0;
1539                 hc->wdbyte = hc->wdbyte == V_GPIO_OUT2 ?
1540                     V_GPIO_OUT3 : V_GPIO_OUT2;
1541
1542         /* printk("Sending Watchdog Kill %x\n",hc->wdbyte); */
1543                 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3);
1544                 HFC_outb(hc, R_GPIO_OUT0, hc->wdbyte);
1545         }
1546 }
1547
1548
1549
1550 /*
1551  * output leds
1552  */
1553 static void
1554 hfcmulti_leds(struct hfc_multi *hc)
1555 {
1556         unsigned long lled;
1557         unsigned long leddw;
1558         int i, state, active, leds;
1559         struct dchannel *dch;
1560         int led[4];
1561
1562         hc->ledcount += poll;
1563         if (hc->ledcount > 4096) {
1564                 hc->ledcount -= 4096;
1565                 hc->ledstate = 0xAFFEAFFE;
1566         }
1567
1568         switch (hc->leds) {
1569         case 1: /* HFC-E1 OEM */
1570                 /* 2 red blinking: NT mode deactivate
1571                  * 2 red steady:   TE mode deactivate
1572                  * left green:     L1 active
1573                  * left red:       frame sync, but no L1
1574                  * right green:    L2 active
1575                  */
1576                 if (hc->chan[hc->dslot].sync != 2) { /* no frame sync */
1577                         if (hc->chan[hc->dslot].dch->dev.D.protocol
1578                                 != ISDN_P_NT_E1) {
1579                                 led[0] = 1;
1580                                 led[1] = 1;
1581                         } else if (hc->ledcount>>11) {
1582                                 led[0] = 1;
1583                                 led[1] = 1;
1584                         } else {
1585                                 led[0] = 0;
1586                                 led[1] = 0;
1587                         }
1588                         led[2] = 0;
1589                         led[3] = 0;
1590                 } else { /* with frame sync */
1591                         /* TODO make it work */
1592                         led[0] = 0;
1593                         led[1] = 0;
1594                         led[2] = 0;
1595                         led[3] = 1;
1596                 }
1597                 leds = (led[0] | (led[1]<<2) | (led[2]<<1) | (led[3]<<3))^0xF;
1598                         /* leds are inverted */
1599                 if (leds != (int)hc->ledstate) {
1600                         HFC_outb_nodebug(hc, R_GPIO_OUT1, leds);
1601                         hc->ledstate = leds;
1602                 }
1603                 break;
1604
1605         case 2: /* HFC-4S OEM */
1606                 /* red blinking = PH_DEACTIVATE NT Mode
1607                  * red steady   = PH_DEACTIVATE TE Mode
1608                  * green steady = PH_ACTIVATE
1609                  */
1610                 for (i = 0; i < 4; i++) {
1611                         state = 0;
1612                         active = -1;
1613                         dch = hc->chan[(i << 2) | 2].dch;
1614                         if (dch) {
1615                                 state = dch->state;
1616                                 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1617                                         active = 3;
1618                                 else
1619                                         active = 7;
1620                         }
1621                         if (state) {
1622                                 if (state == active) {
1623                                         led[i] = 1; /* led green */
1624                                 } else
1625                                         if (dch->dev.D.protocol == ISDN_P_TE_S0)
1626                                                 /* TE mode: led red */
1627                                                 led[i] = 2;
1628                                         else
1629                                                 if (hc->ledcount>>11)
1630                                                         /* led red */
1631                                                         led[i] = 2;
1632                                                 else
1633                                                         /* led off */
1634                                                         led[i] = 0;
1635                         } else
1636                                 led[i] = 0; /* led off */
1637                 }
1638                 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
1639                         leds = 0;
1640                         for (i = 0; i < 4; i++) {
1641                                 if (led[i] == 1) {
1642                                         /*green*/
1643                                         leds |= (0x2 << (i * 2));
1644                                 } else if (led[i] == 2) {
1645                                         /*red*/
1646                                         leds |= (0x1 << (i * 2));
1647                                 }
1648                         }
1649                         if (leds != (int)hc->ledstate) {
1650                                 vpm_out(hc, 0, 0x1a8 + 3, leds);
1651                                 hc->ledstate = leds;
1652                         }
1653                 } else {
1654                         leds = ((led[3] > 0) << 0) | ((led[1] > 0) << 1) |
1655                             ((led[0] > 0) << 2) | ((led[2] > 0) << 3) |
1656                             ((led[3] & 1) << 4) | ((led[1] & 1) << 5) |
1657                             ((led[0] & 1) << 6) | ((led[2] & 1) << 7);
1658                         if (leds != (int)hc->ledstate) {
1659                                 HFC_outb_nodebug(hc, R_GPIO_EN1, leds & 0x0F);
1660                                 HFC_outb_nodebug(hc, R_GPIO_OUT1, leds >> 4);
1661                                 hc->ledstate = leds;
1662                         }
1663                 }
1664                 break;
1665
1666         case 3: /* HFC 1S/2S Beronet */
1667                 /* red blinking = PH_DEACTIVATE NT Mode
1668                  * red steady   = PH_DEACTIVATE TE Mode
1669                  * green steady = PH_ACTIVATE
1670                  */
1671                 for (i = 0; i < 2; i++) {
1672                         state = 0;
1673                         active = -1;
1674                         dch = hc->chan[(i << 2) | 2].dch;
1675                         if (dch) {
1676                                 state = dch->state;
1677                                 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1678                                         active = 3;
1679                                 else
1680                                         active = 7;
1681                         }
1682                         if (state) {
1683                                 if (state == active) {
1684                                         led[i] = 1; /* led green */
1685                                 } else
1686                                         if (dch->dev.D.protocol == ISDN_P_TE_S0)
1687                                                 /* TE mode: led red */
1688                                                 led[i] = 2;
1689                                         else
1690                                                 if (hc->ledcount >> 11)
1691                                                         /* led red */
1692                                                         led[i] = 2;
1693                                                 else
1694                                                         /* led off */
1695                                                         led[i] = 0;
1696                         } else
1697                                 led[i] = 0; /* led off */
1698                 }
1699
1700
1701                 leds = (led[0] > 0) | ((led[1] > 0)<<1) | ((led[0]&1)<<2)
1702                         | ((led[1]&1)<<3);
1703                 if (leds != (int)hc->ledstate) {
1704                         HFC_outb_nodebug(hc, R_GPIO_EN1,
1705                             ((led[0] > 0) << 2) | ((led[1] > 0) << 3));
1706                         HFC_outb_nodebug(hc, R_GPIO_OUT1,
1707                             ((led[0] & 1) << 2) | ((led[1] & 1) << 3));
1708                         hc->ledstate = leds;
1709                 }
1710                 break;
1711         case 8: /* HFC 8S+ Beronet */
1712                 lled = 0;
1713
1714                 for (i = 0; i < 8; i++) {
1715                         state = 0;
1716                         active = -1;
1717                         dch = hc->chan[(i << 2) | 2].dch;
1718                         if (dch) {
1719                                 state = dch->state;
1720                                 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1721                                         active = 3;
1722                                 else
1723                                         active = 7;
1724                         }
1725                         if (state) {
1726                                 if (state == active) {
1727                                         lled |= 0 << i;
1728                                 } else
1729                                         if (hc->ledcount >> 11)
1730                                                 lled |= 0 << i;
1731                                         else
1732                                                 lled |= 1 << i;
1733                         } else
1734                                 lled |= 1 << i;
1735                 }
1736                 leddw = lled << 24 | lled << 16 | lled << 8 | lled;
1737                 if (leddw != hc->ledstate) {
1738                         /* HFC_outb(hc, R_BRG_PCM_CFG, 1);
1739                         HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); */
1740                         /* was _io before */
1741                         HFC_outb_nodebug(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK);
1742                         outw(0x4000, hc->pci_iobase + 4);
1743                         outl(leddw, hc->pci_iobase);
1744                         HFC_outb_nodebug(hc, R_BRG_PCM_CFG, V_PCM_CLK);
1745                         hc->ledstate = leddw;
1746                 }
1747                 break;
1748         }
1749 }
1750 /*
1751  * read dtmf coefficients
1752  */
1753
1754 static void
1755 hfcmulti_dtmf(struct hfc_multi *hc)
1756 {
1757         s32             *coeff;
1758         u_int           mantissa;
1759         int             co, ch;
1760         struct bchannel *bch = NULL;
1761         u8              exponent;
1762         int             dtmf = 0;
1763         int             addr;
1764         u16             w_float;
1765         struct sk_buff  *skb;
1766         struct mISDNhead *hh;
1767
1768         if (debug & DEBUG_HFCMULTI_DTMF)
1769                 printk(KERN_DEBUG "%s: dtmf detection irq\n", __func__);
1770         for (ch = 0; ch <= 31; ch++) {
1771                 /* only process enabled B-channels */
1772                 bch = hc->chan[ch].bch;
1773                 if (!bch)
1774                         continue;
1775                 if (!hc->created[hc->chan[ch].port])
1776                         continue;
1777                 if (!test_bit(FLG_TRANSPARENT, &bch->Flags))
1778                         continue;
1779                 if (debug & DEBUG_HFCMULTI_DTMF)
1780                         printk(KERN_DEBUG "%s: dtmf channel %d:",
1781                                 __func__, ch);
1782                 coeff = &(hc->chan[ch].coeff[hc->chan[ch].coeff_count * 16]);
1783                 dtmf = 1;
1784                 for (co = 0; co < 8; co++) {
1785                         /* read W(n-1) coefficient */
1786                         addr = hc->DTMFbase + ((co<<7) | (ch<<2));
1787                         HFC_outb_nodebug(hc, R_RAM_ADDR0, addr);
1788                         HFC_outb_nodebug(hc, R_RAM_ADDR1, addr>>8);
1789                         HFC_outb_nodebug(hc, R_RAM_ADDR2, (addr>>16)
1790                                 | V_ADDR_INC);
1791                         w_float = HFC_inb_nodebug(hc, R_RAM_DATA);
1792                         w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8);
1793                         if (debug & DEBUG_HFCMULTI_DTMF)
1794                                 printk(" %04x", w_float);
1795
1796                         /* decode float (see chip doc) */
1797                         mantissa = w_float & 0x0fff;
1798                         if (w_float & 0x8000)
1799                                 mantissa |= 0xfffff000;
1800                         exponent = (w_float>>12) & 0x7;
1801                         if (exponent) {
1802                                 mantissa ^= 0x1000;
1803                                 mantissa <<= (exponent-1);
1804                         }
1805
1806                         /* store coefficient */
1807                         coeff[co<<1] = mantissa;
1808
1809                         /* read W(n) coefficient */
1810                         w_float = HFC_inb_nodebug(hc, R_RAM_DATA);
1811                         w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8);
1812                         if (debug & DEBUG_HFCMULTI_DTMF)
1813                                 printk(" %04x", w_float);
1814
1815                         /* decode float (see chip doc) */
1816                         mantissa = w_float & 0x0fff;
1817                         if (w_float & 0x8000)
1818                                 mantissa |= 0xfffff000;
1819                         exponent = (w_float>>12) & 0x7;
1820                         if (exponent) {
1821                                 mantissa ^= 0x1000;
1822                                 mantissa <<= (exponent-1);
1823                         }
1824
1825                         /* store coefficient */
1826                         coeff[(co<<1)|1] = mantissa;
1827                 }
1828                 if (debug & DEBUG_HFCMULTI_DTMF)
1829                         printk("%s: DTMF ready %08x %08x %08x %08x "
1830                             "%08x %08x %08x %08x\n", __func__,
1831                             coeff[0], coeff[1], coeff[2], coeff[3],
1832                             coeff[4], coeff[5], coeff[6], coeff[7]);
1833                 hc->chan[ch].coeff_count++;
1834                 if (hc->chan[ch].coeff_count == 8) {
1835                         hc->chan[ch].coeff_count = 0;
1836                         skb = mI_alloc_skb(512, GFP_ATOMIC);
1837                         if (!skb) {
1838                                 printk(KERN_WARNING "%s: No memory for skb\n",
1839                                     __func__);
1840                                 continue;
1841                         }
1842                         hh = mISDN_HEAD_P(skb);
1843                         hh->prim = PH_CONTROL_IND;
1844                         hh->id = DTMF_HFC_COEF;
1845                         memcpy(skb_put(skb, 512), hc->chan[ch].coeff, 512);
1846                         recv_Bchannel_skb(bch, skb);
1847                 }
1848         }
1849
1850         /* restart DTMF processing */
1851         hc->dtmf = dtmf;
1852         if (dtmf)
1853                 HFC_outb_nodebug(hc, R_DTMF, hc->hw.r_dtmf | V_RST_DTMF);
1854 }
1855
1856
1857 /*
1858  * fill fifo as much as possible
1859  */
1860
1861 static void
1862 hfcmulti_tx(struct hfc_multi *hc, int ch)
1863 {
1864         int i, ii, temp, len = 0;
1865         int Zspace, z1, z2; /* must be int for calculation */
1866         int Fspace, f1, f2;
1867         u_char *d;
1868         int *txpending, slot_tx;
1869         struct  bchannel *bch;
1870         struct  dchannel *dch;
1871         struct  sk_buff **sp = NULL;
1872         int *idxp;
1873
1874         bch = hc->chan[ch].bch;
1875         dch = hc->chan[ch].dch;
1876         if ((!dch) && (!bch))
1877                 return;
1878
1879         txpending = &hc->chan[ch].txpending;
1880         slot_tx = hc->chan[ch].slot_tx;
1881         if (dch) {
1882                 if (!test_bit(FLG_ACTIVE, &dch->Flags))
1883                         return;
1884                 sp = &dch->tx_skb;
1885                 idxp = &dch->tx_idx;
1886         } else {
1887                 if (!test_bit(FLG_ACTIVE, &bch->Flags))
1888                         return;
1889                 sp = &bch->tx_skb;
1890                 idxp = &bch->tx_idx;
1891         }
1892         if (*sp)
1893                 len = (*sp)->len;
1894
1895         if ((!len) && *txpending != 1)
1896                 return; /* no data */
1897
1898         if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
1899             (hc->chan[ch].protocol == ISDN_P_B_RAW) &&
1900             (hc->chan[ch].slot_rx < 0) &&
1901             (hc->chan[ch].slot_tx < 0))
1902                 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch << 1));
1903         else
1904                 HFC_outb_nodebug(hc, R_FIFO, ch << 1);
1905         HFC_wait_nodebug(hc);
1906
1907         if (*txpending == 2) {
1908                 /* reset fifo */
1909                 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
1910                 HFC_wait_nodebug(hc);
1911                 HFC_outb(hc, A_SUBCH_CFG, 0);
1912                 *txpending = 1;
1913         }
1914 next_frame:
1915         if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
1916                 f1 = HFC_inb_nodebug(hc, A_F1);
1917                 f2 = HFC_inb_nodebug(hc, A_F2);
1918                 while (f2 != (temp = HFC_inb_nodebug(hc, A_F2))) {
1919                         if (debug & DEBUG_HFCMULTI_FIFO)
1920                                 printk(KERN_DEBUG
1921                                     "%s(card %d): reread f2 because %d!=%d\n",
1922                                     __func__, hc->id + 1, temp, f2);
1923                         f2 = temp; /* repeat until F2 is equal */
1924                 }
1925                 Fspace = f2 - f1 - 1;
1926                 if (Fspace < 0)
1927                         Fspace += hc->Flen;
1928                 /*
1929                  * Old FIFO handling doesn't give us the current Z2 read
1930                  * pointer, so we cannot send the next frame before the fifo
1931                  * is empty. It makes no difference except for a slightly
1932                  * lower performance.
1933                  */
1934                 if (test_bit(HFC_CHIP_REVISION0, &hc->chip)) {
1935                         if (f1 != f2)
1936                                 Fspace = 0;
1937                         else
1938                                 Fspace = 1;
1939                 }
1940                 /* one frame only for ST D-channels, to allow resending */
1941                 if (hc->type != 1 && dch) {
1942                         if (f1 != f2)
1943                                 Fspace = 0;
1944                 }
1945                 /* F-counter full condition */
1946                 if (Fspace == 0)
1947                         return;
1948         }
1949         z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin;
1950         z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin;
1951         while (z2 != (temp = (HFC_inw_nodebug(hc, A_Z2) - hc->Zmin))) {
1952                 if (debug & DEBUG_HFCMULTI_FIFO)
1953                         printk(KERN_DEBUG "%s(card %d): reread z2 because "
1954                                 "%d!=%d\n", __func__, hc->id + 1, temp, z2);
1955                 z2 = temp; /* repeat unti Z2 is equal */
1956         }
1957         Zspace = z2 - z1;
1958         if (Zspace <= 0)
1959                 Zspace += hc->Zlen;
1960         Zspace -= 4; /* keep not too full, so pointers will not overrun */
1961         /* fill transparent data only to maxinum transparent load (minus 4) */
1962         if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
1963                 Zspace = Zspace - hc->Zlen + hc->max_trans;
1964         if (Zspace <= 0) /* no space of 4 bytes */
1965                 return;
1966
1967         /* if no data */
1968         if (!len) {
1969                 if (z1 == z2) { /* empty */
1970                         /* if done with FIFO audio data during PCM connection */
1971                         if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) &&
1972                             *txpending && slot_tx >= 0) {
1973                                 if (debug & DEBUG_HFCMULTI_MODE)
1974                                         printk(KERN_DEBUG
1975                                             "%s: reconnecting PCM due to no "
1976                                             "more FIFO data: channel %d "
1977                                             "slot_tx %d\n",
1978                                             __func__, ch, slot_tx);
1979                                 /* connect slot */
1980                                 HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
1981                                     V_HDLC_TRP | V_IFF);
1982                                 HFC_outb_nodebug(hc, R_FIFO, ch<<1 | 1);
1983                                 HFC_wait_nodebug(hc);
1984                                 HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
1985                                     V_HDLC_TRP | V_IFF);
1986                                 HFC_outb_nodebug(hc, R_FIFO, ch<<1);
1987                                 HFC_wait_nodebug(hc);
1988                         }
1989                         *txpending = 0;
1990                 }
1991                 return; /* no data */
1992         }
1993
1994         /* if audio data and connected slot */
1995         if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) && (!*txpending)
1996                 && slot_tx >= 0) {
1997                 if (debug & DEBUG_HFCMULTI_MODE)
1998                         printk(KERN_DEBUG "%s: disconnecting PCM due to "
1999                             "FIFO data: channel %d slot_tx %d\n",
2000                             __func__, ch, slot_tx);
2001                 /* disconnect slot */
2002                 HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 | V_HDLC_TRP | V_IFF);
2003                 HFC_outb_nodebug(hc, R_FIFO, ch<<1 | 1);
2004                 HFC_wait_nodebug(hc);
2005                 HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 | V_HDLC_TRP | V_IFF);
2006                 HFC_outb_nodebug(hc, R_FIFO, ch<<1);
2007                 HFC_wait_nodebug(hc);
2008         }
2009         *txpending = 1;
2010
2011         /* show activity */
2012         hc->activity[hc->chan[ch].port] = 1;
2013
2014         /* fill fifo to what we have left */
2015         ii = len;
2016         if (dch || test_bit(FLG_HDLC, &bch->Flags))
2017                 temp = 1;
2018         else
2019                 temp = 0;
2020         i = *idxp;
2021         d = (*sp)->data + i;
2022         if (ii - i > Zspace)
2023                 ii = Zspace + i;
2024         if (debug & DEBUG_HFCMULTI_FIFO)
2025                 printk(KERN_DEBUG "%s(card %d): fifo(%d) has %d bytes space "
2026                     "left (z1=%04x, z2=%04x) sending %d of %d bytes %s\n",
2027                         __func__, hc->id + 1, ch, Zspace, z1, z2, ii-i, len-i,
2028                         temp ? "HDLC":"TRANS");
2029
2030
2031         /* Have to prep the audio data */
2032         hc->write_fifo(hc, d, ii - i);
2033         *idxp = ii;
2034
2035         /* if not all data has been written */
2036         if (ii != len) {
2037                 /* NOTE: fifo is started by the calling function */
2038                 return;
2039         }
2040
2041         /* if all data has been written, terminate frame */
2042         if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2043                 /* increment f-counter */
2044                 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F);
2045                 HFC_wait_nodebug(hc);
2046         }
2047
2048         /* send confirm, since get_net_bframe will not do it with trans */
2049         if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
2050                 confirm_Bsend(bch);
2051
2052         /* check for next frame */
2053         dev_kfree_skb(*sp);
2054         if (bch && get_next_bframe(bch)) { /* hdlc is confirmed here */
2055                 len = (*sp)->len;
2056                 goto next_frame;
2057         }
2058         if (dch && get_next_dframe(dch)) {
2059                 len = (*sp)->len;
2060                 goto next_frame;
2061         }
2062
2063         /*
2064          * now we have no more data, so in case of transparent,
2065          * we set the last byte in fifo to 'silence' in case we will get
2066          * no more data at all. this prevents sending an undefined value.
2067          */
2068         if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
2069                 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, silence);
2070 }
2071
2072
2073 /* NOTE: only called if E1 card is in active state */
2074 static void
2075 hfcmulti_rx(struct hfc_multi *hc, int ch)
2076 {
2077         int temp;
2078         int Zsize, z1, z2 = 0; /* = 0, to make GCC happy */
2079         int f1 = 0, f2 = 0; /* = 0, to make GCC happy */
2080         int again = 0;
2081         struct  bchannel *bch;
2082         struct  dchannel *dch;
2083         struct sk_buff  *skb, **sp = NULL;
2084         int     maxlen;
2085
2086         bch = hc->chan[ch].bch;
2087         dch = hc->chan[ch].dch;
2088         if ((!dch) && (!bch))
2089                 return;
2090         if (dch) {
2091                 if (!test_bit(FLG_ACTIVE, &dch->Flags))
2092                         return;
2093                 sp = &dch->rx_skb;
2094                 maxlen = dch->maxlen;
2095         } else {
2096                 if (!test_bit(FLG_ACTIVE, &bch->Flags))
2097                         return;
2098                 sp = &bch->rx_skb;
2099                 maxlen = bch->maxlen;
2100         }
2101 next_frame:
2102         /* on first AND before getting next valid frame, R_FIFO must be written
2103            to. */
2104         if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
2105             (hc->chan[ch].protocol == ISDN_P_B_RAW) &&
2106             (hc->chan[ch].slot_rx < 0) &&
2107             (hc->chan[ch].slot_tx < 0))
2108                 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch<<1) | 1);
2109         else
2110                 HFC_outb_nodebug(hc, R_FIFO, (ch<<1)|1);
2111         HFC_wait_nodebug(hc);
2112
2113         /* ignore if rx is off BUT change fifo (above) to start pending TX */
2114         if (hc->chan[ch].rx_off)
2115                 return;
2116
2117         if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2118                 f1 = HFC_inb_nodebug(hc, A_F1);
2119                 while (f1 != (temp = HFC_inb_nodebug(hc, A_F1))) {
2120                         if (debug & DEBUG_HFCMULTI_FIFO)
2121                                 printk(KERN_DEBUG
2122                                     "%s(card %d): reread f1 because %d!=%d\n",
2123                                     __func__, hc->id + 1, temp, f1);
2124                         f1 = temp; /* repeat until F1 is equal */
2125                 }
2126                 f2 = HFC_inb_nodebug(hc, A_F2);
2127         }
2128         z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin;
2129         while (z1 != (temp = (HFC_inw_nodebug(hc, A_Z1) - hc->Zmin))) {
2130                 if (debug & DEBUG_HFCMULTI_FIFO)
2131                         printk(KERN_DEBUG "%s(card %d): reread z2 because "
2132                                 "%d!=%d\n", __func__, hc->id + 1, temp, z2);
2133                 z1 = temp; /* repeat until Z1 is equal */
2134         }
2135         z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin;
2136         Zsize = z1 - z2;
2137         if ((dch || test_bit(FLG_HDLC, &bch->Flags)) && f1 != f2)
2138                 /* complete hdlc frame */
2139                 Zsize++;
2140         if (Zsize < 0)
2141                 Zsize += hc->Zlen;
2142         /* if buffer is empty */
2143         if (Zsize <= 0)
2144                 return;
2145
2146         if (*sp == NULL) {
2147                 *sp = mI_alloc_skb(maxlen + 3, GFP_ATOMIC);
2148                 if (*sp == NULL) {
2149                         printk(KERN_DEBUG "%s: No mem for rx_skb\n",
2150                             __func__);
2151                         return;
2152                 }
2153         }
2154         /* show activity */
2155         hc->activity[hc->chan[ch].port] = 1;
2156
2157         /* empty fifo with what we have */
2158         if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2159                 if (debug & DEBUG_HFCMULTI_FIFO)
2160                         printk(KERN_DEBUG "%s(card %d): fifo(%d) reading %d "
2161                             "bytes (z1=%04x, z2=%04x) HDLC %s (f1=%d, f2=%d) "
2162                             "got=%d (again %d)\n", __func__, hc->id + 1, ch,
2163                             Zsize, z1, z2, (f1 == f2) ? "fragment" : "COMPLETE",
2164                             f1, f2, Zsize + (*sp)->len, again);
2165                 /* HDLC */
2166                 if ((Zsize + (*sp)->len) > (maxlen + 3)) {
2167                         if (debug & DEBUG_HFCMULTI_FIFO)
2168                                 printk(KERN_DEBUG
2169                                     "%s(card %d): hdlc-frame too large.\n",
2170                                     __func__, hc->id + 1);
2171                         skb_trim(*sp, 0);
2172                         HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
2173                         HFC_wait_nodebug(hc);
2174                         return;
2175                 }
2176
2177                 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize);
2178
2179                 if (f1 != f2) {
2180                         /* increment Z2,F2-counter */
2181                         HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F);
2182                         HFC_wait_nodebug(hc);
2183                         /* check size */
2184                         if ((*sp)->len < 4) {
2185                                 if (debug & DEBUG_HFCMULTI_FIFO)
2186                                         printk(KERN_DEBUG
2187                                             "%s(card %d): Frame below minimum "
2188                                             "size\n", __func__, hc->id + 1);
2189                                 skb_trim(*sp, 0);
2190                                 goto next_frame;
2191                         }
2192                         /* there is at least one complete frame, check crc */
2193                         if ((*sp)->data[(*sp)->len - 1]) {
2194                                 if (debug & DEBUG_HFCMULTI_CRC)
2195                                         printk(KERN_DEBUG
2196                                             "%s: CRC-error\n", __func__);
2197                                 skb_trim(*sp, 0);
2198                                 goto next_frame;
2199                         }
2200                         skb_trim(*sp, (*sp)->len - 3);
2201                         if ((*sp)->len < MISDN_COPY_SIZE) {
2202                                 skb = *sp;
2203                                 *sp = mI_alloc_skb(skb->len, GFP_ATOMIC);
2204                                 if (*sp) {
2205                                         memcpy(skb_put(*sp, skb->len),
2206                                             skb->data, skb->len);
2207                                         skb_trim(skb, 0);
2208                                 } else {
2209                                         printk(KERN_DEBUG "%s: No mem\n",
2210                                             __func__);
2211                                         *sp = skb;
2212                                         skb = NULL;
2213                                 }
2214                         } else {
2215                                 skb = NULL;
2216                         }
2217                         if (debug & DEBUG_HFCMULTI_FIFO) {
2218                                 printk(KERN_DEBUG "%s(card %d):",
2219                                         __func__, hc->id + 1);
2220                                 temp = 0;
2221                                 while (temp < (*sp)->len)
2222                                         printk(" %02x", (*sp)->data[temp++]);
2223                                 printk("\n");
2224                         }
2225                         if (dch)
2226                                 recv_Dchannel(dch);
2227                         else
2228                                 recv_Bchannel(bch);
2229                         *sp = skb;
2230                         again++;
2231                         goto next_frame;
2232                 }
2233                 /* there is an incomplete frame */
2234         } else {
2235                 /* transparent */
2236                 if (Zsize > skb_tailroom(*sp))
2237                         Zsize = skb_tailroom(*sp);
2238                 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize);
2239                 if (((*sp)->len) < MISDN_COPY_SIZE) {
2240                         skb = *sp;
2241                         *sp = mI_alloc_skb(skb->len, GFP_ATOMIC);
2242                         if (*sp) {
2243                                 memcpy(skb_put(*sp, skb->len),
2244                                     skb->data, skb->len);
2245                                 skb_trim(skb, 0);
2246                         } else {
2247                                 printk(KERN_DEBUG "%s: No mem\n", __func__);
2248                                 *sp = skb;
2249                                 skb = NULL;
2250                         }
2251                 } else {
2252                         skb = NULL;
2253                 }
2254                 if (debug & DEBUG_HFCMULTI_FIFO)
2255                         printk(KERN_DEBUG
2256                             "%s(card %d): fifo(%d) reading %d bytes "
2257                             "(z1=%04x, z2=%04x) TRANS\n",
2258                                 __func__, hc->id + 1, ch, Zsize, z1, z2);
2259                 /* only bch is transparent */
2260                 recv_Bchannel(bch);
2261                 *sp = skb;
2262         }
2263 }
2264
2265
2266 /*
2267  * Interrupt handler
2268  */
2269 static void
2270 signal_state_up(struct dchannel *dch, int info, char *msg)
2271 {
2272         struct sk_buff  *skb;
2273         int             id, data = info;
2274
2275         if (debug & DEBUG_HFCMULTI_STATE)
2276                 printk(KERN_DEBUG "%s: %s\n", __func__, msg);
2277
2278         id = TEI_SAPI | (GROUP_TEI << 8); /* manager address */
2279
2280         skb = _alloc_mISDN_skb(MPH_INFORMATION_IND, id, sizeof(data), &data,
2281                 GFP_ATOMIC);
2282         if (!skb)
2283                 return;
2284         recv_Dchannel_skb(dch, skb);
2285 }
2286
2287 static inline void
2288 handle_timer_irq(struct hfc_multi *hc)
2289 {
2290         int             ch, temp;
2291         struct dchannel *dch;
2292         u_long          flags;
2293
2294         /* process queued resync jobs */
2295         if (hc->e1_resync) {
2296                 /* lock, so e1_resync gets not changed */
2297                 spin_lock_irqsave(&HFClock, flags);
2298                 if (hc->e1_resync & 1) {
2299                         if (debug & DEBUG_HFCMULTI_PLXSD)
2300                                 printk(KERN_DEBUG "Enable SYNC_I\n");
2301                         HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC);
2302                         /* disable JATT, if RX_SYNC is set */
2303                         if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip))
2304                                 HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX);
2305                 }
2306                 if (hc->e1_resync & 2) {
2307                         if (debug & DEBUG_HFCMULTI_PLXSD)
2308                                 printk(KERN_DEBUG "Enable jatt PLL\n");
2309                         HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS);
2310                 }
2311                 if (hc->e1_resync & 4) {
2312                         if (debug & DEBUG_HFCMULTI_PLXSD)
2313                                 printk(KERN_DEBUG
2314                                     "Enable QUARTZ for HFC-E1\n");
2315                         /* set jatt to quartz */
2316                         HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC
2317                                 | V_JATT_OFF);
2318                         /* switch to JATT, in case it is not already */
2319                         HFC_outb(hc, R_SYNC_OUT, 0);
2320                 }
2321                 hc->e1_resync = 0;
2322                 spin_unlock_irqrestore(&HFClock, flags);
2323         }
2324
2325         if (hc->type != 1 || hc->e1_state == 1)
2326                 for (ch = 0; ch <= 31; ch++) {
2327                         if (hc->created[hc->chan[ch].port]) {
2328                                 hfcmulti_tx(hc, ch);
2329                                 /* fifo is started when switching to rx-fifo */
2330                                 hfcmulti_rx(hc, ch);
2331                                 if (hc->chan[ch].dch &&
2332                                     hc->chan[ch].nt_timer > -1) {
2333                                         dch = hc->chan[ch].dch;
2334                                         if (!(--hc->chan[ch].nt_timer)) {
2335                                                 schedule_event(dch,
2336                                                     FLG_PHCHANGE);
2337                                                 if (debug &
2338                                                     DEBUG_HFCMULTI_STATE)
2339                                                         printk(KERN_DEBUG
2340                                                             "%s: nt_timer at "
2341                                                             "state %x\n",
2342                                                             __func__,
2343                                                             dch->state);
2344                                         }
2345                                 }
2346                         }
2347                 }
2348         if (hc->type == 1 && hc->created[0]) {
2349                 dch = hc->chan[hc->dslot].dch;
2350                 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dslot].cfg)) {
2351                         /* LOS */
2352                         temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_SIG_LOS;
2353                         if (!temp && hc->chan[hc->dslot].los)
2354                                 signal_state_up(dch, L1_SIGNAL_LOS_ON,
2355                                     "LOS detected");
2356                         if (temp && !hc->chan[hc->dslot].los)
2357                                 signal_state_up(dch, L1_SIGNAL_LOS_OFF,
2358                                     "LOS gone");
2359                         hc->chan[hc->dslot].los = temp;
2360                 }
2361                 if (test_bit(HFC_CFG_REPORT_AIS, &hc->chan[hc->dslot].cfg)) {
2362                         /* AIS */
2363                         temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_AIS;
2364                         if (!temp && hc->chan[hc->dslot].ais)
2365                                 signal_state_up(dch, L1_SIGNAL_AIS_ON,
2366                                     "AIS detected");
2367                         if (temp && !hc->chan[hc->dslot].ais)
2368                                 signal_state_up(dch, L1_SIGNAL_AIS_OFF,
2369                                     "AIS gone");
2370                         hc->chan[hc->dslot].ais = temp;
2371                 }
2372                 if (test_bit(HFC_CFG_REPORT_SLIP, &hc->chan[hc->dslot].cfg)) {
2373                         /* SLIP */
2374                         temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_RX;
2375                         if (!temp && hc->chan[hc->dslot].slip_rx)
2376                                 signal_state_up(dch, L1_SIGNAL_SLIP_RX,
2377                                     " bit SLIP detected RX");
2378                         hc->chan[hc->dslot].slip_rx = temp;
2379                         temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_TX;
2380                         if (!temp && hc->chan[hc->dslot].slip_tx)
2381                                 signal_state_up(dch, L1_SIGNAL_SLIP_TX,
2382                                     " bit SLIP detected TX");
2383                         hc->chan[hc->dslot].slip_tx = temp;
2384                 }
2385                 if (test_bit(HFC_CFG_REPORT_RDI, &hc->chan[hc->dslot].cfg)) {
2386                         /* RDI */
2387                         temp = HFC_inb_nodebug(hc, R_RX_SL0_0) & V_A;
2388                         if (!temp && hc->chan[hc->dslot].rdi)
2389                                 signal_state_up(dch, L1_SIGNAL_RDI_ON,
2390                                     "RDI detected");
2391                         if (temp && !hc->chan[hc->dslot].rdi)
2392                                 signal_state_up(dch, L1_SIGNAL_RDI_OFF,
2393                                     "RDI gone");
2394                         hc->chan[hc->dslot].rdi = temp;
2395                 }
2396                 temp = HFC_inb_nodebug(hc, R_JATT_DIR);
2397                 switch (hc->chan[hc->dslot].sync) {
2398                 case 0:
2399                         if ((temp & 0x60) == 0x60) {
2400                                 if (debug & DEBUG_HFCMULTI_SYNC)
2401                                         printk(KERN_DEBUG
2402                                             "%s: (id=%d) E1 now "
2403                                             "in clock sync\n",
2404                                             __func__, hc->id);
2405                                 HFC_outb(hc, R_RX_OFF,
2406                                     hc->chan[hc->dslot].jitter | V_RX_INIT);
2407                                 HFC_outb(hc, R_TX_OFF,
2408                                     hc->chan[hc->dslot].jitter | V_RX_INIT);
2409                                 hc->chan[hc->dslot].sync = 1;
2410                                 goto check_framesync;
2411                         }
2412                         break;
2413                 case 1:
2414                         if ((temp & 0x60) != 0x60) {
2415                                 if (debug & DEBUG_HFCMULTI_SYNC)
2416                                         printk(KERN_DEBUG
2417                                             "%s: (id=%d) E1 "
2418                                             "lost clock sync\n",
2419                                             __func__, hc->id);
2420                                 hc->chan[hc->dslot].sync = 0;
2421                                 break;
2422                         }
2423 check_framesync:
2424                         temp = HFC_inb_nodebug(hc, R_SYNC_STA);
2425                         if (temp == 0x27) {
2426                                 if (debug & DEBUG_HFCMULTI_SYNC)
2427                                         printk(KERN_DEBUG
2428                                             "%s: (id=%d) E1 "
2429                                             "now in frame sync\n",
2430                                             __func__, hc->id);
2431                                 hc->chan[hc->dslot].sync = 2;
2432                         }
2433                         break;
2434                 case 2:
2435                         if ((temp & 0x60) != 0x60) {
2436                                 if (debug & DEBUG_HFCMULTI_SYNC)
2437                                         printk(KERN_DEBUG
2438                                             "%s: (id=%d) E1 lost "
2439                                             "clock & frame sync\n",
2440                                             __func__, hc->id);
2441                                 hc->chan[hc->dslot].sync = 0;
2442                                 break;
2443                         }
2444                         temp = HFC_inb_nodebug(hc, R_SYNC_STA);
2445                         if (temp != 0x27) {
2446                                 if (debug & DEBUG_HFCMULTI_SYNC)
2447                                         printk(KERN_DEBUG
2448                                             "%s: (id=%d) E1 "
2449                                             "lost frame sync\n",
2450                                             __func__, hc->id);
2451                                 hc->chan[hc->dslot].sync = 1;
2452                         }
2453                         break;
2454                 }
2455         }
2456
2457         if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip))
2458                 hfcmulti_watchdog(hc);
2459
2460         if (hc->leds)
2461                 hfcmulti_leds(hc);
2462 }
2463
2464 static void
2465 ph_state_irq(struct hfc_multi *hc, u_char r_irq_statech)
2466 {
2467         struct dchannel *dch;
2468         int             ch;
2469         int             active;
2470         u_char          st_status, temp;
2471
2472         /* state machine */
2473         for (ch = 0; ch <= 31; ch++) {
2474                 if (hc->chan[ch].dch) {
2475                         dch = hc->chan[ch].dch;
2476                         if (r_irq_statech & 1) {
2477                                 HFC_outb_nodebug(hc, R_ST_SEL,
2478                                         hc->chan[ch].port);
2479                                 /* undocumented: delay after R_ST_SEL */
2480                                 udelay(1);
2481                                 /* undocumented: status changes during read */
2482                                 st_status = HFC_inb_nodebug(hc, A_ST_RD_STATE);
2483                                 while (st_status != (temp =
2484                                         HFC_inb_nodebug(hc, A_ST_RD_STATE))) {
2485                                         if (debug & DEBUG_HFCMULTI_STATE)
2486                                                 printk(KERN_DEBUG "%s: reread "
2487                                                     "STATE because %d!=%d\n",
2488                                                     __func__, temp,
2489                                                     st_status);
2490                                         st_status = temp; /* repeat */
2491                                 }
2492
2493                                 /* Speech Design TE-sync indication */
2494                                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) &&
2495                                         dch->dev.D.protocol == ISDN_P_TE_S0) {
2496                                         if (st_status & V_FR_SYNC_ST)
2497                                                 hc->syncronized |=
2498                                                     (1 << hc->chan[ch].port);
2499                                         else
2500                                                 hc->syncronized &=
2501                                                    ~(1 << hc->chan[ch].port);
2502                                 }
2503                                 dch->state = st_status & 0x0f;
2504                                 if (dch->dev.D.protocol == ISDN_P_NT_S0)
2505                                         active = 3;
2506                                 else
2507                                         active = 7;
2508                                 if (dch->state == active) {
2509                                         HFC_outb_nodebug(hc, R_FIFO,
2510                                                 (ch << 1) | 1);
2511                                         HFC_wait_nodebug(hc);
2512                                         HFC_outb_nodebug(hc,
2513                                                 R_INC_RES_FIFO, V_RES_F);
2514                                         HFC_wait_nodebug(hc);
2515                                         dch->tx_idx = 0;
2516                                 }
2517                                 schedule_event(dch, FLG_PHCHANGE);
2518                                 if (debug & DEBUG_HFCMULTI_STATE)
2519                                         printk(KERN_DEBUG
2520                                             "%s: S/T newstate %x port %d\n",
2521                                             __func__, dch->state,
2522                                             hc->chan[ch].port);
2523                         }
2524                         r_irq_statech >>= 1;
2525                 }
2526         }
2527         if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
2528                 plxsd_checksync(hc, 0);
2529 }
2530
2531 static void
2532 fifo_irq(struct hfc_multi *hc, int block)
2533 {
2534         int     ch, j;
2535         struct dchannel *dch;
2536         struct bchannel *bch;
2537         u_char r_irq_fifo_bl;
2538
2539         r_irq_fifo_bl = HFC_inb_nodebug(hc, R_IRQ_FIFO_BL0 + block);
2540         j = 0;
2541         while (j < 8) {
2542                 ch = (block << 2) + (j >> 1);
2543                 dch = hc->chan[ch].dch;
2544                 bch = hc->chan[ch].bch;
2545                 if (((!dch) && (!bch)) || (!hc->created[hc->chan[ch].port])) {
2546                         j += 2;
2547                         continue;
2548                 }
2549                 if (dch && (r_irq_fifo_bl & (1 << j)) &&
2550                     test_bit(FLG_ACTIVE, &dch->Flags)) {
2551                         hfcmulti_tx(hc, ch);
2552                         /* start fifo */
2553                         HFC_outb_nodebug(hc, R_FIFO, 0);
2554                         HFC_wait_nodebug(hc);
2555                 }
2556                 if (bch && (r_irq_fifo_bl & (1 << j)) &&
2557                     test_bit(FLG_ACTIVE, &bch->Flags)) {
2558                         hfcmulti_tx(hc, ch);
2559                         /* start fifo */
2560                         HFC_outb_nodebug(hc, R_FIFO, 0);
2561                         HFC_wait_nodebug(hc);
2562                 }
2563                 j++;
2564                 if (dch && (r_irq_fifo_bl & (1 << j)) &&
2565                     test_bit(FLG_ACTIVE, &dch->Flags)) {
2566                         hfcmulti_rx(hc, ch);
2567                 }
2568                 if (bch && (r_irq_fifo_bl & (1 << j)) &&
2569                     test_bit(FLG_ACTIVE, &bch->Flags)) {
2570                         hfcmulti_rx(hc, ch);
2571                 }
2572                 j++;
2573         }
2574 }
2575
2576 #ifdef IRQ_DEBUG
2577 int irqsem;
2578 #endif
2579 static irqreturn_t
2580 hfcmulti_interrupt(int intno, void *dev_id)
2581 {
2582 #ifdef IRQCOUNT_DEBUG
2583         static int iq1 = 0, iq2 = 0, iq3 = 0, iq4 = 0,
2584             iq5 = 0, iq6 = 0, iqcnt = 0;
2585 #endif
2586         static int              count;
2587         struct hfc_multi        *hc = dev_id;
2588         struct dchannel         *dch;
2589         u_char                  r_irq_statech, status, r_irq_misc, r_irq_oview;
2590         int                     i;
2591         void __iomem            *plx_acc;
2592         u_short                 wval;
2593         u_char                  e1_syncsta, temp;
2594         u_long                  flags;
2595
2596         if (!hc) {
2597                 printk(KERN_ERR "HFC-multi: Spurious interrupt!\n");
2598                 return IRQ_NONE;
2599         }
2600
2601         spin_lock(&hc->lock);
2602
2603 #ifdef IRQ_DEBUG
2604         if (irqsem)
2605                 printk(KERN_ERR "irq for card %d during irq from "
2606                 "card %d, this is no bug.\n", hc->id + 1, irqsem);
2607         irqsem = hc->id + 1;
2608 #endif
2609
2610         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
2611                 spin_lock_irqsave(&plx_lock, flags);
2612                 plx_acc = hc->plx_membase + PLX_INTCSR;
2613                 wval = readw(plx_acc);
2614                 spin_unlock_irqrestore(&plx_lock, flags);
2615                 if (!(wval & PLX_INTCSR_LINTI1_STATUS))
2616                         goto irq_notforus;
2617         }
2618
2619         status = HFC_inb_nodebug(hc, R_STATUS);
2620         r_irq_statech = HFC_inb_nodebug(hc, R_IRQ_STATECH);
2621 #ifdef IRQCOUNT_DEBUG
2622         if (r_irq_statech)
2623                 iq1++;
2624         if (status & V_DTMF_STA)
2625                 iq2++;
2626         if (status & V_LOST_STA)
2627                 iq3++;
2628         if (status & V_EXT_IRQSTA)
2629                 iq4++;
2630         if (status & V_MISC_IRQSTA)
2631                 iq5++;
2632         if (status & V_FR_IRQSTA)
2633                 iq6++;
2634         if (iqcnt++ > 5000) {
2635                 printk(KERN_ERR "iq1:%x iq2:%x iq3:%x iq4:%x iq5:%x iq6:%x\n",
2636                     iq1, iq2, iq3, iq4, iq5, iq6);
2637                 iqcnt = 0;
2638         }
2639 #endif
2640         if (!r_irq_statech &&
2641             !(status & (V_DTMF_STA | V_LOST_STA | V_EXT_IRQSTA |
2642             V_MISC_IRQSTA | V_FR_IRQSTA))) {
2643                 /* irq is not for us */
2644                 goto irq_notforus;
2645         }
2646         hc->irqcnt++;
2647         if (r_irq_statech) {
2648                 if (hc->type != 1)
2649                         ph_state_irq(hc, r_irq_statech);
2650         }
2651         if (status & V_EXT_IRQSTA)
2652                 ; /* external IRQ */
2653         if (status & V_LOST_STA) {
2654                 /* LOST IRQ */
2655                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_LOST); /* clear irq! */
2656         }
2657         if (status & V_MISC_IRQSTA) {
2658                 /* misc IRQ */
2659                 r_irq_misc = HFC_inb_nodebug(hc, R_IRQ_MISC);
2660                 if (r_irq_misc & V_STA_IRQ) {
2661                         if (hc->type == 1) {
2662                                 /* state machine */
2663                                 dch = hc->chan[hc->dslot].dch;
2664                                 e1_syncsta = HFC_inb_nodebug(hc, R_SYNC_STA);
2665                                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)
2666                                  && hc->e1_getclock) {
2667                                         if (e1_syncsta & V_FR_SYNC_E1)
2668                                                 hc->syncronized = 1;
2669                                         else
2670                                                 hc->syncronized = 0;
2671                                 }
2672                                 /* undocumented: status changes during read */
2673                                 dch->state = HFC_inb_nodebug(hc, R_E1_RD_STA);
2674                                 while (dch->state != (temp =
2675                                         HFC_inb_nodebug(hc, R_E1_RD_STA))) {
2676                                         if (debug & DEBUG_HFCMULTI_STATE)
2677                                                 printk(KERN_DEBUG "%s: reread "
2678                                                     "STATE because %d!=%d\n",
2679                                                     __func__, temp,
2680                                                     dch->state);
2681                                         dch->state = temp; /* repeat */
2682                                 }
2683                                 dch->state = HFC_inb_nodebug(hc, R_E1_RD_STA)
2684                                         & 0x7;
2685                                 schedule_event(dch, FLG_PHCHANGE);
2686                                 if (debug & DEBUG_HFCMULTI_STATE)
2687                                         printk(KERN_DEBUG
2688                                             "%s: E1 (id=%d) newstate %x\n",
2689                                             __func__, hc->id, dch->state);
2690                                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
2691                                         plxsd_checksync(hc, 0);
2692                         }
2693                 }
2694                 if (r_irq_misc & V_TI_IRQ)
2695                         handle_timer_irq(hc);
2696
2697                 if (r_irq_misc & V_DTMF_IRQ) {
2698                         /* -> DTMF IRQ */
2699                         hfcmulti_dtmf(hc);
2700                 }
2701                 /* TODO: REPLACE !!!! 125 us Interrupts are not acceptable  */
2702                 if (r_irq_misc & V_IRQ_PROC) {
2703                         /* IRQ every 125us */
2704                         count++;
2705                         /* generate 1kHz signal */
2706                         if (count == 8) {
2707                                 if (hfc_interrupt)
2708                                         hfc_interrupt();
2709                                 count = 0;
2710                         }
2711                 }
2712
2713         }
2714         if (status & V_FR_IRQSTA) {
2715                 /* FIFO IRQ */
2716                 r_irq_oview = HFC_inb_nodebug(hc, R_IRQ_OVIEW);
2717                 for (i = 0; i < 8; i++) {
2718                         if (r_irq_oview & (1 << i))
2719                                 fifo_irq(hc, i);
2720                 }
2721         }
2722
2723 #ifdef IRQ_DEBUG
2724         irqsem = 0;
2725 #endif
2726         spin_unlock(&hc->lock);
2727         return IRQ_HANDLED;
2728
2729 irq_notforus:
2730 #ifdef IRQ_DEBUG
2731         irqsem = 0;
2732 #endif
2733         spin_unlock(&hc->lock);
2734         return IRQ_NONE;
2735 }
2736
2737
2738 /*
2739  * timer callback for D-chan busy resolution. Currently no function
2740  */
2741
2742 static void
2743 hfcmulti_dbusy_timer(struct hfc_multi *hc)
2744 {
2745 }
2746
2747
2748 /*
2749  * activate/deactivate hardware for selected channels and mode
2750  *
2751  * configure B-channel with the given protocol
2752  * ch eqals to the HFC-channel (0-31)
2753  * ch is the number of channel (0-4,4-7,8-11,12-15,16-19,20-23,24-27,28-31
2754  * for S/T, 1-31 for E1)
2755  * the hdlc interrupts will be set/unset
2756  */
2757 static int
2758 mode_hfcmulti(struct hfc_multi *hc, int ch, int protocol, int slot_tx,
2759     int bank_tx, int slot_rx, int bank_rx)
2760 {
2761         int flow_tx = 0, flow_rx = 0, routing = 0;
2762         int oslot_tx, oslot_rx;
2763         int conf;
2764
2765         if (ch < 0 || ch > 31)
2766                 return EINVAL;
2767         oslot_tx = hc->chan[ch].slot_tx;
2768         oslot_rx = hc->chan[ch].slot_rx;
2769         conf = hc->chan[ch].conf;
2770
2771         if (debug & DEBUG_HFCMULTI_MODE)
2772                 printk(KERN_DEBUG
2773                     "%s: card %d channel %d protocol %x slot old=%d new=%d "
2774                     "bank new=%d (TX) slot old=%d new=%d bank new=%d (RX)\n",
2775                     __func__, hc->id, ch, protocol, oslot_tx, slot_tx,
2776                     bank_tx, oslot_rx, slot_rx, bank_rx);
2777
2778         if (oslot_tx >= 0 && slot_tx != oslot_tx) {
2779                 /* remove from slot */
2780                 if (debug & DEBUG_HFCMULTI_MODE)
2781                         printk(KERN_DEBUG "%s: remove from slot %d (TX)\n",
2782                             __func__, oslot_tx);
2783                 if (hc->slot_owner[oslot_tx<<1] == ch) {
2784                         HFC_outb(hc, R_SLOT, oslot_tx << 1);
2785                         HFC_outb(hc, A_SL_CFG, 0);
2786                         HFC_outb(hc, A_CONF, 0);
2787                         hc->slot_owner[oslot_tx<<1] = -1;
2788                 } else {
2789                         if (debug & DEBUG_HFCMULTI_MODE)
2790                                 printk(KERN_DEBUG
2791                                     "%s: we are not owner of this tx slot "
2792                                     "anymore, channel %d is.\n",
2793                                     __func__, hc->slot_owner[oslot_tx<<1]);
2794                 }
2795         }
2796
2797         if (oslot_rx >= 0 && slot_rx != oslot_rx) {
2798                 /* remove from slot */
2799                 if (debug & DEBUG_HFCMULTI_MODE)
2800                         printk(KERN_DEBUG
2801                             "%s: remove from slot %d (RX)\n",
2802                             __func__, oslot_rx);
2803                 if (hc->slot_owner[(oslot_rx << 1) | 1] == ch) {
2804                         HFC_outb(hc, R_SLOT, (oslot_rx << 1) | V_SL_DIR);
2805                         HFC_outb(hc, A_SL_CFG, 0);
2806                         hc->slot_owner[(oslot_rx << 1) | 1] = -1;
2807                 } else {
2808                         if (debug & DEBUG_HFCMULTI_MODE)
2809                                 printk(KERN_DEBUG
2810                                     "%s: we are not owner of this rx slot "
2811                                     "anymore, channel %d is.\n",
2812                                     __func__,
2813                                     hc->slot_owner[(oslot_rx << 1) | 1]);
2814                 }
2815         }
2816
2817         if (slot_tx < 0) {
2818                 flow_tx = 0x80; /* FIFO->ST */
2819                 /* disable pcm slot */
2820                 hc->chan[ch].slot_tx = -1;
2821                 hc->chan[ch].bank_tx = 0;
2822         } else {
2823                 /* set pcm slot */
2824                 if (hc->chan[ch].txpending)
2825                         flow_tx = 0x80; /* FIFO->ST */
2826                 else
2827                         flow_tx = 0xc0; /* PCM->ST */
2828                 /* put on slot */
2829                 routing = bank_tx ? 0xc0 : 0x80;
2830                 if (conf >= 0 || bank_tx > 1)
2831                         routing = 0x40; /* loop */
2832                 if (debug & DEBUG_HFCMULTI_MODE)
2833                         printk(KERN_DEBUG "%s: put channel %d to slot %d bank"
2834                             " %d flow %02x routing %02x conf %d (TX)\n",
2835                             __func__, ch, slot_tx, bank_tx,
2836                             flow_tx, routing, conf);
2837                 HFC_outb(hc, R_SLOT, slot_tx << 1);
2838                 HFC_outb(hc, A_SL_CFG, (ch<<1) | routing);
2839                 HFC_outb(hc, A_CONF, (conf < 0) ? 0 : (conf | V_CONF_SL));
2840                 hc->slot_owner[slot_tx << 1] = ch;
2841                 hc->chan[ch].slot_tx = slot_tx;
2842                 hc->chan[ch].bank_tx = bank_tx;
2843         }
2844         if (slot_rx < 0) {
2845                 /* disable pcm slot */
2846                 flow_rx = 0x80; /* ST->FIFO */
2847                 hc->chan[ch].slot_rx = -1;
2848                 hc->chan[ch].bank_rx = 0;
2849         } else {
2850                 /* set pcm slot */
2851                 if (hc->chan[ch].txpending)
2852                         flow_rx = 0x80; /* ST->FIFO */
2853                 else
2854                         flow_rx = 0xc0; /* ST->(FIFO,PCM) */
2855                 /* put on slot */
2856                 routing = bank_rx?0x80:0xc0; /* reversed */
2857                 if (conf >= 0 || bank_rx > 1)
2858                         routing = 0x40; /* loop */
2859                 if (debug & DEBUG_HFCMULTI_MODE)
2860                         printk(KERN_DEBUG "%s: put channel %d to slot %d bank"
2861                             " %d flow %02x routing %02x conf %d (RX)\n",
2862                             __func__, ch, slot_rx, bank_rx,
2863                             flow_rx, routing, conf);
2864                 HFC_outb(hc, R_SLOT, (slot_rx<<1) | V_SL_DIR);
2865                 HFC_outb(hc, A_SL_CFG, (ch<<1) | V_CH_DIR | routing);
2866                 hc->slot_owner[(slot_rx<<1)|1] = ch;
2867                 hc->chan[ch].slot_rx = slot_rx;
2868                 hc->chan[ch].bank_rx = bank_rx;
2869         }
2870
2871         switch (protocol) {
2872         case (ISDN_P_NONE):
2873                 /* disable TX fifo */
2874                 HFC_outb(hc, R_FIFO, ch << 1);
2875                 HFC_wait(hc);
2876                 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 | V_IFF);
2877                 HFC_outb(hc, A_SUBCH_CFG, 0);
2878                 HFC_outb(hc, A_IRQ_MSK, 0);
2879                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2880                 HFC_wait(hc);
2881                 /* disable RX fifo */
2882                 HFC_outb(hc, R_FIFO, (ch<<1)|1);
2883                 HFC_wait(hc);
2884                 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00);
2885                 HFC_outb(hc, A_SUBCH_CFG, 0);
2886                 HFC_outb(hc, A_IRQ_MSK, 0);
2887                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2888                 HFC_wait(hc);
2889                 if (hc->chan[ch].bch && hc->type != 1) {
2890                         hc->hw.a_st_ctrl0[hc->chan[ch].port] &=
2891                             ((ch & 0x3) == 0)? ~V_B1_EN: ~V_B2_EN;
2892                         HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
2893                         /* undocumented: delay after R_ST_SEL */
2894                         udelay(1);
2895                         HFC_outb(hc, A_ST_CTRL0,
2896                             hc->hw.a_st_ctrl0[hc->chan[ch].port]);
2897                 }
2898                 if (hc->chan[ch].bch) {
2899                         test_and_clear_bit(FLG_HDLC, &hc->chan[ch].bch->Flags);
2900                         test_and_clear_bit(FLG_TRANSPARENT,
2901                             &hc->chan[ch].bch->Flags);
2902                 }
2903                 break;
2904         case (ISDN_P_B_RAW): /* B-channel */
2905
2906                 if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
2907                     (hc->chan[ch].slot_rx < 0) &&
2908                     (hc->chan[ch].slot_tx < 0)) {
2909
2910                         printk(KERN_DEBUG
2911                             "Setting B-channel %d to echo cancelable "
2912                             "state on PCM slot %d\n", ch,
2913                             ((ch / 4) * 8) + ((ch % 4) * 4) + 1);
2914                         printk(KERN_DEBUG
2915                             "Enabling pass through for channel\n");
2916                         vpm_out(hc, ch, ((ch / 4) * 8) +
2917                             ((ch % 4) * 4) + 1, 0x01);
2918                         /* rx path */
2919                         /* S/T -> PCM */
2920                         HFC_outb(hc, R_FIFO, (ch << 1));
2921                         HFC_wait(hc);
2922                         HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF);
2923                         HFC_outb(hc, R_SLOT, (((ch / 4) * 8) +
2924                             ((ch % 4) * 4) + 1) << 1);
2925                         HFC_outb(hc, A_SL_CFG, 0x80 | (ch << 1));
2926
2927                         /* PCM -> FIFO */
2928                         HFC_outb(hc, R_FIFO, 0x20 | (ch << 1) | 1);
2929                         HFC_wait(hc);
2930                         HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF);
2931                         HFC_outb(hc, A_SUBCH_CFG, 0);
2932                         HFC_outb(hc, A_IRQ_MSK, 0);
2933                         HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2934                         HFC_wait(hc);
2935                         HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) +
2936                             ((ch % 4) * 4) + 1) << 1) | 1);
2937                         HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1) | 1);
2938
2939                         /* tx path */
2940                         /* PCM -> S/T */
2941                         HFC_outb(hc, R_FIFO, (ch << 1) | 1);
2942                         HFC_wait(hc);
2943                         HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF);
2944                         HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) +
2945                             ((ch % 4) * 4)) << 1) | 1);
2946                         HFC_outb(hc, A_SL_CFG, 0x80 | 0x40 | (ch << 1) | 1);
2947
2948                         /* FIFO -> PCM */
2949                         HFC_outb(hc, R_FIFO, 0x20 | (ch << 1));
2950                         HFC_wait(hc);
2951                         HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF);
2952                         HFC_outb(hc, A_SUBCH_CFG, 0);
2953                         HFC_outb(hc, A_IRQ_MSK, 0);
2954                         HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2955                         HFC_wait(hc);
2956                         /* tx silence */
2957                         HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, silence);
2958                         HFC_outb(hc, R_SLOT, (((ch / 4) * 8) +
2959                             ((ch % 4) * 4)) << 1);
2960                         HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1));
2961                 } else {
2962                         /* enable TX fifo */
2963                         HFC_outb(hc, R_FIFO, ch << 1);
2964                         HFC_wait(hc);
2965                         HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 |
2966                             V_HDLC_TRP | V_IFF);
2967                         HFC_outb(hc, A_SUBCH_CFG, 0);
2968                         HFC_outb(hc, A_IRQ_MSK, 0);
2969                         HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2970                         HFC_wait(hc);
2971                         /* tx silence */
2972                         HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, silence);
2973                         /* enable RX fifo */
2974                         HFC_outb(hc, R_FIFO, (ch<<1)|1);
2975                         HFC_wait(hc);
2976                         HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00 | V_HDLC_TRP);
2977                         HFC_outb(hc, A_SUBCH_CFG, 0);
2978                         HFC_outb(hc, A_IRQ_MSK, 0);
2979                         HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2980                         HFC_wait(hc);
2981                 }
2982                 if (hc->type != 1) {
2983                         hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
2984                             ((ch & 0x3) == 0) ? V_B1_EN : V_B2_EN;
2985                         HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
2986                         /* undocumented: delay after R_ST_SEL */
2987                         udelay(1);
2988                         HFC_outb(hc, A_ST_CTRL0,
2989                             hc->hw.a_st_ctrl0[hc->chan[ch].port]);
2990                 }
2991                 if (hc->chan[ch].bch)
2992                         test_and_set_bit(FLG_TRANSPARENT,
2993                             &hc->chan[ch].bch->Flags);
2994                 break;
2995         case (ISDN_P_B_HDLC): /* B-channel */
2996         case (ISDN_P_TE_S0): /* D-channel */
2997         case (ISDN_P_NT_S0):
2998         case (ISDN_P_TE_E1):
2999         case (ISDN_P_NT_E1):
3000                 /* enable TX fifo */
3001                 HFC_outb(hc, R_FIFO, ch<<1);
3002                 HFC_wait(hc);
3003                 if (hc->type == 1 || hc->chan[ch].bch) {
3004                         /* E1 or B-channel */
3005                         HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04);
3006                         HFC_outb(hc, A_SUBCH_CFG, 0);
3007                 } else {
3008                         /* D-Channel without HDLC fill flags */
3009                         HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04 | V_IFF);
3010                         HFC_outb(hc, A_SUBCH_CFG, 2);
3011                 }
3012                 HFC_outb(hc, A_IRQ_MSK, V_IRQ);
3013                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3014                 HFC_wait(hc);
3015                 /* enable RX fifo */
3016                 HFC_outb(hc, R_FIFO, (ch<<1)|1);
3017                 HFC_wait(hc);
3018                 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x04);
3019                 if (hc->type == 1 || hc->chan[ch].bch)
3020                         HFC_outb(hc, A_SUBCH_CFG, 0); /* full 8 bits */
3021                 else
3022                         HFC_outb(hc, A_SUBCH_CFG, 2); /* 2 bits dchannel */
3023                 HFC_outb(hc, A_IRQ_MSK, V_IRQ);
3024                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3025                 HFC_wait(hc);
3026                 if (hc->chan[ch].bch) {
3027                         test_and_set_bit(FLG_HDLC, &hc->chan[ch].bch->Flags);
3028                         if (hc->type != 1) {
3029                                 hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
3030                                   ((ch&0x3) == 0) ? V_B1_EN : V_B2_EN;
3031                                 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
3032                                 /* undocumented: delay after R_ST_SEL */
3033                                 udelay(1);
3034                                 HFC_outb(hc, A_ST_CTRL0,
3035                                   hc->hw.a_st_ctrl0[hc->chan[ch].port]);
3036                         }
3037                 }
3038                 break;
3039         default:
3040                 printk(KERN_DEBUG "%s: protocol not known %x\n",
3041                     __func__, protocol);
3042                 hc->chan[ch].protocol = ISDN_P_NONE;
3043                 return -ENOPROTOOPT;
3044         }
3045         hc->chan[ch].protocol = protocol;
3046         return 0;
3047 }
3048
3049
3050 /*
3051  * connect/disconnect PCM
3052  */
3053
3054 static void
3055 hfcmulti_pcm(struct hfc_multi *hc, int ch, int slot_tx, int bank_tx,
3056     int slot_rx, int bank_rx)
3057 {
3058         if (slot_rx < 0 || slot_rx < 0 || bank_tx < 0 || bank_rx < 0) {
3059                 /* disable PCM */
3060                 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, -1, 0, -1, 0);
3061                 return;
3062         }
3063
3064         /* enable pcm */
3065         mode_hfcmulti(hc, ch, hc->chan[ch].protocol, slot_tx, bank_tx,
3066                 slot_rx, bank_rx);
3067 }
3068
3069 /*
3070  * set/disable conference
3071  */
3072
3073 static void
3074 hfcmulti_conf(struct hfc_multi *hc, int ch, int num)
3075 {
3076         if (num >= 0 && num <= 7)
3077                 hc->chan[ch].conf = num;
3078         else
3079                 hc->chan[ch].conf = -1;
3080         mode_hfcmulti(hc, ch, hc->chan[ch].protocol, hc->chan[ch].slot_tx,
3081             hc->chan[ch].bank_tx, hc->chan[ch].slot_rx,
3082             hc->chan[ch].bank_rx);
3083 }
3084
3085
3086 /*
3087  * set/disable sample loop
3088  */
3089
3090 /* NOTE: this function is experimental and therefore disabled */
3091
3092 /*
3093  * Layer 1 callback function
3094  */
3095 static int
3096 hfcm_l1callback(struct dchannel *dch, u_int cmd)
3097 {
3098         struct hfc_multi        *hc = dch->hw;
3099         u_long  flags;
3100
3101         switch (cmd) {
3102         case INFO3_P8:
3103         case INFO3_P10:
3104                 break;
3105         case HW_RESET_REQ:
3106                 /* start activation */
3107                 spin_lock_irqsave(&hc->lock, flags);
3108                 if (hc->type == 1) {
3109                         if (debug & DEBUG_HFCMULTI_MSG)
3110                                 printk(KERN_DEBUG
3111                                     "%s: HW_RESET_REQ no BRI\n",
3112                                     __func__);
3113                 } else {
3114                         HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3115                         /* undocumented: delay after R_ST_SEL */
3116                         udelay(1);
3117                         HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 3); /* F3 */
3118                         udelay(6); /* wait at least 5,21us */
3119                         HFC_outb(hc, A_ST_WR_STATE, 3);
3120                         HFC_outb(hc, A_ST_WR_STATE, 3 | (V_ST_ACT*3));
3121                                 /* activate */
3122                 }
3123                 spin_unlock_irqrestore(&hc->lock, flags);
3124                 l1_event(dch->l1, HW_POWERUP_IND);
3125                 break;
3126         case HW_DEACT_REQ:
3127                 /* start deactivation */
3128                 spin_lock_irqsave(&hc->lock, flags);
3129                 if (hc->type == 1) {
3130                         if (debug & DEBUG_HFCMULTI_MSG)
3131                                 printk(KERN_DEBUG
3132                                     "%s: HW_DEACT_REQ no BRI\n",
3133                                     __func__);
3134                 } else {
3135                         HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3136                         /* undocumented: delay after R_ST_SEL */
3137                         udelay(1);
3138                         HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT*2);
3139                                 /* deactivate */
3140                         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3141                                 hc->syncronized &=
3142                                    ~(1 << hc->chan[dch->slot].port);
3143                                 plxsd_checksync(hc, 0);
3144                         }
3145                 }
3146                 skb_queue_purge(&dch->squeue);
3147                 if (dch->tx_skb) {
3148                         dev_kfree_skb(dch->tx_skb);
3149                         dch->tx_skb = NULL;
3150                 }
3151                 dch->tx_idx = 0;
3152                 if (dch->rx_skb) {
3153                         dev_kfree_skb(dch->rx_skb);
3154                         dch->rx_skb = NULL;
3155                 }
3156                 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
3157                 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
3158                         del_timer(&dch->timer);
3159                 spin_unlock_irqrestore(&hc->lock, flags);
3160                 break;
3161         case HW_POWERUP_REQ:
3162                 spin_lock_irqsave(&hc->lock, flags);
3163                 if (hc->type == 1) {
3164                         if (debug & DEBUG_HFCMULTI_MSG)
3165                                 printk(KERN_DEBUG
3166                                     "%s: HW_POWERUP_REQ no BRI\n",
3167                                     __func__);
3168                 } else {
3169                         HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3170                         /* undocumented: delay after R_ST_SEL */
3171                         udelay(1);
3172                         HFC_outb(hc, A_ST_WR_STATE, 3 | 0x10); /* activate */
3173                         udelay(6); /* wait at least 5,21us */
3174                         HFC_outb(hc, A_ST_WR_STATE, 3); /* activate */
3175                 }
3176                 spin_unlock_irqrestore(&hc->lock, flags);
3177                 break;
3178         case PH_ACTIVATE_IND:
3179                 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3180                 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
3181                         GFP_ATOMIC);
3182                 break;
3183         case PH_DEACTIVATE_IND:
3184                 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3185                 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
3186                         GFP_ATOMIC);
3187                 break;
3188         default:
3189                 if (dch->debug & DEBUG_HW)
3190                         printk(KERN_DEBUG "%s: unknown command %x\n",
3191                             __func__, cmd);
3192                 return -1;
3193         }
3194         return 0;
3195 }
3196
3197 /*
3198  * Layer2 -> Layer 1 Transfer
3199  */
3200
3201 static int
3202 handle_dmsg(struct mISDNchannel *ch, struct sk_buff *skb)
3203 {
3204         struct mISDNdevice      *dev = container_of(ch, struct mISDNdevice, D);
3205         struct dchannel         *dch = container_of(dev, struct dchannel, dev);
3206         struct hfc_multi        *hc = dch->hw;
3207         struct mISDNhead        *hh = mISDN_HEAD_P(skb);
3208         int                     ret = -EINVAL;
3209         unsigned int            id;
3210         u_long                  flags;
3211
3212         switch (hh->prim) {
3213         case PH_DATA_REQ:
3214                 if (skb->len < 1)
3215                         break;
3216                 spin_lock_irqsave(&hc->lock, flags);
3217                 ret = dchannel_senddata(dch, skb);
3218                 if (ret > 0) { /* direct TX */
3219                         id = hh->id; /* skb can be freed */
3220                         hfcmulti_tx(hc, dch->slot);
3221                         ret = 0;
3222                         /* start fifo */
3223                         HFC_outb(hc, R_FIFO, 0);
3224                         HFC_wait(hc);
3225                         spin_unlock_irqrestore(&hc->lock, flags);
3226                         queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
3227                 } else
3228                         spin_unlock_irqrestore(&hc->lock, flags);
3229                 return ret;
3230         case PH_ACTIVATE_REQ:
3231                 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
3232                         spin_lock_irqsave(&hc->lock, flags);
3233                         ret = 0;
3234                         if (debug & DEBUG_HFCMULTI_MSG)
3235                                 printk(KERN_DEBUG
3236                                     "%s: PH_ACTIVATE port %d (0..%d)\n",
3237                                     __func__, hc->chan[dch->slot].port,
3238                                     hc->ports-1);
3239                         /* start activation */
3240                         if (hc->type == 1) {
3241                                 ph_state_change(dch);
3242                                 if (debug & DEBUG_HFCMULTI_STATE)
3243                                         printk(KERN_DEBUG
3244                                             "%s: E1 report state %x \n",
3245                                             __func__, dch->state);
3246                         } else {
3247                                 HFC_outb(hc, R_ST_SEL,
3248                                     hc->chan[dch->slot].port);
3249                                 /* undocumented: delay after R_ST_SEL */
3250                                 udelay(1);
3251                                 HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 1);
3252                                     /* G1 */
3253                                 udelay(6); /* wait at least 5,21us */
3254                                 HFC_outb(hc, A_ST_WR_STATE, 1);
3255                                 HFC_outb(hc, A_ST_WR_STATE, 1 |
3256                                     (V_ST_ACT*3)); /* activate */
3257                                 dch->state = 1;
3258                         }
3259                         spin_unlock_irqrestore(&hc->lock, flags);
3260                 } else
3261                         ret = l1_event(dch->l1, hh->prim);
3262                 break;
3263         case PH_DEACTIVATE_REQ:
3264                 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
3265                 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
3266                         spin_lock_irqsave(&hc->lock, flags);
3267                         if (debug & DEBUG_HFCMULTI_MSG)
3268                                 printk(KERN_DEBUG
3269                                     "%s: PH_DEACTIVATE port %d (0..%d)\n",
3270                                     __func__, hc->chan[dch->slot].port,
3271                                     hc->ports-1);
3272                         /* start deactivation */
3273                         if (hc->type == 1) {
3274                                 if (debug & DEBUG_HFCMULTI_MSG)
3275                                         printk(KERN_DEBUG
3276                                             "%s: PH_DEACTIVATE no BRI\n",
3277                                             __func__);
3278                         } else {
3279                                 HFC_outb(hc, R_ST_SEL,
3280                                     hc->chan[dch->slot].port);
3281                                 /* undocumented: delay after R_ST_SEL */
3282                                 udelay(1);
3283                                 HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT * 2);
3284                                     /* deactivate */
3285                                 dch->state = 1;
3286                         }
3287                         skb_queue_purge(&dch->squeue);
3288                         if (dch->tx_skb) {
3289                                 dev_kfree_skb(dch->tx_skb);
3290                                 dch->tx_skb = NULL;
3291                         }
3292                         dch->tx_idx = 0;
3293                         if (dch->rx_skb) {
3294                                 dev_kfree_skb(dch->rx_skb);
3295                                 dch->rx_skb = NULL;
3296                         }
3297                         test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
3298                         if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
3299                                 del_timer(&dch->timer);
3300 #ifdef FIXME
3301                         if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags))
3302                                 dchannel_sched_event(&hc->dch, D_CLEARBUSY);
3303 #endif
3304                         ret = 0;
3305                         spin_unlock_irqrestore(&hc->lock, flags);
3306                 } else
3307                         ret = l1_event(dch->l1, hh->prim);
3308                 break;
3309         }
3310         if (!ret)
3311                 dev_kfree_skb(skb);
3312         return ret;
3313 }
3314
3315 static void
3316 deactivate_bchannel(struct bchannel *bch)
3317 {
3318         struct hfc_multi        *hc = bch->hw;
3319         u_long                  flags;
3320
3321         spin_lock_irqsave(&hc->lock, flags);
3322         if (test_and_clear_bit(FLG_TX_NEXT, &bch->Flags)) {
3323                 dev_kfree_skb(bch->next_skb);
3324                 bch->next_skb = NULL;
3325         }
3326         if (bch->tx_skb) {
3327                 dev_kfree_skb(bch->tx_skb);
3328                 bch->tx_skb = NULL;
3329         }
3330         bch->tx_idx = 0;
3331         if (bch->rx_skb) {
3332                 dev_kfree_skb(bch->rx_skb);
3333                 bch->rx_skb = NULL;
3334         }
3335         hc->chan[bch->slot].coeff_count = 0;
3336         test_and_clear_bit(FLG_ACTIVE, &bch->Flags);
3337         test_and_clear_bit(FLG_TX_BUSY, &bch->Flags);
3338         hc->chan[bch->slot].rx_off = 0;
3339         hc->chan[bch->slot].conf = -1;
3340         mode_hfcmulti(hc, bch->slot, ISDN_P_NONE, -1, 0, -1, 0);
3341         spin_unlock_irqrestore(&hc->lock, flags);
3342 }
3343
3344 static int
3345 handle_bmsg(struct mISDNchannel *ch, struct sk_buff *skb)
3346 {
3347         struct bchannel         *bch = container_of(ch, struct bchannel, ch);
3348         struct hfc_multi        *hc = bch->hw;
3349         int                     ret = -EINVAL;
3350         struct mISDNhead        *hh = mISDN_HEAD_P(skb);
3351         unsigned int            id;
3352         u_long                  flags;
3353
3354         switch (hh->prim) {
3355         case PH_DATA_REQ:
3356                 if (!skb->len)
3357                         break;
3358                 spin_lock_irqsave(&hc->lock, flags);
3359                 ret = bchannel_senddata(bch, skb);
3360                 if (ret > 0) { /* direct TX */
3361                         id = hh->id; /* skb can be freed */
3362                         hfcmulti_tx(hc, bch->slot);
3363                         ret = 0;
3364                         /* start fifo */
3365                         HFC_outb_nodebug(hc, R_FIFO, 0);
3366                         HFC_wait_nodebug(hc);
3367                         if (!test_bit(FLG_TRANSPARENT, &bch->Flags)) {
3368                                 spin_unlock_irqrestore(&hc->lock, flags);
3369                                 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
3370                         } else
3371                                 spin_unlock_irqrestore(&hc->lock, flags);
3372                 } else
3373                         spin_unlock_irqrestore(&hc->lock, flags);
3374                 return ret;
3375         case PH_ACTIVATE_REQ:
3376                 if (debug & DEBUG_HFCMULTI_MSG)
3377                         printk(KERN_DEBUG "%s: PH_ACTIVATE ch %d (0..32)\n",
3378                                 __func__, bch->slot);
3379                 spin_lock_irqsave(&hc->lock, flags);
3380                 /* activate B-channel if not already activated */
3381                 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags)) {
3382                         hc->chan[bch->slot].txpending = 0;
3383                         ret = mode_hfcmulti(hc, bch->slot,
3384                                 ch->protocol,
3385                                 hc->chan[bch->slot].slot_tx,
3386                                 hc->chan[bch->slot].bank_tx,
3387                                 hc->chan[bch->slot].slot_rx,
3388                                 hc->chan[bch->slot].bank_rx);
3389                         if (!ret) {
3390                                 if (ch->protocol == ISDN_P_B_RAW && !hc->dtmf
3391                                         && test_bit(HFC_CHIP_DTMF, &hc->chip)) {
3392                                         /* start decoder */
3393                                         hc->dtmf = 1;
3394                                         if (debug & DEBUG_HFCMULTI_DTMF)
3395                                                 printk(KERN_DEBUG
3396                                                     "%s: start dtmf decoder\n",
3397                                                         __func__);
3398                                         HFC_outb(hc, R_DTMF, hc->hw.r_dtmf |
3399                                             V_RST_DTMF);
3400                                 }
3401                         }
3402                 } else
3403                         ret = 0;
3404                 spin_unlock_irqrestore(&hc->lock, flags);
3405                 if (!ret)
3406                         _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0, NULL,
3407                                 GFP_KERNEL);
3408                 break;
3409         case PH_CONTROL_REQ:
3410                 spin_lock_irqsave(&hc->lock, flags);
3411                 switch (hh->id) {
3412                 case HFC_SPL_LOOP_ON: /* set sample loop */
3413                         if (debug & DEBUG_HFCMULTI_MSG)
3414                         printk(KERN_DEBUG
3415                             "%s: HFC_SPL_LOOP_ON (len = %d)\n",
3416                             __func__, skb->len);
3417                         ret = 0;
3418                         break;
3419                 case HFC_SPL_LOOP_OFF: /* set silence */
3420                         if (debug & DEBUG_HFCMULTI_MSG)
3421                                 printk(KERN_DEBUG "%s: HFC_SPL_LOOP_OFF\n",
3422                                     __func__);
3423                         ret = 0;
3424                         break;
3425                 default:
3426                         printk(KERN_ERR
3427                              "%s: unknown PH_CONTROL_REQ info %x\n",
3428                              __func__, hh->id);
3429                         ret = -EINVAL;
3430                 }
3431                 spin_unlock_irqrestore(&hc->lock, flags);
3432                 break;
3433         case PH_DEACTIVATE_REQ:
3434                 deactivate_bchannel(bch); /* locked there */
3435                 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0, NULL,
3436                         GFP_KERNEL);
3437                 ret = 0;
3438                 break;
3439         }
3440         if (!ret)
3441                 dev_kfree_skb(skb);
3442         return ret;
3443 }
3444
3445 /*
3446  * bchannel control function
3447  */
3448 static int
3449 channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
3450 {
3451         int                     ret = 0;
3452         struct dsp_features     *features =
3453                 (struct dsp_features *)(*((u_long *)&cq->p1));
3454         struct hfc_multi        *hc = bch->hw;
3455         int                     slot_tx;
3456         int                     bank_tx;
3457         int                     slot_rx;
3458         int                     bank_rx;
3459         int                     num;
3460
3461         switch (cq->op) {
3462         case MISDN_CTRL_GETOP:
3463                 cq->op = MISDN_CTRL_HFC_OP | MISDN_CTRL_HW_FEATURES_OP
3464                         | MISDN_CTRL_RX_OFF;
3465                 break;
3466         case MISDN_CTRL_RX_OFF: /* turn off / on rx stream */
3467                 hc->chan[bch->slot].rx_off = !!cq->p1;
3468                 if (!hc->chan[bch->slot].rx_off) {
3469                         /* reset fifo on rx on */
3470                         HFC_outb_nodebug(hc, R_FIFO, (bch->slot << 1) | 1);
3471                         HFC_wait_nodebug(hc);
3472                         HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
3473                         HFC_wait_nodebug(hc);
3474                 }
3475                 if (debug & DEBUG_HFCMULTI_MSG)
3476                         printk(KERN_DEBUG "%s: RX_OFF request (nr=%d off=%d)\n",
3477                             __func__, bch->nr, hc->chan[bch->slot].rx_off);
3478                 break;
3479         case MISDN_CTRL_HW_FEATURES: /* fill features structure */
3480                 if (debug & DEBUG_HFCMULTI_MSG)
3481                         printk(KERN_DEBUG "%s: HW_FEATURE request\n",
3482                             __func__);
3483                 /* create confirm */
3484                 features->hfc_id = hc->id;
3485                 if (test_bit(HFC_CHIP_DTMF, &hc->chip))
3486                         features->hfc_dtmf = 1;
3487                 features->hfc_loops = 0;
3488                 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
3489                         features->hfc_echocanhw = 1;
3490                 } else {
3491                         features->pcm_id = hc->pcm;
3492                         features->pcm_slots = hc->slots;
3493                         features->pcm_banks = 2;
3494                 }
3495                 break;
3496         case MISDN_CTRL_HFC_PCM_CONN: /* connect to pcm timeslot (0..N) */
3497                 slot_tx = cq->p1 & 0xff;
3498                 bank_tx = cq->p1 >> 8;
3499                 slot_rx = cq->p2 & 0xff;
3500                 bank_rx = cq->p2 >> 8;
3501                 if (debug & DEBUG_HFCMULTI_MSG)
3502                         printk(KERN_DEBUG
3503                             "%s: HFC_PCM_CONN slot %d bank %d (TX) "
3504                             "slot %d bank %d (RX)\n",
3505                             __func__, slot_tx, bank_tx,
3506                             slot_rx, bank_rx);
3507                 if (slot_tx < hc->slots && bank_tx <= 2 &&
3508                     slot_rx < hc->slots && bank_rx <= 2)
3509                         hfcmulti_pcm(hc, bch->slot,
3510                             slot_tx, bank_tx, slot_rx, bank_rx);
3511                 else {
3512                         printk(KERN_WARNING
3513                             "%s: HFC_PCM_CONN slot %d bank %d (TX) "
3514                             "slot %d bank %d (RX) out of range\n",
3515                             __func__, slot_tx, bank_tx,
3516                             slot_rx, bank_rx);
3517                         ret = -EINVAL;
3518                 }
3519                 break;
3520         case MISDN_CTRL_HFC_PCM_DISC: /* release interface from pcm timeslot */
3521                 if (debug & DEBUG_HFCMULTI_MSG)
3522                         printk(KERN_DEBUG "%s: HFC_PCM_DISC\n",
3523                             __func__);
3524                 hfcmulti_pcm(hc, bch->slot, -1, 0, -1, 0);
3525                 break;
3526         case MISDN_CTRL_HFC_CONF_JOIN: /* join conference (0..7) */
3527                 num = cq->p1 & 0xff;
3528                 if (debug & DEBUG_HFCMULTI_MSG)
3529                         printk(KERN_DEBUG "%s: HFC_CONF_JOIN conf %d\n",
3530                             __func__, num);
3531                 if (num <= 7)
3532                         hfcmulti_conf(hc, bch->slot, num);
3533                 else {
3534                         printk(KERN_WARNING
3535                             "%s: HW_CONF_JOIN conf %d out of range\n",
3536                             __func__, num);
3537                         ret = -EINVAL;
3538                 }
3539                 break;
3540         case MISDN_CTRL_HFC_CONF_SPLIT: /* split conference */
3541                 if (debug & DEBUG_HFCMULTI_MSG)
3542                         printk(KERN_DEBUG "%s: HFC_CONF_SPLIT\n", __func__);
3543                 hfcmulti_conf(hc, bch->slot, -1);
3544                 break;
3545         case MISDN_CTRL_HFC_ECHOCAN_ON:
3546                 if (debug & DEBUG_HFCMULTI_MSG)
3547                         printk(KERN_DEBUG "%s: HFC_ECHOCAN_ON\n", __func__);
3548                 if (test_bit(HFC_CHIP_B410P, &hc->chip))
3549                         vpm_echocan_on(hc, bch->slot, cq->p1);
3550                 else
3551                         ret = -EINVAL;
3552                 break;
3553
3554         case MISDN_CTRL_HFC_ECHOCAN_OFF:
3555                 if (debug & DEBUG_HFCMULTI_MSG)
3556                         printk(KERN_DEBUG "%s: HFC_ECHOCAN_OFF\n",
3557                                 __func__);
3558                 if (test_bit(HFC_CHIP_B410P, &hc->chip))
3559                         vpm_echocan_off(hc, bch->slot);
3560                 else
3561                         ret = -EINVAL;
3562                 break;
3563         default:
3564                 printk(KERN_WARNING "%s: unknown Op %x\n",
3565                     __func__, cq->op);
3566                 ret = -EINVAL;
3567                 break;
3568         }
3569         return ret;
3570 }
3571
3572 static int
3573 hfcm_bctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
3574 {
3575         struct bchannel         *bch = container_of(ch, struct bchannel, ch);
3576         struct hfc_multi        *hc = bch->hw;
3577         int                     err = -EINVAL;
3578         u_long  flags;
3579
3580         if (bch->debug & DEBUG_HW)
3581                 printk(KERN_DEBUG "%s: cmd:%x %p\n",
3582                     __func__, cmd, arg);
3583         switch (cmd) {
3584         case CLOSE_CHANNEL:
3585                 test_and_clear_bit(FLG_OPEN, &bch->Flags);
3586                 if (test_bit(FLG_ACTIVE, &bch->Flags))
3587                         deactivate_bchannel(bch); /* locked there */
3588                 ch->protocol = ISDN_P_NONE;
3589                 ch->peer = NULL;
3590                 module_put(THIS_MODULE);
3591                 err = 0;
3592                 break;
3593         case CONTROL_CHANNEL:
3594                 spin_lock_irqsave(&hc->lock, flags);
3595                 err = channel_bctrl(bch, arg);
3596                 spin_unlock_irqrestore(&hc->lock, flags);
3597                 break;
3598         default:
3599                 printk(KERN_WARNING "%s: unknown prim(%x)\n",
3600                         __func__, cmd);
3601         }
3602         return err;
3603 }
3604
3605 /*
3606  * handle D-channel events
3607  *
3608  * handle state change event
3609  */
3610 static void
3611 ph_state_change(struct dchannel *dch)
3612 {
3613         struct hfc_multi *hc = dch->hw;
3614         int ch, i;
3615
3616         if (!dch) {
3617                 printk(KERN_WARNING "%s: ERROR given dch is NULL\n",
3618                     __func__);
3619                 return;
3620         }
3621         ch = dch->slot;
3622
3623         if (hc->type == 1) {
3624                 if (dch->dev.D.protocol == ISDN_P_TE_E1) {
3625                         if (debug & DEBUG_HFCMULTI_STATE)
3626                                 printk(KERN_DEBUG
3627                                     "%s: E1 TE (id=%d) newstate %x\n",
3628                                     __func__, hc->id, dch->state);
3629                 } else {
3630                         if (debug & DEBUG_HFCMULTI_STATE)
3631                                 printk(KERN_DEBUG
3632                                     "%s: E1 NT (id=%d) newstate %x\n",
3633                                     __func__, hc->id, dch->state);
3634                 }
3635                 switch (dch->state) {
3636                 case (1):
3637                         if (hc->e1_state != 1) {
3638                             for (i = 1; i <= 31; i++) {
3639                                 /* reset fifos on e1 activation */
3640                                 HFC_outb_nodebug(hc, R_FIFO, (i << 1) | 1);
3641                                 HFC_wait_nodebug(hc);
3642                                 HFC_outb_nodebug(hc,
3643                                         R_INC_RES_FIFO, V_RES_F);
3644                                 HFC_wait_nodebug(hc);
3645                             }
3646                         }
3647                         test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3648                         _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
3649                             MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3650                         break;
3651
3652                 default:
3653                         if (hc->e1_state != 1)
3654                                 return;
3655                         test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3656                         _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
3657                             MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3658                 }
3659                 hc->e1_state = dch->state;
3660         } else {
3661                 if (dch->dev.D.protocol == ISDN_P_TE_S0) {
3662                         if (debug & DEBUG_HFCMULTI_STATE)
3663                                 printk(KERN_DEBUG
3664                                     "%s: S/T TE newstate %x\n",
3665                                     __func__, dch->state);
3666                         switch (dch->state) {
3667                         case (0):
3668                                 l1_event(dch->l1, HW_RESET_IND);
3669                                 break;
3670                         case (3):
3671                                 l1_event(dch->l1, HW_DEACT_IND);
3672                                 break;
3673                         case (5):
3674                         case (8):
3675                                 l1_event(dch->l1, ANYSIGNAL);
3676                                 break;
3677                         case (6):
3678                                 l1_event(dch->l1, INFO2);
3679                                 break;
3680                         case (7):
3681                                 l1_event(dch->l1, INFO4_P8);
3682                                 break;
3683                         }
3684                 } else {
3685                         if (debug & DEBUG_HFCMULTI_STATE)
3686                                 printk(KERN_DEBUG "%s: S/T NT newstate %x\n",
3687                                     __func__, dch->state);
3688                         switch (dch->state) {
3689                         case (2):
3690                                 if (hc->chan[ch].nt_timer == 0) {
3691                                         hc->chan[ch].nt_timer = -1;
3692                                         HFC_outb(hc, R_ST_SEL,
3693                                             hc->chan[ch].port);
3694                                         /* undocumented: delay after R_ST_SEL */
3695                                         udelay(1);
3696                                         HFC_outb(hc, A_ST_WR_STATE, 4 |
3697                                             V_ST_LD_STA); /* G4 */
3698                                         udelay(6); /* wait at least 5,21us */
3699                                         HFC_outb(hc, A_ST_WR_STATE, 4);
3700                                         dch->state = 4;
3701                                 } else {
3702                                         /* one extra count for the next event */
3703                                         hc->chan[ch].nt_timer =
3704                                             nt_t1_count[poll_timer] + 1;
3705                                         HFC_outb(hc, R_ST_SEL,
3706                                             hc->chan[ch].port);
3707                                         /* undocumented: delay after R_ST_SEL */
3708                                         udelay(1);
3709                                         /* allow G2 -> G3 transition */
3710                                         HFC_outb(hc, A_ST_WR_STATE, 2 |
3711                                             V_SET_G2_G3);
3712                                 }
3713                                 break;
3714                         case (1):
3715                                 hc->chan[ch].nt_timer = -1;
3716                                 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3717                                 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
3718                                     MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3719                                 break;
3720                         case (4):
3721                                 hc->chan[ch].nt_timer = -1;
3722                                 break;
3723                         case (3):
3724                                 hc->chan[ch].nt_timer = -1;
3725                                 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3726                                 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
3727                                     MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3728                                 break;
3729                         }
3730                 }
3731         }
3732 }
3733
3734 /*
3735  * called for card mode init message
3736  */
3737
3738 static void
3739 hfcmulti_initmode(struct dchannel *dch)
3740 {
3741         struct hfc_multi *hc = dch->hw;
3742         u_char          a_st_wr_state, r_e1_wr_sta;
3743         int             i, pt;
3744
3745         if (debug & DEBUG_HFCMULTI_INIT)
3746                 printk(KERN_DEBUG "%s: entered\n", __func__);
3747
3748         if (hc->type == 1) {
3749                 hc->chan[hc->dslot].slot_tx = -1;
3750                 hc->chan[hc->dslot].slot_rx = -1;
3751                 hc->chan[hc->dslot].conf = -1;
3752                 if (hc->dslot) {
3753                         mode_hfcmulti(hc, hc->dslot, dch->dev.D.protocol,
3754                                 -1, 0, -1, 0);
3755                         dch->timer.function = (void *) hfcmulti_dbusy_timer;
3756                         dch->timer.data = (long) dch;
3757                         init_timer(&dch->timer);
3758                 }
3759                 for (i = 1; i <= 31; i++) {
3760                         if (i == hc->dslot)
3761                                 continue;
3762                         hc->chan[i].slot_tx = -1;
3763                         hc->chan[i].slot_rx = -1;
3764                         hc->chan[i].conf = -1;
3765                         mode_hfcmulti(hc, i, ISDN_P_NONE, -1, 0, -1, 0);
3766                 }
3767                 /* E1 */
3768                 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dslot].cfg)) {
3769                         HFC_outb(hc, R_LOS0, 255); /* 2 ms */
3770                         HFC_outb(hc, R_LOS1, 255); /* 512 ms */
3771                 }
3772                 if (test_bit(HFC_CFG_OPTICAL, &hc->chan[hc->dslot].cfg)) {
3773                         HFC_outb(hc, R_RX0, 0);
3774                         hc->hw.r_tx0 = 0 | V_OUT_EN;
3775                 } else {
3776                         HFC_outb(hc, R_RX0, 1);
3777                         hc->hw.r_tx0 = 1 | V_OUT_EN;
3778                 }
3779                 hc->hw.r_tx1 = V_ATX | V_NTRI;
3780                 HFC_outb(hc, R_TX0, hc->hw.r_tx0);
3781                 HFC_outb(hc, R_TX1, hc->hw.r_tx1);
3782                 HFC_outb(hc, R_TX_FR0, 0x00);
3783                 HFC_outb(hc, R_TX_FR1, 0xf8);
3784
3785                 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dslot].cfg))
3786                         HFC_outb(hc, R_TX_FR2, V_TX_MF | V_TX_E | V_NEG_E);
3787
3788                 HFC_outb(hc, R_RX_FR0, V_AUTO_RESYNC | V_AUTO_RECO | 0);
3789
3790                 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dslot].cfg))
3791                         HFC_outb(hc, R_RX_FR1, V_RX_MF | V_RX_MF_SYNC);
3792
3793                 if (dch->dev.D.protocol == ISDN_P_NT_E1) {
3794                         if (debug & DEBUG_HFCMULTI_INIT)
3795                                 printk(KERN_DEBUG "%s: E1 port is NT-mode\n",
3796                                     __func__);
3797                         r_e1_wr_sta = 0; /* G0 */
3798                         hc->e1_getclock = 0;
3799                 } else {
3800                         if (debug & DEBUG_HFCMULTI_INIT)
3801                                 printk(KERN_DEBUG "%s: E1 port is TE-mode\n",
3802                                     __func__);
3803                         r_e1_wr_sta = 0; /* F0 */
3804                         hc->e1_getclock = 1;
3805                 }
3806                 if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip))
3807                         HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX);
3808                 else
3809                         HFC_outb(hc, R_SYNC_OUT, 0);
3810                 if (test_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip))
3811                         hc->e1_getclock = 1;
3812                 if (test_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip))
3813                         hc->e1_getclock = 0;
3814                 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
3815                         /* SLAVE (clock master) */
3816                         if (debug & DEBUG_HFCMULTI_INIT)
3817                                 printk(KERN_DEBUG
3818                                     "%s: E1 port is clock master "
3819                                     "(clock from PCM)\n", __func__);
3820                         HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC | V_PCM_SYNC);
3821                 } else {
3822                         if (hc->e1_getclock) {
3823                                 /* MASTER (clock slave) */
3824                                 if (debug & DEBUG_HFCMULTI_INIT)
3825                                         printk(KERN_DEBUG
3826                                             "%s: E1 port is clock slave "
3827                                             "(clock to PCM)\n", __func__);
3828                                 HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS);
3829                         } else {
3830                                 /* MASTER (clock master) */
3831                                 if (debug & DEBUG_HFCMULTI_INIT)
3832                                         printk(KERN_DEBUG "%s: E1 port is "
3833                                             "clock master "
3834                                             "(clock from QUARTZ)\n",
3835                                             __func__);
3836                                 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC |
3837                                     V_PCM_SYNC | V_JATT_OFF);
3838                                 HFC_outb(hc, R_SYNC_OUT, 0);
3839                         }
3840                 }
3841                 HFC_outb(hc, R_JATT_ATT, 0x9c); /* undoc register */
3842                 HFC_outb(hc, R_PWM_MD, V_PWM0_MD);
3843                 HFC_outb(hc, R_PWM0, 0x50);
3844                 HFC_outb(hc, R_PWM1, 0xff);
3845                 /* state machine setup */
3846                 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta | V_E1_LD_STA);
3847                 udelay(6); /* wait at least 5,21us */
3848                 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta);
3849                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3850                         hc->syncronized = 0;
3851                         plxsd_checksync(hc, 0);
3852                 }
3853         } else {
3854                 i = dch->slot;
3855                 hc->chan[i].slot_tx = -1;
3856                 hc->chan[i].slot_rx = -1;
3857                 hc->chan[i].conf = -1;
3858                 mode_hfcmulti(hc, i, dch->dev.D.protocol, -1, 0, -1, 0);
3859                 dch->timer.function = (void *)hfcmulti_dbusy_timer;
3860                 dch->timer.data = (long) dch;
3861                 init_timer(&dch->timer);
3862                 hc->chan[i - 2].slot_tx = -1;
3863                 hc->chan[i - 2].slot_rx = -1;
3864                 hc->chan[i - 2].conf = -1;
3865                 mode_hfcmulti(hc, i - 2, ISDN_P_NONE, -1, 0, -1, 0);
3866                 hc->chan[i - 1].slot_tx = -1;
3867                 hc->chan[i - 1].slot_rx = -1;
3868                 hc->chan[i - 1].conf = -1;
3869                 mode_hfcmulti(hc, i - 1, ISDN_P_NONE, -1, 0, -1, 0);
3870                 /* ST */
3871                 pt = hc->chan[i].port;
3872                 /* select interface */
3873                 HFC_outb(hc, R_ST_SEL, pt);
3874                 /* undocumented: delay after R_ST_SEL */
3875                 udelay(1);
3876                 if (dch->dev.D.protocol == ISDN_P_NT_S0) {
3877                         if (debug & DEBUG_HFCMULTI_INIT)
3878                                 printk(KERN_DEBUG
3879                                     "%s: ST port %d is NT-mode\n",
3880                                     __func__, pt);
3881                         /* clock delay */
3882                         HFC_outb(hc, A_ST_CLK_DLY, clockdelay_nt);
3883                         a_st_wr_state = 1; /* G1 */
3884                         hc->hw.a_st_ctrl0[pt] = V_ST_MD;
3885                 } else {
3886                         if (debug & DEBUG_HFCMULTI_INIT)
3887                                 printk(KERN_DEBUG
3888                                     "%s: ST port %d is TE-mode\n",
3889                                     __func__, pt);
3890                         /* clock delay */
3891                         HFC_outb(hc, A_ST_CLK_DLY, clockdelay_te);
3892                         a_st_wr_state = 2; /* F2 */
3893                         hc->hw.a_st_ctrl0[pt] = 0;
3894                 }
3895                 if (!test_bit(HFC_CFG_NONCAP_TX, &hc->chan[i].cfg))
3896                         hc->hw.a_st_ctrl0[pt] |= V_TX_LI;
3897                 /* line setup */
3898                 HFC_outb(hc, A_ST_CTRL0,  hc->hw.a_st_ctrl0[pt]);
3899                 /* disable E-channel */
3900                 if ((dch->dev.D.protocol == ISDN_P_NT_S0) ||
3901                     test_bit(HFC_CFG_DIS_ECHANNEL, &hc->chan[i].cfg))
3902                         HFC_outb(hc, A_ST_CTRL1, V_E_IGNO);
3903                 else
3904                         HFC_outb(hc, A_ST_CTRL1, 0);
3905                 /* enable B-channel receive */
3906                 HFC_outb(hc, A_ST_CTRL2,  V_B1_RX_EN | V_B2_RX_EN);
3907                 /* state machine setup */
3908                 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state | V_ST_LD_STA);
3909                 udelay(6); /* wait at least 5,21us */
3910                 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state);
3911                 hc->hw.r_sci_msk |= 1 << pt;
3912                 /* state machine interrupts */
3913                 HFC_outb(hc, R_SCI_MSK, hc->hw.r_sci_msk);
3914                 /* unset sync on port */
3915                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3916                         hc->syncronized &=
3917                            ~(1 << hc->chan[dch->slot].port);
3918                         plxsd_checksync(hc, 0);
3919                 }
3920         }
3921         if (debug & DEBUG_HFCMULTI_INIT)
3922                 printk("%s: done\n", __func__);
3923 }
3924
3925
3926 static int
3927 open_dchannel(struct hfc_multi *hc, struct dchannel *dch,
3928     struct channel_req *rq)
3929 {
3930         int     err = 0;
3931         u_long  flags;
3932
3933         if (debug & DEBUG_HW_OPEN)
3934                 printk(KERN_DEBUG "%s: dev(%d) open from %p\n", __func__,
3935                     dch->dev.id, __builtin_return_address(0));
3936         if (rq->protocol == ISDN_P_NONE)
3937                 return -EINVAL;
3938         if ((dch->dev.D.protocol != ISDN_P_NONE) &&
3939             (dch->dev.D.protocol != rq->protocol)) {
3940             if (debug & DEBUG_HFCMULTI_MODE)
3941                 printk(KERN_WARNING "%s: change protocol %x to %x\n",
3942                     __func__, dch->dev.D.protocol, rq->protocol);
3943         }
3944         if ((dch->dev.D.protocol == ISDN_P_TE_S0)
3945          && (rq->protocol != ISDN_P_TE_S0))
3946                 l1_event(dch->l1, CLOSE_CHANNEL);
3947         if (dch->dev.D.protocol != rq->protocol) {
3948                 if (rq->protocol == ISDN_P_TE_S0) {
3949                         err = create_l1(dch, hfcm_l1callback);
3950                         if (err)
3951                                 return err;
3952                 }
3953                 dch->dev.D.protocol = rq->protocol;
3954                 spin_lock_irqsave(&hc->lock, flags);
3955                 hfcmulti_initmode(dch);
3956                 spin_unlock_irqrestore(&hc->lock, flags);
3957         }
3958
3959         if (((rq->protocol == ISDN_P_NT_S0) && (dch->state == 3)) ||
3960             ((rq->protocol == ISDN_P_TE_S0) && (dch->state == 7)) ||
3961             ((rq->protocol == ISDN_P_NT_E1) && (dch->state == 1)) ||
3962             ((rq->protocol == ISDN_P_TE_E1) && (dch->state == 1))) {
3963                 _queue_data(&dch->dev.D, PH_ACTIVATE_IND, MISDN_ID_ANY,
3964                     0, NULL, GFP_KERNEL);
3965         }
3966         rq->ch = &dch->dev.D;
3967         if (!try_module_get(THIS_MODULE))
3968                 printk(KERN_WARNING "%s:cannot get module\n", __func__);
3969         return 0;
3970 }
3971
3972 static int
3973 open_bchannel(struct hfc_multi *hc, struct dchannel *dch,
3974     struct channel_req *rq)
3975 {
3976         struct bchannel *bch;
3977         int             ch;
3978
3979         if (!test_channelmap(rq->adr.channel, dch->dev.channelmap))
3980                 return -EINVAL;
3981         if (rq->protocol == ISDN_P_NONE)
3982                 return -EINVAL;
3983         if (hc->type == 1)
3984                 ch = rq->adr.channel;
3985         else
3986                 ch = (rq->adr.channel - 1) + (dch->slot - 2);
3987         bch = hc->chan[ch].bch;
3988         if (!bch) {
3989                 printk(KERN_ERR "%s:internal error ch %d has no bch\n",
3990                     __func__, ch);
3991                 return -EINVAL;
3992         }
3993         if (test_and_set_bit(FLG_OPEN, &bch->Flags))
3994                 return -EBUSY; /* b-channel can be only open once */
3995         bch->ch.protocol = rq->protocol;
3996         hc->chan[ch].rx_off = 0;
3997         rq->ch = &bch->ch;
3998         if (!try_module_get(THIS_MODULE))
3999                 printk(KERN_WARNING "%s:cannot get module\n", __func__);
4000         return 0;
4001 }
4002
4003 /*
4004  * device control function
4005  */
4006 static int
4007 channel_dctrl(struct dchannel *dch, struct mISDN_ctrl_req *cq)
4008 {
4009         int     ret = 0;
4010
4011         switch (cq->op) {
4012         case MISDN_CTRL_GETOP:
4013                 cq->op = 0;
4014                 break;
4015         default:
4016                 printk(KERN_WARNING "%s: unknown Op %x\n",
4017                     __func__, cq->op);
4018                 ret = -EINVAL;
4019                 break;
4020         }
4021         return ret;
4022 }
4023
4024 static int
4025 hfcm_dctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
4026 {
4027         struct mISDNdevice      *dev = container_of(ch, struct mISDNdevice, D);
4028         struct dchannel         *dch = container_of(dev, struct dchannel, dev);
4029         struct hfc_multi        *hc = dch->hw;
4030         struct channel_req      *rq;
4031         int                     err = 0;
4032         u_long                  flags;
4033
4034         if (dch->debug & DEBUG_HW)
4035                 printk(KERN_DEBUG "%s: cmd:%x %p\n",
4036                     __func__, cmd, arg);
4037         switch (cmd) {
4038         case OPEN_CHANNEL:
4039                 rq = arg;
4040                 switch (rq->protocol) {
4041                 case ISDN_P_TE_S0:
4042                 case ISDN_P_NT_S0:
4043                         if (hc->type == 1) {
4044                                 err = -EINVAL;
4045                                 break;
4046                         }
4047                         err = open_dchannel(hc, dch, rq); /* locked there */
4048                         break;
4049                 case ISDN_P_TE_E1:
4050                 case ISDN_P_NT_E1:
4051                         if (hc->type != 1) {
4052                                 err = -EINVAL;
4053                                 break;
4054                         }
4055                         err = open_dchannel(hc, dch, rq); /* locked there */
4056                         break;
4057                 default:
4058                         spin_lock_irqsave(&hc->lock, flags);
4059                         err = open_bchannel(hc, dch, rq);
4060                         spin_unlock_irqrestore(&hc->lock, flags);
4061                 }
4062                 break;
4063         case CLOSE_CHANNEL:
4064                 if (debug & DEBUG_HW_OPEN)
4065                         printk(KERN_DEBUG "%s: dev(%d) close from %p\n",
4066                             __func__, dch->dev.id,
4067                             __builtin_return_address(0));
4068                 module_put(THIS_MODULE);
4069                 break;
4070         case CONTROL_CHANNEL:
4071                 spin_lock_irqsave(&hc->lock, flags);
4072                 err = channel_dctrl(dch, arg);
4073                 spin_unlock_irqrestore(&hc->lock, flags);
4074                 break;
4075         default:
4076                 if (dch->debug & DEBUG_HW)
4077                         printk(KERN_DEBUG "%s: unknown command %x\n",
4078                             __func__, cmd);
4079                 err = -EINVAL;
4080         }
4081         return err;
4082 }
4083
4084 /*
4085  * initialize the card
4086  */
4087
4088 /*
4089  * start timer irq, wait some time and check if we have interrupts.
4090  * if not, reset chip and try again.
4091  */
4092 static int
4093 init_card(struct hfc_multi *hc)
4094 {
4095         int     err = -EIO;
4096         u_long  flags;
4097         void    __iomem *plx_acc;
4098         u_long  plx_flags;
4099
4100         if (debug & DEBUG_HFCMULTI_INIT)
4101                 printk(KERN_DEBUG "%s: entered\n", __func__);
4102
4103         spin_lock_irqsave(&hc->lock, flags);
4104         /* set interrupts but leave global interrupt disabled */
4105         hc->hw.r_irq_ctrl = V_FIFO_IRQ;
4106         disable_hwirq(hc);
4107         spin_unlock_irqrestore(&hc->lock, flags);
4108
4109         if (request_irq(hc->pci_dev->irq, hfcmulti_interrupt, IRQF_SHARED,
4110             "HFC-multi", hc)) {
4111                 printk(KERN_WARNING "mISDN: Could not get interrupt %d.\n",
4112                     hc->pci_dev->irq);
4113                 return -EIO;
4114         }
4115         hc->irq = hc->pci_dev->irq;
4116
4117         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4118                 spin_lock_irqsave(&plx_lock, plx_flags);
4119                 plx_acc = hc->plx_membase + PLX_INTCSR;
4120                 writew((PLX_INTCSR_PCIINT_ENABLE | PLX_INTCSR_LINTI1_ENABLE),
4121                         plx_acc); /* enable PCI & LINT1 irq */
4122                 spin_unlock_irqrestore(&plx_lock, plx_flags);
4123         }
4124
4125         if (debug & DEBUG_HFCMULTI_INIT)
4126                 printk(KERN_DEBUG "%s: IRQ %d count %d\n",
4127                     __func__, hc->irq, hc->irqcnt);
4128         err = init_chip(hc);
4129         if (err)
4130                 goto error;
4131         /*
4132          * Finally enable IRQ output
4133          * this is only allowed, if an IRQ routine is allready
4134          * established for this HFC, so don't do that earlier
4135          */
4136         spin_lock_irqsave(&hc->lock, flags);
4137         enable_hwirq(hc);
4138         spin_unlock_irqrestore(&hc->lock, flags);
4139         /* printk(KERN_DEBUG "no master irq set!!!\n"); */
4140         set_current_state(TASK_UNINTERRUPTIBLE);
4141         schedule_timeout((100*HZ)/1000); /* Timeout 100ms */
4142         /* turn IRQ off until chip is completely initialized */
4143         spin_lock_irqsave(&hc->lock, flags);
4144         disable_hwirq(hc);
4145         spin_unlock_irqrestore(&hc->lock, flags);
4146         if (debug & DEBUG_HFCMULTI_INIT)
4147                 printk(KERN_DEBUG "%s: IRQ %d count %d\n",
4148                     __func__, hc->irq, hc->irqcnt);
4149         if (hc->irqcnt) {
4150                 if (debug & DEBUG_HFCMULTI_INIT)
4151                         printk(KERN_DEBUG "%s: done\n", __func__);
4152
4153                 return 0;
4154         }
4155         if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
4156                 printk(KERN_INFO "ignoring missing interrupts\n");
4157                 return 0;
4158         }
4159
4160         printk(KERN_ERR "HFC PCI: IRQ(%d) getting no interrupts during init.\n",
4161                 hc->irq);
4162
4163         err = -EIO;
4164
4165 error:
4166         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4167                 spin_lock_irqsave(&plx_lock, plx_flags);
4168                 plx_acc = hc->plx_membase + PLX_INTCSR;
4169                 writew(0x00, plx_acc); /*disable IRQs*/
4170                 spin_unlock_irqrestore(&plx_lock, plx_flags);
4171         }
4172
4173         if (debug & DEBUG_HFCMULTI_INIT)
4174                 printk(KERN_WARNING "%s: free irq %d\n", __func__, hc->irq);
4175         if (hc->irq) {
4176                 free_irq(hc->irq, hc);
4177                 hc->irq = 0;
4178         }
4179
4180         if (debug & DEBUG_HFCMULTI_INIT)
4181                 printk(KERN_DEBUG "%s: done (err=%d)\n", __func__, err);
4182         return err;
4183 }
4184
4185 /*
4186  * find pci device and set it up
4187  */
4188
4189 static int
4190 setup_pci(struct hfc_multi *hc, struct pci_dev *pdev,
4191                 const struct pci_device_id *ent)
4192 {
4193         struct hm_map   *m = (struct hm_map *)ent->driver_data;
4194
4195         printk(KERN_INFO
4196             "HFC-multi: card manufacturer: '%s' card name: '%s' clock: %s\n",
4197             m->vendor_name, m->card_name, m->clock2 ? "double" : "normal");
4198
4199         hc->pci_dev = pdev;
4200         if (m->clock2)
4201                 test_and_set_bit(HFC_CHIP_CLOCK2, &hc->chip);
4202
4203         if (ent->device == 0xB410) {
4204                 test_and_set_bit(HFC_CHIP_B410P, &hc->chip);
4205                 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip);
4206                 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
4207                 hc->slots = 32;
4208         }
4209
4210         if (hc->pci_dev->irq <= 0) {
4211                 printk(KERN_WARNING "HFC-multi: No IRQ for PCI card found.\n");
4212                 return -EIO;
4213         }
4214         if (pci_enable_device(hc->pci_dev)) {
4215                 printk(KERN_WARNING "HFC-multi: Error enabling PCI card.\n");
4216                 return -EIO;
4217         }
4218         hc->leds = m->leds;
4219         hc->ledstate = 0xAFFEAFFE;
4220         hc->opticalsupport = m->opticalsupport;
4221
4222         /* set memory access methods */
4223         if (m->io_mode) /* use mode from card config */
4224                 hc->io_mode = m->io_mode;
4225         switch (hc->io_mode) {
4226         case HFC_IO_MODE_PLXSD:
4227                 test_and_set_bit(HFC_CHIP_PLXSD, &hc->chip);
4228                 hc->slots = 128; /* required */
4229                 /* fall through */
4230         case HFC_IO_MODE_PCIMEM:
4231                 hc->HFC_outb = HFC_outb_pcimem;
4232                 hc->HFC_inb = HFC_inb_pcimem;
4233                 hc->HFC_inw = HFC_inw_pcimem;
4234                 hc->HFC_wait = HFC_wait_pcimem;
4235                 hc->read_fifo = read_fifo_pcimem;
4236                 hc->write_fifo = write_fifo_pcimem;
4237                 break;
4238         case HFC_IO_MODE_REGIO:
4239                 hc->HFC_outb = HFC_outb_regio;
4240                 hc->HFC_inb = HFC_inb_regio;
4241                 hc->HFC_inw = HFC_inw_regio;
4242                 hc->HFC_wait = HFC_wait_regio;
4243                 hc->read_fifo = read_fifo_regio;
4244                 hc->write_fifo = write_fifo_regio;
4245                 break;
4246         default:
4247                 printk(KERN_WARNING "HFC-multi: Invalid IO mode.\n");
4248                 pci_disable_device(hc->pci_dev);
4249                 return -EIO;
4250         }
4251         hc->HFC_outb_nodebug = hc->HFC_outb;
4252         hc->HFC_inb_nodebug = hc->HFC_inb;
4253         hc->HFC_inw_nodebug = hc->HFC_inw;
4254         hc->HFC_wait_nodebug = hc->HFC_wait;
4255 #ifdef HFC_REGISTER_DEBUG
4256         hc->HFC_outb = HFC_outb_debug;
4257         hc->HFC_inb = HFC_inb_debug;
4258         hc->HFC_inw = HFC_inw_debug;
4259         hc->HFC_wait = HFC_wait_debug;
4260 #endif
4261         hc->pci_iobase = 0;
4262         hc->pci_membase = NULL;
4263         hc->plx_membase = NULL;
4264
4265         switch (hc->io_mode) {
4266         case HFC_IO_MODE_PLXSD:
4267                 hc->plx_origmembase =  hc->pci_dev->resource[0].start;
4268                 /* MEMBASE 1 is PLX PCI Bridge */
4269
4270                 if (!hc->plx_origmembase) {
4271                         printk(KERN_WARNING
4272                           "HFC-multi: No IO-Memory for PCI PLX bridge found\n");
4273                         pci_disable_device(hc->pci_dev);
4274                         return -EIO;
4275                 }
4276
4277                 hc->plx_membase = ioremap(hc->plx_origmembase, 0x80);
4278                 if (!hc->plx_membase) {
4279                         printk(KERN_WARNING
4280                             "HFC-multi: failed to remap plx address space. "
4281                             "(internal error)\n");
4282                         pci_disable_device(hc->pci_dev);
4283                         return -EIO;
4284                 }
4285                 printk(KERN_INFO
4286                     "HFC-multi: plx_membase:%#lx plx_origmembase:%#lx\n",
4287                     (u_long)hc->plx_membase, hc->plx_origmembase);
4288
4289                 hc->pci_origmembase =  hc->pci_dev->resource[2].start;
4290                     /* MEMBASE 1 is PLX PCI Bridge */
4291                 if (!hc->pci_origmembase) {
4292                         printk(KERN_WARNING
4293                             "HFC-multi: No IO-Memory for PCI card found\n");
4294                         pci_disable_device(hc->pci_dev);
4295                         return -EIO;
4296                 }
4297
4298                 hc->pci_membase = ioremap(hc->pci_origmembase, 0x400);
4299                 if (!hc->pci_membase) {
4300                         printk(KERN_WARNING "HFC-multi: failed to remap io "
4301                             "address space. (internal error)\n");
4302                         pci_disable_device(hc->pci_dev);
4303                         return -EIO;
4304                 }
4305
4306                 printk(KERN_INFO
4307                     "card %d: defined at MEMBASE %#lx (%#lx) IRQ %d HZ %d "
4308                     "leds-type %d\n",
4309                     hc->id, (u_long)hc->pci_membase, hc->pci_origmembase,
4310                     hc->pci_dev->irq, HZ, hc->leds);
4311                 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
4312                 break;
4313         case HFC_IO_MODE_PCIMEM:
4314                 hc->pci_origmembase = hc->pci_dev->resource[1].start;
4315                 if (!hc->pci_origmembase) {
4316                         printk(KERN_WARNING
4317                             "HFC-multi: No IO-Memory for PCI card found\n");
4318                         pci_disable_device(hc->pci_dev);
4319                         return -EIO;
4320                 }
4321
4322                 hc->pci_membase = ioremap(hc->pci_origmembase, 256);
4323                 if (!hc->pci_membase) {
4324                         printk(KERN_WARNING
4325                             "HFC-multi: failed to remap io address space. "
4326                             "(internal error)\n");
4327                         pci_disable_device(hc->pci_dev);
4328                         return -EIO;
4329                 }
4330                 printk(KERN_INFO "card %d: defined at MEMBASE %#lx (%#lx) IRQ %d "
4331                     "HZ %d leds-type %d\n", hc->id, (u_long)hc->pci_membase,
4332                     hc->pci_origmembase, hc->pci_dev->irq, HZ, hc->leds);
4333                 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
4334                 break;
4335         case HFC_IO_MODE_REGIO:
4336                 hc->pci_iobase = (u_int) hc->pci_dev->resource[0].start;
4337                 if (!hc->pci_iobase) {
4338                         printk(KERN_WARNING
4339                                 "HFC-multi: No IO for PCI card found\n");
4340                         pci_disable_device(hc->pci_dev);
4341                         return -EIO;
4342                 }
4343
4344                 if (!request_region(hc->pci_iobase, 8, "hfcmulti")) {
4345                         printk(KERN_WARNING "HFC-multi: failed to request "
4346                             "address space at 0x%08lx (internal error)\n",
4347                             hc->pci_iobase);
4348                         pci_disable_device(hc->pci_dev);
4349                         return -EIO;
4350                 }
4351
4352                 printk(KERN_INFO
4353                     "%s %s: defined at IOBASE %#x IRQ %d HZ %d leds-type %d\n",
4354                     m->vendor_name, m->card_name, (u_int) hc->pci_iobase,
4355                     hc->pci_dev->irq, HZ, hc->leds);
4356                 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_REGIO);
4357                 break;
4358         default:
4359                 printk(KERN_WARNING "HFC-multi: Invalid IO mode.\n");
4360                 pci_disable_device(hc->pci_dev);
4361                 return -EIO;
4362         }
4363
4364         pci_set_drvdata(hc->pci_dev, hc);
4365
4366         /* At this point the needed PCI config is done */
4367         /* fifos are still not enabled */
4368         return 0;
4369 }
4370
4371
4372 /*
4373  * remove port
4374  */
4375
4376 static void
4377 release_port(struct hfc_multi *hc, struct dchannel *dch)
4378 {
4379         int     pt, ci, i = 0;
4380         u_long  flags;
4381         struct bchannel *pb;
4382
4383         ci = dch->slot;
4384         pt = hc->chan[ci].port;
4385
4386         if (debug & DEBUG_HFCMULTI_INIT)
4387                 printk(KERN_DEBUG "%s: entered for port %d\n",
4388                         __func__, pt + 1);
4389
4390         if (pt >= hc->ports) {
4391                 printk(KERN_WARNING "%s: ERROR port out of range (%d).\n",
4392                      __func__, pt + 1);
4393                 return;
4394         }
4395
4396         if (debug & DEBUG_HFCMULTI_INIT)
4397                 printk(KERN_DEBUG "%s: releasing port=%d\n",
4398                     __func__, pt + 1);
4399
4400         if (dch->dev.D.protocol == ISDN_P_TE_S0)
4401                 l1_event(dch->l1, CLOSE_CHANNEL);
4402
4403         hc->chan[ci].dch = NULL;
4404
4405         if (hc->created[pt]) {
4406                 hc->created[pt] = 0;
4407                 mISDN_unregister_device(&dch->dev);
4408         }
4409
4410         spin_lock_irqsave(&hc->lock, flags);
4411
4412         if (dch->timer.function) {
4413                 del_timer(&dch->timer);
4414                 dch->timer.function = NULL;
4415         }
4416
4417         if (hc->type == 1) { /* E1 */
4418                 /* remove sync */
4419                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4420                         hc->syncronized = 0;
4421                         plxsd_checksync(hc, 1);
4422                 }
4423                 /* free channels */
4424                 for (i = 0; i <= 31; i++) {
4425                         if (hc->chan[i].bch) {
4426                                 if (debug & DEBUG_HFCMULTI_INIT)
4427                                         printk(KERN_DEBUG
4428                                             "%s: free port %d channel %d\n",
4429                                             __func__, hc->chan[i].port+1, i);
4430                                 pb = hc->chan[i].bch;
4431                                 hc->chan[i].bch = NULL;
4432                                 spin_unlock_irqrestore(&hc->lock, flags);
4433                                 mISDN_freebchannel(pb);
4434                                 kfree(pb);
4435                                 kfree(hc->chan[i].coeff);
4436                                 spin_lock_irqsave(&hc->lock, flags);
4437                         }
4438                 }
4439         } else {
4440                 /* remove sync */
4441                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4442                         hc->syncronized &=
4443                            ~(1 << hc->chan[ci].port);
4444                         plxsd_checksync(hc, 1);
4445                 }
4446                 /* free channels */
4447                 if (hc->chan[ci - 2].bch) {
4448                         if (debug & DEBUG_HFCMULTI_INIT)
4449                                 printk(KERN_DEBUG
4450                                     "%s: free port %d channel %d\n",
4451                                     __func__, hc->chan[ci - 2].port+1,
4452                                     ci - 2);
4453                         pb = hc->chan[ci - 2].bch;
4454                         hc->chan[ci - 2].bch = NULL;
4455                         spin_unlock_irqrestore(&hc->lock, flags);
4456                         mISDN_freebchannel(pb);
4457                         kfree(pb);
4458                         kfree(hc->chan[ci - 2].coeff);
4459                         spin_lock_irqsave(&hc->lock, flags);
4460                 }
4461                 if (hc->chan[ci - 1].bch) {
4462                         if (debug & DEBUG_HFCMULTI_INIT)
4463                                 printk(KERN_DEBUG
4464                                     "%s: free port %d channel %d\n",
4465                                     __func__, hc->chan[ci - 1].port+1,
4466                                     ci - 1);
4467                         pb = hc->chan[ci - 1].bch;
4468                         hc->chan[ci - 1].bch = NULL;
4469                         spin_unlock_irqrestore(&hc->lock, flags);
4470                         mISDN_freebchannel(pb);
4471                         kfree(pb);
4472                         kfree(hc->chan[ci - 1].coeff);
4473                         spin_lock_irqsave(&hc->lock, flags);
4474                 }
4475         }
4476
4477         spin_unlock_irqrestore(&hc->lock, flags);
4478
4479         if (debug & DEBUG_HFCMULTI_INIT)
4480                 printk(KERN_DEBUG "%s: free port %d channel D\n", __func__, pt);
4481         mISDN_freedchannel(dch);
4482         kfree(dch);
4483
4484         if (debug & DEBUG_HFCMULTI_INIT)
4485                 printk(KERN_DEBUG "%s: done!\n", __func__);
4486 }
4487
4488 static void
4489 release_card(struct hfc_multi *hc)
4490 {
4491         u_long  flags;
4492         int     ch;
4493
4494         if (debug & DEBUG_HFCMULTI_INIT)
4495                 printk(KERN_WARNING "%s: release card (%d) entered\n",
4496                     __func__, hc->id);
4497
4498         spin_lock_irqsave(&hc->lock, flags);
4499         disable_hwirq(hc);
4500         spin_unlock_irqrestore(&hc->lock, flags);
4501
4502         udelay(1000);
4503
4504         /* dimm leds */
4505         if (hc->leds)
4506                 hfcmulti_leds(hc);
4507
4508         /* disable D-channels & B-channels */
4509         if (debug & DEBUG_HFCMULTI_INIT)
4510                 printk(KERN_DEBUG "%s: disable all channels (d and b)\n",
4511                     __func__);
4512         for (ch = 0; ch <= 31; ch++) {
4513                 if (hc->chan[ch].dch)
4514                         release_port(hc, hc->chan[ch].dch);
4515         }
4516
4517         /* release hardware & irq */
4518         if (hc->irq) {
4519                 if (debug & DEBUG_HFCMULTI_INIT)
4520                         printk(KERN_WARNING "%s: free irq %d\n",
4521                             __func__, hc->irq);
4522                 free_irq(hc->irq, hc);
4523                 hc->irq = 0;
4524
4525         }
4526         release_io_hfcmulti(hc);
4527
4528         if (debug & DEBUG_HFCMULTI_INIT)
4529                 printk(KERN_WARNING "%s: remove instance from list\n",
4530                      __func__);
4531         list_del(&hc->list);
4532
4533         if (debug & DEBUG_HFCMULTI_INIT)
4534                 printk(KERN_WARNING "%s: delete instance\n", __func__);
4535         if (hc == syncmaster)
4536                 syncmaster = NULL;
4537         kfree(hc);
4538         if (debug & DEBUG_HFCMULTI_INIT)
4539                 printk(KERN_WARNING "%s: card successfully removed\n",
4540                     __func__);
4541 }
4542
4543 static int
4544 init_e1_port(struct hfc_multi *hc, struct hm_map *m)
4545 {
4546         struct dchannel *dch;
4547         struct bchannel *bch;
4548         int             ch, ret = 0;
4549         char            name[MISDN_MAX_IDLEN];
4550
4551         dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL);
4552         if (!dch)
4553                 return -ENOMEM;
4554         dch->debug = debug;
4555         mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change);
4556         dch->hw = hc;
4557         dch->dev.Dprotocols = (1 << ISDN_P_TE_E1) | (1 << ISDN_P_NT_E1);
4558         dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
4559             (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
4560         dch->dev.D.send = handle_dmsg;
4561         dch->dev.D.ctrl = hfcm_dctrl;
4562         dch->dev.nrbchan = (hc->dslot)?30:31;
4563         dch->slot = hc->dslot;
4564         hc->chan[hc->dslot].dch = dch;
4565         hc->chan[hc->dslot].port = 0;
4566         hc->chan[hc->dslot].nt_timer = -1;
4567         for (ch = 1; ch <= 31; ch++) {
4568                 if (ch == hc->dslot) /* skip dchannel */
4569                         continue;
4570                 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL);
4571                 if (!bch) {
4572                         printk(KERN_ERR "%s: no memory for bchannel\n",
4573                             __func__);
4574                         ret = -ENOMEM;
4575                         goto free_chan;
4576                 }
4577                 hc->chan[ch].coeff = kzalloc(512, GFP_KERNEL);
4578                 if (!hc->chan[ch].coeff) {
4579                         printk(KERN_ERR "%s: no memory for coeffs\n",
4580                             __func__);
4581                         ret = -ENOMEM;
4582                         goto free_chan;
4583                 }
4584                 bch->nr = ch;
4585                 bch->slot = ch;
4586                 bch->debug = debug;
4587                 mISDN_initbchannel(bch, MAX_DATA_MEM);
4588                 bch->hw = hc;
4589                 bch->ch.send = handle_bmsg;
4590                 bch->ch.ctrl = hfcm_bctrl;
4591                 bch->ch.nr = ch;
4592                 list_add(&bch->ch.list, &dch->dev.bchannels);
4593                 hc->chan[ch].bch = bch;
4594                 hc->chan[ch].port = 0;
4595                 set_channelmap(bch->nr, dch->dev.channelmap);
4596         }
4597         /* set optical line type */
4598         if (port[Port_cnt] & 0x001) {
4599                 if (!m->opticalsupport)  {
4600                         printk(KERN_INFO
4601                             "This board has no optical "
4602                             "support\n");
4603                 } else {
4604                         if (debug & DEBUG_HFCMULTI_INIT)
4605                                 printk(KERN_DEBUG
4606                                     "%s: PORT set optical "
4607                                     "interfacs: card(%d) "
4608                                     "port(%d)\n",
4609                                     __func__,
4610                                     HFC_cnt + 1, 1);
4611                         test_and_set_bit(HFC_CFG_OPTICAL,
4612                             &hc->chan[hc->dslot].cfg);
4613                 }
4614         }
4615         /* set LOS report */
4616         if (port[Port_cnt] & 0x004) {
4617                 if (debug & DEBUG_HFCMULTI_INIT)
4618                         printk(KERN_DEBUG "%s: PORT set "
4619                             "LOS report: card(%d) port(%d)\n",
4620                             __func__, HFC_cnt + 1, 1);
4621                 test_and_set_bit(HFC_CFG_REPORT_LOS,
4622                     &hc->chan[hc->dslot].cfg);
4623         }
4624         /* set AIS report */
4625         if (port[Port_cnt] & 0x008) {
4626                 if (debug & DEBUG_HFCMULTI_INIT)
4627                         printk(KERN_DEBUG "%s: PORT set "
4628                             "AIS report: card(%d) port(%d)\n",
4629                             __func__, HFC_cnt + 1, 1);
4630                 test_and_set_bit(HFC_CFG_REPORT_AIS,
4631                     &hc->chan[hc->dslot].cfg);
4632         }
4633         /* set SLIP report */
4634         if (port[Port_cnt] & 0x010) {
4635                 if (debug & DEBUG_HFCMULTI_INIT)
4636                         printk(KERN_DEBUG
4637                             "%s: PORT set SLIP report: "
4638                             "card(%d) port(%d)\n",
4639                             __func__, HFC_cnt + 1, 1);
4640                 test_and_set_bit(HFC_CFG_REPORT_SLIP,
4641                     &hc->chan[hc->dslot].cfg);
4642         }
4643         /* set RDI report */
4644         if (port[Port_cnt] & 0x020) {
4645                 if (debug & DEBUG_HFCMULTI_INIT)
4646                         printk(KERN_DEBUG
4647                             "%s: PORT set RDI report: "
4648                             "card(%d) port(%d)\n",
4649                             __func__, HFC_cnt + 1, 1);
4650                 test_and_set_bit(HFC_CFG_REPORT_RDI,
4651                     &hc->chan[hc->dslot].cfg);
4652         }
4653         /* set CRC-4 Mode */
4654         if (!(port[Port_cnt] & 0x100)) {
4655                 if (debug & DEBUG_HFCMULTI_INIT)
4656                         printk(KERN_DEBUG "%s: PORT turn on CRC4 report:"
4657                                 " card(%d) port(%d)\n",
4658                                 __func__, HFC_cnt + 1, 1);
4659                 test_and_set_bit(HFC_CFG_CRC4,
4660                     &hc->chan[hc->dslot].cfg);
4661         } else {
4662                 if (debug & DEBUG_HFCMULTI_INIT)
4663                         printk(KERN_DEBUG "%s: PORT turn off CRC4"
4664                                 " report: card(%d) port(%d)\n",
4665                                 __func__, HFC_cnt + 1, 1);
4666         }
4667         /* set forced clock */
4668         if (port[Port_cnt] & 0x0200) {
4669                 if (debug & DEBUG_HFCMULTI_INIT)
4670                         printk(KERN_DEBUG "%s: PORT force getting clock from "
4671                                 "E1: card(%d) port(%d)\n",
4672                                 __func__, HFC_cnt + 1, 1);
4673                 test_and_set_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip);
4674         } else
4675         if (port[Port_cnt] & 0x0400) {
4676                 if (debug & DEBUG_HFCMULTI_INIT)
4677                         printk(KERN_DEBUG "%s: PORT force putting clock to "
4678                                 "E1: card(%d) port(%d)\n",
4679                                 __func__, HFC_cnt + 1, 1);
4680                 test_and_set_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip);
4681         }
4682         /* set JATT PLL */
4683         if (port[Port_cnt] & 0x0800) {
4684                 if (debug & DEBUG_HFCMULTI_INIT)
4685                         printk(KERN_DEBUG "%s: PORT disable JATT PLL on "
4686                                 "E1: card(%d) port(%d)\n",
4687                                 __func__, HFC_cnt + 1, 1);
4688                 test_and_set_bit(HFC_CHIP_RX_SYNC, &hc->chip);
4689         }
4690         /* set elastic jitter buffer */
4691         if (port[Port_cnt] & 0x3000) {
4692                 hc->chan[hc->dslot].jitter = (port[Port_cnt]>>12) & 0x3;
4693                 if (debug & DEBUG_HFCMULTI_INIT)
4694                         printk(KERN_DEBUG
4695                             "%s: PORT set elastic "
4696                             "buffer to %d: card(%d) port(%d)\n",
4697                             __func__, hc->chan[hc->dslot].jitter,
4698                             HFC_cnt + 1, 1);
4699         } else
4700                 hc->chan[hc->dslot].jitter = 2; /* default */
4701         snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-e1.%d", HFC_cnt + 1);
4702         ret = mISDN_register_device(&dch->dev, name);
4703         if (ret)
4704                 goto free_chan;
4705         hc->created[0] = 1;
4706         return ret;
4707 free_chan:
4708         release_port(hc, dch);
4709         return ret;
4710 }
4711
4712 static int
4713 init_multi_port(struct hfc_multi *hc, int pt)
4714 {
4715         struct dchannel *dch;
4716         struct bchannel *bch;
4717         int             ch, i, ret = 0;
4718         char            name[MISDN_MAX_IDLEN];
4719
4720         dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL);
4721         if (!dch)
4722                 return -ENOMEM;
4723         dch->debug = debug;
4724         mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change);
4725         dch->hw = hc;
4726         dch->dev.Dprotocols = (1 << ISDN_P_TE_S0) | (1 << ISDN_P_NT_S0);
4727         dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
4728             (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
4729         dch->dev.D.send = handle_dmsg;
4730         dch->dev.D.ctrl = hfcm_dctrl;
4731         dch->dev.nrbchan = 2;
4732         i = pt << 2;
4733         dch->slot = i + 2;
4734         hc->chan[i + 2].dch = dch;
4735         hc->chan[i + 2].port = pt;
4736         hc->chan[i + 2].nt_timer = -1;
4737         for (ch = 0; ch < dch->dev.nrbchan; ch++) {
4738                 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL);
4739                 if (!bch) {
4740                         printk(KERN_ERR "%s: no memory for bchannel\n",
4741                             __func__);
4742                         ret = -ENOMEM;
4743                         goto free_chan;
4744                 }
4745                 hc->chan[i + ch].coeff = kzalloc(512, GFP_KERNEL);
4746                 if (!hc->chan[i + ch].coeff) {
4747                         printk(KERN_ERR "%s: no memory for coeffs\n",
4748                             __func__);
4749                         ret = -ENOMEM;
4750                         goto free_chan;
4751                 }
4752                 bch->nr = ch + 1;
4753                 bch->slot = i + ch;
4754                 bch->debug = debug;
4755                 mISDN_initbchannel(bch, MAX_DATA_MEM);
4756                 bch->hw = hc;
4757                 bch->ch.send = handle_bmsg;
4758                 bch->ch.ctrl = hfcm_bctrl;
4759                 bch->ch.nr = ch + 1;
4760                 list_add(&bch->ch.list, &dch->dev.bchannels);
4761                 hc->chan[i + ch].bch = bch;
4762                 hc->chan[i + ch].port = pt;
4763                 set_channelmap(bch->nr, dch->dev.channelmap);
4764         }
4765         /* set master clock */
4766         if (port[Port_cnt] & 0x001) {
4767                 if (debug & DEBUG_HFCMULTI_INIT)
4768                         printk(KERN_DEBUG
4769                             "%s: PROTOCOL set master clock: "
4770                             "card(%d) port(%d)\n",
4771                             __func__, HFC_cnt + 1, pt + 1);
4772                 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
4773                         printk(KERN_ERR "Error: Master clock "
4774                             "for port(%d) of card(%d) is only"
4775                             " possible with TE-mode\n",
4776                             pt + 1, HFC_cnt + 1);
4777                         ret = -EINVAL;
4778                         goto free_chan;
4779                 }
4780                 if (hc->masterclk >= 0) {
4781                         printk(KERN_ERR "Error: Master clock "
4782                             "for port(%d) of card(%d) already "
4783                             "defined for port(%d)\n",
4784                             pt + 1, HFC_cnt + 1, hc->masterclk+1);
4785                         ret = -EINVAL;
4786                         goto free_chan;
4787                 }
4788                 hc->masterclk = pt;
4789         }
4790         /* set transmitter line to non capacitive */
4791         if (port[Port_cnt] & 0x002) {
4792                 if (debug & DEBUG_HFCMULTI_INIT)
4793                         printk(KERN_DEBUG
4794                             "%s: PROTOCOL set non capacitive "
4795                             "transmitter: card(%d) port(%d)\n",
4796                             __func__, HFC_cnt + 1, pt + 1);
4797                 test_and_set_bit(HFC_CFG_NONCAP_TX,
4798                     &hc->chan[i + 2].cfg);
4799         }
4800         /* disable E-channel */
4801         if (port[Port_cnt] & 0x004) {
4802         if (debug & DEBUG_HFCMULTI_INIT)
4803                         printk(KERN_DEBUG
4804                             "%s: PROTOCOL disable E-channel: "
4805                             "card(%d) port(%d)\n",
4806                             __func__, HFC_cnt + 1, pt + 1);
4807                 test_and_set_bit(HFC_CFG_DIS_ECHANNEL,
4808                     &hc->chan[i + 2].cfg);
4809         }
4810         snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-%ds.%d/%d",
4811                 hc->type, HFC_cnt + 1, pt + 1);
4812         ret = mISDN_register_device(&dch->dev, name);
4813         if (ret)
4814                 goto free_chan;
4815         hc->created[pt] = 1;
4816         return ret;
4817 free_chan:
4818         release_port(hc, dch);
4819         return ret;
4820 }
4821
4822 static int
4823 hfcmulti_init(struct pci_dev *pdev, const struct pci_device_id *ent)
4824 {
4825         struct hm_map   *m = (struct hm_map *)ent->driver_data;
4826         int             ret_err = 0;
4827         int             pt;
4828         struct hfc_multi        *hc;
4829         u_long          flags;
4830         u_char          dips = 0, pmj = 0; /* dip settings, port mode Jumpers */
4831
4832         if (HFC_cnt >= MAX_CARDS) {
4833                 printk(KERN_ERR "too many cards (max=%d).\n",
4834                         MAX_CARDS);
4835                 return -EINVAL;
4836         }
4837         if ((type[HFC_cnt] & 0xff) && (type[HFC_cnt] & 0xff) != m->type) {
4838                 printk(KERN_WARNING "HFC-MULTI: Card '%s:%s' type %d found but "
4839                     "type[%d] %d was supplied as module parameter\n",
4840                     m->vendor_name, m->card_name, m->type, HFC_cnt,
4841                     type[HFC_cnt] & 0xff);
4842                 printk(KERN_WARNING "HFC-MULTI: Load module without parameters "
4843                         "first, to see cards and their types.");
4844                 return -EINVAL;
4845         }
4846         if (debug & DEBUG_HFCMULTI_INIT)
4847                 printk(KERN_DEBUG "%s: Registering %s:%s chip type %d (0x%x)\n",
4848                     __func__, m->vendor_name, m->card_name, m->type,
4849                     type[HFC_cnt]);
4850
4851         /* allocate card+fifo structure */
4852         hc = kzalloc(sizeof(struct hfc_multi), GFP_KERNEL);
4853         if (!hc) {
4854                 printk(KERN_ERR "No kmem for HFC-Multi card\n");
4855                 return -ENOMEM;
4856         }
4857         spin_lock_init(&hc->lock);
4858         hc->mtyp = m;
4859         hc->type =  m->type;
4860         hc->ports = m->ports;
4861         hc->id = HFC_cnt;
4862         hc->pcm = pcm[HFC_cnt];
4863         hc->io_mode = iomode[HFC_cnt];
4864         if (dslot[HFC_cnt] < 0) {
4865                 hc->dslot = 0;
4866                 printk(KERN_INFO "HFC-E1 card has disabled D-channel, but "
4867                         "31 B-channels\n");
4868         } if (dslot[HFC_cnt] > 0 && dslot[HFC_cnt] < 32) {
4869                 hc->dslot = dslot[HFC_cnt];
4870                 printk(KERN_INFO "HFC-E1 card has alternating D-channel on "
4871                         "time slot %d\n", dslot[HFC_cnt]);
4872         } else
4873                 hc->dslot = 16;
4874
4875         /* set chip specific features */
4876         hc->masterclk = -1;
4877         if (type[HFC_cnt] & 0x100) {
4878                 test_and_set_bit(HFC_CHIP_ULAW, &hc->chip);
4879                 silence = 0xff; /* ulaw silence */
4880         } else
4881                 silence = 0x2a; /* alaw silence */
4882         if (!(type[HFC_cnt] & 0x200))
4883                 test_and_set_bit(HFC_CHIP_DTMF, &hc->chip);
4884
4885         if (type[HFC_cnt] & 0x800)
4886                 test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
4887         if (type[HFC_cnt] & 0x1000) {
4888                 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip);
4889                 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
4890         }
4891         if (type[HFC_cnt] & 0x4000)
4892                 test_and_set_bit(HFC_CHIP_EXRAM_128, &hc->chip);
4893         if (type[HFC_cnt] & 0x8000)
4894                 test_and_set_bit(HFC_CHIP_EXRAM_512, &hc->chip);
4895         hc->slots = 32;
4896         if (type[HFC_cnt] & 0x10000)
4897                 hc->slots = 64;
4898         if (type[HFC_cnt] & 0x20000)
4899                 hc->slots = 128;
4900         if (type[HFC_cnt] & 0x80000) {
4901                 test_and_set_bit(HFC_CHIP_WATCHDOG, &hc->chip);
4902                 hc->wdcount = 0;
4903                 hc->wdbyte = V_GPIO_OUT2;
4904                 printk(KERN_NOTICE "Watchdog enabled\n");
4905         }
4906
4907         /* setup pci, hc->slots may change due to PLXSD */
4908         ret_err = setup_pci(hc, pdev, ent);
4909         if (ret_err) {
4910                 if (hc == syncmaster)
4911                         syncmaster = NULL;
4912                 kfree(hc);
4913                 return ret_err;
4914         }
4915
4916         /* crate channels */
4917         for (pt = 0; pt < hc->ports; pt++) {
4918                 if (Port_cnt >= MAX_PORTS) {
4919                         printk(KERN_ERR "too many ports (max=%d).\n",
4920                                 MAX_PORTS);
4921                         ret_err = -EINVAL;
4922                         goto free_card;
4923                 }
4924                 if (hc->type == 1)
4925                         ret_err = init_e1_port(hc, m);
4926                 else
4927                         ret_err = init_multi_port(hc, pt);
4928                 if (debug & DEBUG_HFCMULTI_INIT)
4929                         printk(KERN_DEBUG
4930                             "%s: Registering D-channel, card(%d) port(%d)"
4931                             "result %d\n",
4932                             __func__, HFC_cnt + 1, pt, ret_err);
4933
4934                 if (ret_err) {
4935                         while (pt) { /* release already registered ports */
4936                                 pt--;
4937                                 release_port(hc, hc->chan[(pt << 2) + 2].dch);
4938                         }
4939                         goto free_card;
4940                 }
4941                 Port_cnt++;
4942         }
4943
4944         /* disp switches */
4945         switch (m->dip_type) {
4946         case DIP_4S:
4947                 /*
4948                  * get DIP Setting for beroNet 1S/2S/4S cards
4949                  *  check if Port Jumper config matches
4950                  * module param 'protocol'
4951                  * DIP Setting: (collect GPIO 13/14/15 (R_GPIO_IN1) +
4952                  * GPI 19/23 (R_GPI_IN2))
4953                  */
4954                 dips = ((~HFC_inb(hc, R_GPIO_IN1) & 0xE0) >> 5) |
4955                         ((~HFC_inb(hc, R_GPI_IN2) & 0x80) >> 3) |
4956                         (~HFC_inb(hc, R_GPI_IN2) & 0x08);
4957
4958                 /* Port mode (TE/NT) jumpers */
4959                 pmj = ((HFC_inb(hc, R_GPI_IN3) >> 4)  & 0xf);
4960
4961                 if (test_bit(HFC_CHIP_B410P, &hc->chip))
4962                         pmj = ~pmj & 0xf;
4963
4964                 printk(KERN_INFO "%s: %s DIPs(0x%x) jumpers(0x%x)\n",
4965                         m->vendor_name, m->card_name, dips, pmj);
4966                 break;
4967         case DIP_8S:
4968                 /*
4969                  * get DIP Setting for beroNet 8S0+ cards
4970                  *
4971                  * enable PCI auxbridge function
4972                  */
4973                 HFC_outb(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK);
4974                 /* prepare access to auxport */
4975                 outw(0x4000, hc->pci_iobase + 4);
4976                 /*
4977                  * some dummy reads are required to
4978                  * read valid DIP switch data
4979                  */
4980                 dips = inb(hc->pci_iobase);
4981                 dips = inb(hc->pci_iobase);
4982                 dips = inb(hc->pci_iobase);
4983                 dips = ~inb(hc->pci_iobase) & 0x3F;
4984                 outw(0x0, hc->pci_iobase + 4);
4985                 /* disable PCI auxbridge function */
4986                 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK);
4987                 printk(KERN_INFO "%s: %s DIPs(0x%x)\n",
4988                     m->vendor_name, m->card_name, dips);
4989                 break;
4990         case DIP_E1:
4991                 /*
4992                  * get DIP Setting for beroNet E1 cards
4993                  * DIP Setting: collect GPI 4/5/6/7 (R_GPI_IN0)
4994                  */
4995                 dips = (~HFC_inb(hc, R_GPI_IN0) & 0xF0)>>4;
4996                 printk(KERN_INFO "%s: %s DIPs(0x%x)\n",
4997                     m->vendor_name, m->card_name, dips);
4998                 break;
4999         }
5000
5001         /* add to list */
5002         spin_lock_irqsave(&HFClock, flags);
5003         list_add_tail(&hc->list, &HFClist);
5004         spin_unlock_irqrestore(&HFClock, flags);
5005
5006         /* initialize hardware */
5007         ret_err = init_card(hc);
5008         if (ret_err) {
5009                 printk(KERN_ERR "init card returns %d\n", ret_err);
5010                 release_card(hc);
5011                 return ret_err;
5012         }
5013
5014         /* start IRQ and return */
5015         spin_lock_irqsave(&hc->lock, flags);
5016         enable_hwirq(hc);
5017         spin_unlock_irqrestore(&hc->lock, flags);
5018         return 0;
5019
5020 free_card:
5021         release_io_hfcmulti(hc);
5022         if (hc == syncmaster)
5023                 syncmaster = NULL;
5024         kfree(hc);
5025         return ret_err;
5026 }
5027
5028 static void __devexit hfc_remove_pci(struct pci_dev *pdev)
5029 {
5030         struct hfc_multi        *card = pci_get_drvdata(pdev);
5031         u_long                  flags;
5032
5033         if (debug)
5034                 printk(KERN_INFO "removing hfc_multi card vendor:%x "
5035                     "device:%x subvendor:%x subdevice:%x\n",
5036                     pdev->vendor, pdev->device,
5037                     pdev->subsystem_vendor, pdev->subsystem_device);
5038
5039         if (card) {
5040                 spin_lock_irqsave(&HFClock, flags);
5041                 release_card(card);
5042                 spin_unlock_irqrestore(&HFClock, flags);
5043         }  else {
5044                 if (debug)
5045                         printk(KERN_WARNING "%s: drvdata allready removed\n",
5046                             __func__);
5047         }
5048 }
5049
5050 #define VENDOR_CCD      "Cologne Chip AG"
5051 #define VENDOR_BN       "beroNet GmbH"
5052 #define VENDOR_DIG      "Digium Inc."
5053 #define VENDOR_JH       "Junghanns.NET GmbH"
5054 #define VENDOR_PRIM     "PrimuX"
5055
5056 static const struct hm_map hfcm_map[] = {
5057 /*0*/   {VENDOR_BN, "HFC-1S Card (mini PCI)", 4, 1, 1, 3, 0, DIP_4S, 0},
5058 /*1*/   {VENDOR_BN, "HFC-2S Card", 4, 2, 1, 3, 0, DIP_4S, 0},
5059 /*2*/   {VENDOR_BN, "HFC-2S Card (mini PCI)", 4, 2, 1, 3, 0, DIP_4S, 0},
5060 /*3*/   {VENDOR_BN, "HFC-4S Card", 4, 4, 1, 2, 0, DIP_4S, 0},
5061 /*4*/   {VENDOR_BN, "HFC-4S Card (mini PCI)", 4, 4, 1, 2, 0, 0, 0},
5062 /*5*/   {VENDOR_CCD, "HFC-4S Eval (old)", 4, 4, 0, 0, 0, 0, 0},
5063 /*6*/   {VENDOR_CCD, "HFC-4S IOB4ST", 4, 4, 1, 2, 0, DIP_4S, 0},
5064 /*7*/   {VENDOR_CCD, "HFC-4S", 4, 4, 1, 2, 0, 0, 0},
5065 /*8*/   {VENDOR_DIG, "HFC-4S Card", 4, 4, 0, 2, 0, 0, HFC_IO_MODE_REGIO},
5066 /*9*/   {VENDOR_CCD, "HFC-4S Swyx 4xS0 SX2 QuadBri", 4, 4, 1, 2, 0, 0, 0},
5067 /*10*/  {VENDOR_JH, "HFC-4S (junghanns 2.0)", 4, 4, 1, 2, 0, 0, 0},
5068 /*11*/  {VENDOR_PRIM, "HFC-2S Primux Card", 4, 2, 0, 0, 0, 0, 0},
5069
5070 /*12*/  {VENDOR_BN, "HFC-8S Card", 8, 8, 1, 0, 0, 0, 0},
5071 /*13*/  {VENDOR_BN, "HFC-8S Card (+)", 8, 8, 1, 8, 0, DIP_8S,
5072                 HFC_IO_MODE_REGIO},
5073 /*14*/  {VENDOR_CCD, "HFC-8S Eval (old)", 8, 8, 0, 0, 0, 0, 0},
5074 /*15*/  {VENDOR_CCD, "HFC-8S IOB4ST Recording", 8, 8, 1, 0, 0, 0, 0},
5075
5076 /*16*/  {VENDOR_CCD, "HFC-8S IOB8ST", 8, 8, 1, 0, 0, 0, 0},
5077 /*17*/  {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0},
5078 /*18*/  {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0},
5079
5080 /*19*/  {VENDOR_BN, "HFC-E1 Card", 1, 1, 0, 1, 0, DIP_E1, 0},
5081 /*20*/  {VENDOR_BN, "HFC-E1 Card (mini PCI)", 1, 1, 0, 1, 0, 0, 0},
5082 /*21*/  {VENDOR_BN, "HFC-E1+ Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0},
5083 /*22*/  {VENDOR_BN, "HFC-E1 Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0},
5084
5085 /*23*/  {VENDOR_CCD, "HFC-E1 Eval (old)", 1, 1, 0, 0, 0, 0, 0},
5086 /*24*/  {VENDOR_CCD, "HFC-E1 IOB1E1", 1, 1, 0, 1, 0, 0, 0},
5087 /*25*/  {VENDOR_CCD, "HFC-E1", 1, 1, 0, 1, 0, 0, 0},
5088
5089 /*26*/  {VENDOR_CCD, "HFC-4S Speech Design", 4, 4, 0, 0, 0, 0,
5090                 HFC_IO_MODE_PLXSD},
5091 /*27*/  {VENDOR_CCD, "HFC-E1 Speech Design", 1, 1, 0, 0, 0, 0,
5092                 HFC_IO_MODE_PLXSD},
5093 /*28*/  {VENDOR_CCD, "HFC-4S OpenVox", 4, 4, 1, 0, 0, 0, 0},
5094 /*29*/  {VENDOR_CCD, "HFC-2S OpenVox", 4, 2, 1, 0, 0, 0, 0},
5095 /*30*/  {VENDOR_CCD, "HFC-8S OpenVox", 8, 8, 1, 0, 0, 0, 0},
5096 };
5097
5098 #undef H
5099 #define H(x)    ((unsigned long)&hfcm_map[x])
5100 static struct pci_device_id hfmultipci_ids[] __devinitdata = {
5101
5102         /* Cards with HFC-4S Chip */
5103         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5104                 PCI_SUBDEVICE_ID_CCD_BN1SM, 0, 0, H(0)}, /* BN1S mini PCI */
5105         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5106                 PCI_SUBDEVICE_ID_CCD_BN2S, 0, 0, H(1)}, /* BN2S */
5107         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5108                 PCI_SUBDEVICE_ID_CCD_BN2SM, 0, 0, H(2)}, /* BN2S mini PCI */
5109         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5110                 PCI_SUBDEVICE_ID_CCD_BN4S, 0, 0, H(3)}, /* BN4S */
5111         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5112                 PCI_SUBDEVICE_ID_CCD_BN4SM, 0, 0, H(4)}, /* BN4S mini PCI */
5113         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5114                 PCI_DEVICE_ID_CCD_HFC4S, 0, 0, H(5)}, /* Old Eval */
5115         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5116                 PCI_SUBDEVICE_ID_CCD_IOB4ST, 0, 0, H(6)}, /* IOB4ST */
5117         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5118                 PCI_SUBDEVICE_ID_CCD_HFC4S, 0, 0, H(7)}, /* 4S */
5119         { PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S,
5120                 PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S, 0, 0, H(8)},
5121         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5122                 PCI_SUBDEVICE_ID_CCD_SWYX4S, 0, 0, H(9)}, /* 4S Swyx */
5123         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5124                 PCI_SUBDEVICE_ID_CCD_JH4S20, 0, 0, H(10)},
5125         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5126                 PCI_SUBDEVICE_ID_CCD_PMX2S, 0, 0, H(11)}, /* Primux */
5127         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5128                 PCI_SUBDEVICE_ID_CCD_OV4S, 0, 0, H(28)}, /* OpenVox 4 */
5129         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5130                 PCI_SUBDEVICE_ID_CCD_OV2S, 0, 0, H(29)}, /* OpenVox 2 */
5131
5132         /* Cards with HFC-8S Chip */
5133         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5134         PCI_SUBDEVICE_ID_CCD_BN8S, 0, 0, H(12)}, /* BN8S */
5135         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5136         PCI_SUBDEVICE_ID_CCD_BN8SP, 0, 0, H(13)}, /* BN8S+ */
5137         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5138         PCI_DEVICE_ID_CCD_HFC8S, 0, 0, H(14)}, /* old Eval */
5139         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5140         PCI_SUBDEVICE_ID_CCD_IOB8STR, 0, 0, H(15)},
5141             /* IOB8ST Recording */
5142         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5143                 PCI_SUBDEVICE_ID_CCD_IOB8ST, 0, 0, H(16)}, /* IOB8ST  */
5144         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5145                 PCI_SUBDEVICE_ID_CCD_IOB8ST_1, 0, 0, H(17)}, /* IOB8ST  */
5146         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5147                 PCI_SUBDEVICE_ID_CCD_HFC8S, 0, 0, H(18)}, /* 8S */
5148         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5149                 PCI_SUBDEVICE_ID_CCD_OV8S, 0, 0, H(30)}, /* OpenVox 8 */
5150
5151
5152         /* Cards with HFC-E1 Chip */
5153         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5154                 PCI_SUBDEVICE_ID_CCD_BNE1, 0, 0, H(19)}, /* BNE1 */
5155         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5156                 PCI_SUBDEVICE_ID_CCD_BNE1M, 0, 0, H(20)}, /* BNE1 mini PCI */
5157         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5158                 PCI_SUBDEVICE_ID_CCD_BNE1DP, 0, 0, H(21)}, /* BNE1 + (Dual) */
5159         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5160                 PCI_SUBDEVICE_ID_CCD_BNE1D, 0, 0, H(22)}, /* BNE1 (Dual) */
5161
5162         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5163                 PCI_DEVICE_ID_CCD_HFCE1, 0, 0, H(23)}, /* Old Eval */
5164         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5165                 PCI_SUBDEVICE_ID_CCD_IOB1E1, 0, 0, H(24)}, /* IOB1E1 */
5166         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5167                 PCI_SUBDEVICE_ID_CCD_HFCE1, 0, 0, H(25)}, /* E1 */
5168
5169         { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD,
5170                 PCI_SUBDEVICE_ID_CCD_SPD4S, 0, 0, H(26)}, /* PLX PCI Bridge */
5171         { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD,
5172                 PCI_SUBDEVICE_ID_CCD_SPDE1, 0, 0, H(27)}, /* PLX PCI Bridge */
5173         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_ANY_ID, PCI_ANY_ID,
5174                 0, 0, 0},
5175         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_ANY_ID, PCI_ANY_ID,
5176                 0, 0, 0},
5177         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_ANY_ID, PCI_ANY_ID,
5178                 0, 0, 0},
5179         {0, }
5180 };
5181 #undef H
5182
5183 MODULE_DEVICE_TABLE(pci, hfmultipci_ids);
5184
5185 static int
5186 hfcmulti_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
5187 {
5188         struct hm_map   *m = (struct hm_map *)ent->driver_data;
5189         int             ret;
5190
5191         if (m == NULL) {
5192                 if (ent->vendor == PCI_VENDOR_ID_CCD)
5193                         if (ent->device == PCI_DEVICE_ID_CCD_HFC4S ||
5194                             ent->device == PCI_DEVICE_ID_CCD_HFC8S ||
5195                             ent->device == PCI_DEVICE_ID_CCD_HFCE1)
5196                                 printk(KERN_ERR
5197                                     "unknown HFC multiport controller "
5198                                     "(vendor:%x device:%x subvendor:%x "
5199                                     "subdevice:%x) Please contact the "
5200                                     "driver maintainer for support.\n",
5201                                     ent->vendor, ent->device,
5202                                     ent->subvendor, ent->subdevice);
5203                 return -ENODEV;
5204         }
5205         ret = hfcmulti_init(pdev, ent);
5206         if (ret)
5207                 return ret;
5208         HFC_cnt++;
5209         printk(KERN_INFO "%d devices registered\n", HFC_cnt);
5210         return 0;
5211 }
5212
5213 static struct pci_driver hfcmultipci_driver = {
5214         .name           = "hfc_multi",
5215         .probe          = hfcmulti_probe,
5216         .remove         = __devexit_p(hfc_remove_pci),
5217         .id_table       = hfmultipci_ids,
5218 };
5219
5220 static void __exit
5221 HFCmulti_cleanup(void)
5222 {
5223         struct hfc_multi *card, *next;
5224
5225         /* unload interrupt function symbol */
5226         if (hfc_interrupt)
5227                 symbol_put(ztdummy_extern_interrupt);
5228         if (register_interrupt)
5229                 symbol_put(ztdummy_register_interrupt);
5230         if (unregister_interrupt) {
5231                 if (interrupt_registered) {
5232                         interrupt_registered = 0;
5233                         unregister_interrupt();
5234                 }
5235                 symbol_put(ztdummy_unregister_interrupt);
5236         }
5237
5238         list_for_each_entry_safe(card, next, &HFClist, list)
5239                 release_card(card);
5240         /* get rid of all devices of this driver */
5241         pci_unregister_driver(&hfcmultipci_driver);
5242 }
5243
5244 static int __init
5245 HFCmulti_init(void)
5246 {
5247         int err;
5248
5249 #ifdef IRQ_DEBUG
5250         printk(KERN_ERR "%s: IRQ_DEBUG IS ENABLED!\n", __func__);
5251 #endif
5252
5253         spin_lock_init(&HFClock);
5254         spin_lock_init(&plx_lock);
5255
5256         if (debug & DEBUG_HFCMULTI_INIT)
5257                 printk(KERN_DEBUG "%s: init entered\n", __func__);
5258
5259         hfc_interrupt = symbol_get(ztdummy_extern_interrupt);
5260         register_interrupt = symbol_get(ztdummy_register_interrupt);
5261         unregister_interrupt = symbol_get(ztdummy_unregister_interrupt);
5262         printk(KERN_INFO "mISDN: HFC-multi driver %s\n",
5263             hfcmulti_revision);
5264
5265         switch (poll) {
5266         case 0:
5267                 poll_timer = 6;
5268                 poll = 128;
5269                 break;
5270                 /*
5271                  * wenn dieses break nochmal verschwindet,
5272                  * gibt es heisse ohren :-)
5273                  * "without the break you will get hot ears ???"
5274                  */
5275         case 8:
5276                 poll_timer = 2;
5277                 break;
5278         case 16:
5279                 poll_timer = 3;
5280                 break;
5281         case 32:
5282                 poll_timer = 4;
5283                 break;
5284         case 64:
5285                 poll_timer = 5;
5286                 break;
5287         case 128:
5288                 poll_timer = 6;
5289                 break;
5290         case 256:
5291                 poll_timer = 7;
5292                 break;
5293         default:
5294                 printk(KERN_ERR
5295                     "%s: Wrong poll value (%d).\n", __func__, poll);
5296                 err = -EINVAL;
5297                 return err;
5298
5299         }
5300
5301         err = pci_register_driver(&hfcmultipci_driver);
5302         if (err < 0) {
5303                 printk(KERN_ERR "error registering pci driver: %x\n", err);
5304                 if (hfc_interrupt)
5305                         symbol_put(ztdummy_extern_interrupt);
5306                 if (register_interrupt)
5307                         symbol_put(ztdummy_register_interrupt);
5308                 if (unregister_interrupt) {
5309                         if (interrupt_registered) {
5310                                 interrupt_registered = 0;
5311                                 unregister_interrupt();
5312                         }
5313                         symbol_put(ztdummy_unregister_interrupt);
5314                 }
5315                 return err;
5316         }
5317         return 0;
5318 }
5319
5320
5321 module_init(HFCmulti_init);
5322 module_exit(HFCmulti_cleanup);