drivers/infiniband/hw/nes/nes_hw.h

   1 /*
   2 * Copyright (c) 2006 - 2009 Intel-NE, Inc.  All rights reserved.
   3 *
   4 * This software is available to you under a choice of one of two
   5 * licenses.  You may choose to be licensed under the terms of the GNU
   6 * General Public License (GPL) Version 2, available from the file
   7 * COPYING in the main directory of this source tree, or the
   8 * OpenIB.org BSD license below:
   9 *
  10 *     Redistribution and use in source and binary forms, with or
  11 *     without modification, are permitted provided that the following
  12 *     conditions are met:
  13 *
  14 *      - Redistributions of source code must retain the above
  15 *        copyright notice, this list of conditions and the following
  16 *        disclaimer.
  17 *
  18 *      - Redistributions in binary form must reproduce the above
  19 *        copyright notice, this list of conditions and the following
  20 *        disclaimer in the documentation and/or other materials
  21 *        provided with the distribution.
  22 *
  23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30 * SOFTWARE.
  31 */
  32
  33 #ifndef __NES_HW_H
  34 #define __NES_HW_H
  35
  36 #include <linux/inet_lro.h>
  37
  38 #define NES_PHY_TYPE_CX4       1
  39 #define NES_PHY_TYPE_1G        2
  40 #define NES_PHY_TYPE_IRIS      3
  41 #define NES_PHY_TYPE_ARGUS     4
  42 #define NES_PHY_TYPE_PUMA_1G   5
  43 #define NES_PHY_TYPE_PUMA_10G  6
  44 #define NES_PHY_TYPE_GLADIUS   7
  45 #define NES_PHY_TYPE_SFP_D     8
  46
  47 #define NES_MULTICAST_PF_MAX 8
  48
  49 enum pci_regs {
  50         NES_INT_STAT = 0x0000,
  51         NES_INT_MASK = 0x0004,
  52         NES_INT_PENDING = 0x0008,
  53         NES_INTF_INT_STAT = 0x000C,
  54         NES_INTF_INT_MASK = 0x0010,
  55         NES_TIMER_STAT = 0x0014,
  56         NES_PERIODIC_CONTROL = 0x0018,
  57         NES_ONE_SHOT_CONTROL = 0x001C,
  58         NES_EEPROM_COMMAND = 0x0020,
  59         NES_EEPROM_DATA = 0x0024,
  60         NES_FLASH_COMMAND = 0x0028,
  61         NES_FLASH_DATA  = 0x002C,
  62         NES_SOFTWARE_RESET = 0x0030,
  63         NES_CQ_ACK = 0x0034,
  64         NES_WQE_ALLOC = 0x0040,
  65         NES_CQE_ALLOC = 0x0044,
  66         NES_AEQ_ALLOC = 0x0048
  67 };
  68
  69 enum indexed_regs {
  70         NES_IDX_CREATE_CQP_LOW = 0x0000,
  71         NES_IDX_CREATE_CQP_HIGH = 0x0004,
  72         NES_IDX_QP_CONTROL = 0x0040,
  73         NES_IDX_FLM_CONTROL = 0x0080,
  74         NES_IDX_INT_CPU_STATUS = 0x00a0,
  75         NES_IDX_GPIO_CONTROL = 0x00f0,
  76         NES_IDX_GPIO_DATA = 0x00f4,
  77         NES_IDX_TCP_CONFIG0 = 0x01e4,
  78         NES_IDX_TCP_TIMER_CONFIG = 0x01ec,
  79         NES_IDX_TCP_NOW = 0x01f0,
  80         NES_IDX_QP_MAX_CFG_SIZES = 0x0200,
  81         NES_IDX_QP_CTX_SIZE = 0x0218,
  82         NES_IDX_TCP_TIMER_SIZE0 = 0x0238,
  83         NES_IDX_TCP_TIMER_SIZE1 = 0x0240,
  84         NES_IDX_ARP_CACHE_SIZE = 0x0258,
  85         NES_IDX_CQ_CTX_SIZE = 0x0260,
  86         NES_IDX_MRT_SIZE = 0x0278,
  87         NES_IDX_PBL_REGION_SIZE = 0x0280,
  88         NES_IDX_IRRQ_COUNT = 0x02b0,
  89         NES_IDX_RX_WINDOW_BUFFER_PAGE_TABLE_SIZE = 0x02f0,
  90         NES_IDX_RX_WINDOW_BUFFER_SIZE = 0x0300,
  91         NES_IDX_DST_IP_ADDR = 0x0400,
  92         NES_IDX_PCIX_DIAG = 0x08e8,
  93         NES_IDX_MPP_DEBUG = 0x0a00,
  94         NES_IDX_PORT_RX_DISCARDS = 0x0a30,
  95         NES_IDX_PORT_TX_DISCARDS = 0x0a34,
  96         NES_IDX_MPP_LB_DEBUG = 0x0b00,
  97         NES_IDX_DENALI_CTL_22 = 0x1058,
  98         NES_IDX_MAC_TX_CONTROL = 0x2000,
  99         NES_IDX_MAC_TX_CONFIG = 0x2004,
 100         NES_IDX_MAC_TX_PAUSE_QUANTA = 0x2008,
 101         NES_IDX_MAC_RX_CONTROL = 0x200c,
 102         NES_IDX_MAC_RX_CONFIG = 0x2010,
 103         NES_IDX_MAC_EXACT_MATCH_BOTTOM = 0x201c,
 104         NES_IDX_MAC_MDIO_CONTROL = 0x2084,
 105         NES_IDX_MAC_TX_OCTETS_LOW = 0x2100,
 106         NES_IDX_MAC_TX_OCTETS_HIGH = 0x2104,
 107         NES_IDX_MAC_TX_FRAMES_LOW = 0x2108,
 108         NES_IDX_MAC_TX_FRAMES_HIGH = 0x210c,
 109         NES_IDX_MAC_TX_PAUSE_FRAMES = 0x2118,
 110         NES_IDX_MAC_TX_ERRORS = 0x2138,
 111         NES_IDX_MAC_RX_OCTETS_LOW = 0x213c,
 112         NES_IDX_MAC_RX_OCTETS_HIGH = 0x2140,
 113         NES_IDX_MAC_RX_FRAMES_LOW = 0x2144,
 114         NES_IDX_MAC_RX_FRAMES_HIGH = 0x2148,
 115         NES_IDX_MAC_RX_BC_FRAMES_LOW = 0x214c,
 116         NES_IDX_MAC_RX_MC_FRAMES_HIGH = 0x2150,
 117         NES_IDX_MAC_RX_PAUSE_FRAMES = 0x2154,
 118         NES_IDX_MAC_RX_SHORT_FRAMES = 0x2174,
 119         NES_IDX_MAC_RX_OVERSIZED_FRAMES = 0x2178,
 120         NES_IDX_MAC_RX_JABBER_FRAMES = 0x217c,
 121         NES_IDX_MAC_RX_CRC_ERR_FRAMES = 0x2180,
 122         NES_IDX_MAC_RX_LENGTH_ERR_FRAMES = 0x2184,
 123         NES_IDX_MAC_RX_SYMBOL_ERR_FRAMES = 0x2188,
 124         NES_IDX_MAC_INT_STATUS = 0x21f0,
 125         NES_IDX_MAC_INT_MASK = 0x21f4,
 126         NES_IDX_PHY_PCS_CONTROL_STATUS0 = 0x2800,
 127         NES_IDX_PHY_PCS_CONTROL_STATUS1 = 0x2a00,
 128         NES_IDX_ETH_SERDES_COMMON_CONTROL0 = 0x2808,
 129         NES_IDX_ETH_SERDES_COMMON_CONTROL1 = 0x2a08,
 130         NES_IDX_ETH_SERDES_COMMON_STATUS0 = 0x280c,
 131         NES_IDX_ETH_SERDES_COMMON_STATUS1 = 0x2a0c,
 132         NES_IDX_ETH_SERDES_TX_EMP0 = 0x2810,
 133         NES_IDX_ETH_SERDES_TX_EMP1 = 0x2a10,
 134         NES_IDX_ETH_SERDES_TX_DRIVE0 = 0x2814,
 135         NES_IDX_ETH_SERDES_TX_DRIVE1 = 0x2a14,
 136         NES_IDX_ETH_SERDES_RX_MODE0 = 0x2818,
 137         NES_IDX_ETH_SERDES_RX_MODE1 = 0x2a18,
 138         NES_IDX_ETH_SERDES_RX_SIGDET0 = 0x281c,
 139         NES_IDX_ETH_SERDES_RX_SIGDET1 = 0x2a1c,
 140         NES_IDX_ETH_SERDES_BYPASS0 = 0x2820,
 141         NES_IDX_ETH_SERDES_BYPASS1 = 0x2a20,
 142         NES_IDX_ETH_SERDES_LOOPBACK_CONTROL0 = 0x2824,
 143         NES_IDX_ETH_SERDES_LOOPBACK_CONTROL1 = 0x2a24,
 144         NES_IDX_ETH_SERDES_RX_EQ_CONTROL0 = 0x2828,
 145         NES_IDX_ETH_SERDES_RX_EQ_CONTROL1 = 0x2a28,
 146         NES_IDX_ETH_SERDES_RX_EQ_STATUS0 = 0x282c,
 147         NES_IDX_ETH_SERDES_RX_EQ_STATUS1 = 0x2a2c,
 148         NES_IDX_ETH_SERDES_CDR_RESET0 = 0x2830,
 149         NES_IDX_ETH_SERDES_CDR_RESET1 = 0x2a30,
 150         NES_IDX_ETH_SERDES_CDR_CONTROL0 = 0x2834,
 151         NES_IDX_ETH_SERDES_CDR_CONTROL1 = 0x2a34,
 152         NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE0 = 0x2838,
 153         NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE1 = 0x2a38,
 154         NES_IDX_ENDNODE0_NSTAT_RX_DISCARD = 0x3080,
 155         NES_IDX_ENDNODE0_NSTAT_RX_OCTETS_LO = 0x3000,
 156         NES_IDX_ENDNODE0_NSTAT_RX_OCTETS_HI = 0x3004,
 157         NES_IDX_ENDNODE0_NSTAT_RX_FRAMES_LO = 0x3008,
 158         NES_IDX_ENDNODE0_NSTAT_RX_FRAMES_HI = 0x300c,
 159         NES_IDX_ENDNODE0_NSTAT_TX_OCTETS_LO = 0x7000,
 160         NES_IDX_ENDNODE0_NSTAT_TX_OCTETS_HI = 0x7004,
 161         NES_IDX_ENDNODE0_NSTAT_TX_FRAMES_LO = 0x7008,
 162         NES_IDX_ENDNODE0_NSTAT_TX_FRAMES_HI = 0x700c,
 163         NES_IDX_WQM_CONFIG1 = 0x5004,
 164         NES_IDX_CM_CONFIG = 0x5100,
 165         NES_IDX_NIC_LOGPORT_TO_PHYPORT = 0x6000,
 166         NES_IDX_NIC_PHYPORT_TO_USW = 0x6008,
 167         NES_IDX_NIC_ACTIVE = 0x6010,
 168         NES_IDX_NIC_UNICAST_ALL = 0x6018,
 169         NES_IDX_NIC_MULTICAST_ALL = 0x6020,
 170         NES_IDX_NIC_MULTICAST_ENABLE = 0x6028,
 171         NES_IDX_NIC_BROADCAST_ON = 0x6030,
 172         NES_IDX_USED_CHUNKS_TX = 0x60b0,
 173         NES_IDX_TX_POOL_SIZE = 0x60b8,
 174         NES_IDX_QUAD_HASH_TABLE_SIZE = 0x6148,
 175         NES_IDX_PERFECT_FILTER_LOW = 0x6200,
 176         NES_IDX_PERFECT_FILTER_HIGH = 0x6204,
 177         NES_IDX_IPV4_TCP_REXMITS = 0x7080,
 178         NES_IDX_DEBUG_ERROR_CONTROL_STATUS = 0x913c,
 179         NES_IDX_DEBUG_ERROR_MASKS0 = 0x9140,
 180         NES_IDX_DEBUG_ERROR_MASKS1 = 0x9144,
 181         NES_IDX_DEBUG_ERROR_MASKS2 = 0x9148,
 182         NES_IDX_DEBUG_ERROR_MASKS3 = 0x914c,
 183         NES_IDX_DEBUG_ERROR_MASKS4 = 0x9150,
 184         NES_IDX_DEBUG_ERROR_MASKS5 = 0x9154,
 185 };
 186
 187 #define NES_IDX_MAC_TX_CONFIG_ENABLE_PAUSE   1
 188 #define NES_IDX_MPP_DEBUG_PORT_DISABLE_PAUSE (1 << 17)
 189
 190 enum nes_cqp_opcodes {
 191         NES_CQP_CREATE_QP = 0x00,
 192         NES_CQP_MODIFY_QP = 0x01,
 193         NES_CQP_DESTROY_QP = 0x02,
 194         NES_CQP_CREATE_CQ = 0x03,
 195         NES_CQP_MODIFY_CQ = 0x04,
 196         NES_CQP_DESTROY_CQ = 0x05,
 197         NES_CQP_ALLOCATE_STAG = 0x09,
 198         NES_CQP_REGISTER_STAG = 0x0a,
 199         NES_CQP_QUERY_STAG = 0x0b,
 200         NES_CQP_REGISTER_SHARED_STAG = 0x0c,
 201         NES_CQP_DEALLOCATE_STAG = 0x0d,
 202         NES_CQP_MANAGE_ARP_CACHE = 0x0f,
 203         NES_CQP_SUSPEND_QPS = 0x11,
 204         NES_CQP_UPLOAD_CONTEXT = 0x13,
 205         NES_CQP_CREATE_CEQ = 0x16,
 206         NES_CQP_DESTROY_CEQ = 0x18,
 207         NES_CQP_CREATE_AEQ = 0x19,
 208         NES_CQP_DESTROY_AEQ = 0x1b,
 209         NES_CQP_LMI_ACCESS = 0x20,
 210         NES_CQP_FLUSH_WQES = 0x22,
 211         NES_CQP_MANAGE_APBVT = 0x23
 212 };
 213
 214 enum nes_cqp_wqe_word_idx {
 215         NES_CQP_WQE_OPCODE_IDX = 0,
 216         NES_CQP_WQE_ID_IDX = 1,
 217         NES_CQP_WQE_COMP_CTX_LOW_IDX = 2,
 218         NES_CQP_WQE_COMP_CTX_HIGH_IDX = 3,
 219         NES_CQP_WQE_COMP_SCRATCH_LOW_IDX = 4,
 220         NES_CQP_WQE_COMP_SCRATCH_HIGH_IDX = 5,
 221 };
 222
 223 enum nes_cqp_cq_wqeword_idx {
 224         NES_CQP_CQ_WQE_PBL_LOW_IDX = 6,
 225         NES_CQP_CQ_WQE_PBL_HIGH_IDX = 7,
 226         NES_CQP_CQ_WQE_CQ_CONTEXT_LOW_IDX = 8,
 227         NES_CQP_CQ_WQE_CQ_CONTEXT_HIGH_IDX = 9,
 228         NES_CQP_CQ_WQE_DOORBELL_INDEX_HIGH_IDX = 10,
 229 };
 230
 231 enum nes_cqp_stag_wqeword_idx {
 232         NES_CQP_STAG_WQE_PBL_BLK_COUNT_IDX = 1,
 233         NES_CQP_STAG_WQE_LEN_HIGH_PD_IDX = 6,
 234         NES_CQP_STAG_WQE_LEN_LOW_IDX = 7,
 235         NES_CQP_STAG_WQE_STAG_IDX = 8,
 236         NES_CQP_STAG_WQE_VA_LOW_IDX = 10,
 237         NES_CQP_STAG_WQE_VA_HIGH_IDX = 11,
 238         NES_CQP_STAG_WQE_PA_LOW_IDX = 12,
 239         NES_CQP_STAG_WQE_PA_HIGH_IDX = 13,
 240         NES_CQP_STAG_WQE_PBL_LEN_IDX = 14
 241 };
 242
 243 #define NES_CQP_OP_IWARP_STATE_SHIFT 28
 244 #define NES_CQP_OP_TERMLEN_SHIFT     28
 245
 246 enum nes_cqp_qp_bits {
 247         NES_CQP_QP_ARP_VALID = (1<<8),
 248         NES_CQP_QP_WINBUF_VALID = (1<<9),
 249         NES_CQP_QP_CONTEXT_VALID = (1<<10),
 250         NES_CQP_QP_ORD_VALID = (1<<11),
 251         NES_CQP_QP_WINBUF_DATAIND_EN = (1<<12),
 252         NES_CQP_QP_VIRT_WQS = (1<<13),
 253         NES_CQP_QP_DEL_HTE = (1<<14),
 254         NES_CQP_QP_CQS_VALID = (1<<15),
 255         NES_CQP_QP_TYPE_TSA = 0,
 256         NES_CQP_QP_TYPE_IWARP = (1<<16),
 257         NES_CQP_QP_TYPE_CQP = (4<<16),
 258         NES_CQP_QP_TYPE_NIC = (5<<16),
 259         NES_CQP_QP_MSS_CHG = (1<<20),
 260         NES_CQP_QP_STATIC_RESOURCES = (1<<21),
 261         NES_CQP_QP_IGNORE_MW_BOUND = (1<<22),
 262         NES_CQP_QP_VWQ_USE_LMI = (1<<23),
 263         NES_CQP_QP_IWARP_STATE_IDLE = (1<<NES_CQP_OP_IWARP_STATE_SHIFT),
 264         NES_CQP_QP_IWARP_STATE_RTS = (2<<NES_CQP_OP_IWARP_STATE_SHIFT),
 265         NES_CQP_QP_IWARP_STATE_CLOSING = (3<<NES_CQP_OP_IWARP_STATE_SHIFT),
 266         NES_CQP_QP_IWARP_STATE_TERMINATE = (5<<NES_CQP_OP_IWARP_STATE_SHIFT),
 267         NES_CQP_QP_IWARP_STATE_ERROR = (6<<NES_CQP_OP_IWARP_STATE_SHIFT),
 268         NES_CQP_QP_IWARP_STATE_MASK = (7<<NES_CQP_OP_IWARP_STATE_SHIFT),
 269         NES_CQP_QP_TERM_DONT_SEND_FIN = (1<<24),
 270         NES_CQP_QP_TERM_DONT_SEND_TERM_MSG = (1<<25),
 271         NES_CQP_QP_RESET = (1<<31),
 272 };
 273
 274 enum nes_cqp_qp_wqe_word_idx {
 275         NES_CQP_QP_WQE_CONTEXT_LOW_IDX = 6,
 276         NES_CQP_QP_WQE_CONTEXT_HIGH_IDX = 7,
 277         NES_CQP_QP_WQE_FLUSH_SQ_CODE = 8,
 278         NES_CQP_QP_WQE_FLUSH_RQ_CODE = 9,
 279         NES_CQP_QP_WQE_NEW_MSS_IDX = 15,
 280 };
 281
 282 enum nes_nic_ctx_bits {
 283         NES_NIC_CTX_RQ_SIZE_32 = (3<<8),
 284         NES_NIC_CTX_RQ_SIZE_512 = (3<<8),
 285         NES_NIC_CTX_SQ_SIZE_32 = (1<<10),
 286         NES_NIC_CTX_SQ_SIZE_512 = (3<<10),
 287 };
 288
 289 enum nes_nic_qp_ctx_word_idx {
 290         NES_NIC_CTX_MISC_IDX = 0,
 291         NES_NIC_CTX_SQ_LOW_IDX = 2,
 292         NES_NIC_CTX_SQ_HIGH_IDX = 3,
 293         NES_NIC_CTX_RQ_LOW_IDX = 4,
 294         NES_NIC_CTX_RQ_HIGH_IDX = 5,
 295 };
 296
 297 enum nes_cqp_cq_bits {
 298         NES_CQP_CQ_CEQE_MASK = (1<<9),
 299         NES_CQP_CQ_CEQ_VALID = (1<<10),
 300         NES_CQP_CQ_RESIZE = (1<<11),
 301         NES_CQP_CQ_CHK_OVERFLOW = (1<<12),
 302         NES_CQP_CQ_4KB_CHUNK = (1<<14),
 303         NES_CQP_CQ_VIRT = (1<<15),
 304 };
 305
 306 enum nes_cqp_stag_bits {
 307         NES_CQP_STAG_VA_TO = (1<<9),
 308         NES_CQP_STAG_DEALLOC_PBLS = (1<<10),
 309         NES_CQP_STAG_PBL_BLK_SIZE = (1<<11),
 310         NES_CQP_STAG_MR = (1<<13),
 311         NES_CQP_STAG_RIGHTS_LOCAL_READ = (1<<16),
 312         NES_CQP_STAG_RIGHTS_LOCAL_WRITE = (1<<17),
 313         NES_CQP_STAG_RIGHTS_REMOTE_READ = (1<<18),
 314         NES_CQP_STAG_RIGHTS_REMOTE_WRITE = (1<<19),
 315         NES_CQP_STAG_RIGHTS_WINDOW_BIND = (1<<20),
 316         NES_CQP_STAG_REM_ACC_EN = (1<<21),
 317         NES_CQP_STAG_LEAVE_PENDING = (1<<31),
 318 };
 319
 320 enum nes_cqp_ceq_wqeword_idx {
 321         NES_CQP_CEQ_WQE_ELEMENT_COUNT_IDX = 1,
 322         NES_CQP_CEQ_WQE_PBL_LOW_IDX = 6,
 323         NES_CQP_CEQ_WQE_PBL_HIGH_IDX = 7,
 324 };
 325
 326 enum nes_cqp_ceq_bits {
 327         NES_CQP_CEQ_4KB_CHUNK = (1<<14),
 328         NES_CQP_CEQ_VIRT = (1<<15),
 329 };
 330
 331 enum nes_cqp_aeq_wqeword_idx {
 332         NES_CQP_AEQ_WQE_ELEMENT_COUNT_IDX = 1,
 333         NES_CQP_AEQ_WQE_PBL_LOW_IDX = 6,
 334         NES_CQP_AEQ_WQE_PBL_HIGH_IDX = 7,
 335 };
 336
 337 enum nes_cqp_aeq_bits {
 338         NES_CQP_AEQ_4KB_CHUNK = (1<<14),
 339         NES_CQP_AEQ_VIRT = (1<<15),
 340 };
 341
 342 enum nes_cqp_lmi_wqeword_idx {
 343         NES_CQP_LMI_WQE_LMI_OFFSET_IDX = 1,
 344         NES_CQP_LMI_WQE_FRAG_LOW_IDX = 8,
 345         NES_CQP_LMI_WQE_FRAG_HIGH_IDX = 9,
 346         NES_CQP_LMI_WQE_FRAG_LEN_IDX = 10,
 347 };
 348
 349 enum nes_cqp_arp_wqeword_idx {
 350         NES_CQP_ARP_WQE_MAC_ADDR_LOW_IDX = 6,
 351         NES_CQP_ARP_WQE_MAC_HIGH_IDX = 7,
 352         NES_CQP_ARP_WQE_REACHABILITY_MAX_IDX = 1,
 353 };
 354
 355 enum nes_cqp_upload_wqeword_idx {
 356         NES_CQP_UPLOAD_WQE_CTXT_LOW_IDX = 6,
 357         NES_CQP_UPLOAD_WQE_CTXT_HIGH_IDX = 7,
 358         NES_CQP_UPLOAD_WQE_HTE_IDX = 8,
 359 };
 360
 361 enum nes_cqp_arp_bits {
 362         NES_CQP_ARP_VALID = (1<<8),
 363         NES_CQP_ARP_PERM = (1<<9),
 364 };
 365
 366 enum nes_cqp_flush_bits {
 367         NES_CQP_FLUSH_SQ = (1<<30),
 368         NES_CQP_FLUSH_RQ = (1<<31),
 369         NES_CQP_FLUSH_MAJ_MIN = (1<<28),
 370 };
 371
 372 enum nes_cqe_opcode_bits {
 373         NES_CQE_STAG_VALID = (1<<6),
 374         NES_CQE_ERROR = (1<<7),
 375         NES_CQE_SQ = (1<<8),
 376         NES_CQE_SE = (1<<9),
 377         NES_CQE_PSH = (1<<29),
 378         NES_CQE_FIN = (1<<30),
 379         NES_CQE_VALID = (1<<31),
 380 };
 381
 382
 383 enum nes_cqe_word_idx {
 384         NES_CQE_PAYLOAD_LENGTH_IDX = 0,
 385         NES_CQE_COMP_COMP_CTX_LOW_IDX = 2,
 386         NES_CQE_COMP_COMP_CTX_HIGH_IDX = 3,
 387         NES_CQE_INV_STAG_IDX = 4,
 388         NES_CQE_QP_ID_IDX = 5,
 389         NES_CQE_ERROR_CODE_IDX = 6,
 390         NES_CQE_OPCODE_IDX = 7,
 391 };
 392
 393 enum nes_ceqe_word_idx {
 394         NES_CEQE_CQ_CTX_LOW_IDX = 0,
 395         NES_CEQE_CQ_CTX_HIGH_IDX = 1,
 396 };
 397
 398 enum nes_ceqe_status_bit {
 399         NES_CEQE_VALID = (1<<31),
 400 };
 401
 402 enum nes_int_bits {
 403         NES_INT_CEQ0 = (1<<0),
 404         NES_INT_CEQ1 = (1<<1),
 405         NES_INT_CEQ2 = (1<<2),
 406         NES_INT_CEQ3 = (1<<3),
 407         NES_INT_CEQ4 = (1<<4),
 408         NES_INT_CEQ5 = (1<<5),
 409         NES_INT_CEQ6 = (1<<6),
 410         NES_INT_CEQ7 = (1<<7),
 411         NES_INT_CEQ8 = (1<<8),
 412         NES_INT_CEQ9 = (1<<9),
 413         NES_INT_CEQ10 = (1<<10),
 414         NES_INT_CEQ11 = (1<<11),
 415         NES_INT_CEQ12 = (1<<12),
 416         NES_INT_CEQ13 = (1<<13),
 417         NES_INT_CEQ14 = (1<<14),
 418         NES_INT_CEQ15 = (1<<15),
 419         NES_INT_AEQ0 = (1<<16),
 420         NES_INT_AEQ1 = (1<<17),
 421         NES_INT_AEQ2 = (1<<18),
 422         NES_INT_AEQ3 = (1<<19),
 423         NES_INT_AEQ4 = (1<<20),
 424         NES_INT_AEQ5 = (1<<21),
 425         NES_INT_AEQ6 = (1<<22),
 426         NES_INT_AEQ7 = (1<<23),
 427         NES_INT_MAC0 = (1<<24),
 428         NES_INT_MAC1 = (1<<25),
 429         NES_INT_MAC2 = (1<<26),
 430         NES_INT_MAC3 = (1<<27),
 431         NES_INT_TSW = (1<<28),
 432         NES_INT_TIMER = (1<<29),
 433         NES_INT_INTF = (1<<30),
 434 };
 435
 436 enum nes_intf_int_bits {
 437         NES_INTF_INT_PCIERR = (1<<0),
 438         NES_INTF_PERIODIC_TIMER = (1<<2),
 439         NES_INTF_ONE_SHOT_TIMER = (1<<3),
 440         NES_INTF_INT_CRITERR = (1<<14),
 441         NES_INTF_INT_AEQ0_OFLOW = (1<<16),
 442         NES_INTF_INT_AEQ1_OFLOW = (1<<17),
 443         NES_INTF_INT_AEQ2_OFLOW = (1<<18),
 444         NES_INTF_INT_AEQ3_OFLOW = (1<<19),
 445         NES_INTF_INT_AEQ4_OFLOW = (1<<20),
 446         NES_INTF_INT_AEQ5_OFLOW = (1<<21),
 447         NES_INTF_INT_AEQ6_OFLOW = (1<<22),
 448         NES_INTF_INT_AEQ7_OFLOW = (1<<23),
 449         NES_INTF_INT_AEQ_OFLOW = (0xff<<16),
 450 };
 451
 452 enum nes_mac_int_bits {
 453         NES_MAC_INT_LINK_STAT_CHG = (1<<1),
 454         NES_MAC_INT_XGMII_EXT = (1<<2),
 455         NES_MAC_INT_TX_UNDERFLOW = (1<<6),
 456         NES_MAC_INT_TX_ERROR = (1<<7),
 457 };
 458
 459 enum nes_cqe_allocate_bits {
 460         NES_CQE_ALLOC_INC_SELECT = (1<<28),
 461         NES_CQE_ALLOC_NOTIFY_NEXT = (1<<29),
 462         NES_CQE_ALLOC_NOTIFY_SE = (1<<30),
 463         NES_CQE_ALLOC_RESET = (1<<31),
 464 };
 465
 466 enum nes_nic_rq_wqe_word_idx {
 467         NES_NIC_RQ_WQE_LENGTH_1_0_IDX = 0,
 468         NES_NIC_RQ_WQE_LENGTH_3_2_IDX = 1,
 469         NES_NIC_RQ_WQE_FRAG0_LOW_IDX = 2,
 470         NES_NIC_RQ_WQE_FRAG0_HIGH_IDX = 3,
 471         NES_NIC_RQ_WQE_FRAG1_LOW_IDX = 4,
 472         NES_NIC_RQ_WQE_FRAG1_HIGH_IDX = 5,
 473         NES_NIC_RQ_WQE_FRAG2_LOW_IDX = 6,
 474         NES_NIC_RQ_WQE_FRAG2_HIGH_IDX = 7,
 475         NES_NIC_RQ_WQE_FRAG3_LOW_IDX = 8,
 476         NES_NIC_RQ_WQE_FRAG3_HIGH_IDX = 9,
 477 };
 478
 479 enum nes_nic_sq_wqe_word_idx {
 480         NES_NIC_SQ_WQE_MISC_IDX = 0,
 481         NES_NIC_SQ_WQE_TOTAL_LENGTH_IDX = 1,
 482         NES_NIC_SQ_WQE_LSO_INFO_IDX = 2,
 483         NES_NIC_SQ_WQE_LENGTH_0_TAG_IDX = 3,
 484         NES_NIC_SQ_WQE_LENGTH_2_1_IDX = 4,
 485         NES_NIC_SQ_WQE_LENGTH_4_3_IDX = 5,
 486         NES_NIC_SQ_WQE_FRAG0_LOW_IDX = 6,
 487         NES_NIC_SQ_WQE_FRAG0_HIGH_IDX = 7,
 488         NES_NIC_SQ_WQE_FRAG1_LOW_IDX = 8,
 489         NES_NIC_SQ_WQE_FRAG1_HIGH_IDX = 9,
 490         NES_NIC_SQ_WQE_FRAG2_LOW_IDX = 10,
 491         NES_NIC_SQ_WQE_FRAG2_HIGH_IDX = 11,
 492         NES_NIC_SQ_WQE_FRAG3_LOW_IDX = 12,
 493         NES_NIC_SQ_WQE_FRAG3_HIGH_IDX = 13,
 494         NES_NIC_SQ_WQE_FRAG4_LOW_IDX = 14,
 495         NES_NIC_SQ_WQE_FRAG4_HIGH_IDX = 15,
 496 };
 497
 498 enum nes_iwarp_sq_wqe_word_idx {
 499         NES_IWARP_SQ_WQE_MISC_IDX = 0,
 500         NES_IWARP_SQ_WQE_TOTAL_PAYLOAD_IDX = 1,
 501         NES_IWARP_SQ_WQE_COMP_CTX_LOW_IDX = 2,
 502         NES_IWARP_SQ_WQE_COMP_CTX_HIGH_IDX = 3,
 503         NES_IWARP_SQ_WQE_COMP_SCRATCH_LOW_IDX = 4,
 504         NES_IWARP_SQ_WQE_COMP_SCRATCH_HIGH_IDX = 5,
 505         NES_IWARP_SQ_WQE_INV_STAG_LOW_IDX = 7,
 506         NES_IWARP_SQ_WQE_RDMA_TO_LOW_IDX = 8,
 507         NES_IWARP_SQ_WQE_RDMA_TO_HIGH_IDX = 9,
 508         NES_IWARP_SQ_WQE_RDMA_LENGTH_IDX = 10,
 509         NES_IWARP_SQ_WQE_RDMA_STAG_IDX = 11,
 510         NES_IWARP_SQ_WQE_IMM_DATA_START_IDX = 12,
 511         NES_IWARP_SQ_WQE_FRAG0_LOW_IDX = 16,
 512         NES_IWARP_SQ_WQE_FRAG0_HIGH_IDX = 17,
 513         NES_IWARP_SQ_WQE_LENGTH0_IDX = 18,
 514         NES_IWARP_SQ_WQE_STAG0_IDX = 19,
 515         NES_IWARP_SQ_WQE_FRAG1_LOW_IDX = 20,
 516         NES_IWARP_SQ_WQE_FRAG1_HIGH_IDX = 21,
 517         NES_IWARP_SQ_WQE_LENGTH1_IDX = 22,
 518         NES_IWARP_SQ_WQE_STAG1_IDX = 23,
 519         NES_IWARP_SQ_WQE_FRAG2_LOW_IDX = 24,
 520         NES_IWARP_SQ_WQE_FRAG2_HIGH_IDX = 25,
 521         NES_IWARP_SQ_WQE_LENGTH2_IDX = 26,
 522         NES_IWARP_SQ_WQE_STAG2_IDX = 27,
 523         NES_IWARP_SQ_WQE_FRAG3_LOW_IDX = 28,
 524         NES_IWARP_SQ_WQE_FRAG3_HIGH_IDX = 29,
 525         NES_IWARP_SQ_WQE_LENGTH3_IDX = 30,
 526         NES_IWARP_SQ_WQE_STAG3_IDX = 31,
 527 };
 528
 529 enum nes_iwarp_sq_bind_wqe_word_idx {
 530         NES_IWARP_SQ_BIND_WQE_MR_IDX = 6,
 531         NES_IWARP_SQ_BIND_WQE_MW_IDX = 7,
 532         NES_IWARP_SQ_BIND_WQE_LENGTH_LOW_IDX = 8,
 533         NES_IWARP_SQ_BIND_WQE_LENGTH_HIGH_IDX = 9,
 534         NES_IWARP_SQ_BIND_WQE_VA_FBO_LOW_IDX = 10,
 535         NES_IWARP_SQ_BIND_WQE_VA_FBO_HIGH_IDX = 11,
 536 };
 537
 538 enum nes_iwarp_sq_fmr_wqe_word_idx {
 539         NES_IWARP_SQ_FMR_WQE_MR_STAG_IDX = 7,
 540         NES_IWARP_SQ_FMR_WQE_LENGTH_LOW_IDX = 8,
 541         NES_IWARP_SQ_FMR_WQE_LENGTH_HIGH_IDX = 9,
 542         NES_IWARP_SQ_FMR_WQE_VA_FBO_LOW_IDX = 10,
 543         NES_IWARP_SQ_FMR_WQE_VA_FBO_HIGH_IDX = 11,
 544         NES_IWARP_SQ_FMR_WQE_PBL_ADDR_LOW_IDX = 12,
 545         NES_IWARP_SQ_FMR_WQE_PBL_ADDR_HIGH_IDX = 13,
 546         NES_IWARP_SQ_FMR_WQE_PBL_LENGTH_IDX = 14,
 547 };
 548
 549 enum nes_iwarp_sq_locinv_wqe_word_idx {
 550         NES_IWARP_SQ_LOCINV_WQE_INV_STAG_IDX = 6,
 551 };
 552
 553
 554 enum nes_iwarp_rq_wqe_word_idx {
 555         NES_IWARP_RQ_WQE_TOTAL_PAYLOAD_IDX = 1,
 556         NES_IWARP_RQ_WQE_COMP_CTX_LOW_IDX = 2,
 557         NES_IWARP_RQ_WQE_COMP_CTX_HIGH_IDX = 3,
 558         NES_IWARP_RQ_WQE_COMP_SCRATCH_LOW_IDX = 4,
 559         NES_IWARP_RQ_WQE_COMP_SCRATCH_HIGH_IDX = 5,
 560         NES_IWARP_RQ_WQE_FRAG0_LOW_IDX = 8,
 561         NES_IWARP_RQ_WQE_FRAG0_HIGH_IDX = 9,
 562         NES_IWARP_RQ_WQE_LENGTH0_IDX = 10,
 563         NES_IWARP_RQ_WQE_STAG0_IDX = 11,
 564         NES_IWARP_RQ_WQE_FRAG1_LOW_IDX = 12,
 565         NES_IWARP_RQ_WQE_FRAG1_HIGH_IDX = 13,
 566         NES_IWARP_RQ_WQE_LENGTH1_IDX = 14,
 567         NES_IWARP_RQ_WQE_STAG1_IDX = 15,
 568         NES_IWARP_RQ_WQE_FRAG2_LOW_IDX = 16,
 569         NES_IWARP_RQ_WQE_FRAG2_HIGH_IDX = 17,
 570         NES_IWARP_RQ_WQE_LENGTH2_IDX = 18,
 571         NES_IWARP_RQ_WQE_STAG2_IDX = 19,
 572         NES_IWARP_RQ_WQE_FRAG3_LOW_IDX = 20,
 573         NES_IWARP_RQ_WQE_FRAG3_HIGH_IDX = 21,
 574         NES_IWARP_RQ_WQE_LENGTH3_IDX = 22,
 575         NES_IWARP_RQ_WQE_STAG3_IDX = 23,
 576 };
 577
 578 enum nes_nic_sq_wqe_bits {
 579         NES_NIC_SQ_WQE_PHDR_CS_READY =  (1<<21),
 580         NES_NIC_SQ_WQE_LSO_ENABLE = (1<<22),
 581         NES_NIC_SQ_WQE_TAGVALUE_ENABLE = (1<<23),
 582         NES_NIC_SQ_WQE_DISABLE_CHKSUM = (1<<30),
 583         NES_NIC_SQ_WQE_COMPLETION = (1<<31),
 584 };
 585
 586 enum nes_nic_cqe_word_idx {
 587         NES_NIC_CQE_ACCQP_ID_IDX = 0,
 588         NES_NIC_CQE_TAG_PKT_TYPE_IDX = 2,
 589         NES_NIC_CQE_MISC_IDX = 3,
 590 };
 591
 592 #define NES_PKT_TYPE_APBVT_BITS 0xC112
 593 #define NES_PKT_TYPE_APBVT_MASK 0xff3e
 594
 595 #define NES_PKT_TYPE_PVALID_BITS 0x10000000
 596 #define NES_PKT_TYPE_PVALID_MASK 0x30000000
 597
 598 #define NES_PKT_TYPE_TCPV4_BITS 0x0110
 599 #define NES_PKT_TYPE_TCPV4_MASK 0x3f30
 600
 601 #define NES_PKT_TYPE_UDPV4_BITS 0x0210
 602 #define NES_PKT_TYPE_UDPV4_MASK 0x3f30
 603
 604 #define NES_PKT_TYPE_IPV4_BITS  0x0010
 605 #define NES_PKT_TYPE_IPV4_MASK  0x3f30
 606
 607 #define NES_PKT_TYPE_OTHER_BITS 0x0000
 608 #define NES_PKT_TYPE_OTHER_MASK 0x0030
 609
 610 #define NES_NIC_CQE_ERRV_SHIFT 16
 611 enum nes_nic_ev_bits {
 612         NES_NIC_ERRV_BITS_MODE = (1<<0),
 613         NES_NIC_ERRV_BITS_IPV4_CSUM_ERR = (1<<1),
 614         NES_NIC_ERRV_BITS_TCPUDP_CSUM_ERR = (1<<2),
 615         NES_NIC_ERRV_BITS_WQE_OVERRUN = (1<<3),
 616         NES_NIC_ERRV_BITS_IPH_ERR = (1<<4),
 617 };
 618
 619 enum nes_nic_cqe_bits {
 620         NES_NIC_CQE_ERRV_MASK = (0xff<<NES_NIC_CQE_ERRV_SHIFT),
 621         NES_NIC_CQE_SQ = (1<<24),
 622         NES_NIC_CQE_ACCQP_PORT = (1<<28),
 623         NES_NIC_CQE_ACCQP_VALID = (1<<29),
 624         NES_NIC_CQE_TAG_VALID = (1<<30),
 625         NES_NIC_CQE_VALID = (1<<31),
 626 };
 627
 628 enum nes_aeqe_word_idx {
 629         NES_AEQE_COMP_CTXT_LOW_IDX = 0,
 630         NES_AEQE_COMP_CTXT_HIGH_IDX = 1,
 631         NES_AEQE_COMP_QP_CQ_ID_IDX = 2,
 632         NES_AEQE_MISC_IDX = 3,
 633 };
 634
 635 enum nes_aeqe_bits {
 636         NES_AEQE_QP = (1<<16),
 637         NES_AEQE_CQ = (1<<17),
 638         NES_AEQE_SQ = (1<<18),
 639         NES_AEQE_INBOUND_RDMA = (1<<19),
 640         NES_AEQE_IWARP_STATE_MASK = (7<<20),
 641         NES_AEQE_TCP_STATE_MASK = (0xf<<24),
 642         NES_AEQE_Q2_DATA_WRITTEN = (0x3<<28),
 643         NES_AEQE_VALID = (1<<31),
 644 };
 645
 646 #define NES_AEQE_IWARP_STATE_SHIFT      20
 647 #define NES_AEQE_TCP_STATE_SHIFT        24
 648 #define NES_AEQE_Q2_DATA_ETHERNET       (1<<28)
 649 #define NES_AEQE_Q2_DATA_MPA            (1<<29)
 650
 651 enum nes_aeqe_iwarp_state {
 652         NES_AEQE_IWARP_STATE_NON_EXISTANT = 0,
 653         NES_AEQE_IWARP_STATE_IDLE = 1,
 654         NES_AEQE_IWARP_STATE_RTS = 2,
 655         NES_AEQE_IWARP_STATE_CLOSING = 3,
 656         NES_AEQE_IWARP_STATE_TERMINATE = 5,
 657         NES_AEQE_IWARP_STATE_ERROR = 6
 658 };
 659
 660 enum nes_aeqe_tcp_state {
 661         NES_AEQE_TCP_STATE_NON_EXISTANT = 0,
 662         NES_AEQE_TCP_STATE_CLOSED = 1,
 663         NES_AEQE_TCP_STATE_LISTEN = 2,
 664         NES_AEQE_TCP_STATE_SYN_SENT = 3,
 665         NES_AEQE_TCP_STATE_SYN_RCVD = 4,
 666         NES_AEQE_TCP_STATE_ESTABLISHED = 5,
 667         NES_AEQE_TCP_STATE_CLOSE_WAIT = 6,
 668         NES_AEQE_TCP_STATE_FIN_WAIT_1 = 7,
 669         NES_AEQE_TCP_STATE_CLOSING = 8,
 670         NES_AEQE_TCP_STATE_LAST_ACK = 9,
 671         NES_AEQE_TCP_STATE_FIN_WAIT_2 = 10,
 672         NES_AEQE_TCP_STATE_TIME_WAIT = 11
 673 };
 674
 675 enum nes_aeqe_aeid {
 676         NES_AEQE_AEID_AMP_UNALLOCATED_STAG                            = 0x0102,
 677         NES_AEQE_AEID_AMP_INVALID_STAG                                = 0x0103,
 678         NES_AEQE_AEID_AMP_BAD_QP                                      = 0x0104,
 679         NES_AEQE_AEID_AMP_BAD_PD                                      = 0x0105,
 680         NES_AEQE_AEID_AMP_BAD_STAG_KEY                                = 0x0106,
 681         NES_AEQE_AEID_AMP_BAD_STAG_INDEX                              = 0x0107,
 682         NES_AEQE_AEID_AMP_BOUNDS_VIOLATION                            = 0x0108,
 683         NES_AEQE_AEID_AMP_RIGHTS_VIOLATION                            = 0x0109,
 684         NES_AEQE_AEID_AMP_TO_WRAP                                     = 0x010a,
 685         NES_AEQE_AEID_AMP_FASTREG_SHARED                              = 0x010b,
 686         NES_AEQE_AEID_AMP_FASTREG_VALID_STAG                          = 0x010c,
 687         NES_AEQE_AEID_AMP_FASTREG_MW_STAG                             = 0x010d,
 688         NES_AEQE_AEID_AMP_FASTREG_INVALID_RIGHTS                      = 0x010e,
 689         NES_AEQE_AEID_AMP_FASTREG_PBL_TABLE_OVERFLOW                  = 0x010f,
 690         NES_AEQE_AEID_AMP_FASTREG_INVALID_LENGTH                      = 0x0110,
 691         NES_AEQE_AEID_AMP_INVALIDATE_SHARED                           = 0x0111,
 692         NES_AEQE_AEID_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS          = 0x0112,
 693         NES_AEQE_AEID_AMP_INVALIDATE_MR_WITH_BOUND_WINDOWS            = 0x0113,
 694         NES_AEQE_AEID_AMP_MWBIND_VALID_STAG                           = 0x0114,
 695         NES_AEQE_AEID_AMP_MWBIND_OF_MR_STAG                           = 0x0115,
 696         NES_AEQE_AEID_AMP_MWBIND_TO_ZERO_BASED_STAG                   = 0x0116,
 697         NES_AEQE_AEID_AMP_MWBIND_TO_MW_STAG                           = 0x0117,
 698         NES_AEQE_AEID_AMP_MWBIND_INVALID_RIGHTS                       = 0x0118,
 699         NES_AEQE_AEID_AMP_MWBIND_INVALID_BOUNDS                       = 0x0119,
 700         NES_AEQE_AEID_AMP_MWBIND_TO_INVALID_PARENT                    = 0x011a,
 701         NES_AEQE_AEID_AMP_MWBIND_BIND_DISABLED                        = 0x011b,
 702         NES_AEQE_AEID_BAD_CLOSE                                       = 0x0201,
 703         NES_AEQE_AEID_RDMAP_ROE_BAD_LLP_CLOSE                         = 0x0202,
 704         NES_AEQE_AEID_CQ_OPERATION_ERROR                              = 0x0203,
 705         NES_AEQE_AEID_PRIV_OPERATION_DENIED                           = 0x0204,
 706         NES_AEQE_AEID_RDMA_READ_WHILE_ORD_ZERO                        = 0x0205,
 707         NES_AEQE_AEID_STAG_ZERO_INVALID                               = 0x0206,
 708         NES_AEQE_AEID_DDP_INVALID_MSN_GAP_IN_MSN                      = 0x0301,
 709         NES_AEQE_AEID_DDP_INVALID_MSN_RANGE_IS_NOT_VALID              = 0x0302,
 710         NES_AEQE_AEID_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER = 0x0303,
 711         NES_AEQE_AEID_DDP_UBE_INVALID_DDP_VERSION                     = 0x0304,
 712         NES_AEQE_AEID_DDP_UBE_INVALID_MO                              = 0x0305,
 713         NES_AEQE_AEID_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE         = 0x0306,
 714         NES_AEQE_AEID_DDP_UBE_INVALID_QN                              = 0x0307,
 715         NES_AEQE_AEID_DDP_NO_L_BIT                                    = 0x0308,
 716         NES_AEQE_AEID_RDMAP_ROE_INVALID_RDMAP_VERSION                 = 0x0311,
 717         NES_AEQE_AEID_RDMAP_ROE_UNEXPECTED_OPCODE                     = 0x0312,
 718         NES_AEQE_AEID_ROE_INVALID_RDMA_READ_REQUEST                   = 0x0313,
 719         NES_AEQE_AEID_ROE_INVALID_RDMA_WRITE_OR_READ_RESP             = 0x0314,
 720         NES_AEQE_AEID_INVALID_ARP_ENTRY                               = 0x0401,
 721         NES_AEQE_AEID_INVALID_TCP_OPTION_RCVD                         = 0x0402,
 722         NES_AEQE_AEID_STALE_ARP_ENTRY                                 = 0x0403,
 723         NES_AEQE_AEID_LLP_CLOSE_COMPLETE                              = 0x0501,
 724         NES_AEQE_AEID_LLP_CONNECTION_RESET                            = 0x0502,
 725         NES_AEQE_AEID_LLP_FIN_RECEIVED                                = 0x0503,
 726         NES_AEQE_AEID_LLP_RECEIVED_MARKER_AND_LENGTH_FIELDS_DONT_MATCH =  0x0504,
 727         NES_AEQE_AEID_LLP_RECEIVED_MPA_CRC_ERROR                      = 0x0505,
 728         NES_AEQE_AEID_LLP_SEGMENT_TOO_LARGE                           = 0x0506,
 729         NES_AEQE_AEID_LLP_SEGMENT_TOO_SMALL                           = 0x0507,
 730         NES_AEQE_AEID_LLP_SYN_RECEIVED                                = 0x0508,
 731         NES_AEQE_AEID_LLP_TERMINATE_RECEIVED                          = 0x0509,
 732         NES_AEQE_AEID_LLP_TOO_MANY_RETRIES                            = 0x050a,
 733         NES_AEQE_AEID_LLP_TOO_MANY_KEEPALIVE_RETRIES                  = 0x050b,
 734         NES_AEQE_AEID_RESET_SENT                                      = 0x0601,
 735         NES_AEQE_AEID_TERMINATE_SENT                                  = 0x0602,
 736         NES_AEQE_AEID_DDP_LCE_LOCAL_CATASTROPHIC                      = 0x0700
 737 };
 738
 739 enum nes_iwarp_sq_opcodes {
 740         NES_IWARP_SQ_WQE_WRPDU = (1<<15),
 741         NES_IWARP_SQ_WQE_PSH = (1<<21),
 742         NES_IWARP_SQ_WQE_STREAMING = (1<<23),
 743         NES_IWARP_SQ_WQE_IMM_DATA = (1<<28),
 744         NES_IWARP_SQ_WQE_READ_FENCE = (1<<29),
 745         NES_IWARP_SQ_WQE_LOCAL_FENCE = (1<<30),
 746         NES_IWARP_SQ_WQE_SIGNALED_COMPL = (1<<31),
 747 };
 748
 749 enum nes_iwarp_sq_wqe_bits {
 750         NES_IWARP_SQ_OP_RDMAW = 0,
 751         NES_IWARP_SQ_OP_RDMAR = 1,
 752         NES_IWARP_SQ_OP_SEND = 3,
 753         NES_IWARP_SQ_OP_SENDINV = 4,
 754         NES_IWARP_SQ_OP_SENDSE = 5,
 755         NES_IWARP_SQ_OP_SENDSEINV = 6,
 756         NES_IWARP_SQ_OP_BIND = 8,
 757         NES_IWARP_SQ_OP_FAST_REG = 9,
 758         NES_IWARP_SQ_OP_LOCINV = 10,
 759         NES_IWARP_SQ_OP_RDMAR_LOCINV = 11,
 760         NES_IWARP_SQ_OP_NOP = 12,
 761 };
 762
 763 enum nes_iwarp_cqe_major_code {
 764         NES_IWARP_CQE_MAJOR_FLUSH = 1,
 765         NES_IWARP_CQE_MAJOR_DRV = 0x8000
 766 };
 767
 768 enum nes_iwarp_cqe_minor_code {
 769         NES_IWARP_CQE_MINOR_FLUSH = 1
 770 };
 771
 772 #define NES_EEPROM_READ_REQUEST (1<<16)
 773 #define NES_MAC_ADDR_VALID      (1<<20)
 774
 775 /*
 776  * NES index registers init values.
 777  */
 778 struct nes_init_values {
 779         u32 index;
 780         u32 data;
 781         u8  wrt;
 782 };
 783
 784 /*
 785  * NES registers in BAR0.
 786  */
 787 struct nes_pci_regs {
 788         u32 int_status;
 789         u32 int_mask;
 790         u32 int_pending;
 791         u32 intf_int_status;
 792         u32 intf_int_mask;
 793         u32 other_regs[59];      /* pad out to 256 bytes for now */
 794 };
 795
 796 #define NES_CQP_SQ_SIZE    128
 797 #define NES_CCQ_SIZE       128
 798 #define NES_NIC_WQ_SIZE    512
 799 #define NES_NIC_CTX_SIZE   ((NES_NIC_CTX_RQ_SIZE_512) | (NES_NIC_CTX_SQ_SIZE_512))
 800 #define NES_NIC_BACK_STORE 0x00038000
 801
 802 struct nes_device;
 803
 804 struct nes_hw_nic_qp_context {
 805         __le32 context_words[6];
 806 };
 807
 808 struct nes_hw_nic_sq_wqe {
 809         __le32 wqe_words[16];
 810 };
 811
 812 struct nes_hw_nic_rq_wqe {
 813         __le32 wqe_words[16];
 814 };
 815
 816 struct nes_hw_nic_cqe {
 817         __le32 cqe_words[4];
 818 };
 819
 820 struct nes_hw_cqp_qp_context {
 821         __le32 context_words[4];
 822 };
 823
 824 struct nes_hw_cqp_wqe {
 825         __le32 wqe_words[16];
 826 };
 827
 828 struct nes_hw_qp_wqe {
 829         __le32 wqe_words[32];
 830 };
 831
 832 struct nes_hw_cqe {
 833         __le32 cqe_words[8];
 834 };
 835
 836 struct nes_hw_ceqe {
 837         __le32 ceqe_words[2];
 838 };
 839
 840 struct nes_hw_aeqe {
 841         __le32 aeqe_words[4];
 842 };
 843
 844 struct nes_cqp_request {
 845         union {
 846                 u64 cqp_callback_context;
 847                 void *cqp_callback_pointer;
 848         };
 849         wait_queue_head_t     waitq;
 850         struct nes_hw_cqp_wqe cqp_wqe;
 851         struct list_head      list;
 852         atomic_t              refcount;
 853         void (*cqp_callback)(struct nes_device *nesdev, struct nes_cqp_request *cqp_request);
 854         u16                   major_code;
 855         u16                   minor_code;
 856         u8                    waiting;
 857         u8                    request_done;
 858         u8                    dynamic;
 859         u8                    callback;
 860 };
 861
 862 struct nes_hw_cqp {
 863         struct nes_hw_cqp_wqe *sq_vbase;
 864         dma_addr_t            sq_pbase;
 865         spinlock_t            lock;
 866         wait_queue_head_t     waitq;
 867         u16                   qp_id;
 868         u16                   sq_head;
 869         u16                   sq_tail;
 870         u16                   sq_size;
 871 };
 872
 873 #define NES_FIRST_FRAG_SIZE 128
 874 struct nes_first_frag {
 875         u8 buffer[NES_FIRST_FRAG_SIZE];
 876 };
 877
 878 struct nes_hw_nic {
 879         struct nes_first_frag    *first_frag_vbase;     /* virtual address of first frags */
 880         struct nes_hw_nic_sq_wqe *sq_vbase;                     /* virtual address of sq */
 881         struct nes_hw_nic_rq_wqe *rq_vbase;                     /* virtual address of rq */
 882         struct sk_buff           *tx_skb[NES_NIC_WQ_SIZE];
 883         struct sk_buff           *rx_skb[NES_NIC_WQ_SIZE];
 884         dma_addr_t frag_paddr[NES_NIC_WQ_SIZE];
 885         unsigned long first_frag_overflow[BITS_TO_LONGS(NES_NIC_WQ_SIZE)];
 886         dma_addr_t sq_pbase;                    /* PCI memory for host rings */
 887         dma_addr_t rq_pbase;                    /* PCI memory for host rings */
 888
 889         u16 qp_id;
 890         u16 sq_head;
 891         u16 sq_tail;
 892         u16 sq_size;
 893         u16 rq_head;
 894         u16 rq_tail;
 895         u16 rq_size;
 896         u8 replenishing_rq;
 897         u8 reserved;
 898
 899         spinlock_t rq_lock;
 900 };
 901
 902 struct nes_hw_nic_cq {
 903         struct nes_hw_nic_cqe volatile *cq_vbase;       /* PCI memory for host rings */
 904         void (*ce_handler)(struct nes_device *nesdev, struct nes_hw_nic_cq *cq);
 905         dma_addr_t cq_pbase;    /* PCI memory for host rings */
 906         int rx_cqes_completed;
 907         int cqe_allocs_pending;
 908         int rx_pkts_indicated;
 909         u16 cq_head;
 910         u16 cq_size;
 911         u16 cq_number;
 912         u8  cqes_pending;
 913 };
 914
 915 struct nes_hw_qp {
 916         struct nes_hw_qp_wqe *sq_vbase;         /* PCI memory for host rings */
 917         struct nes_hw_qp_wqe *rq_vbase;         /* PCI memory for host rings */
 918         void                 *q2_vbase;                 /* PCI memory for host rings */
 919         dma_addr_t sq_pbase;    /* PCI memory for host rings */
 920         dma_addr_t rq_pbase;    /* PCI memory for host rings */
 921         dma_addr_t q2_pbase;    /* PCI memory for host rings */
 922         u32 qp_id;
 923         u16 sq_head;
 924         u16 sq_tail;
 925         u16 sq_size;
 926         u16 rq_head;
 927         u16 rq_tail;
 928         u16 rq_size;
 929         u8  rq_encoded_size;
 930         u8  sq_encoded_size;
 931 };
 932
 933 struct nes_hw_cq {
 934         struct nes_hw_cqe *cq_vbase;    /* PCI memory for host rings */
 935         void (*ce_handler)(struct nes_device *nesdev, struct nes_hw_cq *cq);
 936         dma_addr_t cq_pbase;    /* PCI memory for host rings */
 937         u16 cq_head;
 938         u16 cq_size;
 939         u16 cq_number;
 940 };
 941
 942 struct nes_hw_ceq {
 943         struct nes_hw_ceqe volatile *ceq_vbase; /* PCI memory for host rings */
 944         dma_addr_t ceq_pbase;   /* PCI memory for host rings */
 945         u16 ceq_head;
 946         u16 ceq_size;
 947 };
 948
 949 struct nes_hw_aeq {
 950         struct nes_hw_aeqe volatile *aeq_vbase; /* PCI memory for host rings */
 951         dma_addr_t aeq_pbase;   /* PCI memory for host rings */
 952         u16 aeq_head;
 953         u16 aeq_size;
 954 };
 955
 956 struct nic_qp_map {
 957         u8 qpid;
 958         u8 nic_index;
 959         u8 logical_port;
 960         u8 is_hnic;
 961 };
 962
 963 #define NES_CQP_ARP_AEQ_INDEX_MASK  0x000f0000
 964 #define NES_CQP_ARP_AEQ_INDEX_SHIFT 16
 965
 966 #define NES_CQP_APBVT_ADD                       0x00008000
 967 #define NES_CQP_APBVT_NIC_SHIFT         16
 968
 969 #define NES_ARP_ADD     1
 970 #define NES_ARP_DELETE  2
 971 #define NES_ARP_RESOLVE 3
 972
 973 #define NES_MAC_SW_IDLE      0
 974 #define NES_MAC_SW_INTERRUPT 1
 975 #define NES_MAC_SW_MH        2
 976
 977 struct nes_arp_entry {
 978         u32 ip_addr;
 979         u8  mac_addr[ETH_ALEN];
 980 };
 981
 982 #define NES_NIC_FAST_TIMER          96
 983 #define NES_NIC_FAST_TIMER_LOW      40
 984 #define NES_NIC_FAST_TIMER_HIGH     1000
 985 #define DEFAULT_NES_QL_HIGH         256
 986 #define DEFAULT_NES_QL_LOW          16
 987 #define DEFAULT_NES_QL_TARGET       64
 988 #define DEFAULT_JUMBO_NES_QL_LOW    12
 989 #define DEFAULT_JUMBO_NES_QL_TARGET 40
 990 #define DEFAULT_JUMBO_NES_QL_HIGH   128
 991 #define NES_NIC_CQ_DOWNWARD_TREND   16
 992 #define NES_PFT_SIZE                48
 993
 994 struct nes_hw_tune_timer {
 995     /* u16 cq_count; */
 996     u16 threshold_low;
 997     u16 threshold_target;
 998     u16 threshold_high;
 999     u16 timer_in_use;
1000     u16 timer_in_use_old;
1001     u16 timer_in_use_min;
1002     u16 timer_in_use_max;
1003     u8  timer_direction_upward;
1004     u8  timer_direction_downward;
1005     u16 cq_count_old;
1006     u8  cq_direction_downward;
1007 };
1008
1009 #define NES_TIMER_INT_LIMIT         2
1010 #define NES_TIMER_INT_LIMIT_DYNAMIC 10
1011 #define NES_TIMER_ENABLE_LIMIT      4
1012 #define NES_MAX_LINK_INTERRUPTS     128
1013 #define NES_MAX_LINK_CHECK          200
1014 #define NES_MAX_LRO_DESCRIPTORS     32
1015 #define NES_LRO_MAX_AGGR            64
1016
1017 struct nes_adapter {
1018         u64              fw_ver;
1019         unsigned long    *allocated_qps;
1020         unsigned long    *allocated_cqs;
1021         unsigned long    *allocated_mrs;
1022         unsigned long    *allocated_pds;
1023         unsigned long    *allocated_arps;
1024         struct nes_qp    **qp_table;
1025         struct workqueue_struct *work_q;
1026
1027         struct list_head list;
1028         struct list_head active_listeners;
1029         /* list of the netdev's associated with each logical port */
1030         struct list_head nesvnic_list[4];
1031
1032         struct timer_list  mh_timer;
1033         struct timer_list  lc_timer;
1034         struct work_struct work;
1035         spinlock_t         resource_lock;
1036         spinlock_t         phy_lock;
1037         spinlock_t         pbl_lock;
1038         spinlock_t         periodic_timer_lock;
1039
1040         struct nes_arp_entry arp_table[NES_MAX_ARP_TABLE_SIZE];
1041
1042         /* Adapter CEQ and AEQs */
1043         struct nes_hw_ceq ceq[16];
1044         struct nes_hw_aeq aeq[8];
1045
1046         struct nes_hw_tune_timer tune_timer;
1047
1048         unsigned long doorbell_start;
1049
1050         u32 hw_rev;
1051         u32 vendor_id;
1052         u32 vendor_part_id;
1053         u32 device_cap_flags;
1054         u32 tick_delta;
1055         u32 timer_int_req;
1056         u32 arp_table_size;
1057         u32 next_arp_index;
1058
1059         u32 max_mr;
1060         u32 max_256pbl;
1061         u32 max_4kpbl;
1062         u32 free_256pbl;
1063         u32 free_4kpbl;
1064         u32 max_mr_size;
1065         u32 max_qp;
1066         u32 next_qp;
1067         u32 max_irrq;
1068         u32 max_qp_wr;
1069         u32 max_sge;
1070         u32 max_cq;
1071         u32 next_cq;
1072         u32 max_cqe;
1073         u32 max_pd;
1074         u32 base_pd;
1075         u32 next_pd;
1076         u32 hte_index_mask;
1077
1078         /* EEPROM information */
1079         u32 rx_pool_size;
1080         u32 tx_pool_size;
1081         u32 rx_threshold;
1082         u32 tcp_timer_core_clk_divisor;
1083         u32 iwarp_config;
1084         u32 cm_config;
1085         u32 sws_timer_config;
1086         u32 tcp_config1;
1087         u32 wqm_wat;
1088         u32 core_clock;
1089         u32 firmware_version;
1090
1091         u32 nic_rx_eth_route_err;
1092
1093         u32 et_rx_coalesce_usecs;
1094         u32     et_rx_max_coalesced_frames;
1095         u32 et_rx_coalesce_usecs_irq;
1096         u32 et_rx_max_coalesced_frames_irq;
1097         u32 et_pkt_rate_low;
1098         u32 et_rx_coalesce_usecs_low;
1099         u32 et_rx_max_coalesced_frames_low;
1100         u32 et_pkt_rate_high;
1101         u32 et_rx_coalesce_usecs_high;
1102         u32 et_rx_max_coalesced_frames_high;
1103         u32 et_rate_sample_interval;
1104         u32 timer_int_limit;
1105         u32 wqm_quanta;
1106
1107         /* Adapter base MAC address */
1108         u32 mac_addr_low;
1109         u16 mac_addr_high;
1110
1111         u16 firmware_eeprom_offset;
1112         u16 software_eeprom_offset;
1113
1114         u16 max_irrq_wr;
1115
1116         /* pd config for each port */
1117         u16 pd_config_size[4];
1118         u16 pd_config_base[4];
1119
1120         u16 link_interrupt_count[4];
1121         u8 crit_error_count[32];
1122
1123         /* the phy index for each port */
1124         u8  phy_index[4];
1125         u8  mac_sw_state[4];
1126         u8  mac_link_down[4];
1127         u8  phy_type[4];
1128         u8  log_port;
1129
1130         /* PCI information */
1131         unsigned int  devfn;
1132         unsigned char bus_number;
1133         unsigned char OneG_Mode;
1134
1135         unsigned char ref_count;
1136         u8            netdev_count;
1137         u8            netdev_max;       /* from host nic address count in EEPROM */
1138         u8            port_count;
1139         u8            virtwq;
1140         u8            send_term_ok;
1141         u8            et_use_adaptive_rx_coalesce;
1142         u8            adapter_fcn_count;
1143         u8 pft_mcast_map[NES_PFT_SIZE];
1144 };
1145
1146 struct nes_pbl {
1147         u64              *pbl_vbase;
1148         dma_addr_t       pbl_pbase;
1149         struct page      *page;
1150         unsigned long    user_base;
1151         u32              pbl_size;
1152         struct list_head list;
1153         /* TODO: need to add list for two level tables */
1154 };
1155
1156 struct nes_listener {
1157         struct work_struct      work;
1158         struct workqueue_struct *wq;
1159         struct nes_vnic         *nesvnic;
1160         struct iw_cm_id         *cm_id;
1161         struct list_head        list;
1162         unsigned long           socket;
1163         u8                      accept_failed;
1164 };
1165
1166 struct nes_ib_device;
1167
1168 struct nes_vnic {
1169         struct nes_ib_device *nesibdev;
1170         u64 sq_full;
1171         u64 tso_requests;
1172         u64 segmented_tso_requests;
1173         u64 linearized_skbs;
1174         u64 tx_sw_dropped;
1175         u64 endnode_nstat_rx_discard;
1176         u64 endnode_nstat_rx_octets;
1177         u64 endnode_nstat_rx_frames;
1178         u64 endnode_nstat_tx_octets;
1179         u64 endnode_nstat_tx_frames;
1180         u64 endnode_ipv4_tcp_retransmits;
1181         /* void *mem; */
1182         struct nes_device *nesdev;
1183         struct net_device *netdev;
1184         struct vlan_group *vlan_grp;
1185         atomic_t          rx_skbs_needed;
1186         atomic_t          rx_skb_timer_running;
1187         int               budget;
1188         u32               msg_enable;
1189         /* u32 tx_avail; */
1190         __be32            local_ipaddr;
1191         struct napi_struct   napi;
1192         spinlock_t           tx_lock;   /* could use netdev tx lock? */
1193         struct timer_list    rq_wqes_timer;
1194         u32                  nic_mem_size;
1195         void                 *nic_vbase;
1196         dma_addr_t           nic_pbase;
1197         struct nes_hw_nic    nic;
1198         struct nes_hw_nic_cq nic_cq;
1199         u32    mcrq_qp_id;
1200         struct nes_ucontext *mcrq_ucontext;
1201         struct nes_cqp_request* (*get_cqp_request)(struct nes_device *nesdev);
1202         void (*post_cqp_request)(struct nes_device*, struct nes_cqp_request *);
1203         int (*mcrq_mcast_filter)( struct nes_vnic* nesvnic, __u8* dmi_addr );
1204         struct net_device_stats netstats;
1205         /* used to put the netdev on the adapters logical port list */
1206         struct list_head list;
1207         u16 max_frame_size;
1208         u8  netdev_open;
1209         u8  linkup;
1210         u8  logical_port;
1211         u8  netdev_index;  /* might not be needed, indexes nesdev->netdev */
1212         u8  perfect_filter_index;
1213         u8  nic_index;
1214         u8  qp_nic_index[4];
1215         u8  next_qp_nic_index;
1216         u8  of_device_registered;
1217         u8  rdma_enabled;
1218         u8  rx_checksum_disabled;
1219         u32 lro_max_aggr;
1220         struct net_lro_mgr lro_mgr;
1221         struct net_lro_desc lro_desc[NES_MAX_LRO_DESCRIPTORS];
1222 };
1223
1224 struct nes_ib_device {
1225         struct ib_device ibdev;
1226         struct nes_vnic *nesvnic;
1227
1228         /* Virtual RNIC Limits */
1229         u32 max_mr;
1230         u32 max_qp;
1231         u32 max_cq;
1232         u32 max_pd;
1233         u32 num_mr;
1234         u32 num_qp;
1235         u32 num_cq;
1236         u32 num_pd;
1237 };
1238
1239 enum nes_hdrct_flags {
1240         DDP_LEN_FLAG                    = 0x80,
1241         DDP_HDR_FLAG                    = 0x40,
1242         RDMA_HDR_FLAG                   = 0x20
1243 };
1244
1245 enum nes_term_layers {
1246         LAYER_RDMA                      = 0,
1247         LAYER_DDP                       = 1,
1248         LAYER_MPA                       = 2
1249 };
1250
1251 enum nes_term_error_types {
1252         RDMAP_CATASTROPHIC              = 0,
1253         RDMAP_REMOTE_PROT               = 1,
1254         RDMAP_REMOTE_OP                 = 2,
1255         DDP_CATASTROPHIC                = 0,
1256         DDP_TAGGED_BUFFER               = 1,
1257         DDP_UNTAGGED_BUFFER             = 2,
1258         DDP_LLP                         = 3
1259 };
1260
1261 enum nes_term_rdma_errors {
1262         RDMAP_INV_STAG                  = 0x00,
1263         RDMAP_INV_BOUNDS                = 0x01,
1264         RDMAP_ACCESS                    = 0x02,
1265         RDMAP_UNASSOC_STAG              = 0x03,
1266         RDMAP_TO_WRAP                   = 0x04,
1267         RDMAP_INV_RDMAP_VER             = 0x05,
1268         RDMAP_UNEXPECTED_OP             = 0x06,
1269         RDMAP_CATASTROPHIC_LOCAL        = 0x07,
1270         RDMAP_CATASTROPHIC_GLOBAL       = 0x08,
1271         RDMAP_CANT_INV_STAG             = 0x09,
1272         RDMAP_UNSPECIFIED               = 0xff
1273 };
1274
1275 enum nes_term_ddp_errors {
1276         DDP_CATASTROPHIC_LOCAL          = 0x00,
1277         DDP_TAGGED_INV_STAG             = 0x00,
1278         DDP_TAGGED_BOUNDS               = 0x01,
1279         DDP_TAGGED_UNASSOC_STAG         = 0x02,
1280         DDP_TAGGED_TO_WRAP              = 0x03,
1281         DDP_TAGGED_INV_DDP_VER          = 0x04,
1282         DDP_UNTAGGED_INV_QN             = 0x01,
1283         DDP_UNTAGGED_INV_MSN_NO_BUF     = 0x02,
1284         DDP_UNTAGGED_INV_MSN_RANGE      = 0x03,
1285         DDP_UNTAGGED_INV_MO             = 0x04,
1286         DDP_UNTAGGED_INV_TOO_LONG       = 0x05,
1287         DDP_UNTAGGED_INV_DDP_VER        = 0x06
1288 };
1289
1290 enum nes_term_mpa_errors {
1291         MPA_CLOSED                      = 0x01,
1292         MPA_CRC                         = 0x02,
1293         MPA_MARKER                      = 0x03,
1294         MPA_REQ_RSP                     = 0x04,
1295 };
1296
1297 struct nes_terminate_hdr {
1298         u8 layer_etype;
1299         u8 error_code;
1300         u8 hdrct;
1301         u8 rsvd;
1302 };
1303
1304 /* Used to determine how to fill in terminate error codes */
1305 #define IWARP_OPCODE_WRITE              0
1306 #define IWARP_OPCODE_READREQ            1
1307 #define IWARP_OPCODE_READRSP            2
1308 #define IWARP_OPCODE_SEND               3
1309 #define IWARP_OPCODE_SEND_INV           4
1310 #define IWARP_OPCODE_SEND_SE            5
1311 #define IWARP_OPCODE_SEND_SE_INV        6
1312 #define IWARP_OPCODE_TERM               7
1313
1314 /* These values are used only during terminate processing */
1315 #define TERM_DDP_LEN_TAGGED     14
1316 #define TERM_DDP_LEN_UNTAGGED   18
1317 #define TERM_RDMA_LEN           28
1318 #define RDMA_OPCODE_MASK        0x0f
1319 #define RDMA_READ_REQ_OPCODE    1
1320 #define BAD_FRAME_OFFSET        64
1321 #define CQE_MAJOR_DRV           0x8000
1322
1323 #define nes_vlan_rx vlan_hwaccel_receive_skb
1324 #define nes_netif_rx netif_receive_skb
1325
1326 #endif          /* __NES_HW_H */