drivers/infiniband/hw/nes/nes_hw.h

   1 /*
   2 * Copyright (c) 2006 - 2009 Intel Corporation.  All rights reserved.
   3 *
   4 * This software is available to you under a choice of one of two
   5 * licenses.  You may choose to be licensed under the terms of the GNU
   6 * General Public License (GPL) Version 2, available from the file
   7 * COPYING in the main directory of this source tree, or the
   8 * OpenIB.org BSD license below:
   9 *
  10 *     Redistribution and use in source and binary forms, with or
  11 *     without modification, are permitted provided that the following
  12 *     conditions are met:
  13 *
  14 *      - Redistributions of source code must retain the above
  15 *        copyright notice, this list of conditions and the following
  16 *        disclaimer.
  17 *
  18 *      - Redistributions in binary form must reproduce the above
  19 *        copyright notice, this list of conditions and the following
  20 *        disclaimer in the documentation and/or other materials
  21 *        provided with the distribution.
  22 *
  23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30 * SOFTWARE.
  31 */
  32
  33 #ifndef __NES_HW_H
  34 #define __NES_HW_H
  35
  36 #include <linux/inet_lro.h>
  37
  38 #define NES_PHY_TYPE_CX4       1
  39 #define NES_PHY_TYPE_1G        2
  40 #define NES_PHY_TYPE_ARGUS     4
  41 #define NES_PHY_TYPE_PUMA_1G   5
  42 #define NES_PHY_TYPE_PUMA_10G  6
  43 #define NES_PHY_TYPE_GLADIUS   7
  44 #define NES_PHY_TYPE_SFP_D     8
  45 #define NES_PHY_TYPE_KR        9
  46
  47 #define NES_MULTICAST_PF_MAX 8
  48 #define NES_A0 3
  49
  50 enum pci_regs {
  51         NES_INT_STAT = 0x0000,
  52         NES_INT_MASK = 0x0004,
  53         NES_INT_PENDING = 0x0008,
  54         NES_INTF_INT_STAT = 0x000C,
  55         NES_INTF_INT_MASK = 0x0010,
  56         NES_TIMER_STAT = 0x0014,
  57         NES_PERIODIC_CONTROL = 0x0018,
  58         NES_ONE_SHOT_CONTROL = 0x001C,
  59         NES_EEPROM_COMMAND = 0x0020,
  60         NES_EEPROM_DATA = 0x0024,
  61         NES_FLASH_COMMAND = 0x0028,
  62         NES_FLASH_DATA  = 0x002C,
  63         NES_SOFTWARE_RESET = 0x0030,
  64         NES_CQ_ACK = 0x0034,
  65         NES_WQE_ALLOC = 0x0040,
  66         NES_CQE_ALLOC = 0x0044,
  67         NES_AEQ_ALLOC = 0x0048
  68 };
  69
  70 enum indexed_regs {
  71         NES_IDX_CREATE_CQP_LOW = 0x0000,
  72         NES_IDX_CREATE_CQP_HIGH = 0x0004,
  73         NES_IDX_QP_CONTROL = 0x0040,
  74         NES_IDX_FLM_CONTROL = 0x0080,
  75         NES_IDX_INT_CPU_STATUS = 0x00a0,
  76         NES_IDX_GPIO_CONTROL = 0x00f0,
  77         NES_IDX_GPIO_DATA = 0x00f4,
  78         NES_IDX_TCP_CONFIG0 = 0x01e4,
  79         NES_IDX_TCP_TIMER_CONFIG = 0x01ec,
  80         NES_IDX_TCP_NOW = 0x01f0,
  81         NES_IDX_QP_MAX_CFG_SIZES = 0x0200,
  82         NES_IDX_QP_CTX_SIZE = 0x0218,
  83         NES_IDX_TCP_TIMER_SIZE0 = 0x0238,
  84         NES_IDX_TCP_TIMER_SIZE1 = 0x0240,
  85         NES_IDX_ARP_CACHE_SIZE = 0x0258,
  86         NES_IDX_CQ_CTX_SIZE = 0x0260,
  87         NES_IDX_MRT_SIZE = 0x0278,
  88         NES_IDX_PBL_REGION_SIZE = 0x0280,
  89         NES_IDX_IRRQ_COUNT = 0x02b0,
  90         NES_IDX_RX_WINDOW_BUFFER_PAGE_TABLE_SIZE = 0x02f0,
  91         NES_IDX_RX_WINDOW_BUFFER_SIZE = 0x0300,
  92         NES_IDX_DST_IP_ADDR = 0x0400,
  93         NES_IDX_PCIX_DIAG = 0x08e8,
  94         NES_IDX_MPP_DEBUG = 0x0a00,
  95         NES_IDX_PORT_RX_DISCARDS = 0x0a30,
  96         NES_IDX_PORT_TX_DISCARDS = 0x0a34,
  97         NES_IDX_MPP_LB_DEBUG = 0x0b00,
  98         NES_IDX_DENALI_CTL_22 = 0x1058,
  99         NES_IDX_MAC_TX_CONTROL = 0x2000,
 100         NES_IDX_MAC_TX_CONFIG = 0x2004,
 101         NES_IDX_MAC_TX_PAUSE_QUANTA = 0x2008,
 102         NES_IDX_MAC_RX_CONTROL = 0x200c,
 103         NES_IDX_MAC_RX_CONFIG = 0x2010,
 104         NES_IDX_MAC_EXACT_MATCH_BOTTOM = 0x201c,
 105         NES_IDX_MAC_MDIO_CONTROL = 0x2084,
 106         NES_IDX_MAC_TX_OCTETS_LOW = 0x2100,
 107         NES_IDX_MAC_TX_OCTETS_HIGH = 0x2104,
 108         NES_IDX_MAC_TX_FRAMES_LOW = 0x2108,
 109         NES_IDX_MAC_TX_FRAMES_HIGH = 0x210c,
 110         NES_IDX_MAC_TX_PAUSE_FRAMES = 0x2118,
 111         NES_IDX_MAC_TX_ERRORS = 0x2138,
 112         NES_IDX_MAC_RX_OCTETS_LOW = 0x213c,
 113         NES_IDX_MAC_RX_OCTETS_HIGH = 0x2140,
 114         NES_IDX_MAC_RX_FRAMES_LOW = 0x2144,
 115         NES_IDX_MAC_RX_FRAMES_HIGH = 0x2148,
 116         NES_IDX_MAC_RX_BC_FRAMES_LOW = 0x214c,
 117         NES_IDX_MAC_RX_MC_FRAMES_HIGH = 0x2150,
 118         NES_IDX_MAC_RX_PAUSE_FRAMES = 0x2154,
 119         NES_IDX_MAC_RX_SHORT_FRAMES = 0x2174,
 120         NES_IDX_MAC_RX_OVERSIZED_FRAMES = 0x2178,
 121         NES_IDX_MAC_RX_JABBER_FRAMES = 0x217c,
 122         NES_IDX_MAC_RX_CRC_ERR_FRAMES = 0x2180,
 123         NES_IDX_MAC_RX_LENGTH_ERR_FRAMES = 0x2184,
 124         NES_IDX_MAC_RX_SYMBOL_ERR_FRAMES = 0x2188,
 125         NES_IDX_MAC_INT_STATUS = 0x21f0,
 126         NES_IDX_MAC_INT_MASK = 0x21f4,
 127         NES_IDX_PHY_PCS_CONTROL_STATUS0 = 0x2800,
 128         NES_IDX_PHY_PCS_CONTROL_STATUS1 = 0x2a00,
 129         NES_IDX_ETH_SERDES_COMMON_CONTROL0 = 0x2808,
 130         NES_IDX_ETH_SERDES_COMMON_CONTROL1 = 0x2a08,
 131         NES_IDX_ETH_SERDES_COMMON_STATUS0 = 0x280c,
 132         NES_IDX_ETH_SERDES_COMMON_STATUS1 = 0x2a0c,
 133         NES_IDX_ETH_SERDES_TX_EMP0 = 0x2810,
 134         NES_IDX_ETH_SERDES_TX_EMP1 = 0x2a10,
 135         NES_IDX_ETH_SERDES_TX_DRIVE0 = 0x2814,
 136         NES_IDX_ETH_SERDES_TX_DRIVE1 = 0x2a14,
 137         NES_IDX_ETH_SERDES_RX_MODE0 = 0x2818,
 138         NES_IDX_ETH_SERDES_RX_MODE1 = 0x2a18,
 139         NES_IDX_ETH_SERDES_RX_SIGDET0 = 0x281c,
 140         NES_IDX_ETH_SERDES_RX_SIGDET1 = 0x2a1c,
 141         NES_IDX_ETH_SERDES_BYPASS0 = 0x2820,
 142         NES_IDX_ETH_SERDES_BYPASS1 = 0x2a20,
 143         NES_IDX_ETH_SERDES_LOOPBACK_CONTROL0 = 0x2824,
 144         NES_IDX_ETH_SERDES_LOOPBACK_CONTROL1 = 0x2a24,
 145         NES_IDX_ETH_SERDES_RX_EQ_CONTROL0 = 0x2828,
 146         NES_IDX_ETH_SERDES_RX_EQ_CONTROL1 = 0x2a28,
 147         NES_IDX_ETH_SERDES_RX_EQ_STATUS0 = 0x282c,
 148         NES_IDX_ETH_SERDES_RX_EQ_STATUS1 = 0x2a2c,
 149         NES_IDX_ETH_SERDES_CDR_RESET0 = 0x2830,
 150         NES_IDX_ETH_SERDES_CDR_RESET1 = 0x2a30,
 151         NES_IDX_ETH_SERDES_CDR_CONTROL0 = 0x2834,
 152         NES_IDX_ETH_SERDES_CDR_CONTROL1 = 0x2a34,
 153         NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE0 = 0x2838,
 154         NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE1 = 0x2a38,
 155         NES_IDX_ENDNODE0_NSTAT_RX_DISCARD = 0x3080,
 156         NES_IDX_ENDNODE0_NSTAT_RX_OCTETS_LO = 0x3000,
 157         NES_IDX_ENDNODE0_NSTAT_RX_OCTETS_HI = 0x3004,
 158         NES_IDX_ENDNODE0_NSTAT_RX_FRAMES_LO = 0x3008,
 159         NES_IDX_ENDNODE0_NSTAT_RX_FRAMES_HI = 0x300c,
 160         NES_IDX_ENDNODE0_NSTAT_TX_OCTETS_LO = 0x7000,
 161         NES_IDX_ENDNODE0_NSTAT_TX_OCTETS_HI = 0x7004,
 162         NES_IDX_ENDNODE0_NSTAT_TX_FRAMES_LO = 0x7008,
 163         NES_IDX_ENDNODE0_NSTAT_TX_FRAMES_HI = 0x700c,
 164         NES_IDX_WQM_CONFIG0 = 0x5000,
 165         NES_IDX_WQM_CONFIG1 = 0x5004,
 166         NES_IDX_CM_CONFIG = 0x5100,
 167         NES_IDX_NIC_LOGPORT_TO_PHYPORT = 0x6000,
 168         NES_IDX_NIC_PHYPORT_TO_USW = 0x6008,
 169         NES_IDX_NIC_ACTIVE = 0x6010,
 170         NES_IDX_NIC_UNICAST_ALL = 0x6018,
 171         NES_IDX_NIC_MULTICAST_ALL = 0x6020,
 172         NES_IDX_NIC_MULTICAST_ENABLE = 0x6028,
 173         NES_IDX_NIC_BROADCAST_ON = 0x6030,
 174         NES_IDX_USED_CHUNKS_TX = 0x60b0,
 175         NES_IDX_TX_POOL_SIZE = 0x60b8,
 176         NES_IDX_QUAD_HASH_TABLE_SIZE = 0x6148,
 177         NES_IDX_PERFECT_FILTER_LOW = 0x6200,
 178         NES_IDX_PERFECT_FILTER_HIGH = 0x6204,
 179         NES_IDX_IPV4_TCP_REXMITS = 0x7080,
 180         NES_IDX_DEBUG_ERROR_CONTROL_STATUS = 0x913c,
 181         NES_IDX_DEBUG_ERROR_MASKS0 = 0x9140,
 182         NES_IDX_DEBUG_ERROR_MASKS1 = 0x9144,
 183         NES_IDX_DEBUG_ERROR_MASKS2 = 0x9148,
 184         NES_IDX_DEBUG_ERROR_MASKS3 = 0x914c,
 185         NES_IDX_DEBUG_ERROR_MASKS4 = 0x9150,
 186         NES_IDX_DEBUG_ERROR_MASKS5 = 0x9154,
 187 };
 188
 189 #define NES_IDX_MAC_TX_CONFIG_ENABLE_PAUSE   1
 190 #define NES_IDX_MPP_DEBUG_PORT_DISABLE_PAUSE (1 << 17)
 191
 192 enum nes_cqp_opcodes {
 193         NES_CQP_CREATE_QP = 0x00,
 194         NES_CQP_MODIFY_QP = 0x01,
 195         NES_CQP_DESTROY_QP = 0x02,
 196         NES_CQP_CREATE_CQ = 0x03,
 197         NES_CQP_MODIFY_CQ = 0x04,
 198         NES_CQP_DESTROY_CQ = 0x05,
 199         NES_CQP_ALLOCATE_STAG = 0x09,
 200         NES_CQP_REGISTER_STAG = 0x0a,
 201         NES_CQP_QUERY_STAG = 0x0b,
 202         NES_CQP_REGISTER_SHARED_STAG = 0x0c,
 203         NES_CQP_DEALLOCATE_STAG = 0x0d,
 204         NES_CQP_MANAGE_ARP_CACHE = 0x0f,
 205         NES_CQP_SUSPEND_QPS = 0x11,
 206         NES_CQP_UPLOAD_CONTEXT = 0x13,
 207         NES_CQP_CREATE_CEQ = 0x16,
 208         NES_CQP_DESTROY_CEQ = 0x18,
 209         NES_CQP_CREATE_AEQ = 0x19,
 210         NES_CQP_DESTROY_AEQ = 0x1b,
 211         NES_CQP_LMI_ACCESS = 0x20,
 212         NES_CQP_FLUSH_WQES = 0x22,
 213         NES_CQP_MANAGE_APBVT = 0x23
 214 };
 215
 216 enum nes_cqp_wqe_word_idx {
 217         NES_CQP_WQE_OPCODE_IDX = 0,
 218         NES_CQP_WQE_ID_IDX = 1,
 219         NES_CQP_WQE_COMP_CTX_LOW_IDX = 2,
 220         NES_CQP_WQE_COMP_CTX_HIGH_IDX = 3,
 221         NES_CQP_WQE_COMP_SCRATCH_LOW_IDX = 4,
 222         NES_CQP_WQE_COMP_SCRATCH_HIGH_IDX = 5,
 223 };
 224
 225 enum nes_cqp_cq_wqeword_idx {
 226         NES_CQP_CQ_WQE_PBL_LOW_IDX = 6,
 227         NES_CQP_CQ_WQE_PBL_HIGH_IDX = 7,
 228         NES_CQP_CQ_WQE_CQ_CONTEXT_LOW_IDX = 8,
 229         NES_CQP_CQ_WQE_CQ_CONTEXT_HIGH_IDX = 9,
 230         NES_CQP_CQ_WQE_DOORBELL_INDEX_HIGH_IDX = 10,
 231 };
 232
 233 enum nes_cqp_stag_wqeword_idx {
 234         NES_CQP_STAG_WQE_PBL_BLK_COUNT_IDX = 1,
 235         NES_CQP_STAG_WQE_LEN_HIGH_PD_IDX = 6,
 236         NES_CQP_STAG_WQE_LEN_LOW_IDX = 7,
 237         NES_CQP_STAG_WQE_STAG_IDX = 8,
 238         NES_CQP_STAG_WQE_VA_LOW_IDX = 10,
 239         NES_CQP_STAG_WQE_VA_HIGH_IDX = 11,
 240         NES_CQP_STAG_WQE_PA_LOW_IDX = 12,
 241         NES_CQP_STAG_WQE_PA_HIGH_IDX = 13,
 242         NES_CQP_STAG_WQE_PBL_LEN_IDX = 14
 243 };
 244
 245 #define NES_CQP_OP_IWARP_STATE_SHIFT 28
 246 #define NES_CQP_OP_TERMLEN_SHIFT     28
 247
 248 enum nes_cqp_qp_bits {
 249         NES_CQP_QP_ARP_VALID = (1<<8),
 250         NES_CQP_QP_WINBUF_VALID = (1<<9),
 251         NES_CQP_QP_CONTEXT_VALID = (1<<10),
 252         NES_CQP_QP_ORD_VALID = (1<<11),
 253         NES_CQP_QP_WINBUF_DATAIND_EN = (1<<12),
 254         NES_CQP_QP_VIRT_WQS = (1<<13),
 255         NES_CQP_QP_DEL_HTE = (1<<14),
 256         NES_CQP_QP_CQS_VALID = (1<<15),
 257         NES_CQP_QP_TYPE_TSA = 0,
 258         NES_CQP_QP_TYPE_IWARP = (1<<16),
 259         NES_CQP_QP_TYPE_CQP = (4<<16),
 260         NES_CQP_QP_TYPE_NIC = (5<<16),
 261         NES_CQP_QP_MSS_CHG = (1<<20),
 262         NES_CQP_QP_STATIC_RESOURCES = (1<<21),
 263         NES_CQP_QP_IGNORE_MW_BOUND = (1<<22),
 264         NES_CQP_QP_VWQ_USE_LMI = (1<<23),
 265         NES_CQP_QP_IWARP_STATE_IDLE = (1<<NES_CQP_OP_IWARP_STATE_SHIFT),
 266         NES_CQP_QP_IWARP_STATE_RTS = (2<<NES_CQP_OP_IWARP_STATE_SHIFT),
 267         NES_CQP_QP_IWARP_STATE_CLOSING = (3<<NES_CQP_OP_IWARP_STATE_SHIFT),
 268         NES_CQP_QP_IWARP_STATE_TERMINATE = (5<<NES_CQP_OP_IWARP_STATE_SHIFT),
 269         NES_CQP_QP_IWARP_STATE_ERROR = (6<<NES_CQP_OP_IWARP_STATE_SHIFT),
 270         NES_CQP_QP_IWARP_STATE_MASK = (7<<NES_CQP_OP_IWARP_STATE_SHIFT),
 271         NES_CQP_QP_TERM_DONT_SEND_FIN = (1<<24),
 272         NES_CQP_QP_TERM_DONT_SEND_TERM_MSG = (1<<25),
 273         NES_CQP_QP_RESET = (1<<31),
 274 };
 275
 276 enum nes_cqp_qp_wqe_word_idx {
 277         NES_CQP_QP_WQE_CONTEXT_LOW_IDX = 6,
 278         NES_CQP_QP_WQE_CONTEXT_HIGH_IDX = 7,
 279         NES_CQP_QP_WQE_FLUSH_SQ_CODE = 8,
 280         NES_CQP_QP_WQE_FLUSH_RQ_CODE = 9,
 281         NES_CQP_QP_WQE_NEW_MSS_IDX = 15,
 282 };
 283
 284 enum nes_nic_ctx_bits {
 285         NES_NIC_CTX_RQ_SIZE_32 = (3<<8),
 286         NES_NIC_CTX_RQ_SIZE_512 = (3<<8),
 287         NES_NIC_CTX_SQ_SIZE_32 = (1<<10),
 288         NES_NIC_CTX_SQ_SIZE_512 = (3<<10),
 289 };
 290
 291 enum nes_nic_qp_ctx_word_idx {
 292         NES_NIC_CTX_MISC_IDX = 0,
 293         NES_NIC_CTX_SQ_LOW_IDX = 2,
 294         NES_NIC_CTX_SQ_HIGH_IDX = 3,
 295         NES_NIC_CTX_RQ_LOW_IDX = 4,
 296         NES_NIC_CTX_RQ_HIGH_IDX = 5,
 297 };
 298
 299 enum nes_cqp_cq_bits {
 300         NES_CQP_CQ_CEQE_MASK = (1<<9),
 301         NES_CQP_CQ_CEQ_VALID = (1<<10),
 302         NES_CQP_CQ_RESIZE = (1<<11),
 303         NES_CQP_CQ_CHK_OVERFLOW = (1<<12),
 304         NES_CQP_CQ_4KB_CHUNK = (1<<14),
 305         NES_CQP_CQ_VIRT = (1<<15),
 306 };
 307
 308 enum nes_cqp_stag_bits {
 309         NES_CQP_STAG_VA_TO = (1<<9),
 310         NES_CQP_STAG_DEALLOC_PBLS = (1<<10),
 311         NES_CQP_STAG_PBL_BLK_SIZE = (1<<11),
 312         NES_CQP_STAG_MR = (1<<13),
 313         NES_CQP_STAG_RIGHTS_LOCAL_READ = (1<<16),
 314         NES_CQP_STAG_RIGHTS_LOCAL_WRITE = (1<<17),
 315         NES_CQP_STAG_RIGHTS_REMOTE_READ = (1<<18),
 316         NES_CQP_STAG_RIGHTS_REMOTE_WRITE = (1<<19),
 317         NES_CQP_STAG_RIGHTS_WINDOW_BIND = (1<<20),
 318         NES_CQP_STAG_REM_ACC_EN = (1<<21),
 319         NES_CQP_STAG_LEAVE_PENDING = (1<<31),
 320 };
 321
 322 enum nes_cqp_ceq_wqeword_idx {
 323         NES_CQP_CEQ_WQE_ELEMENT_COUNT_IDX = 1,
 324         NES_CQP_CEQ_WQE_PBL_LOW_IDX = 6,
 325         NES_CQP_CEQ_WQE_PBL_HIGH_IDX = 7,
 326 };
 327
 328 enum nes_cqp_ceq_bits {
 329         NES_CQP_CEQ_4KB_CHUNK = (1<<14),
 330         NES_CQP_CEQ_VIRT = (1<<15),
 331 };
 332
 333 enum nes_cqp_aeq_wqeword_idx {
 334         NES_CQP_AEQ_WQE_ELEMENT_COUNT_IDX = 1,
 335         NES_CQP_AEQ_WQE_PBL_LOW_IDX = 6,
 336         NES_CQP_AEQ_WQE_PBL_HIGH_IDX = 7,
 337 };
 338
 339 enum nes_cqp_aeq_bits {
 340         NES_CQP_AEQ_4KB_CHUNK = (1<<14),
 341         NES_CQP_AEQ_VIRT = (1<<15),
 342 };
 343
 344 enum nes_cqp_lmi_wqeword_idx {
 345         NES_CQP_LMI_WQE_LMI_OFFSET_IDX = 1,
 346         NES_CQP_LMI_WQE_FRAG_LOW_IDX = 8,
 347         NES_CQP_LMI_WQE_FRAG_HIGH_IDX = 9,
 348         NES_CQP_LMI_WQE_FRAG_LEN_IDX = 10,
 349 };
 350
 351 enum nes_cqp_arp_wqeword_idx {
 352         NES_CQP_ARP_WQE_MAC_ADDR_LOW_IDX = 6,
 353         NES_CQP_ARP_WQE_MAC_HIGH_IDX = 7,
 354         NES_CQP_ARP_WQE_REACHABILITY_MAX_IDX = 1,
 355 };
 356
 357 enum nes_cqp_upload_wqeword_idx {
 358         NES_CQP_UPLOAD_WQE_CTXT_LOW_IDX = 6,
 359         NES_CQP_UPLOAD_WQE_CTXT_HIGH_IDX = 7,
 360         NES_CQP_UPLOAD_WQE_HTE_IDX = 8,
 361 };
 362
 363 enum nes_cqp_arp_bits {
 364         NES_CQP_ARP_VALID = (1<<8),
 365         NES_CQP_ARP_PERM = (1<<9),
 366 };
 367
 368 enum nes_cqp_flush_bits {
 369         NES_CQP_FLUSH_SQ = (1<<30),
 370         NES_CQP_FLUSH_RQ = (1<<31),
 371         NES_CQP_FLUSH_MAJ_MIN = (1<<28),
 372 };
 373
 374 enum nes_cqe_opcode_bits {
 375         NES_CQE_STAG_VALID = (1<<6),
 376         NES_CQE_ERROR = (1<<7),
 377         NES_CQE_SQ = (1<<8),
 378         NES_CQE_SE = (1<<9),
 379         NES_CQE_PSH = (1<<29),
 380         NES_CQE_FIN = (1<<30),
 381         NES_CQE_VALID = (1<<31),
 382 };
 383
 384
 385 enum nes_cqe_word_idx {
 386         NES_CQE_PAYLOAD_LENGTH_IDX = 0,
 387         NES_CQE_COMP_COMP_CTX_LOW_IDX = 2,
 388         NES_CQE_COMP_COMP_CTX_HIGH_IDX = 3,
 389         NES_CQE_INV_STAG_IDX = 4,
 390         NES_CQE_QP_ID_IDX = 5,
 391         NES_CQE_ERROR_CODE_IDX = 6,
 392         NES_CQE_OPCODE_IDX = 7,
 393 };
 394
 395 enum nes_ceqe_word_idx {
 396         NES_CEQE_CQ_CTX_LOW_IDX = 0,
 397         NES_CEQE_CQ_CTX_HIGH_IDX = 1,
 398 };
 399
 400 enum nes_ceqe_status_bit {
 401         NES_CEQE_VALID = (1<<31),
 402 };
 403
 404 enum nes_int_bits {
 405         NES_INT_CEQ0 = (1<<0),
 406         NES_INT_CEQ1 = (1<<1),
 407         NES_INT_CEQ2 = (1<<2),
 408         NES_INT_CEQ3 = (1<<3),
 409         NES_INT_CEQ4 = (1<<4),
 410         NES_INT_CEQ5 = (1<<5),
 411         NES_INT_CEQ6 = (1<<6),
 412         NES_INT_CEQ7 = (1<<7),
 413         NES_INT_CEQ8 = (1<<8),
 414         NES_INT_CEQ9 = (1<<9),
 415         NES_INT_CEQ10 = (1<<10),
 416         NES_INT_CEQ11 = (1<<11),
 417         NES_INT_CEQ12 = (1<<12),
 418         NES_INT_CEQ13 = (1<<13),
 419         NES_INT_CEQ14 = (1<<14),
 420         NES_INT_CEQ15 = (1<<15),
 421         NES_INT_AEQ0 = (1<<16),
 422         NES_INT_AEQ1 = (1<<17),
 423         NES_INT_AEQ2 = (1<<18),
 424         NES_INT_AEQ3 = (1<<19),
 425         NES_INT_AEQ4 = (1<<20),
 426         NES_INT_AEQ5 = (1<<21),
 427         NES_INT_AEQ6 = (1<<22),
 428         NES_INT_AEQ7 = (1<<23),
 429         NES_INT_MAC0 = (1<<24),
 430         NES_INT_MAC1 = (1<<25),
 431         NES_INT_MAC2 = (1<<26),
 432         NES_INT_MAC3 = (1<<27),
 433         NES_INT_TSW = (1<<28),
 434         NES_INT_TIMER = (1<<29),
 435         NES_INT_INTF = (1<<30),
 436 };
 437
 438 enum nes_intf_int_bits {
 439         NES_INTF_INT_PCIERR = (1<<0),
 440         NES_INTF_PERIODIC_TIMER = (1<<2),
 441         NES_INTF_ONE_SHOT_TIMER = (1<<3),
 442         NES_INTF_INT_CRITERR = (1<<14),
 443         NES_INTF_INT_AEQ0_OFLOW = (1<<16),
 444         NES_INTF_INT_AEQ1_OFLOW = (1<<17),
 445         NES_INTF_INT_AEQ2_OFLOW = (1<<18),
 446         NES_INTF_INT_AEQ3_OFLOW = (1<<19),
 447         NES_INTF_INT_AEQ4_OFLOW = (1<<20),
 448         NES_INTF_INT_AEQ5_OFLOW = (1<<21),
 449         NES_INTF_INT_AEQ6_OFLOW = (1<<22),
 450         NES_INTF_INT_AEQ7_OFLOW = (1<<23),
 451         NES_INTF_INT_AEQ_OFLOW = (0xff<<16),
 452 };
 453
 454 enum nes_mac_int_bits {
 455         NES_MAC_INT_LINK_STAT_CHG = (1<<1),
 456         NES_MAC_INT_XGMII_EXT = (1<<2),
 457         NES_MAC_INT_TX_UNDERFLOW = (1<<6),
 458         NES_MAC_INT_TX_ERROR = (1<<7),
 459 };
 460
 461 enum nes_cqe_allocate_bits {
 462         NES_CQE_ALLOC_INC_SELECT = (1<<28),
 463         NES_CQE_ALLOC_NOTIFY_NEXT = (1<<29),
 464         NES_CQE_ALLOC_NOTIFY_SE = (1<<30),
 465         NES_CQE_ALLOC_RESET = (1<<31),
 466 };
 467
 468 enum nes_nic_rq_wqe_word_idx {
 469         NES_NIC_RQ_WQE_LENGTH_1_0_IDX = 0,
 470         NES_NIC_RQ_WQE_LENGTH_3_2_IDX = 1,
 471         NES_NIC_RQ_WQE_FRAG0_LOW_IDX = 2,
 472         NES_NIC_RQ_WQE_FRAG0_HIGH_IDX = 3,
 473         NES_NIC_RQ_WQE_FRAG1_LOW_IDX = 4,
 474         NES_NIC_RQ_WQE_FRAG1_HIGH_IDX = 5,
 475         NES_NIC_RQ_WQE_FRAG2_LOW_IDX = 6,
 476         NES_NIC_RQ_WQE_FRAG2_HIGH_IDX = 7,
 477         NES_NIC_RQ_WQE_FRAG3_LOW_IDX = 8,
 478         NES_NIC_RQ_WQE_FRAG3_HIGH_IDX = 9,
 479 };
 480
 481 enum nes_nic_sq_wqe_word_idx {
 482         NES_NIC_SQ_WQE_MISC_IDX = 0,
 483         NES_NIC_SQ_WQE_TOTAL_LENGTH_IDX = 1,
 484         NES_NIC_SQ_WQE_LSO_INFO_IDX = 2,
 485         NES_NIC_SQ_WQE_LENGTH_0_TAG_IDX = 3,
 486         NES_NIC_SQ_WQE_LENGTH_2_1_IDX = 4,
 487         NES_NIC_SQ_WQE_LENGTH_4_3_IDX = 5,
 488         NES_NIC_SQ_WQE_FRAG0_LOW_IDX = 6,
 489         NES_NIC_SQ_WQE_FRAG0_HIGH_IDX = 7,
 490         NES_NIC_SQ_WQE_FRAG1_LOW_IDX = 8,
 491         NES_NIC_SQ_WQE_FRAG1_HIGH_IDX = 9,
 492         NES_NIC_SQ_WQE_FRAG2_LOW_IDX = 10,
 493         NES_NIC_SQ_WQE_FRAG2_HIGH_IDX = 11,
 494         NES_NIC_SQ_WQE_FRAG3_LOW_IDX = 12,
 495         NES_NIC_SQ_WQE_FRAG3_HIGH_IDX = 13,
 496         NES_NIC_SQ_WQE_FRAG4_LOW_IDX = 14,
 497         NES_NIC_SQ_WQE_FRAG4_HIGH_IDX = 15,
 498 };
 499
 500 enum nes_iwarp_sq_wqe_word_idx {
 501         NES_IWARP_SQ_WQE_MISC_IDX = 0,
 502         NES_IWARP_SQ_WQE_TOTAL_PAYLOAD_IDX = 1,
 503         NES_IWARP_SQ_WQE_COMP_CTX_LOW_IDX = 2,
 504         NES_IWARP_SQ_WQE_COMP_CTX_HIGH_IDX = 3,
 505         NES_IWARP_SQ_WQE_COMP_SCRATCH_LOW_IDX = 4,
 506         NES_IWARP_SQ_WQE_COMP_SCRATCH_HIGH_IDX = 5,
 507         NES_IWARP_SQ_WQE_INV_STAG_LOW_IDX = 7,
 508         NES_IWARP_SQ_WQE_RDMA_TO_LOW_IDX = 8,
 509         NES_IWARP_SQ_WQE_RDMA_TO_HIGH_IDX = 9,
 510         NES_IWARP_SQ_WQE_RDMA_LENGTH_IDX = 10,
 511         NES_IWARP_SQ_WQE_RDMA_STAG_IDX = 11,
 512         NES_IWARP_SQ_WQE_IMM_DATA_START_IDX = 12,
 513         NES_IWARP_SQ_WQE_FRAG0_LOW_IDX = 16,
 514         NES_IWARP_SQ_WQE_FRAG0_HIGH_IDX = 17,
 515         NES_IWARP_SQ_WQE_LENGTH0_IDX = 18,
 516         NES_IWARP_SQ_WQE_STAG0_IDX = 19,
 517         NES_IWARP_SQ_WQE_FRAG1_LOW_IDX = 20,
 518         NES_IWARP_SQ_WQE_FRAG1_HIGH_IDX = 21,
 519         NES_IWARP_SQ_WQE_LENGTH1_IDX = 22,
 520         NES_IWARP_SQ_WQE_STAG1_IDX = 23,
 521         NES_IWARP_SQ_WQE_FRAG2_LOW_IDX = 24,
 522         NES_IWARP_SQ_WQE_FRAG2_HIGH_IDX = 25,
 523         NES_IWARP_SQ_WQE_LENGTH2_IDX = 26,
 524         NES_IWARP_SQ_WQE_STAG2_IDX = 27,
 525         NES_IWARP_SQ_WQE_FRAG3_LOW_IDX = 28,
 526         NES_IWARP_SQ_WQE_FRAG3_HIGH_IDX = 29,
 527         NES_IWARP_SQ_WQE_LENGTH3_IDX = 30,
 528         NES_IWARP_SQ_WQE_STAG3_IDX = 31,
 529 };
 530
 531 enum nes_iwarp_sq_bind_wqe_word_idx {
 532         NES_IWARP_SQ_BIND_WQE_MR_IDX = 6,
 533         NES_IWARP_SQ_BIND_WQE_MW_IDX = 7,
 534         NES_IWARP_SQ_BIND_WQE_LENGTH_LOW_IDX = 8,
 535         NES_IWARP_SQ_BIND_WQE_LENGTH_HIGH_IDX = 9,
 536         NES_IWARP_SQ_BIND_WQE_VA_FBO_LOW_IDX = 10,
 537         NES_IWARP_SQ_BIND_WQE_VA_FBO_HIGH_IDX = 11,
 538 };
 539
 540 enum nes_iwarp_sq_fmr_wqe_word_idx {
 541         NES_IWARP_SQ_FMR_WQE_MR_STAG_IDX = 7,
 542         NES_IWARP_SQ_FMR_WQE_LENGTH_LOW_IDX = 8,
 543         NES_IWARP_SQ_FMR_WQE_LENGTH_HIGH_IDX = 9,
 544         NES_IWARP_SQ_FMR_WQE_VA_FBO_LOW_IDX = 10,
 545         NES_IWARP_SQ_FMR_WQE_VA_FBO_HIGH_IDX = 11,
 546         NES_IWARP_SQ_FMR_WQE_PBL_ADDR_LOW_IDX = 12,
 547         NES_IWARP_SQ_FMR_WQE_PBL_ADDR_HIGH_IDX = 13,
 548         NES_IWARP_SQ_FMR_WQE_PBL_LENGTH_IDX = 14,
 549 };
 550
 551 enum nes_iwarp_sq_fmr_opcodes {
 552         NES_IWARP_SQ_FMR_WQE_ZERO_BASED                 = (1<<6),
 553         NES_IWARP_SQ_FMR_WQE_PAGE_SIZE_4K               = (0<<7),
 554         NES_IWARP_SQ_FMR_WQE_PAGE_SIZE_2M               = (1<<7),
 555         NES_IWARP_SQ_FMR_WQE_RIGHTS_ENABLE_LOCAL_READ   = (1<<16),
 556         NES_IWARP_SQ_FMR_WQE_RIGHTS_ENABLE_LOCAL_WRITE  = (1<<17),
 557         NES_IWARP_SQ_FMR_WQE_RIGHTS_ENABLE_REMOTE_READ  = (1<<18),
 558         NES_IWARP_SQ_FMR_WQE_RIGHTS_ENABLE_REMOTE_WRITE = (1<<19),
 559         NES_IWARP_SQ_FMR_WQE_RIGHTS_ENABLE_WINDOW_BIND  = (1<<20),
 560 };
 561
 562 #define NES_IWARP_SQ_FMR_WQE_MR_LENGTH_HIGH_MASK        0xFF;
 563
 564 enum nes_iwarp_sq_locinv_wqe_word_idx {
 565         NES_IWARP_SQ_LOCINV_WQE_INV_STAG_IDX = 6,
 566 };
 567
 568 enum nes_iwarp_rq_wqe_word_idx {
 569         NES_IWARP_RQ_WQE_TOTAL_PAYLOAD_IDX = 1,
 570         NES_IWARP_RQ_WQE_COMP_CTX_LOW_IDX = 2,
 571         NES_IWARP_RQ_WQE_COMP_CTX_HIGH_IDX = 3,
 572         NES_IWARP_RQ_WQE_COMP_SCRATCH_LOW_IDX = 4,
 573         NES_IWARP_RQ_WQE_COMP_SCRATCH_HIGH_IDX = 5,
 574         NES_IWARP_RQ_WQE_FRAG0_LOW_IDX = 8,
 575         NES_IWARP_RQ_WQE_FRAG0_HIGH_IDX = 9,
 576         NES_IWARP_RQ_WQE_LENGTH0_IDX = 10,
 577         NES_IWARP_RQ_WQE_STAG0_IDX = 11,
 578         NES_IWARP_RQ_WQE_FRAG1_LOW_IDX = 12,
 579         NES_IWARP_RQ_WQE_FRAG1_HIGH_IDX = 13,
 580         NES_IWARP_RQ_WQE_LENGTH1_IDX = 14,
 581         NES_IWARP_RQ_WQE_STAG1_IDX = 15,
 582         NES_IWARP_RQ_WQE_FRAG2_LOW_IDX = 16,
 583         NES_IWARP_RQ_WQE_FRAG2_HIGH_IDX = 17,
 584         NES_IWARP_RQ_WQE_LENGTH2_IDX = 18,
 585         NES_IWARP_RQ_WQE_STAG2_IDX = 19,
 586         NES_IWARP_RQ_WQE_FRAG3_LOW_IDX = 20,
 587         NES_IWARP_RQ_WQE_FRAG3_HIGH_IDX = 21,
 588         NES_IWARP_RQ_WQE_LENGTH3_IDX = 22,
 589         NES_IWARP_RQ_WQE_STAG3_IDX = 23,
 590 };
 591
 592 enum nes_nic_sq_wqe_bits {
 593         NES_NIC_SQ_WQE_PHDR_CS_READY =  (1<<21),
 594         NES_NIC_SQ_WQE_LSO_ENABLE = (1<<22),
 595         NES_NIC_SQ_WQE_TAGVALUE_ENABLE = (1<<23),
 596         NES_NIC_SQ_WQE_DISABLE_CHKSUM = (1<<30),
 597         NES_NIC_SQ_WQE_COMPLETION = (1<<31),
 598 };
 599
 600 enum nes_nic_cqe_word_idx {
 601         NES_NIC_CQE_ACCQP_ID_IDX = 0,
 602         NES_NIC_CQE_TAG_PKT_TYPE_IDX = 2,
 603         NES_NIC_CQE_MISC_IDX = 3,
 604 };
 605
 606 #define NES_PKT_TYPE_APBVT_BITS 0xC112
 607 #define NES_PKT_TYPE_APBVT_MASK 0xff3e
 608
 609 #define NES_PKT_TYPE_PVALID_BITS 0x10000000
 610 #define NES_PKT_TYPE_PVALID_MASK 0x30000000
 611
 612 #define NES_PKT_TYPE_TCPV4_BITS 0x0110
 613 #define NES_PKT_TYPE_TCPV4_MASK 0x3f30
 614
 615 #define NES_PKT_TYPE_UDPV4_BITS 0x0210
 616 #define NES_PKT_TYPE_UDPV4_MASK 0x3f30
 617
 618 #define NES_PKT_TYPE_IPV4_BITS  0x0010
 619 #define NES_PKT_TYPE_IPV4_MASK  0x3f30
 620
 621 #define NES_PKT_TYPE_OTHER_BITS 0x0000
 622 #define NES_PKT_TYPE_OTHER_MASK 0x0030
 623
 624 #define NES_NIC_CQE_ERRV_SHIFT 16
 625 enum nes_nic_ev_bits {
 626         NES_NIC_ERRV_BITS_MODE = (1<<0),
 627         NES_NIC_ERRV_BITS_IPV4_CSUM_ERR = (1<<1),
 628         NES_NIC_ERRV_BITS_TCPUDP_CSUM_ERR = (1<<2),
 629         NES_NIC_ERRV_BITS_WQE_OVERRUN = (1<<3),
 630         NES_NIC_ERRV_BITS_IPH_ERR = (1<<4),
 631 };
 632
 633 enum nes_nic_cqe_bits {
 634         NES_NIC_CQE_ERRV_MASK = (0xff<<NES_NIC_CQE_ERRV_SHIFT),
 635         NES_NIC_CQE_SQ = (1<<24),
 636         NES_NIC_CQE_ACCQP_PORT = (1<<28),
 637         NES_NIC_CQE_ACCQP_VALID = (1<<29),
 638         NES_NIC_CQE_TAG_VALID = (1<<30),
 639         NES_NIC_CQE_VALID = (1<<31),
 640 };
 641
 642 enum nes_aeqe_word_idx {
 643         NES_AEQE_COMP_CTXT_LOW_IDX = 0,
 644         NES_AEQE_COMP_CTXT_HIGH_IDX = 1,
 645         NES_AEQE_COMP_QP_CQ_ID_IDX = 2,
 646         NES_AEQE_MISC_IDX = 3,
 647 };
 648
 649 enum nes_aeqe_bits {
 650         NES_AEQE_QP = (1<<16),
 651         NES_AEQE_CQ = (1<<17),
 652         NES_AEQE_SQ = (1<<18),
 653         NES_AEQE_INBOUND_RDMA = (1<<19),
 654         NES_AEQE_IWARP_STATE_MASK = (7<<20),
 655         NES_AEQE_TCP_STATE_MASK = (0xf<<24),
 656         NES_AEQE_Q2_DATA_WRITTEN = (0x3<<28),
 657         NES_AEQE_VALID = (1<<31),
 658 };
 659
 660 #define NES_AEQE_IWARP_STATE_SHIFT      20
 661 #define NES_AEQE_TCP_STATE_SHIFT        24
 662 #define NES_AEQE_Q2_DATA_ETHERNET       (1<<28)
 663 #define NES_AEQE_Q2_DATA_MPA            (1<<29)
 664
 665 enum nes_aeqe_iwarp_state {
 666         NES_AEQE_IWARP_STATE_NON_EXISTANT = 0,
 667         NES_AEQE_IWARP_STATE_IDLE = 1,
 668         NES_AEQE_IWARP_STATE_RTS = 2,
 669         NES_AEQE_IWARP_STATE_CLOSING = 3,
 670         NES_AEQE_IWARP_STATE_TERMINATE = 5,
 671         NES_AEQE_IWARP_STATE_ERROR = 6
 672 };
 673
 674 enum nes_aeqe_tcp_state {
 675         NES_AEQE_TCP_STATE_NON_EXISTANT = 0,
 676         NES_AEQE_TCP_STATE_CLOSED = 1,
 677         NES_AEQE_TCP_STATE_LISTEN = 2,
 678         NES_AEQE_TCP_STATE_SYN_SENT = 3,
 679         NES_AEQE_TCP_STATE_SYN_RCVD = 4,
 680         NES_AEQE_TCP_STATE_ESTABLISHED = 5,
 681         NES_AEQE_TCP_STATE_CLOSE_WAIT = 6,
 682         NES_AEQE_TCP_STATE_FIN_WAIT_1 = 7,
 683         NES_AEQE_TCP_STATE_CLOSING = 8,
 684         NES_AEQE_TCP_STATE_LAST_ACK = 9,
 685         NES_AEQE_TCP_STATE_FIN_WAIT_2 = 10,
 686         NES_AEQE_TCP_STATE_TIME_WAIT = 11
 687 };
 688
 689 enum nes_aeqe_aeid {
 690         NES_AEQE_AEID_AMP_UNALLOCATED_STAG                            = 0x0102,
 691         NES_AEQE_AEID_AMP_INVALID_STAG                                = 0x0103,
 692         NES_AEQE_AEID_AMP_BAD_QP                                      = 0x0104,
 693         NES_AEQE_AEID_AMP_BAD_PD                                      = 0x0105,
 694         NES_AEQE_AEID_AMP_BAD_STAG_KEY                                = 0x0106,
 695         NES_AEQE_AEID_AMP_BAD_STAG_INDEX                              = 0x0107,
 696         NES_AEQE_AEID_AMP_BOUNDS_VIOLATION                            = 0x0108,
 697         NES_AEQE_AEID_AMP_RIGHTS_VIOLATION                            = 0x0109,
 698         NES_AEQE_AEID_AMP_TO_WRAP                                     = 0x010a,
 699         NES_AEQE_AEID_AMP_FASTREG_SHARED                              = 0x010b,
 700         NES_AEQE_AEID_AMP_FASTREG_VALID_STAG                          = 0x010c,
 701         NES_AEQE_AEID_AMP_FASTREG_MW_STAG                             = 0x010d,
 702         NES_AEQE_AEID_AMP_FASTREG_INVALID_RIGHTS                      = 0x010e,
 703         NES_AEQE_AEID_AMP_FASTREG_PBL_TABLE_OVERFLOW                  = 0x010f,
 704         NES_AEQE_AEID_AMP_FASTREG_INVALID_LENGTH                      = 0x0110,
 705         NES_AEQE_AEID_AMP_INVALIDATE_SHARED                           = 0x0111,
 706         NES_AEQE_AEID_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS          = 0x0112,
 707         NES_AEQE_AEID_AMP_INVALIDATE_MR_WITH_BOUND_WINDOWS            = 0x0113,
 708         NES_AEQE_AEID_AMP_MWBIND_VALID_STAG                           = 0x0114,
 709         NES_AEQE_AEID_AMP_MWBIND_OF_MR_STAG                           = 0x0115,
 710         NES_AEQE_AEID_AMP_MWBIND_TO_ZERO_BASED_STAG                   = 0x0116,
 711         NES_AEQE_AEID_AMP_MWBIND_TO_MW_STAG                           = 0x0117,
 712         NES_AEQE_AEID_AMP_MWBIND_INVALID_RIGHTS                       = 0x0118,
 713         NES_AEQE_AEID_AMP_MWBIND_INVALID_BOUNDS                       = 0x0119,
 714         NES_AEQE_AEID_AMP_MWBIND_TO_INVALID_PARENT                    = 0x011a,
 715         NES_AEQE_AEID_AMP_MWBIND_BIND_DISABLED                        = 0x011b,
 716         NES_AEQE_AEID_BAD_CLOSE                                       = 0x0201,
 717         NES_AEQE_AEID_RDMAP_ROE_BAD_LLP_CLOSE                         = 0x0202,
 718         NES_AEQE_AEID_CQ_OPERATION_ERROR                              = 0x0203,
 719         NES_AEQE_AEID_PRIV_OPERATION_DENIED                           = 0x0204,
 720         NES_AEQE_AEID_RDMA_READ_WHILE_ORD_ZERO                        = 0x0205,
 721         NES_AEQE_AEID_STAG_ZERO_INVALID                               = 0x0206,
 722         NES_AEQE_AEID_DDP_INVALID_MSN_GAP_IN_MSN                      = 0x0301,
 723         NES_AEQE_AEID_DDP_INVALID_MSN_RANGE_IS_NOT_VALID              = 0x0302,
 724         NES_AEQE_AEID_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER = 0x0303,
 725         NES_AEQE_AEID_DDP_UBE_INVALID_DDP_VERSION                     = 0x0304,
 726         NES_AEQE_AEID_DDP_UBE_INVALID_MO                              = 0x0305,
 727         NES_AEQE_AEID_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE         = 0x0306,
 728         NES_AEQE_AEID_DDP_UBE_INVALID_QN                              = 0x0307,
 729         NES_AEQE_AEID_DDP_NO_L_BIT                                    = 0x0308,
 730         NES_AEQE_AEID_RDMAP_ROE_INVALID_RDMAP_VERSION                 = 0x0311,
 731         NES_AEQE_AEID_RDMAP_ROE_UNEXPECTED_OPCODE                     = 0x0312,
 732         NES_AEQE_AEID_ROE_INVALID_RDMA_READ_REQUEST                   = 0x0313,
 733         NES_AEQE_AEID_ROE_INVALID_RDMA_WRITE_OR_READ_RESP             = 0x0314,
 734         NES_AEQE_AEID_INVALID_ARP_ENTRY                               = 0x0401,
 735         NES_AEQE_AEID_INVALID_TCP_OPTION_RCVD                         = 0x0402,
 736         NES_AEQE_AEID_STALE_ARP_ENTRY                                 = 0x0403,
 737         NES_AEQE_AEID_LLP_CLOSE_COMPLETE                              = 0x0501,
 738         NES_AEQE_AEID_LLP_CONNECTION_RESET                            = 0x0502,
 739         NES_AEQE_AEID_LLP_FIN_RECEIVED                                = 0x0503,
 740         NES_AEQE_AEID_LLP_RECEIVED_MARKER_AND_LENGTH_FIELDS_DONT_MATCH =  0x0504,
 741         NES_AEQE_AEID_LLP_RECEIVED_MPA_CRC_ERROR                      = 0x0505,
 742         NES_AEQE_AEID_LLP_SEGMENT_TOO_LARGE                           = 0x0506,
 743         NES_AEQE_AEID_LLP_SEGMENT_TOO_SMALL                           = 0x0507,
 744         NES_AEQE_AEID_LLP_SYN_RECEIVED                                = 0x0508,
 745         NES_AEQE_AEID_LLP_TERMINATE_RECEIVED                          = 0x0509,
 746         NES_AEQE_AEID_LLP_TOO_MANY_RETRIES                            = 0x050a,
 747         NES_AEQE_AEID_LLP_TOO_MANY_KEEPALIVE_RETRIES                  = 0x050b,
 748         NES_AEQE_AEID_RESET_SENT                                      = 0x0601,
 749         NES_AEQE_AEID_TERMINATE_SENT                                  = 0x0602,
 750         NES_AEQE_AEID_DDP_LCE_LOCAL_CATASTROPHIC                      = 0x0700
 751 };
 752
 753 enum nes_iwarp_sq_opcodes {
 754         NES_IWARP_SQ_WQE_WRPDU = (1<<15),
 755         NES_IWARP_SQ_WQE_PSH = (1<<21),
 756         NES_IWARP_SQ_WQE_STREAMING = (1<<23),
 757         NES_IWARP_SQ_WQE_IMM_DATA = (1<<28),
 758         NES_IWARP_SQ_WQE_READ_FENCE = (1<<29),
 759         NES_IWARP_SQ_WQE_LOCAL_FENCE = (1<<30),
 760         NES_IWARP_SQ_WQE_SIGNALED_COMPL = (1<<31),
 761 };
 762
 763 enum nes_iwarp_sq_wqe_bits {
 764         NES_IWARP_SQ_OP_RDMAW = 0,
 765         NES_IWARP_SQ_OP_RDMAR = 1,
 766         NES_IWARP_SQ_OP_SEND = 3,
 767         NES_IWARP_SQ_OP_SENDINV = 4,
 768         NES_IWARP_SQ_OP_SENDSE = 5,
 769         NES_IWARP_SQ_OP_SENDSEINV = 6,
 770         NES_IWARP_SQ_OP_BIND = 8,
 771         NES_IWARP_SQ_OP_FAST_REG = 9,
 772         NES_IWARP_SQ_OP_LOCINV = 10,
 773         NES_IWARP_SQ_OP_RDMAR_LOCINV = 11,
 774         NES_IWARP_SQ_OP_NOP = 12,
 775 };
 776
 777 enum nes_iwarp_cqe_major_code {
 778         NES_IWARP_CQE_MAJOR_FLUSH = 1,
 779         NES_IWARP_CQE_MAJOR_DRV = 0x8000
 780 };
 781
 782 enum nes_iwarp_cqe_minor_code {
 783         NES_IWARP_CQE_MINOR_FLUSH = 1
 784 };
 785
 786 #define NES_EEPROM_READ_REQUEST (1<<16)
 787 #define NES_MAC_ADDR_VALID      (1<<20)
 788
 789 /*
 790  * NES index registers init values.
 791  */
 792 struct nes_init_values {
 793         u32 index;
 794         u32 data;
 795         u8  wrt;
 796 };
 797
 798 /*
 799  * NES registers in BAR0.
 800  */
 801 struct nes_pci_regs {
 802         u32 int_status;
 803         u32 int_mask;
 804         u32 int_pending;
 805         u32 intf_int_status;
 806         u32 intf_int_mask;
 807         u32 other_regs[59];      /* pad out to 256 bytes for now */
 808 };
 809
 810 #define NES_CQP_SQ_SIZE    128
 811 #define NES_CCQ_SIZE       128
 812 #define NES_NIC_WQ_SIZE    512
 813 #define NES_NIC_CTX_SIZE   ((NES_NIC_CTX_RQ_SIZE_512) | (NES_NIC_CTX_SQ_SIZE_512))
 814 #define NES_NIC_BACK_STORE 0x00038000
 815
 816 struct nes_device;
 817
 818 struct nes_hw_nic_qp_context {
 819         __le32 context_words[6];
 820 };
 821
 822 struct nes_hw_nic_sq_wqe {
 823         __le32 wqe_words[16];
 824 };
 825
 826 struct nes_hw_nic_rq_wqe {
 827         __le32 wqe_words[16];
 828 };
 829
 830 struct nes_hw_nic_cqe {
 831         __le32 cqe_words[4];
 832 };
 833
 834 struct nes_hw_cqp_qp_context {
 835         __le32 context_words[4];
 836 };
 837
 838 struct nes_hw_cqp_wqe {
 839         __le32 wqe_words[16];
 840 };
 841
 842 struct nes_hw_qp_wqe {
 843         __le32 wqe_words[32];
 844 };
 845
 846 struct nes_hw_cqe {
 847         __le32 cqe_words[8];
 848 };
 849
 850 struct nes_hw_ceqe {
 851         __le32 ceqe_words[2];
 852 };
 853
 854 struct nes_hw_aeqe {
 855         __le32 aeqe_words[4];
 856 };
 857
 858 struct nes_cqp_request {
 859         union {
 860                 u64 cqp_callback_context;
 861                 void *cqp_callback_pointer;
 862         };
 863         wait_queue_head_t     waitq;
 864         struct nes_hw_cqp_wqe cqp_wqe;
 865         struct list_head      list;
 866         atomic_t              refcount;
 867         void (*cqp_callback)(struct nes_device *nesdev, struct nes_cqp_request *cqp_request);
 868         u16                   major_code;
 869         u16                   minor_code;
 870         u8                    waiting;
 871         u8                    request_done;
 872         u8                    dynamic;
 873         u8                    callback;
 874 };
 875
 876 struct nes_hw_cqp {
 877         struct nes_hw_cqp_wqe *sq_vbase;
 878         dma_addr_t            sq_pbase;
 879         spinlock_t            lock;
 880         wait_queue_head_t     waitq;
 881         u16                   qp_id;
 882         u16                   sq_head;
 883         u16                   sq_tail;
 884         u16                   sq_size;
 885 };
 886
 887 #define NES_FIRST_FRAG_SIZE 128
 888 struct nes_first_frag {
 889         u8 buffer[NES_FIRST_FRAG_SIZE];
 890 };
 891
 892 struct nes_hw_nic {
 893         struct nes_first_frag    *first_frag_vbase;     /* virtual address of first frags */
 894         struct nes_hw_nic_sq_wqe *sq_vbase;                     /* virtual address of sq */
 895         struct nes_hw_nic_rq_wqe *rq_vbase;                     /* virtual address of rq */
 896         struct sk_buff           *tx_skb[NES_NIC_WQ_SIZE];
 897         struct sk_buff           *rx_skb[NES_NIC_WQ_SIZE];
 898         dma_addr_t frag_paddr[NES_NIC_WQ_SIZE];
 899         unsigned long first_frag_overflow[BITS_TO_LONGS(NES_NIC_WQ_SIZE)];
 900         dma_addr_t sq_pbase;                    /* PCI memory for host rings */
 901         dma_addr_t rq_pbase;                    /* PCI memory for host rings */
 902
 903         u16 qp_id;
 904         u16 sq_head;
 905         u16 sq_tail;
 906         u16 sq_size;
 907         u16 rq_head;
 908         u16 rq_tail;
 909         u16 rq_size;
 910         u8 replenishing_rq;
 911         u8 reserved;
 912
 913         spinlock_t rq_lock;
 914 };
 915
 916 struct nes_hw_nic_cq {
 917         struct nes_hw_nic_cqe volatile *cq_vbase;       /* PCI memory for host rings */
 918         void (*ce_handler)(struct nes_device *nesdev, struct nes_hw_nic_cq *cq);
 919         dma_addr_t cq_pbase;    /* PCI memory for host rings */
 920         int rx_cqes_completed;
 921         int cqe_allocs_pending;
 922         int rx_pkts_indicated;
 923         u16 cq_head;
 924         u16 cq_size;
 925         u16 cq_number;
 926         u8  cqes_pending;
 927 };
 928
 929 struct nes_hw_qp {
 930         struct nes_hw_qp_wqe *sq_vbase;         /* PCI memory for host rings */
 931         struct nes_hw_qp_wqe *rq_vbase;         /* PCI memory for host rings */
 932         void                 *q2_vbase;                 /* PCI memory for host rings */
 933         dma_addr_t sq_pbase;    /* PCI memory for host rings */
 934         dma_addr_t rq_pbase;    /* PCI memory for host rings */
 935         dma_addr_t q2_pbase;    /* PCI memory for host rings */
 936         u32 qp_id;
 937         u16 sq_head;
 938         u16 sq_tail;
 939         u16 sq_size;
 940         u16 rq_head;
 941         u16 rq_tail;
 942         u16 rq_size;
 943         u8  rq_encoded_size;
 944         u8  sq_encoded_size;
 945 };
 946
 947 struct nes_hw_cq {
 948         struct nes_hw_cqe *cq_vbase;    /* PCI memory for host rings */
 949         void (*ce_handler)(struct nes_device *nesdev, struct nes_hw_cq *cq);
 950         dma_addr_t cq_pbase;    /* PCI memory for host rings */
 951         u16 cq_head;
 952         u16 cq_size;
 953         u16 cq_number;
 954 };
 955
 956 struct nes_hw_ceq {
 957         struct nes_hw_ceqe volatile *ceq_vbase; /* PCI memory for host rings */
 958         dma_addr_t ceq_pbase;   /* PCI memory for host rings */
 959         u16 ceq_head;
 960         u16 ceq_size;
 961 };
 962
 963 struct nes_hw_aeq {
 964         struct nes_hw_aeqe volatile *aeq_vbase; /* PCI memory for host rings */
 965         dma_addr_t aeq_pbase;   /* PCI memory for host rings */
 966         u16 aeq_head;
 967         u16 aeq_size;
 968 };
 969
 970 struct nic_qp_map {
 971         u8 qpid;
 972         u8 nic_index;
 973         u8 logical_port;
 974         u8 is_hnic;
 975 };
 976
 977 #define NES_CQP_ARP_AEQ_INDEX_MASK  0x000f0000
 978 #define NES_CQP_ARP_AEQ_INDEX_SHIFT 16
 979
 980 #define NES_CQP_APBVT_ADD                       0x00008000
 981 #define NES_CQP_APBVT_NIC_SHIFT         16
 982
 983 #define NES_ARP_ADD     1
 984 #define NES_ARP_DELETE  2
 985 #define NES_ARP_RESOLVE 3
 986
 987 #define NES_MAC_SW_IDLE      0
 988 #define NES_MAC_SW_INTERRUPT 1
 989 #define NES_MAC_SW_MH        2
 990
 991 struct nes_arp_entry {
 992         u32 ip_addr;
 993         u8  mac_addr[ETH_ALEN];
 994 };
 995
 996 #define NES_NIC_FAST_TIMER          96
 997 #define NES_NIC_FAST_TIMER_LOW      40
 998 #define NES_NIC_FAST_TIMER_HIGH     1000
 999 #define DEFAULT_NES_QL_HIGH         256
1000 #define DEFAULT_NES_QL_LOW          16
1001 #define DEFAULT_NES_QL_TARGET       64
1002 #define DEFAULT_JUMBO_NES_QL_LOW    12
1003 #define DEFAULT_JUMBO_NES_QL_TARGET 40
1004 #define DEFAULT_JUMBO_NES_QL_HIGH   128
1005 #define NES_NIC_CQ_DOWNWARD_TREND   16
1006 #define NES_PFT_SIZE                48
1007
1008 struct nes_hw_tune_timer {
1009     /* u16 cq_count; */
1010     u16 threshold_low;
1011     u16 threshold_target;
1012     u16 threshold_high;
1013     u16 timer_in_use;
1014     u16 timer_in_use_old;
1015     u16 timer_in_use_min;
1016     u16 timer_in_use_max;
1017     u8  timer_direction_upward;
1018     u8  timer_direction_downward;
1019     u16 cq_count_old;
1020     u8  cq_direction_downward;
1021 };
1022
1023 #define NES_TIMER_INT_LIMIT         2
1024 #define NES_TIMER_INT_LIMIT_DYNAMIC 10
1025 #define NES_TIMER_ENABLE_LIMIT      4
1026 #define NES_MAX_LINK_INTERRUPTS     128
1027 #define NES_MAX_LINK_CHECK          200
1028 #define NES_MAX_LRO_DESCRIPTORS     32
1029 #define NES_LRO_MAX_AGGR            64
1030
1031 struct nes_adapter {
1032         u64              fw_ver;
1033         unsigned long    *allocated_qps;
1034         unsigned long    *allocated_cqs;
1035         unsigned long    *allocated_mrs;
1036         unsigned long    *allocated_pds;
1037         unsigned long    *allocated_arps;
1038         struct nes_qp    **qp_table;
1039         struct workqueue_struct *work_q;
1040
1041         struct list_head list;
1042         struct list_head active_listeners;
1043         /* list of the netdev's associated with each logical port */
1044         struct list_head nesvnic_list[4];
1045
1046         struct timer_list  mh_timer;
1047         struct timer_list  lc_timer;
1048         struct work_struct work;
1049         spinlock_t         resource_lock;
1050         spinlock_t         phy_lock;
1051         spinlock_t         pbl_lock;
1052         spinlock_t         periodic_timer_lock;
1053
1054         struct nes_arp_entry arp_table[NES_MAX_ARP_TABLE_SIZE];
1055
1056         /* Adapter CEQ and AEQs */
1057         struct nes_hw_ceq ceq[16];
1058         struct nes_hw_aeq aeq[8];
1059
1060         struct nes_hw_tune_timer tune_timer;
1061
1062         unsigned long doorbell_start;
1063
1064         u32 hw_rev;
1065         u32 vendor_id;
1066         u32 vendor_part_id;
1067         u32 device_cap_flags;
1068         u32 tick_delta;
1069         u32 timer_int_req;
1070         u32 arp_table_size;
1071         u32 next_arp_index;
1072
1073         u32 max_mr;
1074         u32 max_256pbl;
1075         u32 max_4kpbl;
1076         u32 free_256pbl;
1077         u32 free_4kpbl;
1078         u32 max_mr_size;
1079         u32 max_qp;
1080         u32 next_qp;
1081         u32 max_irrq;
1082         u32 max_qp_wr;
1083         u32 max_sge;
1084         u32 max_cq;
1085         u32 next_cq;
1086         u32 max_cqe;
1087         u32 max_pd;
1088         u32 base_pd;
1089         u32 next_pd;
1090         u32 hte_index_mask;
1091
1092         /* EEPROM information */
1093         u32 rx_pool_size;
1094         u32 tx_pool_size;
1095         u32 rx_threshold;
1096         u32 tcp_timer_core_clk_divisor;
1097         u32 iwarp_config;
1098         u32 cm_config;
1099         u32 sws_timer_config;
1100         u32 tcp_config1;
1101         u32 wqm_wat;
1102         u32 core_clock;
1103         u32 firmware_version;
1104         u32 eeprom_version;
1105
1106         u32 nic_rx_eth_route_err;
1107
1108         u32 et_rx_coalesce_usecs;
1109         u32 et_rx_max_coalesced_frames;
1110         u32 et_rx_coalesce_usecs_irq;
1111         u32 et_rx_max_coalesced_frames_irq;
1112         u32 et_pkt_rate_low;
1113         u32 et_rx_coalesce_usecs_low;
1114         u32 et_rx_max_coalesced_frames_low;
1115         u32 et_pkt_rate_high;
1116         u32 et_rx_coalesce_usecs_high;
1117         u32 et_rx_max_coalesced_frames_high;
1118         u32 et_rate_sample_interval;
1119         u32 timer_int_limit;
1120         u32 wqm_quanta;
1121
1122         /* Adapter base MAC address */
1123         u32 mac_addr_low;
1124         u16 mac_addr_high;
1125
1126         u16 firmware_eeprom_offset;
1127         u16 software_eeprom_offset;
1128
1129         u16 max_irrq_wr;
1130
1131         /* pd config for each port */
1132         u16 pd_config_size[4];
1133         u16 pd_config_base[4];
1134
1135         u16 link_interrupt_count[4];
1136         u8 crit_error_count[32];
1137
1138         /* the phy index for each port */
1139         u8  phy_index[4];
1140         u8  mac_sw_state[4];
1141         u8  mac_link_down[4];
1142         u8  phy_type[4];
1143         u8  log_port;
1144
1145         /* PCI information */
1146         unsigned int  devfn;
1147         unsigned char bus_number;
1148         unsigned char OneG_Mode;
1149
1150         unsigned char ref_count;
1151         u8            netdev_count;
1152         u8            netdev_max;       /* from host nic address count in EEPROM */
1153         u8            port_count;
1154         u8            virtwq;
1155         u8            send_term_ok;
1156         u8            et_use_adaptive_rx_coalesce;
1157         u8            adapter_fcn_count;
1158         u8 pft_mcast_map[NES_PFT_SIZE];
1159 };
1160
1161 struct nes_pbl {
1162         u64              *pbl_vbase;
1163         dma_addr_t       pbl_pbase;
1164         struct page      *page;
1165         unsigned long    user_base;
1166         u32              pbl_size;
1167         struct list_head list;
1168         /* TODO: need to add list for two level tables */
1169 };
1170
1171 #define NES_4K_PBL_CHUNK_SIZE   4096
1172
1173 struct nes_fast_mr_wqe_pbl {
1174         u64             *kva;
1175         dma_addr_t      paddr;
1176 };
1177
1178 struct nes_ib_fast_reg_page_list {
1179         struct ib_fast_reg_page_list    ibfrpl;
1180         struct nes_fast_mr_wqe_pbl      nes_wqe_pbl;
1181         u64                             pbl;
1182 };
1183
1184 struct nes_listener {
1185         struct work_struct      work;
1186         struct workqueue_struct *wq;
1187         struct nes_vnic         *nesvnic;
1188         struct iw_cm_id         *cm_id;
1189         struct list_head        list;
1190         unsigned long           socket;
1191         u8                      accept_failed;
1192 };
1193
1194 struct nes_ib_device;
1195
1196 #define NES_EVENT_DELAY msecs_to_jiffies(100)
1197
1198 struct nes_vnic {
1199         struct nes_ib_device *nesibdev;
1200         u64 sq_full;
1201         u64 tso_requests;
1202         u64 segmented_tso_requests;
1203         u64 linearized_skbs;
1204         u64 tx_sw_dropped;
1205         u64 endnode_nstat_rx_discard;
1206         u64 endnode_nstat_rx_octets;
1207         u64 endnode_nstat_rx_frames;
1208         u64 endnode_nstat_tx_octets;
1209         u64 endnode_nstat_tx_frames;
1210         u64 endnode_ipv4_tcp_retransmits;
1211         /* void *mem; */
1212         struct nes_device *nesdev;
1213         struct net_device *netdev;
1214         atomic_t          rx_skbs_needed;
1215         atomic_t          rx_skb_timer_running;
1216         int               budget;
1217         u32               msg_enable;
1218         /* u32 tx_avail; */
1219         __be32            local_ipaddr;
1220         struct napi_struct   napi;
1221         spinlock_t           tx_lock;   /* could use netdev tx lock? */
1222         struct timer_list    rq_wqes_timer;
1223         u32                  nic_mem_size;
1224         void                 *nic_vbase;
1225         dma_addr_t           nic_pbase;
1226         struct nes_hw_nic    nic;
1227         struct nes_hw_nic_cq nic_cq;
1228         u32    mcrq_qp_id;
1229         struct nes_ucontext *mcrq_ucontext;
1230         struct nes_cqp_request* (*get_cqp_request)(struct nes_device *nesdev);
1231         void (*post_cqp_request)(struct nes_device*, struct nes_cqp_request *);
1232         int (*mcrq_mcast_filter)( struct nes_vnic* nesvnic, __u8* dmi_addr );
1233         struct net_device_stats netstats;
1234         /* used to put the netdev on the adapters logical port list */
1235         struct list_head list;
1236         u16 max_frame_size;
1237         u8  netdev_open;
1238         u8  linkup;
1239         u8  logical_port;
1240         u8  netdev_index;  /* might not be needed, indexes nesdev->netdev */
1241         u8  perfect_filter_index;
1242         u8  nic_index;
1243         u8  qp_nic_index[4];
1244         u8  next_qp_nic_index;
1245         u8  of_device_registered;
1246         u8  rdma_enabled;
1247         u32 lro_max_aggr;
1248         struct net_lro_mgr lro_mgr;
1249         struct net_lro_desc lro_desc[NES_MAX_LRO_DESCRIPTORS];
1250         struct timer_list event_timer;
1251         enum ib_event_type delayed_event;
1252         enum ib_event_type last_dispatched_event;
1253         spinlock_t port_ibevent_lock;
1254 };
1255
1256 struct nes_ib_device {
1257         struct ib_device ibdev;
1258         struct nes_vnic *nesvnic;
1259
1260         /* Virtual RNIC Limits */
1261         u32 max_mr;
1262         u32 max_qp;
1263         u32 max_cq;
1264         u32 max_pd;
1265         u32 num_mr;
1266         u32 num_qp;
1267         u32 num_cq;
1268         u32 num_pd;
1269 };
1270
1271 enum nes_hdrct_flags {
1272         DDP_LEN_FLAG                    = 0x80,
1273         DDP_HDR_FLAG                    = 0x40,
1274         RDMA_HDR_FLAG                   = 0x20
1275 };
1276
1277 enum nes_term_layers {
1278         LAYER_RDMA                      = 0,
1279         LAYER_DDP                       = 1,
1280         LAYER_MPA                       = 2
1281 };
1282
1283 enum nes_term_error_types {
1284         RDMAP_CATASTROPHIC              = 0,
1285         RDMAP_REMOTE_PROT               = 1,
1286         RDMAP_REMOTE_OP                 = 2,
1287         DDP_CATASTROPHIC                = 0,
1288         DDP_TAGGED_BUFFER               = 1,
1289         DDP_UNTAGGED_BUFFER             = 2,
1290         DDP_LLP                         = 3
1291 };
1292
1293 enum nes_term_rdma_errors {
1294         RDMAP_INV_STAG                  = 0x00,
1295         RDMAP_INV_BOUNDS                = 0x01,
1296         RDMAP_ACCESS                    = 0x02,
1297         RDMAP_UNASSOC_STAG              = 0x03,
1298         RDMAP_TO_WRAP                   = 0x04,
1299         RDMAP_INV_RDMAP_VER             = 0x05,
1300         RDMAP_UNEXPECTED_OP             = 0x06,
1301         RDMAP_CATASTROPHIC_LOCAL        = 0x07,
1302         RDMAP_CATASTROPHIC_GLOBAL       = 0x08,
1303         RDMAP_CANT_INV_STAG             = 0x09,
1304         RDMAP_UNSPECIFIED               = 0xff
1305 };
1306
1307 enum nes_term_ddp_errors {
1308         DDP_CATASTROPHIC_LOCAL          = 0x00,
1309         DDP_TAGGED_INV_STAG             = 0x00,
1310         DDP_TAGGED_BOUNDS               = 0x01,
1311         DDP_TAGGED_UNASSOC_STAG         = 0x02,
1312         DDP_TAGGED_TO_WRAP              = 0x03,
1313         DDP_TAGGED_INV_DDP_VER          = 0x04,
1314         DDP_UNTAGGED_INV_QN             = 0x01,
1315         DDP_UNTAGGED_INV_MSN_NO_BUF     = 0x02,
1316         DDP_UNTAGGED_INV_MSN_RANGE      = 0x03,
1317         DDP_UNTAGGED_INV_MO             = 0x04,
1318         DDP_UNTAGGED_INV_TOO_LONG       = 0x05,
1319         DDP_UNTAGGED_INV_DDP_VER        = 0x06
1320 };
1321
1322 enum nes_term_mpa_errors {
1323         MPA_CLOSED                      = 0x01,
1324         MPA_CRC                         = 0x02,
1325         MPA_MARKER                      = 0x03,
1326         MPA_REQ_RSP                     = 0x04,
1327 };
1328
1329 struct nes_terminate_hdr {
1330         u8 layer_etype;
1331         u8 error_code;
1332         u8 hdrct;
1333         u8 rsvd;
1334 };
1335
1336 /* Used to determine how to fill in terminate error codes */
1337 #define IWARP_OPCODE_WRITE              0
1338 #define IWARP_OPCODE_READREQ            1
1339 #define IWARP_OPCODE_READRSP            2
1340 #define IWARP_OPCODE_SEND               3
1341 #define IWARP_OPCODE_SEND_INV           4
1342 #define IWARP_OPCODE_SEND_SE            5
1343 #define IWARP_OPCODE_SEND_SE_INV        6
1344 #define IWARP_OPCODE_TERM               7
1345
1346 /* These values are used only during terminate processing */
1347 #define TERM_DDP_LEN_TAGGED     14
1348 #define TERM_DDP_LEN_UNTAGGED   18
1349 #define TERM_RDMA_LEN           28
1350 #define RDMA_OPCODE_MASK        0x0f
1351 #define RDMA_READ_REQ_OPCODE    1
1352 #define BAD_FRAME_OFFSET        64
1353 #define CQE_MAJOR_DRV           0x8000
1354
1355 /* Used for link status recheck after interrupt processing */
1356 #define NES_LINK_RECHECK_DELAY  msecs_to_jiffies(50)
1357 #define NES_LINK_RECHECK_MAX    60
1358
1359 #endif          /* __NES_HW_H */