drivers/infiniband/hw/mthca/mthca_qp.c

   1 /*
   2  * Copyright (c) 2004 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Cisco Systems. All rights reserved.
   4  * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
   5  * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * OpenIB.org BSD license below:
  12  *
  13  *     Redistribution and use in source and binary forms, with or
  14  *     without modification, are permitted provided that the following
  15  *     conditions are met:
  16  *
  17  *      - Redistributions of source code must retain the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer.
  20  *
  21  *      - Redistributions in binary form must reproduce the above
  22  *        copyright notice, this list of conditions and the following
  23  *        disclaimer in the documentation and/or other materials
  24  *        provided with the distribution.
  25  *
  26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33  * SOFTWARE.
  34  *
  35  * $Id: mthca_qp.c 1355 2004-12-17 15:23:43Z roland $
  36  */
  37
  38 #include <linux/string.h>
  39 #include <linux/slab.h>
  40
  41 #include <asm/io.h>
  42
  43 #include <rdma/ib_verbs.h>
  44 #include <rdma/ib_cache.h>
  45 #include <rdma/ib_pack.h>
  46
  47 #include "mthca_dev.h"
  48 #include "mthca_cmd.h"
  49 #include "mthca_memfree.h"
  50 #include "mthca_wqe.h"
  51
  52 enum {
  53         MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE,
  54         MTHCA_ACK_REQ_FREQ       = 10,
  55         MTHCA_FLIGHT_LIMIT       = 9,
  56         MTHCA_UD_HEADER_SIZE     = 72, /* largest UD header possible */
  57         MTHCA_INLINE_HEADER_SIZE = 4,  /* data segment overhead for inline */
  58         MTHCA_INLINE_CHUNK_SIZE  = 16  /* inline data segment chunk */
  59 };
  60
  61 enum {
  62         MTHCA_QP_STATE_RST  = 0,
  63         MTHCA_QP_STATE_INIT = 1,
  64         MTHCA_QP_STATE_RTR  = 2,
  65         MTHCA_QP_STATE_RTS  = 3,
  66         MTHCA_QP_STATE_SQE  = 4,
  67         MTHCA_QP_STATE_SQD  = 5,
  68         MTHCA_QP_STATE_ERR  = 6,
  69         MTHCA_QP_STATE_DRAINING = 7
  70 };
  71
  72 enum {
  73         MTHCA_QP_ST_RC  = 0x0,
  74         MTHCA_QP_ST_UC  = 0x1,
  75         MTHCA_QP_ST_RD  = 0x2,
  76         MTHCA_QP_ST_UD  = 0x3,
  77         MTHCA_QP_ST_MLX = 0x7
  78 };
  79
  80 enum {
  81         MTHCA_QP_PM_MIGRATED = 0x3,
  82         MTHCA_QP_PM_ARMED    = 0x0,
  83         MTHCA_QP_PM_REARM    = 0x1
  84 };
  85
  86 enum {
  87         /* qp_context flags */
  88         MTHCA_QP_BIT_DE  = 1 <<  8,
  89         /* params1 */
  90         MTHCA_QP_BIT_SRE = 1 << 15,
  91         MTHCA_QP_BIT_SWE = 1 << 14,
  92         MTHCA_QP_BIT_SAE = 1 << 13,
  93         MTHCA_QP_BIT_SIC = 1 <<  4,
  94         MTHCA_QP_BIT_SSC = 1 <<  3,
  95         /* params2 */
  96         MTHCA_QP_BIT_RRE = 1 << 15,
  97         MTHCA_QP_BIT_RWE = 1 << 14,
  98         MTHCA_QP_BIT_RAE = 1 << 13,
  99         MTHCA_QP_BIT_RIC = 1 <<  4,
 100         MTHCA_QP_BIT_RSC = 1 <<  3
 101 };
 102
 103 enum {
 104         MTHCA_SEND_DOORBELL_FENCE = 1 << 5
 105 };
 106
 107 struct mthca_qp_path {
 108         __be32 port_pkey;
 109         u8     rnr_retry;
 110         u8     g_mylmc;
 111         __be16 rlid;
 112         u8     ackto;
 113         u8     mgid_index;
 114         u8     static_rate;
 115         u8     hop_limit;
 116         __be32 sl_tclass_flowlabel;
 117         u8     rgid[16];
 118 } __attribute__((packed));
 119
 120 struct mthca_qp_context {
 121         __be32 flags;
 122         __be32 tavor_sched_queue; /* Reserved on Arbel */
 123         u8     mtu_msgmax;
 124         u8     rq_size_stride;  /* Reserved on Tavor */
 125         u8     sq_size_stride;  /* Reserved on Tavor */
 126         u8     rlkey_arbel_sched_queue; /* Reserved on Tavor */
 127         __be32 usr_page;
 128         __be32 local_qpn;
 129         __be32 remote_qpn;
 130         u32    reserved1[2];
 131         struct mthca_qp_path pri_path;
 132         struct mthca_qp_path alt_path;
 133         __be32 rdd;
 134         __be32 pd;
 135         __be32 wqe_base;
 136         __be32 wqe_lkey;
 137         __be32 params1;
 138         __be32 reserved2;
 139         __be32 next_send_psn;
 140         __be32 cqn_snd;
 141         __be32 snd_wqe_base_l;  /* Next send WQE on Tavor */
 142         __be32 snd_db_index;    /* (debugging only entries) */
 143         __be32 last_acked_psn;
 144         __be32 ssn;
 145         __be32 params2;
 146         __be32 rnr_nextrecvpsn;
 147         __be32 ra_buff_indx;
 148         __be32 cqn_rcv;
 149         __be32 rcv_wqe_base_l;  /* Next recv WQE on Tavor */
 150         __be32 rcv_db_index;    /* (debugging only entries) */
 151         __be32 qkey;
 152         __be32 srqn;
 153         __be32 rmsn;
 154         __be16 rq_wqe_counter;  /* reserved on Tavor */
 155         __be16 sq_wqe_counter;  /* reserved on Tavor */
 156         u32    reserved3[18];
 157 } __attribute__((packed));
 158
 159 struct mthca_qp_param {
 160         __be32 opt_param_mask;
 161         u32    reserved1;
 162         struct mthca_qp_context context;
 163         u32    reserved2[62];
 164 } __attribute__((packed));
 165
 166 enum {
 167         MTHCA_QP_OPTPAR_ALT_ADDR_PATH     = 1 << 0,
 168         MTHCA_QP_OPTPAR_RRE               = 1 << 1,
 169         MTHCA_QP_OPTPAR_RAE               = 1 << 2,
 170         MTHCA_QP_OPTPAR_RWE               = 1 << 3,
 171         MTHCA_QP_OPTPAR_PKEY_INDEX        = 1 << 4,
 172         MTHCA_QP_OPTPAR_Q_KEY             = 1 << 5,
 173         MTHCA_QP_OPTPAR_RNR_TIMEOUT       = 1 << 6,
 174         MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
 175         MTHCA_QP_OPTPAR_SRA_MAX           = 1 << 8,
 176         MTHCA_QP_OPTPAR_RRA_MAX           = 1 << 9,
 177         MTHCA_QP_OPTPAR_PM_STATE          = 1 << 10,
 178         MTHCA_QP_OPTPAR_PORT_NUM          = 1 << 11,
 179         MTHCA_QP_OPTPAR_RETRY_COUNT       = 1 << 12,
 180         MTHCA_QP_OPTPAR_ALT_RNR_RETRY     = 1 << 13,
 181         MTHCA_QP_OPTPAR_ACK_TIMEOUT       = 1 << 14,
 182         MTHCA_QP_OPTPAR_RNR_RETRY         = 1 << 15,
 183         MTHCA_QP_OPTPAR_SCHED_QUEUE       = 1 << 16
 184 };
 185
 186 static const u8 mthca_opcode[] = {
 187         [IB_WR_SEND]                 = MTHCA_OPCODE_SEND,
 188         [IB_WR_SEND_WITH_IMM]        = MTHCA_OPCODE_SEND_IMM,
 189         [IB_WR_RDMA_WRITE]           = MTHCA_OPCODE_RDMA_WRITE,
 190         [IB_WR_RDMA_WRITE_WITH_IMM]  = MTHCA_OPCODE_RDMA_WRITE_IMM,
 191         [IB_WR_RDMA_READ]            = MTHCA_OPCODE_RDMA_READ,
 192         [IB_WR_ATOMIC_CMP_AND_SWP]   = MTHCA_OPCODE_ATOMIC_CS,
 193         [IB_WR_ATOMIC_FETCH_AND_ADD] = MTHCA_OPCODE_ATOMIC_FA,
 194 };
 195
 196 static int is_sqp(struct mthca_dev *dev, struct mthca_qp *qp)
 197 {
 198         return qp->qpn >= dev->qp_table.sqp_start &&
 199                 qp->qpn <= dev->qp_table.sqp_start + 3;
 200 }
 201
 202 static int is_qp0(struct mthca_dev *dev, struct mthca_qp *qp)
 203 {
 204         return qp->qpn >= dev->qp_table.sqp_start &&
 205                 qp->qpn <= dev->qp_table.sqp_start + 1;
 206 }
 207
 208 static void *get_recv_wqe(struct mthca_qp *qp, int n)
 209 {
 210         if (qp->is_direct)
 211                 return qp->queue.direct.buf + (n << qp->rq.wqe_shift);
 212         else
 213                 return qp->queue.page_list[(n << qp->rq.wqe_shift) >> PAGE_SHIFT].buf +
 214                         ((n << qp->rq.wqe_shift) & (PAGE_SIZE - 1));
 215 }
 216
 217 static void *get_send_wqe(struct mthca_qp *qp, int n)
 218 {
 219         if (qp->is_direct)
 220                 return qp->queue.direct.buf + qp->send_wqe_offset +
 221                         (n << qp->sq.wqe_shift);
 222         else
 223                 return qp->queue.page_list[(qp->send_wqe_offset +
 224                                             (n << qp->sq.wqe_shift)) >>
 225                                            PAGE_SHIFT].buf +
 226                         ((qp->send_wqe_offset + (n << qp->sq.wqe_shift)) &
 227                          (PAGE_SIZE - 1));
 228 }
 229
 230 static void mthca_wq_reset(struct mthca_wq *wq)
 231 {
 232         wq->next_ind  = 0;
 233         wq->last_comp = wq->max - 1;
 234         wq->head      = 0;
 235         wq->tail      = 0;
 236 }
 237
 238 void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
 239                     enum ib_event_type event_type)
 240 {
 241         struct mthca_qp *qp;
 242         struct ib_event event;
 243
 244         spin_lock(&dev->qp_table.lock);
 245         qp = mthca_array_get(&dev->qp_table.qp, qpn & (dev->limits.num_qps - 1));
 246         if (qp)
 247                 ++qp->refcount;
 248         spin_unlock(&dev->qp_table.lock);
 249
 250         if (!qp) {
 251                 mthca_warn(dev, "Async event for bogus QP %08x\n", qpn);
 252                 return;
 253         }
 254
 255         if (event_type == IB_EVENT_PATH_MIG)
 256                 qp->port = qp->alt_port;
 257
 258         event.device      = &dev->ib_dev;
 259         event.event       = event_type;
 260         event.element.qp  = &qp->ibqp;
 261         if (qp->ibqp.event_handler)
 262                 qp->ibqp.event_handler(&event, qp->ibqp.qp_context);
 263
 264         spin_lock(&dev->qp_table.lock);
 265         if (!--qp->refcount)
 266                 wake_up(&qp->wait);
 267         spin_unlock(&dev->qp_table.lock);
 268 }
 269
 270 static int to_mthca_state(enum ib_qp_state ib_state)
 271 {
 272         switch (ib_state) {
 273         case IB_QPS_RESET: return MTHCA_QP_STATE_RST;
 274         case IB_QPS_INIT:  return MTHCA_QP_STATE_INIT;
 275         case IB_QPS_RTR:   return MTHCA_QP_STATE_RTR;
 276         case IB_QPS_RTS:   return MTHCA_QP_STATE_RTS;
 277         case IB_QPS_SQD:   return MTHCA_QP_STATE_SQD;
 278         case IB_QPS_SQE:   return MTHCA_QP_STATE_SQE;
 279         case IB_QPS_ERR:   return MTHCA_QP_STATE_ERR;
 280         default:                return -1;
 281         }
 282 }
 283
 284 enum { RC, UC, UD, RD, RDEE, MLX, NUM_TRANS };
 285
 286 static int to_mthca_st(int transport)
 287 {
 288         switch (transport) {
 289         case RC:  return MTHCA_QP_ST_RC;
 290         case UC:  return MTHCA_QP_ST_UC;
 291         case UD:  return MTHCA_QP_ST_UD;
 292         case RD:  return MTHCA_QP_ST_RD;
 293         case MLX: return MTHCA_QP_ST_MLX;
 294         default:  return -1;
 295         }
 296 }
 297
 298 static void store_attrs(struct mthca_sqp *sqp, struct ib_qp_attr *attr,
 299                         int attr_mask)
 300 {
 301         if (attr_mask & IB_QP_PKEY_INDEX)
 302                 sqp->pkey_index = attr->pkey_index;
 303         if (attr_mask & IB_QP_QKEY)
 304                 sqp->qkey = attr->qkey;
 305         if (attr_mask & IB_QP_SQ_PSN)
 306                 sqp->send_psn = attr->sq_psn;
 307 }
 308
 309 static void init_port(struct mthca_dev *dev, int port)
 310 {
 311         int err;
 312         u8 status;
 313         struct mthca_init_ib_param param;
 314
 315         memset(&param, 0, sizeof param);
 316
 317         param.port_width = dev->limits.port_width_cap;
 318         param.vl_cap     = dev->limits.vl_cap;
 319         param.mtu_cap    = dev->limits.mtu_cap;
 320         param.gid_cap    = dev->limits.gid_table_len;
 321         param.pkey_cap   = dev->limits.pkey_table_len;
 322
 323         err = mthca_INIT_IB(dev, &param, port, &status);
 324         if (err)
 325                 mthca_warn(dev, "INIT_IB failed, return code %d.\n", err);
 326         if (status)
 327                 mthca_warn(dev, "INIT_IB returned status %02x.\n", status);
 328 }
 329
 330 static __be32 get_hw_access_flags(struct mthca_qp *qp, struct ib_qp_attr *attr,
 331                                   int attr_mask)
 332 {
 333         u8 dest_rd_atomic;
 334         u32 access_flags;
 335         u32 hw_access_flags = 0;
 336
 337         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
 338                 dest_rd_atomic = attr->max_dest_rd_atomic;
 339         else
 340                 dest_rd_atomic = qp->resp_depth;
 341
 342         if (attr_mask & IB_QP_ACCESS_FLAGS)
 343                 access_flags = attr->qp_access_flags;
 344         else
 345                 access_flags = qp->atomic_rd_en;
 346
 347         if (!dest_rd_atomic)
 348                 access_flags &= IB_ACCESS_REMOTE_WRITE;
 349
 350         if (access_flags & IB_ACCESS_REMOTE_READ)
 351                 hw_access_flags |= MTHCA_QP_BIT_RRE;
 352         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
 353                 hw_access_flags |= MTHCA_QP_BIT_RAE;
 354         if (access_flags & IB_ACCESS_REMOTE_WRITE)
 355                 hw_access_flags |= MTHCA_QP_BIT_RWE;
 356
 357         return cpu_to_be32(hw_access_flags);
 358 }
 359
 360 static inline enum ib_qp_state to_ib_qp_state(int mthca_state)
 361 {
 362         switch (mthca_state) {
 363         case MTHCA_QP_STATE_RST:      return IB_QPS_RESET;
 364         case MTHCA_QP_STATE_INIT:     return IB_QPS_INIT;
 365         case MTHCA_QP_STATE_RTR:      return IB_QPS_RTR;
 366         case MTHCA_QP_STATE_RTS:      return IB_QPS_RTS;
 367         case MTHCA_QP_STATE_DRAINING:
 368         case MTHCA_QP_STATE_SQD:      return IB_QPS_SQD;
 369         case MTHCA_QP_STATE_SQE:      return IB_QPS_SQE;
 370         case MTHCA_QP_STATE_ERR:      return IB_QPS_ERR;
 371         default:                      return -1;
 372         }
 373 }
 374
 375 static inline enum ib_mig_state to_ib_mig_state(int mthca_mig_state)
 376 {
 377         switch (mthca_mig_state) {
 378         case 0:  return IB_MIG_ARMED;
 379         case 1:  return IB_MIG_REARM;
 380         case 3:  return IB_MIG_MIGRATED;
 381         default: return -1;
 382         }
 383 }
 384
 385 static int to_ib_qp_access_flags(int mthca_flags)
 386 {
 387         int ib_flags = 0;
 388
 389         if (mthca_flags & MTHCA_QP_BIT_RRE)
 390                 ib_flags |= IB_ACCESS_REMOTE_READ;
 391         if (mthca_flags & MTHCA_QP_BIT_RWE)
 392                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
 393         if (mthca_flags & MTHCA_QP_BIT_RAE)
 394                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
 395
 396         return ib_flags;
 397 }
 398
 399 static void to_ib_ah_attr(struct mthca_dev *dev, struct ib_ah_attr *ib_ah_attr,
 400                                 struct mthca_qp_path *path)
 401 {
 402         memset(ib_ah_attr, 0, sizeof *path);
 403         ib_ah_attr->port_num      = (be32_to_cpu(path->port_pkey) >> 24) & 0x3;
 404
 405         if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->limits.num_ports)
 406                 return;
 407
 408         ib_ah_attr->dlid          = be16_to_cpu(path->rlid);
 409         ib_ah_attr->sl            = be32_to_cpu(path->sl_tclass_flowlabel) >> 28;
 410         ib_ah_attr->src_path_bits = path->g_mylmc & 0x7f;
 411         ib_ah_attr->static_rate   = mthca_rate_to_ib(dev,
 412                                                      path->static_rate & 0xf,
 413                                                      ib_ah_attr->port_num);
 414         ib_ah_attr->ah_flags      = (path->g_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
 415         if (ib_ah_attr->ah_flags) {
 416                 ib_ah_attr->grh.sgid_index = path->mgid_index & (dev->limits.gid_table_len - 1);
 417                 ib_ah_attr->grh.hop_limit  = path->hop_limit;
 418                 ib_ah_attr->grh.traffic_class =
 419                         (be32_to_cpu(path->sl_tclass_flowlabel) >> 20) & 0xff;
 420                 ib_ah_attr->grh.flow_label =
 421                         be32_to_cpu(path->sl_tclass_flowlabel) & 0xfffff;
 422                 memcpy(ib_ah_attr->grh.dgid.raw,
 423                         path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
 424         }
 425 }
 426
 427 int mthca_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
 428                    struct ib_qp_init_attr *qp_init_attr)
 429 {
 430         struct mthca_dev *dev = to_mdev(ibqp->device);
 431         struct mthca_qp *qp = to_mqp(ibqp);
 432         int err;
 433         struct mthca_mailbox *mailbox;
 434         struct mthca_qp_param *qp_param;
 435         struct mthca_qp_context *context;
 436         int mthca_state;
 437         u8 status;
 438
 439         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 440         if (IS_ERR(mailbox))
 441                 return PTR_ERR(mailbox);
 442
 443         err = mthca_QUERY_QP(dev, qp->qpn, 0, mailbox, &status);
 444         if (err)
 445                 goto out;
 446         if (status) {
 447                 mthca_warn(dev, "QUERY_QP returned status %02x\n", status);
 448                 err = -EINVAL;
 449                 goto out;
 450         }
 451
 452         qp_param    = mailbox->buf;
 453         context     = &qp_param->context;
 454         mthca_state = be32_to_cpu(context->flags) >> 28;
 455
 456         qp_attr->qp_state            = to_ib_qp_state(mthca_state);
 457         qp_attr->cur_qp_state        = qp_attr->qp_state;
 458         qp_attr->path_mtu            = context->mtu_msgmax >> 5;
 459         qp_attr->path_mig_state      =
 460                 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
 461         qp_attr->qkey                = be32_to_cpu(context->qkey);
 462         qp_attr->rq_psn              = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
 463         qp_attr->sq_psn              = be32_to_cpu(context->next_send_psn) & 0xffffff;
 464         qp_attr->dest_qp_num         = be32_to_cpu(context->remote_qpn) & 0xffffff;
 465         qp_attr->qp_access_flags     =
 466                 to_ib_qp_access_flags(be32_to_cpu(context->params2));
 467         qp_attr->cap.max_send_wr     = qp->sq.max;
 468         qp_attr->cap.max_recv_wr     = qp->rq.max;
 469         qp_attr->cap.max_send_sge    = qp->sq.max_gs;
 470         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
 471         qp_attr->cap.max_inline_data = qp->max_inline_data;
 472
 473         if (qp->transport == RC || qp->transport == UC) {
 474                 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
 475                 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
 476                 qp_attr->alt_pkey_index =
 477                         be32_to_cpu(context->alt_path.port_pkey) & 0x7f;
 478                 qp_attr->alt_port_num   = qp_attr->alt_ah_attr.port_num;
 479         }
 480
 481         qp_attr->pkey_index = be32_to_cpu(context->pri_path.port_pkey) & 0x7f;
 482         qp_attr->port_num   =
 483                 (be32_to_cpu(context->pri_path.port_pkey) >> 24) & 0x3;
 484
 485         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
 486         qp_attr->sq_draining = mthca_state == MTHCA_QP_STATE_DRAINING;
 487
 488         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
 489
 490         qp_attr->max_dest_rd_atomic =
 491                 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
 492         qp_attr->min_rnr_timer      =
 493                 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
 494         qp_attr->timeout            = context->pri_path.ackto >> 3;
 495         qp_attr->retry_cnt          = (be32_to_cpu(context->params1) >> 16) & 0x7;
 496         qp_attr->rnr_retry          = context->pri_path.rnr_retry >> 5;
 497         qp_attr->alt_timeout        = context->alt_path.ackto >> 3;
 498         qp_init_attr->cap           = qp_attr->cap;
 499
 500 out:
 501         mthca_free_mailbox(dev, mailbox);
 502         return err;
 503 }
 504
 505 static int mthca_path_set(struct mthca_dev *dev, struct ib_ah_attr *ah,
 506                           struct mthca_qp_path *path, u8 port)
 507 {
 508         path->g_mylmc     = ah->src_path_bits & 0x7f;
 509         path->rlid        = cpu_to_be16(ah->dlid);
 510         path->static_rate = mthca_get_rate(dev, ah->static_rate, port);
 511
 512         if (ah->ah_flags & IB_AH_GRH) {
 513                 if (ah->grh.sgid_index >= dev->limits.gid_table_len) {
 514                         mthca_dbg(dev, "sgid_index (%u) too large. max is %d\n",
 515                                   ah->grh.sgid_index, dev->limits.gid_table_len-1);
 516                         return -1;
 517                 }
 518
 519                 path->g_mylmc   |= 1 << 7;
 520                 path->mgid_index = ah->grh.sgid_index;
 521                 path->hop_limit  = ah->grh.hop_limit;
 522                 path->sl_tclass_flowlabel =
 523                         cpu_to_be32((ah->sl << 28)                |
 524                                     (ah->grh.traffic_class << 20) |
 525                                     (ah->grh.flow_label));
 526                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
 527         } else
 528                 path->sl_tclass_flowlabel = cpu_to_be32(ah->sl << 28);
 529
 530         return 0;
 531 }
 532
 533 int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask,
 534                     struct ib_udata *udata)
 535 {
 536         struct mthca_dev *dev = to_mdev(ibqp->device);
 537         struct mthca_qp *qp = to_mqp(ibqp);
 538         enum ib_qp_state cur_state, new_state;
 539         struct mthca_mailbox *mailbox;
 540         struct mthca_qp_param *qp_param;
 541         struct mthca_qp_context *qp_context;
 542         u32 sqd_event = 0;
 543         u8 status;
 544         int err = -EINVAL;
 545
 546         mutex_lock(&qp->mutex);
 547
 548         if (attr_mask & IB_QP_CUR_STATE) {
 549                 cur_state = attr->cur_qp_state;
 550         } else {
 551                 spin_lock_irq(&qp->sq.lock);
 552                 spin_lock(&qp->rq.lock);
 553                 cur_state = qp->state;
 554                 spin_unlock(&qp->rq.lock);
 555                 spin_unlock_irq(&qp->sq.lock);
 556         }
 557
 558         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
 559
 560         if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask)) {
 561                 mthca_dbg(dev, "Bad QP transition (transport %d) "
 562                           "%d->%d with attr 0x%08x\n",
 563                           qp->transport, cur_state, new_state,
 564                           attr_mask);
 565                 goto out;
 566         }
 567
 568         if ((attr_mask & IB_QP_PKEY_INDEX) &&
 569              attr->pkey_index >= dev->limits.pkey_table_len) {
 570                 mthca_dbg(dev, "P_Key index (%u) too large. max is %d\n",
 571                           attr->pkey_index, dev->limits.pkey_table_len-1);
 572                 goto out;
 573         }
 574
 575         if ((attr_mask & IB_QP_PORT) &&
 576             (attr->port_num == 0 || attr->port_num > dev->limits.num_ports)) {
 577                 mthca_dbg(dev, "Port number (%u) is invalid\n", attr->port_num);
 578                 goto out;
 579         }
 580
 581         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
 582             attr->max_rd_atomic > dev->limits.max_qp_init_rdma) {
 583                 mthca_dbg(dev, "Max rdma_atomic as initiator %u too large (max is %d)\n",
 584                           attr->max_rd_atomic, dev->limits.max_qp_init_rdma);
 585                 goto out;
 586         }
 587
 588         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
 589             attr->max_dest_rd_atomic > 1 << dev->qp_table.rdb_shift) {
 590                 mthca_dbg(dev, "Max rdma_atomic as responder %u too large (max %d)\n",
 591                           attr->max_dest_rd_atomic, 1 << dev->qp_table.rdb_shift);
 592                 goto out;
 593         }
 594
 595         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 596         if (IS_ERR(mailbox)) {
 597                 err = PTR_ERR(mailbox);
 598                 goto out;
 599         }
 600         qp_param = mailbox->buf;
 601         qp_context = &qp_param->context;
 602         memset(qp_param, 0, sizeof *qp_param);
 603
 604         qp_context->flags      = cpu_to_be32((to_mthca_state(new_state) << 28) |
 605                                              (to_mthca_st(qp->transport) << 16));
 606         qp_context->flags     |= cpu_to_be32(MTHCA_QP_BIT_DE);
 607         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
 608                 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 609         else {
 610                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE);
 611                 switch (attr->path_mig_state) {
 612                 case IB_MIG_MIGRATED:
 613                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 614                         break;
 615                 case IB_MIG_REARM:
 616                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_REARM << 11);
 617                         break;
 618                 case IB_MIG_ARMED:
 619                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_ARMED << 11);
 620                         break;
 621                 }
 622         }
 623
 624         /* leave tavor_sched_queue as 0 */
 625
 626         if (qp->transport == MLX || qp->transport == UD)
 627                 qp_context->mtu_msgmax = (IB_MTU_2048 << 5) | 11;
 628         else if (attr_mask & IB_QP_PATH_MTU) {
 629                 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_2048) {
 630                         mthca_dbg(dev, "path MTU (%u) is invalid\n",
 631                                   attr->path_mtu);
 632                         goto out_mailbox;
 633                 }
 634                 qp_context->mtu_msgmax = (attr->path_mtu << 5) | 31;
 635         }
 636
 637         if (mthca_is_memfree(dev)) {
 638                 if (qp->rq.max)
 639                         qp_context->rq_size_stride = ilog2(qp->rq.max) << 3;
 640                 qp_context->rq_size_stride |= qp->rq.wqe_shift - 4;
 641
 642                 if (qp->sq.max)
 643                         qp_context->sq_size_stride = ilog2(qp->sq.max) << 3;
 644                 qp_context->sq_size_stride |= qp->sq.wqe_shift - 4;
 645         }
 646
 647         /* leave arbel_sched_queue as 0 */
 648
 649         if (qp->ibqp.uobject)
 650                 qp_context->usr_page =
 651                         cpu_to_be32(to_mucontext(qp->ibqp.uobject->context)->uar.index);
 652         else
 653                 qp_context->usr_page = cpu_to_be32(dev->driver_uar.index);
 654         qp_context->local_qpn  = cpu_to_be32(qp->qpn);
 655         if (attr_mask & IB_QP_DEST_QPN) {
 656                 qp_context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
 657         }
 658
 659         if (qp->transport == MLX)
 660                 qp_context->pri_path.port_pkey |=
 661                         cpu_to_be32(qp->port << 24);
 662         else {
 663                 if (attr_mask & IB_QP_PORT) {
 664                         qp_context->pri_path.port_pkey |=
 665                                 cpu_to_be32(attr->port_num << 24);
 666                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM);
 667                 }
 668         }
 669
 670         if (attr_mask & IB_QP_PKEY_INDEX) {
 671                 qp_context->pri_path.port_pkey |=
 672                         cpu_to_be32(attr->pkey_index);
 673                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX);
 674         }
 675
 676         if (attr_mask & IB_QP_RNR_RETRY) {
 677                 qp_context->alt_path.rnr_retry = qp_context->pri_path.rnr_retry =
 678                         attr->rnr_retry << 5;
 679                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY |
 680                                                         MTHCA_QP_OPTPAR_ALT_RNR_RETRY);
 681         }
 682
 683         if (attr_mask & IB_QP_AV) {
 684                 if (mthca_path_set(dev, &attr->ah_attr, &qp_context->pri_path,
 685                                    attr_mask & IB_QP_PORT ? attr->port_num : qp->port))
 686                         goto out_mailbox;
 687
 688                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH);
 689         }
 690
 691         if (attr_mask & IB_QP_TIMEOUT) {
 692                 qp_context->pri_path.ackto = attr->timeout << 3;
 693                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT);
 694         }
 695
 696         if (attr_mask & IB_QP_ALT_PATH) {
 697                 if (attr->alt_pkey_index >= dev->limits.pkey_table_len) {
 698                         mthca_dbg(dev, "Alternate P_Key index (%u) too large. max is %d\n",
 699                                   attr->alt_pkey_index, dev->limits.pkey_table_len-1);
 700                         goto out_mailbox;
 701                 }
 702
 703                 if (attr->alt_port_num == 0 || attr->alt_port_num > dev->limits.num_ports) {
 704                         mthca_dbg(dev, "Alternate port number (%u) is invalid\n",
 705                                 attr->alt_port_num);
 706                         goto out_mailbox;
 707                 }
 708
 709                 if (mthca_path_set(dev, &attr->alt_ah_attr, &qp_context->alt_path,
 710                                    attr->alt_ah_attr.port_num))
 711                         goto out_mailbox;
 712
 713                 qp_context->alt_path.port_pkey |= cpu_to_be32(attr->alt_pkey_index |
 714                                                               attr->alt_port_num << 24);
 715                 qp_context->alt_path.ackto = attr->alt_timeout << 3;
 716                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ALT_ADDR_PATH);
 717         }
 718
 719         /* leave rdd as 0 */
 720         qp_context->pd         = cpu_to_be32(to_mpd(ibqp->pd)->pd_num);
 721         /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */
 722         qp_context->wqe_lkey   = cpu_to_be32(qp->mr.ibmr.lkey);
 723         qp_context->params1    = cpu_to_be32((MTHCA_ACK_REQ_FREQ << 28) |
 724                                              (MTHCA_FLIGHT_LIMIT << 24) |
 725                                              MTHCA_QP_BIT_SWE);
 726         if (qp->sq_policy == IB_SIGNAL_ALL_WR)
 727                 qp_context->params1 |= cpu_to_be32(MTHCA_QP_BIT_SSC);
 728         if (attr_mask & IB_QP_RETRY_CNT) {
 729                 qp_context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
 730                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT);
 731         }
 732
 733         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
 734                 if (attr->max_rd_atomic) {
 735                         qp_context->params1 |=
 736                                 cpu_to_be32(MTHCA_QP_BIT_SRE |
 737                                             MTHCA_QP_BIT_SAE);
 738                         qp_context->params1 |=
 739                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
 740                 }
 741                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX);
 742         }
 743
 744         if (attr_mask & IB_QP_SQ_PSN)
 745                 qp_context->next_send_psn = cpu_to_be32(attr->sq_psn);
 746         qp_context->cqn_snd = cpu_to_be32(to_mcq(ibqp->send_cq)->cqn);
 747
 748         if (mthca_is_memfree(dev)) {
 749                 qp_context->snd_wqe_base_l = cpu_to_be32(qp->send_wqe_offset);
 750                 qp_context->snd_db_index   = cpu_to_be32(qp->sq.db_index);
 751         }
 752
 753         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
 754                 if (attr->max_dest_rd_atomic)
 755                         qp_context->params2 |=
 756                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
 757
 758                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX);
 759         }
 760
 761         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
 762                 qp_context->params2      |= get_hw_access_flags(qp, attr, attr_mask);
 763                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
 764                                                         MTHCA_QP_OPTPAR_RRE |
 765                                                         MTHCA_QP_OPTPAR_RAE);
 766         }
 767
 768         qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC);
 769
 770         if (ibqp->srq)
 771                 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RIC);
 772
 773         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
 774                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
 775                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT);
 776         }
 777         if (attr_mask & IB_QP_RQ_PSN)
 778                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
 779
 780         qp_context->ra_buff_indx =
 781                 cpu_to_be32(dev->qp_table.rdb_base +
 782                             ((qp->qpn & (dev->limits.num_qps - 1)) * MTHCA_RDB_ENTRY_SIZE <<
 783                              dev->qp_table.rdb_shift));
 784
 785         qp_context->cqn_rcv = cpu_to_be32(to_mcq(ibqp->recv_cq)->cqn);
 786
 787         if (mthca_is_memfree(dev))
 788                 qp_context->rcv_db_index   = cpu_to_be32(qp->rq.db_index);
 789
 790         if (attr_mask & IB_QP_QKEY) {
 791                 qp_context->qkey = cpu_to_be32(attr->qkey);
 792                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY);
 793         }
 794
 795         if (ibqp->srq)
 796                 qp_context->srqn = cpu_to_be32(1 << 24 |
 797                                                to_msrq(ibqp->srq)->srqn);
 798
 799         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
 800             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY               &&
 801             attr->en_sqd_async_notify)
 802                 sqd_event = 1 << 31;
 803
 804         err = mthca_MODIFY_QP(dev, cur_state, new_state, qp->qpn, 0,
 805                               mailbox, sqd_event, &status);
 806         if (err)
 807                 goto out_mailbox;
 808         if (status) {
 809                 mthca_warn(dev, "modify QP %d->%d returned status %02x.\n",
 810                            cur_state, new_state, status);
 811                 err = -EINVAL;
 812                 goto out_mailbox;
 813         }
 814
 815         qp->state = new_state;
 816         if (attr_mask & IB_QP_ACCESS_FLAGS)
 817                 qp->atomic_rd_en = attr->qp_access_flags;
 818         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
 819                 qp->resp_depth = attr->max_dest_rd_atomic;
 820         if (attr_mask & IB_QP_PORT)
 821                 qp->port = attr->port_num;
 822         if (attr_mask & IB_QP_ALT_PATH)
 823                 qp->alt_port = attr->alt_port_num;
 824
 825         if (is_sqp(dev, qp))
 826                 store_attrs(to_msqp(qp), attr, attr_mask);
 827
 828         /*
 829          * If we moved QP0 to RTR, bring the IB link up; if we moved
 830          * QP0 to RESET or ERROR, bring the link back down.
 831          */
 832         if (is_qp0(dev, qp)) {
 833                 if (cur_state != IB_QPS_RTR &&
 834                     new_state == IB_QPS_RTR)
 835                         init_port(dev, qp->port);
 836
 837                 if (cur_state != IB_QPS_RESET &&
 838                     cur_state != IB_QPS_ERR &&
 839                     (new_state == IB_QPS_RESET ||
 840                      new_state == IB_QPS_ERR))
 841                         mthca_CLOSE_IB(dev, qp->port, &status);
 842         }
 843
 844         /*
 845          * If we moved a kernel QP to RESET, clean up all old CQ
 846          * entries and reinitialize the QP.
 847          */
 848         if (new_state == IB_QPS_RESET && !qp->ibqp.uobject) {
 849                 mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq), qp->qpn,
 850                                qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
 851                 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
 852                         mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq), qp->qpn, NULL);
 853
 854                 mthca_wq_reset(&qp->sq);
 855                 qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
 856
 857                 mthca_wq_reset(&qp->rq);
 858                 qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
 859
 860                 if (mthca_is_memfree(dev)) {
 861                         *qp->sq.db = 0;
 862                         *qp->rq.db = 0;
 863                 }
 864         }
 865
 866 out_mailbox:
 867         mthca_free_mailbox(dev, mailbox);
 868
 869 out:
 870         mutex_unlock(&qp->mutex);
 871         return err;
 872 }
 873
 874 static int mthca_max_data_size(struct mthca_dev *dev, struct mthca_qp *qp, int desc_sz)
 875 {
 876         /*
 877          * Calculate the maximum size of WQE s/g segments, excluding
 878          * the next segment and other non-data segments.
 879          */
 880         int max_data_size = desc_sz - sizeof (struct mthca_next_seg);
 881
 882         switch (qp->transport) {
 883         case MLX:
 884                 max_data_size -= 2 * sizeof (struct mthca_data_seg);
 885                 break;
 886
 887         case UD:
 888                 if (mthca_is_memfree(dev))
 889                         max_data_size -= sizeof (struct mthca_arbel_ud_seg);
 890                 else
 891                         max_data_size -= sizeof (struct mthca_tavor_ud_seg);
 892                 break;
 893
 894         default:
 895                 max_data_size -= sizeof (struct mthca_raddr_seg);
 896                 break;
 897         }
 898
 899         return max_data_size;
 900 }
 901
 902 static inline int mthca_max_inline_data(struct mthca_pd *pd, int max_data_size)
 903 {
 904         /* We don't support inline data for kernel QPs (yet). */
 905         return pd->ibpd.uobject ? max_data_size - MTHCA_INLINE_HEADER_SIZE : 0;
 906 }
 907
 908 static void mthca_adjust_qp_caps(struct mthca_dev *dev,
 909                                  struct mthca_pd *pd,
 910                                  struct mthca_qp *qp)
 911 {
 912         int max_data_size = mthca_max_data_size(dev, qp,
 913                                                 min(dev->limits.max_desc_sz,
 914                                                     1 << qp->sq.wqe_shift));
 915
 916         qp->max_inline_data = mthca_max_inline_data(pd, max_data_size);
 917
 918         qp->sq.max_gs = min_t(int, dev->limits.max_sg,
 919                               max_data_size / sizeof (struct mthca_data_seg));
 920         qp->rq.max_gs = min_t(int, dev->limits.max_sg,
 921                                (min(dev->limits.max_desc_sz, 1 << qp->rq.wqe_shift) -
 922                                 sizeof (struct mthca_next_seg)) /
 923                                sizeof (struct mthca_data_seg));
 924 }
 925
 926 /*
 927  * Allocate and register buffer for WQEs.  qp->rq.max, sq.max,
 928  * rq.max_gs and sq.max_gs must all be assigned.
 929  * mthca_alloc_wqe_buf will calculate rq.wqe_shift and
 930  * sq.wqe_shift (as well as send_wqe_offset, is_direct, and
 931  * queue)
 932  */
 933 static int mthca_alloc_wqe_buf(struct mthca_dev *dev,
 934                                struct mthca_pd *pd,
 935                                struct mthca_qp *qp)
 936 {
 937         int size;
 938         int err = -ENOMEM;
 939
 940         size = sizeof (struct mthca_next_seg) +
 941                 qp->rq.max_gs * sizeof (struct mthca_data_seg);
 942
 943         if (size > dev->limits.max_desc_sz)
 944                 return -EINVAL;
 945
 946         for (qp->rq.wqe_shift = 6; 1 << qp->rq.wqe_shift < size;
 947              qp->rq.wqe_shift++)
 948                 ; /* nothing */
 949
 950         size = qp->sq.max_gs * sizeof (struct mthca_data_seg);
 951         switch (qp->transport) {
 952         case MLX:
 953                 size += 2 * sizeof (struct mthca_data_seg);
 954                 break;
 955
 956         case UD:
 957                 size += mthca_is_memfree(dev) ?
 958                         sizeof (struct mthca_arbel_ud_seg) :
 959                         sizeof (struct mthca_tavor_ud_seg);
 960                 break;
 961
 962         case UC:
 963                 size += sizeof (struct mthca_raddr_seg);
 964                 break;
 965
 966         case RC:
 967                 size += sizeof (struct mthca_raddr_seg);
 968                 /*
 969                  * An atomic op will require an atomic segment, a
 970                  * remote address segment and one scatter entry.
 971                  */
 972                 size = max_t(int, size,
 973                              sizeof (struct mthca_atomic_seg) +
 974                              sizeof (struct mthca_raddr_seg) +
 975                              sizeof (struct mthca_data_seg));
 976                 break;
 977
 978         default:
 979                 break;
 980         }
 981
 982         /* Make sure that we have enough space for a bind request */
 983         size = max_t(int, size, sizeof (struct mthca_bind_seg));
 984
 985         size += sizeof (struct mthca_next_seg);
 986
 987         if (size > dev->limits.max_desc_sz)
 988                 return -EINVAL;
 989
 990         for (qp->sq.wqe_shift = 6; 1 << qp->sq.wqe_shift < size;
 991              qp->sq.wqe_shift++)
 992                 ; /* nothing */
 993
 994         qp->send_wqe_offset = ALIGN(qp->rq.max << qp->rq.wqe_shift,
 995                                     1 << qp->sq.wqe_shift);
 996
 997         /*
 998          * If this is a userspace QP, we don't actually have to
 999          * allocate anything.  All we need is to calculate the WQE
1000          * sizes and the send_wqe_offset, so we're done now.
1001          */
1002         if (pd->ibpd.uobject)
1003                 return 0;
1004
1005         size = PAGE_ALIGN(qp->send_wqe_offset +
1006                           (qp->sq.max << qp->sq.wqe_shift));
1007
1008         qp->wrid = kmalloc((qp->rq.max + qp->sq.max) * sizeof (u64),
1009                            GFP_KERNEL);
1010         if (!qp->wrid)
1011                 goto err_out;
1012
1013         err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_QP_SIZE,
1014                               &qp->queue, &qp->is_direct, pd, 0, &qp->mr);
1015         if (err)
1016                 goto err_out;
1017
1018         return 0;
1019
1020 err_out:
1021         kfree(qp->wrid);
1022         return err;
1023 }
1024
1025 static void mthca_free_wqe_buf(struct mthca_dev *dev,
1026                                struct mthca_qp *qp)
1027 {
1028         mthca_buf_free(dev, PAGE_ALIGN(qp->send_wqe_offset +
1029                                        (qp->sq.max << qp->sq.wqe_shift)),
1030                        &qp->queue, qp->is_direct, &qp->mr);
1031         kfree(qp->wrid);
1032 }
1033
1034 static int mthca_map_memfree(struct mthca_dev *dev,
1035                              struct mthca_qp *qp)
1036 {
1037         int ret;
1038
1039         if (mthca_is_memfree(dev)) {
1040                 ret = mthca_table_get(dev, dev->qp_table.qp_table, qp->qpn);
1041                 if (ret)
1042                         return ret;
1043
1044                 ret = mthca_table_get(dev, dev->qp_table.eqp_table, qp->qpn);
1045                 if (ret)
1046                         goto err_qpc;
1047
1048                 ret = mthca_table_get(dev, dev->qp_table.rdb_table,
1049                                       qp->qpn << dev->qp_table.rdb_shift);
1050                 if (ret)
1051                         goto err_eqpc;
1052
1053         }
1054
1055         return 0;
1056
1057 err_eqpc:
1058         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1059
1060 err_qpc:
1061         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1062
1063         return ret;
1064 }
1065
1066 static void mthca_unmap_memfree(struct mthca_dev *dev,
1067                                 struct mthca_qp *qp)
1068 {
1069         mthca_table_put(dev, dev->qp_table.rdb_table,
1070                         qp->qpn << dev->qp_table.rdb_shift);
1071         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1072         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1073 }
1074
1075 static int mthca_alloc_memfree(struct mthca_dev *dev,
1076                                struct mthca_qp *qp)
1077 {
1078         int ret = 0;
1079
1080         if (mthca_is_memfree(dev)) {
1081                 qp->rq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_RQ,
1082                                                  qp->qpn, &qp->rq.db);
1083                 if (qp->rq.db_index < 0)
1084                         return ret;
1085
1086                 qp->sq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SQ,
1087                                                  qp->qpn, &qp->sq.db);
1088                 if (qp->sq.db_index < 0)
1089                         mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1090         }
1091
1092         return ret;
1093 }
1094
1095 static void mthca_free_memfree(struct mthca_dev *dev,
1096                                struct mthca_qp *qp)
1097 {
1098         if (mthca_is_memfree(dev)) {
1099                 mthca_free_db(dev, MTHCA_DB_TYPE_SQ, qp->sq.db_index);
1100                 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1101         }
1102 }
1103
1104 static int mthca_alloc_qp_common(struct mthca_dev *dev,
1105                                  struct mthca_pd *pd,
1106                                  struct mthca_cq *send_cq,
1107                                  struct mthca_cq *recv_cq,
1108                                  enum ib_sig_type send_policy,
1109                                  struct mthca_qp *qp)
1110 {
1111         int ret;
1112         int i;
1113
1114         qp->refcount = 1;
1115         init_waitqueue_head(&qp->wait);
1116         mutex_init(&qp->mutex);
1117         qp->state        = IB_QPS_RESET;
1118         qp->atomic_rd_en = 0;
1119         qp->resp_depth   = 0;
1120         qp->sq_policy    = send_policy;
1121         mthca_wq_reset(&qp->sq);
1122         mthca_wq_reset(&qp->rq);
1123
1124         spin_lock_init(&qp->sq.lock);
1125         spin_lock_init(&qp->rq.lock);
1126
1127         ret = mthca_map_memfree(dev, qp);
1128         if (ret)
1129                 return ret;
1130
1131         ret = mthca_alloc_wqe_buf(dev, pd, qp);
1132         if (ret) {
1133                 mthca_unmap_memfree(dev, qp);
1134                 return ret;
1135         }
1136
1137         mthca_adjust_qp_caps(dev, pd, qp);
1138
1139         /*
1140          * If this is a userspace QP, we're done now.  The doorbells
1141          * will be allocated and buffers will be initialized in
1142          * userspace.
1143          */
1144         if (pd->ibpd.uobject)
1145                 return 0;
1146
1147         ret = mthca_alloc_memfree(dev, qp);
1148         if (ret) {
1149                 mthca_free_wqe_buf(dev, qp);
1150                 mthca_unmap_memfree(dev, qp);
1151                 return ret;
1152         }
1153
1154         if (mthca_is_memfree(dev)) {
1155                 struct mthca_next_seg *next;
1156                 struct mthca_data_seg *scatter;
1157                 int size = (sizeof (struct mthca_next_seg) +
1158                             qp->rq.max_gs * sizeof (struct mthca_data_seg)) / 16;
1159
1160                 for (i = 0; i < qp->rq.max; ++i) {
1161                         next = get_recv_wqe(qp, i);
1162                         next->nda_op = cpu_to_be32(((i + 1) & (qp->rq.max - 1)) <<
1163                                                    qp->rq.wqe_shift);
1164                         next->ee_nds = cpu_to_be32(size);
1165
1166                         for (scatter = (void *) (next + 1);
1167                              (void *) scatter < (void *) next + (1 << qp->rq.wqe_shift);
1168                              ++scatter)
1169                                 scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
1170                 }
1171
1172                 for (i = 0; i < qp->sq.max; ++i) {
1173                         next = get_send_wqe(qp, i);
1174                         next->nda_op = cpu_to_be32((((i + 1) & (qp->sq.max - 1)) <<
1175                                                     qp->sq.wqe_shift) +
1176                                                    qp->send_wqe_offset);
1177                 }
1178         }
1179
1180         qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
1181         qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
1182
1183         return 0;
1184 }
1185
1186 static int mthca_set_qp_size(struct mthca_dev *dev, struct ib_qp_cap *cap,
1187                              struct mthca_pd *pd, struct mthca_qp *qp)
1188 {
1189         int max_data_size = mthca_max_data_size(dev, qp, dev->limits.max_desc_sz);
1190
1191         /* Sanity check QP size before proceeding */
1192         if (cap->max_send_wr     > dev->limits.max_wqes ||
1193             cap->max_recv_wr     > dev->limits.max_wqes ||
1194             cap->max_send_sge    > dev->limits.max_sg   ||
1195             cap->max_recv_sge    > dev->limits.max_sg   ||
1196             cap->max_inline_data > mthca_max_inline_data(pd, max_data_size))
1197                 return -EINVAL;
1198
1199         /*
1200          * For MLX transport we need 2 extra S/G entries:
1201          * one for the header and one for the checksum at the end
1202          */
1203         if (qp->transport == MLX && cap->max_recv_sge + 2 > dev->limits.max_sg)
1204                 return -EINVAL;
1205
1206         if (mthca_is_memfree(dev)) {
1207                 qp->rq.max = cap->max_recv_wr ?
1208                         roundup_pow_of_two(cap->max_recv_wr) : 0;
1209                 qp->sq.max = cap->max_send_wr ?
1210                         roundup_pow_of_two(cap->max_send_wr) : 0;
1211         } else {
1212                 qp->rq.max = cap->max_recv_wr;
1213                 qp->sq.max = cap->max_send_wr;
1214         }
1215
1216         qp->rq.max_gs = cap->max_recv_sge;
1217         qp->sq.max_gs = max_t(int, cap->max_send_sge,
1218                               ALIGN(cap->max_inline_data + MTHCA_INLINE_HEADER_SIZE,
1219                                     MTHCA_INLINE_CHUNK_SIZE) /
1220                               sizeof (struct mthca_data_seg));
1221
1222         return 0;
1223 }
1224
1225 int mthca_alloc_qp(struct mthca_dev *dev,
1226                    struct mthca_pd *pd,
1227                    struct mthca_cq *send_cq,
1228                    struct mthca_cq *recv_cq,
1229                    enum ib_qp_type type,
1230                    enum ib_sig_type send_policy,
1231                    struct ib_qp_cap *cap,
1232                    struct mthca_qp *qp)
1233 {
1234         int err;
1235
1236         switch (type) {
1237         case IB_QPT_RC: qp->transport = RC; break;
1238         case IB_QPT_UC: qp->transport = UC; break;
1239         case IB_QPT_UD: qp->transport = UD; break;
1240         default: return -EINVAL;
1241         }
1242
1243         err = mthca_set_qp_size(dev, cap, pd, qp);
1244         if (err)
1245                 return err;
1246
1247         qp->qpn = mthca_alloc(&dev->qp_table.alloc);
1248         if (qp->qpn == -1)
1249                 return -ENOMEM;
1250
1251         /* initialize port to zero for error-catching. */
1252         qp->port = 0;
1253
1254         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1255                                     send_policy, qp);
1256         if (err) {
1257                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1258                 return err;
1259         }
1260
1261         spin_lock_irq(&dev->qp_table.lock);
1262         mthca_array_set(&dev->qp_table.qp,
1263                         qp->qpn & (dev->limits.num_qps - 1), qp);
1264         spin_unlock_irq(&dev->qp_table.lock);
1265
1266         return 0;
1267 }
1268
1269 static void mthca_lock_cqs(struct mthca_cq *send_cq, struct mthca_cq *recv_cq)
1270 {
1271         if (send_cq == recv_cq)
1272                 spin_lock_irq(&send_cq->lock);
1273         else if (send_cq->cqn < recv_cq->cqn) {
1274                 spin_lock_irq(&send_cq->lock);
1275                 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
1276         } else {
1277                 spin_lock_irq(&recv_cq->lock);
1278                 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
1279         }
1280 }
1281
1282 static void mthca_unlock_cqs(struct mthca_cq *send_cq, struct mthca_cq *recv_cq)
1283 {
1284         if (send_cq == recv_cq)
1285                 spin_unlock_irq(&send_cq->lock);
1286         else if (send_cq->cqn < recv_cq->cqn) {
1287                 spin_unlock(&recv_cq->lock);
1288                 spin_unlock_irq(&send_cq->lock);
1289         } else {
1290                 spin_unlock(&send_cq->lock);
1291                 spin_unlock_irq(&recv_cq->lock);
1292         }
1293 }
1294
1295 int mthca_alloc_sqp(struct mthca_dev *dev,
1296                     struct mthca_pd *pd,
1297                     struct mthca_cq *send_cq,
1298                     struct mthca_cq *recv_cq,
1299                     enum ib_sig_type send_policy,
1300                     struct ib_qp_cap *cap,
1301                     int qpn,
1302                     int port,
1303                     struct mthca_sqp *sqp)
1304 {
1305         u32 mqpn = qpn * 2 + dev->qp_table.sqp_start + port - 1;
1306         int err;
1307
1308         sqp->qp.transport = MLX;
1309         err = mthca_set_qp_size(dev, cap, pd, &sqp->qp);
1310         if (err)
1311                 return err;
1312
1313         sqp->header_buf_size = sqp->qp.sq.max * MTHCA_UD_HEADER_SIZE;
1314         sqp->header_buf = dma_alloc_coherent(&dev->pdev->dev, sqp->header_buf_size,
1315                                              &sqp->header_dma, GFP_KERNEL);
1316         if (!sqp->header_buf)
1317                 return -ENOMEM;
1318
1319         spin_lock_irq(&dev->qp_table.lock);
1320         if (mthca_array_get(&dev->qp_table.qp, mqpn))
1321                 err = -EBUSY;
1322         else
1323                 mthca_array_set(&dev->qp_table.qp, mqpn, sqp);
1324         spin_unlock_irq(&dev->qp_table.lock);
1325
1326         if (err)
1327                 goto err_out;
1328
1329         sqp->qp.port      = port;
1330         sqp->qp.qpn       = mqpn;
1331         sqp->qp.transport = MLX;
1332
1333         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1334                                     send_policy, &sqp->qp);
1335         if (err)
1336                 goto err_out_free;
1337
1338         atomic_inc(&pd->sqp_count);
1339
1340         return 0;
1341
1342  err_out_free:
1343         /*
1344          * Lock CQs here, so that CQ polling code can do QP lookup
1345          * without taking a lock.
1346          */
1347         mthca_lock_cqs(send_cq, recv_cq);
1348
1349         spin_lock(&dev->qp_table.lock);
1350         mthca_array_clear(&dev->qp_table.qp, mqpn);
1351         spin_unlock(&dev->qp_table.lock);
1352
1353         mthca_unlock_cqs(send_cq, recv_cq);
1354
1355  err_out:
1356         dma_free_coherent(&dev->pdev->dev, sqp->header_buf_size,
1357                           sqp->header_buf, sqp->header_dma);
1358
1359         return err;
1360 }
1361
1362 static inline int get_qp_refcount(struct mthca_dev *dev, struct mthca_qp *qp)
1363 {
1364         int c;
1365
1366         spin_lock_irq(&dev->qp_table.lock);
1367         c = qp->refcount;
1368         spin_unlock_irq(&dev->qp_table.lock);
1369
1370         return c;
1371 }
1372
1373 void mthca_free_qp(struct mthca_dev *dev,
1374                    struct mthca_qp *qp)
1375 {
1376         u8 status;
1377         struct mthca_cq *send_cq;
1378         struct mthca_cq *recv_cq;
1379
1380         send_cq = to_mcq(qp->ibqp.send_cq);
1381         recv_cq = to_mcq(qp->ibqp.recv_cq);
1382
1383         /*
1384          * Lock CQs here, so that CQ polling code can do QP lookup
1385          * without taking a lock.
1386          */
1387         mthca_lock_cqs(send_cq, recv_cq);
1388
1389         spin_lock(&dev->qp_table.lock);
1390         mthca_array_clear(&dev->qp_table.qp,
1391                           qp->qpn & (dev->limits.num_qps - 1));
1392         --qp->refcount;
1393         spin_unlock(&dev->qp_table.lock);
1394
1395         mthca_unlock_cqs(send_cq, recv_cq);
1396
1397         wait_event(qp->wait, !get_qp_refcount(dev, qp));
1398
1399         if (qp->state != IB_QPS_RESET)
1400                 mthca_MODIFY_QP(dev, qp->state, IB_QPS_RESET, qp->qpn, 0,
1401                                 NULL, 0, &status);
1402
1403         /*
1404          * If this is a userspace QP, the buffers, MR, CQs and so on
1405          * will be cleaned up in userspace, so all we have to do is
1406          * unref the mem-free tables and free the QPN in our table.
1407          */
1408         if (!qp->ibqp.uobject) {
1409                 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq), qp->qpn,
1410                                qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1411                 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
1412                         mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq), qp->qpn,
1413                                        qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1414
1415                 mthca_free_memfree(dev, qp);
1416                 mthca_free_wqe_buf(dev, qp);
1417         }
1418
1419         mthca_unmap_memfree(dev, qp);
1420
1421         if (is_sqp(dev, qp)) {
1422                 atomic_dec(&(to_mpd(qp->ibqp.pd)->sqp_count));
1423                 dma_free_coherent(&dev->pdev->dev,
1424                                   to_msqp(qp)->header_buf_size,
1425                                   to_msqp(qp)->header_buf,
1426                                   to_msqp(qp)->header_dma);
1427         } else
1428                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1429 }
1430
1431 /* Create UD header for an MLX send and build a data segment for it */
1432 static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp,
1433                             int ind, struct ib_send_wr *wr,
1434                             struct mthca_mlx_seg *mlx,
1435                             struct mthca_data_seg *data)
1436 {
1437         int header_size;
1438         int err;
1439         u16 pkey;
1440
1441         ib_ud_header_init(256, /* assume a MAD */
1442                           mthca_ah_grh_present(to_mah(wr->wr.ud.ah)),
1443                           &sqp->ud_header);
1444
1445         err = mthca_read_ah(dev, to_mah(wr->wr.ud.ah), &sqp->ud_header);
1446         if (err)
1447                 return err;
1448         mlx->flags &= ~cpu_to_be32(MTHCA_NEXT_SOLICIT | 1);
1449         mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MTHCA_MLX_VL15 : 0) |
1450                                   (sqp->ud_header.lrh.destination_lid ==
1451                                    IB_LID_PERMISSIVE ? MTHCA_MLX_SLR : 0) |
1452                                   (sqp->ud_header.lrh.service_level << 8));
1453         mlx->rlid = sqp->ud_header.lrh.destination_lid;
1454         mlx->vcrc = 0;
1455
1456         switch (wr->opcode) {
1457         case IB_WR_SEND:
1458                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1459                 sqp->ud_header.immediate_present = 0;
1460                 break;
1461         case IB_WR_SEND_WITH_IMM:
1462                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1463                 sqp->ud_header.immediate_present = 1;
1464                 sqp->ud_header.immediate_data = wr->imm_data;
1465                 break;
1466         default:
1467                 return -EINVAL;
1468         }
1469
1470         sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
1471         if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1472                 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1473         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1474         if (!sqp->qp.ibqp.qp_num)
1475                 ib_get_cached_pkey(&dev->ib_dev, sqp->qp.port,
1476                                    sqp->pkey_index, &pkey);
1477         else
1478                 ib_get_cached_pkey(&dev->ib_dev, sqp->qp.port,
1479                                    wr->wr.ud.pkey_index, &pkey);
1480         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1481         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1482         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1483         sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1484                                                sqp->qkey : wr->wr.ud.remote_qkey);
1485         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1486
1487         header_size = ib_ud_header_pack(&sqp->ud_header,
1488                                         sqp->header_buf +
1489                                         ind * MTHCA_UD_HEADER_SIZE);
1490
1491         data->byte_count = cpu_to_be32(header_size);
1492         data->lkey       = cpu_to_be32(to_mpd(sqp->qp.ibqp.pd)->ntmr.ibmr.lkey);
1493         data->addr       = cpu_to_be64(sqp->header_dma +
1494                                        ind * MTHCA_UD_HEADER_SIZE);
1495
1496         return 0;
1497 }
1498
1499 static inline int mthca_wq_overflow(struct mthca_wq *wq, int nreq,
1500                                     struct ib_cq *ib_cq)
1501 {
1502         unsigned cur;
1503         struct mthca_cq *cq;
1504
1505         cur = wq->head - wq->tail;
1506         if (likely(cur + nreq < wq->max))
1507                 return 0;
1508
1509         cq = to_mcq(ib_cq);
1510         spin_lock(&cq->lock);
1511         cur = wq->head - wq->tail;
1512         spin_unlock(&cq->lock);
1513
1514         return cur + nreq >= wq->max;
1515 }
1516
1517 int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1518                           struct ib_send_wr **bad_wr)
1519 {
1520         struct mthca_dev *dev = to_mdev(ibqp->device);
1521         struct mthca_qp *qp = to_mqp(ibqp);
1522         void *wqe;
1523         void *prev_wqe;
1524         unsigned long flags;
1525         int err = 0;
1526         int nreq;
1527         int i;
1528         int size;
1529         int size0 = 0;
1530         u32 f0;
1531         int ind;
1532         u8 op0 = 0;
1533
1534         spin_lock_irqsave(&qp->sq.lock, flags);
1535
1536         /* XXX check that state is OK to post send */
1537
1538         ind = qp->sq.next_ind;
1539
1540         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1541                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1542                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1543                                         " %d max, %d nreq)\n", qp->qpn,
1544                                         qp->sq.head, qp->sq.tail,
1545                                         qp->sq.max, nreq);
1546                         err = -ENOMEM;
1547                         *bad_wr = wr;
1548                         goto out;
1549                 }
1550
1551                 wqe = get_send_wqe(qp, ind);
1552                 prev_wqe = qp->sq.last;
1553                 qp->sq.last = wqe;
1554
1555                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1556                 ((struct mthca_next_seg *) wqe)->ee_nds = 0;
1557                 ((struct mthca_next_seg *) wqe)->flags =
1558                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1559                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1560                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1561                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1562                         cpu_to_be32(1);
1563                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1564                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1565                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1566
1567                 wqe += sizeof (struct mthca_next_seg);
1568                 size = sizeof (struct mthca_next_seg) / 16;
1569
1570                 switch (qp->transport) {
1571                 case RC:
1572                         switch (wr->opcode) {
1573                         case IB_WR_ATOMIC_CMP_AND_SWP:
1574                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1575                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1576                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1577                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1578                                         cpu_to_be32(wr->wr.atomic.rkey);
1579                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1580
1581                                 wqe += sizeof (struct mthca_raddr_seg);
1582
1583                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1584                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1585                                                 cpu_to_be64(wr->wr.atomic.swap);
1586                                         ((struct mthca_atomic_seg *) wqe)->compare =
1587                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1588                                 } else {
1589                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1590                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1591                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1592                                 }
1593
1594                                 wqe += sizeof (struct mthca_atomic_seg);
1595                                 size += (sizeof (struct mthca_raddr_seg) +
1596                                          sizeof (struct mthca_atomic_seg)) / 16;
1597                                 break;
1598
1599                         case IB_WR_RDMA_WRITE:
1600                         case IB_WR_RDMA_WRITE_WITH_IMM:
1601                         case IB_WR_RDMA_READ:
1602                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1603                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1604                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1605                                         cpu_to_be32(wr->wr.rdma.rkey);
1606                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1607                                 wqe += sizeof (struct mthca_raddr_seg);
1608                                 size += sizeof (struct mthca_raddr_seg) / 16;
1609                                 break;
1610
1611                         default:
1612                                 /* No extra segments required for sends */
1613                                 break;
1614                         }
1615
1616                         break;
1617
1618                 case UC:
1619                         switch (wr->opcode) {
1620                         case IB_WR_RDMA_WRITE:
1621                         case IB_WR_RDMA_WRITE_WITH_IMM:
1622                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1623                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1624                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1625                                         cpu_to_be32(wr->wr.rdma.rkey);
1626                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1627                                 wqe += sizeof (struct mthca_raddr_seg);
1628                                 size += sizeof (struct mthca_raddr_seg) / 16;
1629                                 break;
1630
1631                         default:
1632                                 /* No extra segments required for sends */
1633                                 break;
1634                         }
1635
1636                         break;
1637
1638                 case UD:
1639                         ((struct mthca_tavor_ud_seg *) wqe)->lkey =
1640                                 cpu_to_be32(to_mah(wr->wr.ud.ah)->key);
1641                         ((struct mthca_tavor_ud_seg *) wqe)->av_addr =
1642                                 cpu_to_be64(to_mah(wr->wr.ud.ah)->avdma);
1643                         ((struct mthca_tavor_ud_seg *) wqe)->dqpn =
1644                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1645                         ((struct mthca_tavor_ud_seg *) wqe)->qkey =
1646                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1647
1648                         wqe += sizeof (struct mthca_tavor_ud_seg);
1649                         size += sizeof (struct mthca_tavor_ud_seg) / 16;
1650                         break;
1651
1652                 case MLX:
1653                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1654                                                wqe - sizeof (struct mthca_next_seg),
1655                                                wqe);
1656                         if (err) {
1657                                 *bad_wr = wr;
1658                                 goto out;
1659                         }
1660                         wqe += sizeof (struct mthca_data_seg);
1661                         size += sizeof (struct mthca_data_seg) / 16;
1662                         break;
1663                 }
1664
1665                 if (wr->num_sge > qp->sq.max_gs) {
1666                         mthca_err(dev, "too many gathers\n");
1667                         err = -EINVAL;
1668                         *bad_wr = wr;
1669                         goto out;
1670                 }
1671
1672                 for (i = 0; i < wr->num_sge; ++i) {
1673                         ((struct mthca_data_seg *) wqe)->byte_count =
1674                                 cpu_to_be32(wr->sg_list[i].length);
1675                         ((struct mthca_data_seg *) wqe)->lkey =
1676                                 cpu_to_be32(wr->sg_list[i].lkey);
1677                         ((struct mthca_data_seg *) wqe)->addr =
1678                                 cpu_to_be64(wr->sg_list[i].addr);
1679                         wqe += sizeof (struct mthca_data_seg);
1680                         size += sizeof (struct mthca_data_seg) / 16;
1681                 }
1682
1683                 /* Add one more inline data segment for ICRC */
1684                 if (qp->transport == MLX) {
1685                         ((struct mthca_data_seg *) wqe)->byte_count =
1686                                 cpu_to_be32((1 << 31) | 4);
1687                         ((u32 *) wqe)[1] = 0;
1688                         wqe += sizeof (struct mthca_data_seg);
1689                         size += sizeof (struct mthca_data_seg) / 16;
1690                 }
1691
1692                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1693
1694                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1695                         mthca_err(dev, "opcode invalid\n");
1696                         err = -EINVAL;
1697                         *bad_wr = wr;
1698                         goto out;
1699                 }
1700
1701                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1702                         cpu_to_be32(((ind << qp->sq.wqe_shift) +
1703                                      qp->send_wqe_offset) |
1704                                     mthca_opcode[wr->opcode]);
1705                 wmb();
1706                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1707                         cpu_to_be32((size0 ? 0 : MTHCA_NEXT_DBD) | size |
1708                                     ((wr->send_flags & IB_SEND_FENCE) ?
1709                                     MTHCA_NEXT_FENCE : 0));
1710
1711                 if (!size0) {
1712                         size0 = size;
1713                         op0   = mthca_opcode[wr->opcode];
1714                         f0    = wr->send_flags & IB_SEND_FENCE ?
1715                                 MTHCA_SEND_DOORBELL_FENCE : 0;
1716                 }
1717
1718                 ++ind;
1719                 if (unlikely(ind >= qp->sq.max))
1720                         ind -= qp->sq.max;
1721         }
1722
1723 out:
1724         if (likely(nreq)) {
1725                 __be32 doorbell[2];
1726
1727                 doorbell[0] = cpu_to_be32(((qp->sq.next_ind << qp->sq.wqe_shift) +
1728                                            qp->send_wqe_offset) | f0 | op0);
1729                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1730
1731                 wmb();
1732
1733                 mthca_write64(doorbell,
1734                               dev->kar + MTHCA_SEND_DOORBELL,
1735                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1736                 /*
1737                  * Make sure doorbells don't leak out of SQ spinlock
1738                  * and reach the HCA out of order:
1739                  */
1740                 mmiowb();
1741         }
1742
1743         qp->sq.next_ind = ind;
1744         qp->sq.head    += nreq;
1745
1746         spin_unlock_irqrestore(&qp->sq.lock, flags);
1747         return err;
1748 }
1749
1750 int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1751                              struct ib_recv_wr **bad_wr)
1752 {
1753         struct mthca_dev *dev = to_mdev(ibqp->device);
1754         struct mthca_qp *qp = to_mqp(ibqp);
1755         __be32 doorbell[2];
1756         unsigned long flags;
1757         int err = 0;
1758         int nreq;
1759         int i;
1760         int size;
1761         int size0 = 0;
1762         int ind;
1763         void *wqe;
1764         void *prev_wqe;
1765
1766         spin_lock_irqsave(&qp->rq.lock, flags);
1767
1768         /* XXX check that state is OK to post receive */
1769
1770         ind = qp->rq.next_ind;
1771
1772         for (nreq = 0; wr; wr = wr->next) {
1773                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1774                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
1775                                         " %d max, %d nreq)\n", qp->qpn,
1776                                         qp->rq.head, qp->rq.tail,
1777                                         qp->rq.max, nreq);
1778                         err = -ENOMEM;
1779                         *bad_wr = wr;
1780                         goto out;
1781                 }
1782
1783                 wqe = get_recv_wqe(qp, ind);
1784                 prev_wqe = qp->rq.last;
1785                 qp->rq.last = wqe;
1786
1787                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1788                 ((struct mthca_next_seg *) wqe)->ee_nds =
1789                         cpu_to_be32(MTHCA_NEXT_DBD);
1790                 ((struct mthca_next_seg *) wqe)->flags = 0;
1791
1792                 wqe += sizeof (struct mthca_next_seg);
1793                 size = sizeof (struct mthca_next_seg) / 16;
1794
1795                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1796                         err = -EINVAL;
1797                         *bad_wr = wr;
1798                         goto out;
1799                 }
1800
1801                 for (i = 0; i < wr->num_sge; ++i) {
1802                         ((struct mthca_data_seg *) wqe)->byte_count =
1803                                 cpu_to_be32(wr->sg_list[i].length);
1804                         ((struct mthca_data_seg *) wqe)->lkey =
1805                                 cpu_to_be32(wr->sg_list[i].lkey);
1806                         ((struct mthca_data_seg *) wqe)->addr =
1807                                 cpu_to_be64(wr->sg_list[i].addr);
1808                         wqe += sizeof (struct mthca_data_seg);
1809                         size += sizeof (struct mthca_data_seg) / 16;
1810                 }
1811
1812                 qp->wrid[ind] = wr->wr_id;
1813
1814                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1815                         cpu_to_be32((ind << qp->rq.wqe_shift) | 1);
1816                 wmb();
1817                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1818                         cpu_to_be32(MTHCA_NEXT_DBD | size);
1819
1820                 if (!size0)
1821                         size0 = size;
1822
1823                 ++ind;
1824                 if (unlikely(ind >= qp->rq.max))
1825                         ind -= qp->rq.max;
1826
1827                 ++nreq;
1828                 if (unlikely(nreq == MTHCA_TAVOR_MAX_WQES_PER_RECV_DB)) {
1829                         nreq = 0;
1830
1831                         doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1832                         doorbell[1] = cpu_to_be32(qp->qpn << 8);
1833
1834                         wmb();
1835
1836                         mthca_write64(doorbell,
1837                                       dev->kar + MTHCA_RECEIVE_DOORBELL,
1838                                       MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1839
1840                         qp->rq.head += MTHCA_TAVOR_MAX_WQES_PER_RECV_DB;
1841                         size0 = 0;
1842                 }
1843         }
1844
1845 out:
1846         if (likely(nreq)) {
1847                 doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1848                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | nreq);
1849
1850                 wmb();
1851
1852                 mthca_write64(doorbell,
1853                               dev->kar + MTHCA_RECEIVE_DOORBELL,
1854                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1855         }
1856
1857         qp->rq.next_ind = ind;
1858         qp->rq.head    += nreq;
1859
1860         /*
1861          * Make sure doorbells don't leak out of RQ spinlock and reach
1862          * the HCA out of order:
1863          */
1864         mmiowb();
1865
1866         spin_unlock_irqrestore(&qp->rq.lock, flags);
1867         return err;
1868 }
1869
1870 int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1871                           struct ib_send_wr **bad_wr)
1872 {
1873         struct mthca_dev *dev = to_mdev(ibqp->device);
1874         struct mthca_qp *qp = to_mqp(ibqp);
1875         __be32 doorbell[2];
1876         void *wqe;
1877         void *prev_wqe;
1878         unsigned long flags;
1879         int err = 0;
1880         int nreq;
1881         int i;
1882         int size;
1883         int size0 = 0;
1884         u32 f0;
1885         int ind;
1886         u8 op0 = 0;
1887
1888         spin_lock_irqsave(&qp->sq.lock, flags);
1889
1890         /* XXX check that state is OK to post send */
1891
1892         ind = qp->sq.head & (qp->sq.max - 1);
1893
1894         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1895                 if (unlikely(nreq == MTHCA_ARBEL_MAX_WQES_PER_SEND_DB)) {
1896                         nreq = 0;
1897
1898                         doorbell[0] = cpu_to_be32((MTHCA_ARBEL_MAX_WQES_PER_SEND_DB << 24) |
1899                                                   ((qp->sq.head & 0xffff) << 8) |
1900                                                   f0 | op0);
1901                         doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1902
1903                         qp->sq.head += MTHCA_ARBEL_MAX_WQES_PER_SEND_DB;
1904                         size0 = 0;
1905
1906                         /*
1907                          * Make sure that descriptors are written before
1908                          * doorbell record.
1909                          */
1910                         wmb();
1911                         *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
1912
1913                         /*
1914                          * Make sure doorbell record is written before we
1915                          * write MMIO send doorbell.
1916                          */
1917                         wmb();
1918                         mthca_write64(doorbell,
1919                                       dev->kar + MTHCA_SEND_DOORBELL,
1920                                       MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1921                 }
1922
1923                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1924                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1925                                         " %d max, %d nreq)\n", qp->qpn,
1926                                         qp->sq.head, qp->sq.tail,
1927                                         qp->sq.max, nreq);
1928                         err = -ENOMEM;
1929                         *bad_wr = wr;
1930                         goto out;
1931                 }
1932
1933                 wqe = get_send_wqe(qp, ind);
1934                 prev_wqe = qp->sq.last;
1935                 qp->sq.last = wqe;
1936
1937                 ((struct mthca_next_seg *) wqe)->flags =
1938                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1939                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1940                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1941                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1942                         cpu_to_be32(1);
1943                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1944                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1945                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1946
1947                 wqe += sizeof (struct mthca_next_seg);
1948                 size = sizeof (struct mthca_next_seg) / 16;
1949
1950                 switch (qp->transport) {
1951                 case RC:
1952                         switch (wr->opcode) {
1953                         case IB_WR_ATOMIC_CMP_AND_SWP:
1954                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1955                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1956                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1957                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1958                                         cpu_to_be32(wr->wr.atomic.rkey);
1959                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1960
1961                                 wqe += sizeof (struct mthca_raddr_seg);
1962
1963                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1964                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1965                                                 cpu_to_be64(wr->wr.atomic.swap);
1966                                         ((struct mthca_atomic_seg *) wqe)->compare =
1967                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1968                                 } else {
1969                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1970                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1971                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1972                                 }
1973
1974                                 wqe += sizeof (struct mthca_atomic_seg);
1975                                 size += (sizeof (struct mthca_raddr_seg) +
1976                                          sizeof (struct mthca_atomic_seg)) / 16;
1977                                 break;
1978
1979                         case IB_WR_RDMA_READ:
1980                         case IB_WR_RDMA_WRITE:
1981                         case IB_WR_RDMA_WRITE_WITH_IMM:
1982                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1983                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1984                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1985                                         cpu_to_be32(wr->wr.rdma.rkey);
1986                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1987                                 wqe += sizeof (struct mthca_raddr_seg);
1988                                 size += sizeof (struct mthca_raddr_seg) / 16;
1989                                 break;
1990
1991                         default:
1992                                 /* No extra segments required for sends */
1993                                 break;
1994                         }
1995
1996                         break;
1997
1998                 case UC:
1999                         switch (wr->opcode) {
2000                         case IB_WR_RDMA_WRITE:
2001                         case IB_WR_RDMA_WRITE_WITH_IMM:
2002                                 ((struct mthca_raddr_seg *) wqe)->raddr =
2003                                         cpu_to_be64(wr->wr.rdma.remote_addr);
2004                                 ((struct mthca_raddr_seg *) wqe)->rkey =
2005                                         cpu_to_be32(wr->wr.rdma.rkey);
2006                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
2007                                 wqe += sizeof (struct mthca_raddr_seg);
2008                                 size += sizeof (struct mthca_raddr_seg) / 16;
2009                                 break;
2010
2011                         default:
2012                                 /* No extra segments required for sends */
2013                                 break;
2014                         }
2015
2016                         break;
2017
2018                 case UD:
2019                         memcpy(((struct mthca_arbel_ud_seg *) wqe)->av,
2020                                to_mah(wr->wr.ud.ah)->av, MTHCA_AV_SIZE);
2021                         ((struct mthca_arbel_ud_seg *) wqe)->dqpn =
2022                                 cpu_to_be32(wr->wr.ud.remote_qpn);
2023                         ((struct mthca_arbel_ud_seg *) wqe)->qkey =
2024                                 cpu_to_be32(wr->wr.ud.remote_qkey);
2025
2026                         wqe += sizeof (struct mthca_arbel_ud_seg);
2027                         size += sizeof (struct mthca_arbel_ud_seg) / 16;
2028                         break;
2029
2030                 case MLX:
2031                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
2032                                                wqe - sizeof (struct mthca_next_seg),
2033                                                wqe);
2034                         if (err) {
2035                                 *bad_wr = wr;
2036                                 goto out;
2037                         }
2038                         wqe += sizeof (struct mthca_data_seg);
2039                         size += sizeof (struct mthca_data_seg) / 16;
2040                         break;
2041                 }
2042
2043                 if (wr->num_sge > qp->sq.max_gs) {
2044                         mthca_err(dev, "too many gathers\n");
2045                         err = -EINVAL;
2046                         *bad_wr = wr;
2047                         goto out;
2048                 }
2049
2050                 for (i = 0; i < wr->num_sge; ++i) {
2051                         ((struct mthca_data_seg *) wqe)->byte_count =
2052                                 cpu_to_be32(wr->sg_list[i].length);
2053                         ((struct mthca_data_seg *) wqe)->lkey =
2054                                 cpu_to_be32(wr->sg_list[i].lkey);
2055                         ((struct mthca_data_seg *) wqe)->addr =
2056                                 cpu_to_be64(wr->sg_list[i].addr);
2057                         wqe += sizeof (struct mthca_data_seg);
2058                         size += sizeof (struct mthca_data_seg) / 16;
2059                 }
2060
2061                 /* Add one more inline data segment for ICRC */
2062                 if (qp->transport == MLX) {
2063                         ((struct mthca_data_seg *) wqe)->byte_count =
2064                                 cpu_to_be32((1 << 31) | 4);
2065                         ((u32 *) wqe)[1] = 0;
2066                         wqe += sizeof (struct mthca_data_seg);
2067                         size += sizeof (struct mthca_data_seg) / 16;
2068                 }
2069
2070                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
2071
2072                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
2073                         mthca_err(dev, "opcode invalid\n");
2074                         err = -EINVAL;
2075                         *bad_wr = wr;
2076                         goto out;
2077                 }
2078
2079                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
2080                         cpu_to_be32(((ind << qp->sq.wqe_shift) +
2081                                      qp->send_wqe_offset) |
2082                                     mthca_opcode[wr->opcode]);
2083                 wmb();
2084                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
2085                         cpu_to_be32(MTHCA_NEXT_DBD | size |
2086                                     ((wr->send_flags & IB_SEND_FENCE) ?
2087                                      MTHCA_NEXT_FENCE : 0));
2088
2089                 if (!size0) {
2090                         size0 = size;
2091                         op0   = mthca_opcode[wr->opcode];
2092                         f0    = wr->send_flags & IB_SEND_FENCE ?
2093                                 MTHCA_SEND_DOORBELL_FENCE : 0;
2094                 }
2095
2096                 ++ind;
2097                 if (unlikely(ind >= qp->sq.max))
2098                         ind -= qp->sq.max;
2099         }
2100
2101 out:
2102         if (likely(nreq)) {
2103                 doorbell[0] = cpu_to_be32((nreq << 24)                  |
2104                                           ((qp->sq.head & 0xffff) << 8) |
2105                                           f0 | op0);
2106                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
2107
2108                 qp->sq.head += nreq;
2109
2110                 /*
2111                  * Make sure that descriptors are written before
2112                  * doorbell record.
2113                  */
2114                 wmb();
2115                 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
2116
2117                 /*
2118                  * Make sure doorbell record is written before we
2119                  * write MMIO send doorbell.
2120                  */
2121                 wmb();
2122                 mthca_write64(doorbell,
2123                               dev->kar + MTHCA_SEND_DOORBELL,
2124                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
2125         }
2126
2127         /*
2128          * Make sure doorbells don't leak out of SQ spinlock and reach
2129          * the HCA out of order:
2130          */
2131         mmiowb();
2132
2133         spin_unlock_irqrestore(&qp->sq.lock, flags);
2134         return err;
2135 }
2136
2137 int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2138                              struct ib_recv_wr **bad_wr)
2139 {
2140         struct mthca_dev *dev = to_mdev(ibqp->device);
2141         struct mthca_qp *qp = to_mqp(ibqp);
2142         unsigned long flags;
2143         int err = 0;
2144         int nreq;
2145         int ind;
2146         int i;
2147         void *wqe;
2148
2149         spin_lock_irqsave(&qp->rq.lock, flags);
2150
2151         /* XXX check that state is OK to post receive */
2152
2153         ind = qp->rq.head & (qp->rq.max - 1);
2154
2155         for (nreq = 0; wr; ++nreq, wr = wr->next) {
2156                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2157                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
2158                                         " %d max, %d nreq)\n", qp->qpn,
2159                                         qp->rq.head, qp->rq.tail,
2160                                         qp->rq.max, nreq);
2161                         err = -ENOMEM;
2162                         *bad_wr = wr;
2163                         goto out;
2164                 }
2165
2166                 wqe = get_recv_wqe(qp, ind);
2167
2168                 ((struct mthca_next_seg *) wqe)->flags = 0;
2169
2170                 wqe += sizeof (struct mthca_next_seg);
2171
2172                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2173                         err = -EINVAL;
2174                         *bad_wr = wr;
2175                         goto out;
2176                 }
2177
2178                 for (i = 0; i < wr->num_sge; ++i) {
2179                         ((struct mthca_data_seg *) wqe)->byte_count =
2180                                 cpu_to_be32(wr->sg_list[i].length);
2181                         ((struct mthca_data_seg *) wqe)->lkey =
2182                                 cpu_to_be32(wr->sg_list[i].lkey);
2183                         ((struct mthca_data_seg *) wqe)->addr =
2184                                 cpu_to_be64(wr->sg_list[i].addr);
2185                         wqe += sizeof (struct mthca_data_seg);
2186                 }
2187
2188                 if (i < qp->rq.max_gs) {
2189                         ((struct mthca_data_seg *) wqe)->byte_count = 0;
2190                         ((struct mthca_data_seg *) wqe)->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
2191                         ((struct mthca_data_seg *) wqe)->addr = 0;
2192                 }
2193
2194                 qp->wrid[ind] = wr->wr_id;
2195
2196                 ++ind;
2197                 if (unlikely(ind >= qp->rq.max))
2198                         ind -= qp->rq.max;
2199         }
2200 out:
2201         if (likely(nreq)) {
2202                 qp->rq.head += nreq;
2203
2204                 /*
2205                  * Make sure that descriptors are written before
2206                  * doorbell record.
2207                  */
2208                 wmb();
2209                 *qp->rq.db = cpu_to_be32(qp->rq.head & 0xffff);
2210         }
2211
2212         spin_unlock_irqrestore(&qp->rq.lock, flags);
2213         return err;
2214 }
2215
2216 void mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
2217                         int index, int *dbd, __be32 *new_wqe)
2218 {
2219         struct mthca_next_seg *next;
2220
2221         /*
2222          * For SRQs, all WQEs generate a CQE, so we're always at the
2223          * end of the doorbell chain.
2224          */
2225         if (qp->ibqp.srq) {
2226                 *new_wqe = 0;
2227                 return;
2228         }
2229
2230         if (is_send)
2231                 next = get_send_wqe(qp, index);
2232         else
2233                 next = get_recv_wqe(qp, index);
2234
2235         *dbd = !!(next->ee_nds & cpu_to_be32(MTHCA_NEXT_DBD));
2236         if (next->ee_nds & cpu_to_be32(0x3f))
2237                 *new_wqe = (next->nda_op & cpu_to_be32(~0x3f)) |
2238                         (next->ee_nds & cpu_to_be32(0x3f));
2239         else
2240                 *new_wqe = 0;
2241 }
2242
2243 int mthca_init_qp_table(struct mthca_dev *dev)
2244 {
2245         int err;
2246         u8 status;
2247         int i;
2248
2249         spin_lock_init(&dev->qp_table.lock);
2250
2251         /*
2252          * We reserve 2 extra QPs per port for the special QPs.  The
2253          * special QP for port 1 has to be even, so round up.
2254          */
2255         dev->qp_table.sqp_start = (dev->limits.reserved_qps + 1) & ~1UL;
2256         err = mthca_alloc_init(&dev->qp_table.alloc,
2257                                dev->limits.num_qps,
2258                                (1 << 24) - 1,
2259                                dev->qp_table.sqp_start +
2260                                MTHCA_MAX_PORTS * 2);
2261         if (err)
2262                 return err;
2263
2264         err = mthca_array_init(&dev->qp_table.qp,
2265                                dev->limits.num_qps);
2266         if (err) {
2267                 mthca_alloc_cleanup(&dev->qp_table.alloc);
2268                 return err;
2269         }
2270
2271         for (i = 0; i < 2; ++i) {
2272                 err = mthca_CONF_SPECIAL_QP(dev, i ? IB_QPT_GSI : IB_QPT_SMI,
2273                                             dev->qp_table.sqp_start + i * 2,
2274                                             &status);
2275                 if (err)
2276                         goto err_out;
2277                 if (status) {
2278                         mthca_warn(dev, "CONF_SPECIAL_QP returned "
2279                                    "status %02x, aborting.\n",
2280                                    status);
2281                         err = -EINVAL;
2282                         goto err_out;
2283                 }
2284         }
2285         return 0;
2286
2287  err_out:
2288         for (i = 0; i < 2; ++i)
2289                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2290
2291         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2292         mthca_alloc_cleanup(&dev->qp_table.alloc);
2293
2294         return err;
2295 }
2296
2297 void mthca_cleanup_qp_table(struct mthca_dev *dev)
2298 {
2299         int i;
2300         u8 status;
2301
2302         for (i = 0; i < 2; ++i)
2303                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2304
2305         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2306         mthca_alloc_cleanup(&dev->qp_table.alloc);
2307 }