drivers/infiniband/hw/mthca/mthca_qp.c

   1 /*
   2  * Copyright (c) 2004 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Cisco Systems. All rights reserved.
   4  * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
   5  * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * OpenIB.org BSD license below:
  12  *
  13  *     Redistribution and use in source and binary forms, with or
  14  *     without modification, are permitted provided that the following
  15  *     conditions are met:
  16  *
  17  *      - Redistributions of source code must retain the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer.
  20  *
  21  *      - Redistributions in binary form must reproduce the above
  22  *        copyright notice, this list of conditions and the following
  23  *        disclaimer in the documentation and/or other materials
  24  *        provided with the distribution.
  25  *
  26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33  * SOFTWARE.
  34  *
  35  * $Id: mthca_qp.c 1355 2004-12-17 15:23:43Z roland $
  36  */
  37
  38 #include <linux/init.h>
  39 #include <linux/string.h>
  40 #include <linux/slab.h>
  41
  42 #include <rdma/ib_verbs.h>
  43 #include <rdma/ib_cache.h>
  44 #include <rdma/ib_pack.h>
  45
  46 #include "mthca_dev.h"
  47 #include "mthca_cmd.h"
  48 #include "mthca_memfree.h"
  49 #include "mthca_wqe.h"
  50
  51 enum {
  52         MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE,
  53         MTHCA_ACK_REQ_FREQ       = 10,
  54         MTHCA_FLIGHT_LIMIT       = 9,
  55         MTHCA_UD_HEADER_SIZE     = 72, /* largest UD header possible */
  56         MTHCA_INLINE_HEADER_SIZE = 4,  /* data segment overhead for inline */
  57         MTHCA_INLINE_CHUNK_SIZE  = 16  /* inline data segment chunk */
  58 };
  59
  60 enum {
  61         MTHCA_QP_STATE_RST  = 0,
  62         MTHCA_QP_STATE_INIT = 1,
  63         MTHCA_QP_STATE_RTR  = 2,
  64         MTHCA_QP_STATE_RTS  = 3,
  65         MTHCA_QP_STATE_SQE  = 4,
  66         MTHCA_QP_STATE_SQD  = 5,
  67         MTHCA_QP_STATE_ERR  = 6,
  68         MTHCA_QP_STATE_DRAINING = 7
  69 };
  70
  71 enum {
  72         MTHCA_QP_ST_RC  = 0x0,
  73         MTHCA_QP_ST_UC  = 0x1,
  74         MTHCA_QP_ST_RD  = 0x2,
  75         MTHCA_QP_ST_UD  = 0x3,
  76         MTHCA_QP_ST_MLX = 0x7
  77 };
  78
  79 enum {
  80         MTHCA_QP_PM_MIGRATED = 0x3,
  81         MTHCA_QP_PM_ARMED    = 0x0,
  82         MTHCA_QP_PM_REARM    = 0x1
  83 };
  84
  85 enum {
  86         /* qp_context flags */
  87         MTHCA_QP_BIT_DE  = 1 <<  8,
  88         /* params1 */
  89         MTHCA_QP_BIT_SRE = 1 << 15,
  90         MTHCA_QP_BIT_SWE = 1 << 14,
  91         MTHCA_QP_BIT_SAE = 1 << 13,
  92         MTHCA_QP_BIT_SIC = 1 <<  4,
  93         MTHCA_QP_BIT_SSC = 1 <<  3,
  94         /* params2 */
  95         MTHCA_QP_BIT_RRE = 1 << 15,
  96         MTHCA_QP_BIT_RWE = 1 << 14,
  97         MTHCA_QP_BIT_RAE = 1 << 13,
  98         MTHCA_QP_BIT_RIC = 1 <<  4,
  99         MTHCA_QP_BIT_RSC = 1 <<  3
 100 };
 101
 102 enum {
 103         MTHCA_SEND_DOORBELL_FENCE = 1 << 5
 104 };
 105
 106 struct mthca_qp_path {
 107         __be32 port_pkey;
 108         u8     rnr_retry;
 109         u8     g_mylmc;
 110         __be16 rlid;
 111         u8     ackto;
 112         u8     mgid_index;
 113         u8     static_rate;
 114         u8     hop_limit;
 115         __be32 sl_tclass_flowlabel;
 116         u8     rgid[16];
 117 } __attribute__((packed));
 118
 119 struct mthca_qp_context {
 120         __be32 flags;
 121         __be32 tavor_sched_queue; /* Reserved on Arbel */
 122         u8     mtu_msgmax;
 123         u8     rq_size_stride;  /* Reserved on Tavor */
 124         u8     sq_size_stride;  /* Reserved on Tavor */
 125         u8     rlkey_arbel_sched_queue; /* Reserved on Tavor */
 126         __be32 usr_page;
 127         __be32 local_qpn;
 128         __be32 remote_qpn;
 129         u32    reserved1[2];
 130         struct mthca_qp_path pri_path;
 131         struct mthca_qp_path alt_path;
 132         __be32 rdd;
 133         __be32 pd;
 134         __be32 wqe_base;
 135         __be32 wqe_lkey;
 136         __be32 params1;
 137         __be32 reserved2;
 138         __be32 next_send_psn;
 139         __be32 cqn_snd;
 140         __be32 snd_wqe_base_l;  /* Next send WQE on Tavor */
 141         __be32 snd_db_index;    /* (debugging only entries) */
 142         __be32 last_acked_psn;
 143         __be32 ssn;
 144         __be32 params2;
 145         __be32 rnr_nextrecvpsn;
 146         __be32 ra_buff_indx;
 147         __be32 cqn_rcv;
 148         __be32 rcv_wqe_base_l;  /* Next recv WQE on Tavor */
 149         __be32 rcv_db_index;    /* (debugging only entries) */
 150         __be32 qkey;
 151         __be32 srqn;
 152         __be32 rmsn;
 153         __be16 rq_wqe_counter;  /* reserved on Tavor */
 154         __be16 sq_wqe_counter;  /* reserved on Tavor */
 155         u32    reserved3[18];
 156 } __attribute__((packed));
 157
 158 struct mthca_qp_param {
 159         __be32 opt_param_mask;
 160         u32    reserved1;
 161         struct mthca_qp_context context;
 162         u32    reserved2[62];
 163 } __attribute__((packed));
 164
 165 enum {
 166         MTHCA_QP_OPTPAR_ALT_ADDR_PATH     = 1 << 0,
 167         MTHCA_QP_OPTPAR_RRE               = 1 << 1,
 168         MTHCA_QP_OPTPAR_RAE               = 1 << 2,
 169         MTHCA_QP_OPTPAR_RWE               = 1 << 3,
 170         MTHCA_QP_OPTPAR_PKEY_INDEX        = 1 << 4,
 171         MTHCA_QP_OPTPAR_Q_KEY             = 1 << 5,
 172         MTHCA_QP_OPTPAR_RNR_TIMEOUT       = 1 << 6,
 173         MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
 174         MTHCA_QP_OPTPAR_SRA_MAX           = 1 << 8,
 175         MTHCA_QP_OPTPAR_RRA_MAX           = 1 << 9,
 176         MTHCA_QP_OPTPAR_PM_STATE          = 1 << 10,
 177         MTHCA_QP_OPTPAR_PORT_NUM          = 1 << 11,
 178         MTHCA_QP_OPTPAR_RETRY_COUNT       = 1 << 12,
 179         MTHCA_QP_OPTPAR_ALT_RNR_RETRY     = 1 << 13,
 180         MTHCA_QP_OPTPAR_ACK_TIMEOUT       = 1 << 14,
 181         MTHCA_QP_OPTPAR_RNR_RETRY         = 1 << 15,
 182         MTHCA_QP_OPTPAR_SCHED_QUEUE       = 1 << 16
 183 };
 184
 185 static const u8 mthca_opcode[] = {
 186         [IB_WR_SEND]                 = MTHCA_OPCODE_SEND,
 187         [IB_WR_SEND_WITH_IMM]        = MTHCA_OPCODE_SEND_IMM,
 188         [IB_WR_RDMA_WRITE]           = MTHCA_OPCODE_RDMA_WRITE,
 189         [IB_WR_RDMA_WRITE_WITH_IMM]  = MTHCA_OPCODE_RDMA_WRITE_IMM,
 190         [IB_WR_RDMA_READ]            = MTHCA_OPCODE_RDMA_READ,
 191         [IB_WR_ATOMIC_CMP_AND_SWP]   = MTHCA_OPCODE_ATOMIC_CS,
 192         [IB_WR_ATOMIC_FETCH_AND_ADD] = MTHCA_OPCODE_ATOMIC_FA,
 193 };
 194
 195 static int is_sqp(struct mthca_dev *dev, struct mthca_qp *qp)
 196 {
 197         return qp->qpn >= dev->qp_table.sqp_start &&
 198                 qp->qpn <= dev->qp_table.sqp_start + 3;
 199 }
 200
 201 static int is_qp0(struct mthca_dev *dev, struct mthca_qp *qp)
 202 {
 203         return qp->qpn >= dev->qp_table.sqp_start &&
 204                 qp->qpn <= dev->qp_table.sqp_start + 1;
 205 }
 206
 207 static void *get_recv_wqe(struct mthca_qp *qp, int n)
 208 {
 209         if (qp->is_direct)
 210                 return qp->queue.direct.buf + (n << qp->rq.wqe_shift);
 211         else
 212                 return qp->queue.page_list[(n << qp->rq.wqe_shift) >> PAGE_SHIFT].buf +
 213                         ((n << qp->rq.wqe_shift) & (PAGE_SIZE - 1));
 214 }
 215
 216 static void *get_send_wqe(struct mthca_qp *qp, int n)
 217 {
 218         if (qp->is_direct)
 219                 return qp->queue.direct.buf + qp->send_wqe_offset +
 220                         (n << qp->sq.wqe_shift);
 221         else
 222                 return qp->queue.page_list[(qp->send_wqe_offset +
 223                                             (n << qp->sq.wqe_shift)) >>
 224                                            PAGE_SHIFT].buf +
 225                         ((qp->send_wqe_offset + (n << qp->sq.wqe_shift)) &
 226                          (PAGE_SIZE - 1));
 227 }
 228
 229 static void mthca_wq_reset(struct mthca_wq *wq)
 230 {
 231         wq->next_ind  = 0;
 232         wq->last_comp = wq->max - 1;
 233         wq->head      = 0;
 234         wq->tail      = 0;
 235 }
 236
 237 void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
 238                     enum ib_event_type event_type)
 239 {
 240         struct mthca_qp *qp;
 241         struct ib_event event;
 242
 243         spin_lock(&dev->qp_table.lock);
 244         qp = mthca_array_get(&dev->qp_table.qp, qpn & (dev->limits.num_qps - 1));
 245         if (qp)
 246                 ++qp->refcount;
 247         spin_unlock(&dev->qp_table.lock);
 248
 249         if (!qp) {
 250                 mthca_warn(dev, "Async event for bogus QP %08x\n", qpn);
 251                 return;
 252         }
 253
 254         if (event_type == IB_EVENT_PATH_MIG)
 255                 qp->port = qp->alt_port;
 256
 257         event.device      = &dev->ib_dev;
 258         event.event       = event_type;
 259         event.element.qp  = &qp->ibqp;
 260         if (qp->ibqp.event_handler)
 261                 qp->ibqp.event_handler(&event, qp->ibqp.qp_context);
 262
 263         spin_lock(&dev->qp_table.lock);
 264         if (!--qp->refcount)
 265                 wake_up(&qp->wait);
 266         spin_unlock(&dev->qp_table.lock);
 267 }
 268
 269 static int to_mthca_state(enum ib_qp_state ib_state)
 270 {
 271         switch (ib_state) {
 272         case IB_QPS_RESET: return MTHCA_QP_STATE_RST;
 273         case IB_QPS_INIT:  return MTHCA_QP_STATE_INIT;
 274         case IB_QPS_RTR:   return MTHCA_QP_STATE_RTR;
 275         case IB_QPS_RTS:   return MTHCA_QP_STATE_RTS;
 276         case IB_QPS_SQD:   return MTHCA_QP_STATE_SQD;
 277         case IB_QPS_SQE:   return MTHCA_QP_STATE_SQE;
 278         case IB_QPS_ERR:   return MTHCA_QP_STATE_ERR;
 279         default:                return -1;
 280         }
 281 }
 282
 283 enum { RC, UC, UD, RD, RDEE, MLX, NUM_TRANS };
 284
 285 static int to_mthca_st(int transport)
 286 {
 287         switch (transport) {
 288         case RC:  return MTHCA_QP_ST_RC;
 289         case UC:  return MTHCA_QP_ST_UC;
 290         case UD:  return MTHCA_QP_ST_UD;
 291         case RD:  return MTHCA_QP_ST_RD;
 292         case MLX: return MTHCA_QP_ST_MLX;
 293         default:  return -1;
 294         }
 295 }
 296
 297 static void store_attrs(struct mthca_sqp *sqp, struct ib_qp_attr *attr,
 298                         int attr_mask)
 299 {
 300         if (attr_mask & IB_QP_PKEY_INDEX)
 301                 sqp->pkey_index = attr->pkey_index;
 302         if (attr_mask & IB_QP_QKEY)
 303                 sqp->qkey = attr->qkey;
 304         if (attr_mask & IB_QP_SQ_PSN)
 305                 sqp->send_psn = attr->sq_psn;
 306 }
 307
 308 static void init_port(struct mthca_dev *dev, int port)
 309 {
 310         int err;
 311         u8 status;
 312         struct mthca_init_ib_param param;
 313
 314         memset(&param, 0, sizeof param);
 315
 316         param.port_width = dev->limits.port_width_cap;
 317         param.vl_cap     = dev->limits.vl_cap;
 318         param.mtu_cap    = dev->limits.mtu_cap;
 319         param.gid_cap    = dev->limits.gid_table_len;
 320         param.pkey_cap   = dev->limits.pkey_table_len;
 321
 322         err = mthca_INIT_IB(dev, &param, port, &status);
 323         if (err)
 324                 mthca_warn(dev, "INIT_IB failed, return code %d.\n", err);
 325         if (status)
 326                 mthca_warn(dev, "INIT_IB returned status %02x.\n", status);
 327 }
 328
 329 static __be32 get_hw_access_flags(struct mthca_qp *qp, struct ib_qp_attr *attr,
 330                                   int attr_mask)
 331 {
 332         u8 dest_rd_atomic;
 333         u32 access_flags;
 334         u32 hw_access_flags = 0;
 335
 336         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
 337                 dest_rd_atomic = attr->max_dest_rd_atomic;
 338         else
 339                 dest_rd_atomic = qp->resp_depth;
 340
 341         if (attr_mask & IB_QP_ACCESS_FLAGS)
 342                 access_flags = attr->qp_access_flags;
 343         else
 344                 access_flags = qp->atomic_rd_en;
 345
 346         if (!dest_rd_atomic)
 347                 access_flags &= IB_ACCESS_REMOTE_WRITE;
 348
 349         if (access_flags & IB_ACCESS_REMOTE_READ)
 350                 hw_access_flags |= MTHCA_QP_BIT_RRE;
 351         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
 352                 hw_access_flags |= MTHCA_QP_BIT_RAE;
 353         if (access_flags & IB_ACCESS_REMOTE_WRITE)
 354                 hw_access_flags |= MTHCA_QP_BIT_RWE;
 355
 356         return cpu_to_be32(hw_access_flags);
 357 }
 358
 359 static inline enum ib_qp_state to_ib_qp_state(int mthca_state)
 360 {
 361         switch (mthca_state) {
 362         case MTHCA_QP_STATE_RST:      return IB_QPS_RESET;
 363         case MTHCA_QP_STATE_INIT:     return IB_QPS_INIT;
 364         case MTHCA_QP_STATE_RTR:      return IB_QPS_RTR;
 365         case MTHCA_QP_STATE_RTS:      return IB_QPS_RTS;
 366         case MTHCA_QP_STATE_DRAINING:
 367         case MTHCA_QP_STATE_SQD:      return IB_QPS_SQD;
 368         case MTHCA_QP_STATE_SQE:      return IB_QPS_SQE;
 369         case MTHCA_QP_STATE_ERR:      return IB_QPS_ERR;
 370         default:                      return -1;
 371         }
 372 }
 373
 374 static inline enum ib_mig_state to_ib_mig_state(int mthca_mig_state)
 375 {
 376         switch (mthca_mig_state) {
 377         case 0:  return IB_MIG_ARMED;
 378         case 1:  return IB_MIG_REARM;
 379         case 3:  return IB_MIG_MIGRATED;
 380         default: return -1;
 381         }
 382 }
 383
 384 static int to_ib_qp_access_flags(int mthca_flags)
 385 {
 386         int ib_flags = 0;
 387
 388         if (mthca_flags & MTHCA_QP_BIT_RRE)
 389                 ib_flags |= IB_ACCESS_REMOTE_READ;
 390         if (mthca_flags & MTHCA_QP_BIT_RWE)
 391                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
 392         if (mthca_flags & MTHCA_QP_BIT_RAE)
 393                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
 394
 395         return ib_flags;
 396 }
 397
 398 static void to_ib_ah_attr(struct mthca_dev *dev, struct ib_ah_attr *ib_ah_attr,
 399                                 struct mthca_qp_path *path)
 400 {
 401         memset(ib_ah_attr, 0, sizeof *path);
 402         ib_ah_attr->port_num      = (be32_to_cpu(path->port_pkey) >> 24) & 0x3;
 403
 404         if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->limits.num_ports)
 405                 return;
 406
 407         ib_ah_attr->dlid          = be16_to_cpu(path->rlid);
 408         ib_ah_attr->sl            = be32_to_cpu(path->sl_tclass_flowlabel) >> 28;
 409         ib_ah_attr->src_path_bits = path->g_mylmc & 0x7f;
 410         ib_ah_attr->static_rate   = mthca_rate_to_ib(dev,
 411                                                      path->static_rate & 0xf,
 412                                                      ib_ah_attr->port_num);
 413         ib_ah_attr->ah_flags      = (path->g_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
 414         if (ib_ah_attr->ah_flags) {
 415                 ib_ah_attr->grh.sgid_index = path->mgid_index & (dev->limits.gid_table_len - 1);
 416                 ib_ah_attr->grh.hop_limit  = path->hop_limit;
 417                 ib_ah_attr->grh.traffic_class =
 418                         (be32_to_cpu(path->sl_tclass_flowlabel) >> 20) & 0xff;
 419                 ib_ah_attr->grh.flow_label =
 420                         be32_to_cpu(path->sl_tclass_flowlabel) & 0xfffff;
 421                 memcpy(ib_ah_attr->grh.dgid.raw,
 422                         path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
 423         }
 424 }
 425
 426 int mthca_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
 427                    struct ib_qp_init_attr *qp_init_attr)
 428 {
 429         struct mthca_dev *dev = to_mdev(ibqp->device);
 430         struct mthca_qp *qp = to_mqp(ibqp);
 431         int err;
 432         struct mthca_mailbox *mailbox;
 433         struct mthca_qp_param *qp_param;
 434         struct mthca_qp_context *context;
 435         int mthca_state;
 436         u8 status;
 437
 438         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 439         if (IS_ERR(mailbox))
 440                 return PTR_ERR(mailbox);
 441
 442         err = mthca_QUERY_QP(dev, qp->qpn, 0, mailbox, &status);
 443         if (err)
 444                 goto out;
 445         if (status) {
 446                 mthca_warn(dev, "QUERY_QP returned status %02x\n", status);
 447                 err = -EINVAL;
 448                 goto out;
 449         }
 450
 451         qp_param    = mailbox->buf;
 452         context     = &qp_param->context;
 453         mthca_state = be32_to_cpu(context->flags) >> 28;
 454
 455         qp_attr->qp_state            = to_ib_qp_state(mthca_state);
 456         qp_attr->cur_qp_state        = qp_attr->qp_state;
 457         qp_attr->path_mtu            = context->mtu_msgmax >> 5;
 458         qp_attr->path_mig_state      =
 459                 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
 460         qp_attr->qkey                = be32_to_cpu(context->qkey);
 461         qp_attr->rq_psn              = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
 462         qp_attr->sq_psn              = be32_to_cpu(context->next_send_psn) & 0xffffff;
 463         qp_attr->dest_qp_num         = be32_to_cpu(context->remote_qpn) & 0xffffff;
 464         qp_attr->qp_access_flags     =
 465                 to_ib_qp_access_flags(be32_to_cpu(context->params2));
 466         qp_attr->cap.max_send_wr     = qp->sq.max;
 467         qp_attr->cap.max_recv_wr     = qp->rq.max;
 468         qp_attr->cap.max_send_sge    = qp->sq.max_gs;
 469         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
 470         qp_attr->cap.max_inline_data = qp->max_inline_data;
 471
 472         if (qp->transport == RC || qp->transport == UC) {
 473                 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
 474                 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
 475                 qp_attr->alt_pkey_index =
 476                         be32_to_cpu(context->alt_path.port_pkey) & 0x7f;
 477                 qp_attr->alt_port_num   = qp_attr->alt_ah_attr.port_num;
 478         }
 479
 480         qp_attr->pkey_index = be32_to_cpu(context->pri_path.port_pkey) & 0x7f;
 481         qp_attr->port_num   =
 482                 (be32_to_cpu(context->pri_path.port_pkey) >> 24) & 0x3;
 483
 484         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
 485         qp_attr->sq_draining = mthca_state == MTHCA_QP_STATE_DRAINING;
 486
 487         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
 488
 489         qp_attr->max_dest_rd_atomic =
 490                 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
 491         qp_attr->min_rnr_timer      =
 492                 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
 493         qp_attr->timeout            = context->pri_path.ackto >> 3;
 494         qp_attr->retry_cnt          = (be32_to_cpu(context->params1) >> 16) & 0x7;
 495         qp_attr->rnr_retry          = context->pri_path.rnr_retry >> 5;
 496         qp_attr->alt_timeout        = context->alt_path.ackto >> 3;
 497         qp_init_attr->cap           = qp_attr->cap;
 498
 499 out:
 500         mthca_free_mailbox(dev, mailbox);
 501         return err;
 502 }
 503
 504 static int mthca_path_set(struct mthca_dev *dev, struct ib_ah_attr *ah,
 505                           struct mthca_qp_path *path, u8 port)
 506 {
 507         path->g_mylmc     = ah->src_path_bits & 0x7f;
 508         path->rlid        = cpu_to_be16(ah->dlid);
 509         path->static_rate = mthca_get_rate(dev, ah->static_rate, port);
 510
 511         if (ah->ah_flags & IB_AH_GRH) {
 512                 if (ah->grh.sgid_index >= dev->limits.gid_table_len) {
 513                         mthca_dbg(dev, "sgid_index (%u) too large. max is %d\n",
 514                                   ah->grh.sgid_index, dev->limits.gid_table_len-1);
 515                         return -1;
 516                 }
 517
 518                 path->g_mylmc   |= 1 << 7;
 519                 path->mgid_index = ah->grh.sgid_index;
 520                 path->hop_limit  = ah->grh.hop_limit;
 521                 path->sl_tclass_flowlabel =
 522                         cpu_to_be32((ah->sl << 28)                |
 523                                     (ah->grh.traffic_class << 20) |
 524                                     (ah->grh.flow_label));
 525                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
 526         } else
 527                 path->sl_tclass_flowlabel = cpu_to_be32(ah->sl << 28);
 528
 529         return 0;
 530 }
 531
 532 int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask,
 533                     struct ib_udata *udata)
 534 {
 535         struct mthca_dev *dev = to_mdev(ibqp->device);
 536         struct mthca_qp *qp = to_mqp(ibqp);
 537         enum ib_qp_state cur_state, new_state;
 538         struct mthca_mailbox *mailbox;
 539         struct mthca_qp_param *qp_param;
 540         struct mthca_qp_context *qp_context;
 541         u32 sqd_event = 0;
 542         u8 status;
 543         int err = -EINVAL;
 544
 545         mutex_lock(&qp->mutex);
 546
 547         if (attr_mask & IB_QP_CUR_STATE) {
 548                 cur_state = attr->cur_qp_state;
 549         } else {
 550                 spin_lock_irq(&qp->sq.lock);
 551                 spin_lock(&qp->rq.lock);
 552                 cur_state = qp->state;
 553                 spin_unlock(&qp->rq.lock);
 554                 spin_unlock_irq(&qp->sq.lock);
 555         }
 556
 557         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
 558
 559         if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask)) {
 560                 mthca_dbg(dev, "Bad QP transition (transport %d) "
 561                           "%d->%d with attr 0x%08x\n",
 562                           qp->transport, cur_state, new_state,
 563                           attr_mask);
 564                 goto out;
 565         }
 566
 567         if ((attr_mask & IB_QP_PKEY_INDEX) &&
 568              attr->pkey_index >= dev->limits.pkey_table_len) {
 569                 mthca_dbg(dev, "P_Key index (%u) too large. max is %d\n",
 570                           attr->pkey_index, dev->limits.pkey_table_len-1);
 571                 goto out;
 572         }
 573
 574         if ((attr_mask & IB_QP_PORT) &&
 575             (attr->port_num == 0 || attr->port_num > dev->limits.num_ports)) {
 576                 mthca_dbg(dev, "Port number (%u) is invalid\n", attr->port_num);
 577                 goto out;
 578         }
 579
 580         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
 581             attr->max_rd_atomic > dev->limits.max_qp_init_rdma) {
 582                 mthca_dbg(dev, "Max rdma_atomic as initiator %u too large (max is %d)\n",
 583                           attr->max_rd_atomic, dev->limits.max_qp_init_rdma);
 584                 goto out;
 585         }
 586
 587         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
 588             attr->max_dest_rd_atomic > 1 << dev->qp_table.rdb_shift) {
 589                 mthca_dbg(dev, "Max rdma_atomic as responder %u too large (max %d)\n",
 590                           attr->max_dest_rd_atomic, 1 << dev->qp_table.rdb_shift);
 591                 goto out;
 592         }
 593
 594         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 595         if (IS_ERR(mailbox)) {
 596                 err = PTR_ERR(mailbox);
 597                 goto out;
 598         }
 599         qp_param = mailbox->buf;
 600         qp_context = &qp_param->context;
 601         memset(qp_param, 0, sizeof *qp_param);
 602
 603         qp_context->flags      = cpu_to_be32((to_mthca_state(new_state) << 28) |
 604                                              (to_mthca_st(qp->transport) << 16));
 605         qp_context->flags     |= cpu_to_be32(MTHCA_QP_BIT_DE);
 606         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
 607                 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 608         else {
 609                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE);
 610                 switch (attr->path_mig_state) {
 611                 case IB_MIG_MIGRATED:
 612                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 613                         break;
 614                 case IB_MIG_REARM:
 615                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_REARM << 11);
 616                         break;
 617                 case IB_MIG_ARMED:
 618                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_ARMED << 11);
 619                         break;
 620                 }
 621         }
 622
 623         /* leave tavor_sched_queue as 0 */
 624
 625         if (qp->transport == MLX || qp->transport == UD)
 626                 qp_context->mtu_msgmax = (IB_MTU_2048 << 5) | 11;
 627         else if (attr_mask & IB_QP_PATH_MTU) {
 628                 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_2048) {
 629                         mthca_dbg(dev, "path MTU (%u) is invalid\n",
 630                                   attr->path_mtu);
 631                         goto out_mailbox;
 632                 }
 633                 qp_context->mtu_msgmax = (attr->path_mtu << 5) | 31;
 634         }
 635
 636         if (mthca_is_memfree(dev)) {
 637                 if (qp->rq.max)
 638                         qp_context->rq_size_stride = long_log2(qp->rq.max) << 3;
 639                 qp_context->rq_size_stride |= qp->rq.wqe_shift - 4;
 640
 641                 if (qp->sq.max)
 642                         qp_context->sq_size_stride = long_log2(qp->sq.max) << 3;
 643                 qp_context->sq_size_stride |= qp->sq.wqe_shift - 4;
 644         }
 645
 646         /* leave arbel_sched_queue as 0 */
 647
 648         if (qp->ibqp.uobject)
 649                 qp_context->usr_page =
 650                         cpu_to_be32(to_mucontext(qp->ibqp.uobject->context)->uar.index);
 651         else
 652                 qp_context->usr_page = cpu_to_be32(dev->driver_uar.index);
 653         qp_context->local_qpn  = cpu_to_be32(qp->qpn);
 654         if (attr_mask & IB_QP_DEST_QPN) {
 655                 qp_context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
 656         }
 657
 658         if (qp->transport == MLX)
 659                 qp_context->pri_path.port_pkey |=
 660                         cpu_to_be32(qp->port << 24);
 661         else {
 662                 if (attr_mask & IB_QP_PORT) {
 663                         qp_context->pri_path.port_pkey |=
 664                                 cpu_to_be32(attr->port_num << 24);
 665                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM);
 666                 }
 667         }
 668
 669         if (attr_mask & IB_QP_PKEY_INDEX) {
 670                 qp_context->pri_path.port_pkey |=
 671                         cpu_to_be32(attr->pkey_index);
 672                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX);
 673         }
 674
 675         if (attr_mask & IB_QP_RNR_RETRY) {
 676                 qp_context->alt_path.rnr_retry = qp_context->pri_path.rnr_retry =
 677                         attr->rnr_retry << 5;
 678                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY |
 679                                                         MTHCA_QP_OPTPAR_ALT_RNR_RETRY);
 680         }
 681
 682         if (attr_mask & IB_QP_AV) {
 683                 if (mthca_path_set(dev, &attr->ah_attr, &qp_context->pri_path,
 684                                    attr_mask & IB_QP_PORT ? attr->port_num : qp->port))
 685                         goto out_mailbox;
 686
 687                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH);
 688         }
 689
 690         if (attr_mask & IB_QP_TIMEOUT) {
 691                 qp_context->pri_path.ackto = attr->timeout << 3;
 692                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT);
 693         }
 694
 695         if (attr_mask & IB_QP_ALT_PATH) {
 696                 if (attr->alt_pkey_index >= dev->limits.pkey_table_len) {
 697                         mthca_dbg(dev, "Alternate P_Key index (%u) too large. max is %d\n",
 698                                   attr->alt_pkey_index, dev->limits.pkey_table_len-1);
 699                         goto out_mailbox;
 700                 }
 701
 702                 if (attr->alt_port_num == 0 || attr->alt_port_num > dev->limits.num_ports) {
 703                         mthca_dbg(dev, "Alternate port number (%u) is invalid\n",
 704                                 attr->alt_port_num);
 705                         goto out_mailbox;
 706                 }
 707
 708                 if (mthca_path_set(dev, &attr->alt_ah_attr, &qp_context->alt_path,
 709                                    attr->alt_ah_attr.port_num))
 710                         goto out_mailbox;
 711
 712                 qp_context->alt_path.port_pkey |= cpu_to_be32(attr->alt_pkey_index |
 713                                                               attr->alt_port_num << 24);
 714                 qp_context->alt_path.ackto = attr->alt_timeout << 3;
 715                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ALT_ADDR_PATH);
 716         }
 717
 718         /* leave rdd as 0 */
 719         qp_context->pd         = cpu_to_be32(to_mpd(ibqp->pd)->pd_num);
 720         /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */
 721         qp_context->wqe_lkey   = cpu_to_be32(qp->mr.ibmr.lkey);
 722         qp_context->params1    = cpu_to_be32((MTHCA_ACK_REQ_FREQ << 28) |
 723                                              (MTHCA_FLIGHT_LIMIT << 24) |
 724                                              MTHCA_QP_BIT_SWE);
 725         if (qp->sq_policy == IB_SIGNAL_ALL_WR)
 726                 qp_context->params1 |= cpu_to_be32(MTHCA_QP_BIT_SSC);
 727         if (attr_mask & IB_QP_RETRY_CNT) {
 728                 qp_context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
 729                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT);
 730         }
 731
 732         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
 733                 if (attr->max_rd_atomic) {
 734                         qp_context->params1 |=
 735                                 cpu_to_be32(MTHCA_QP_BIT_SRE |
 736                                             MTHCA_QP_BIT_SAE);
 737                         qp_context->params1 |=
 738                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
 739                 }
 740                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX);
 741         }
 742
 743         if (attr_mask & IB_QP_SQ_PSN)
 744                 qp_context->next_send_psn = cpu_to_be32(attr->sq_psn);
 745         qp_context->cqn_snd = cpu_to_be32(to_mcq(ibqp->send_cq)->cqn);
 746
 747         if (mthca_is_memfree(dev)) {
 748                 qp_context->snd_wqe_base_l = cpu_to_be32(qp->send_wqe_offset);
 749                 qp_context->snd_db_index   = cpu_to_be32(qp->sq.db_index);
 750         }
 751
 752         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
 753                 if (attr->max_dest_rd_atomic)
 754                         qp_context->params2 |=
 755                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
 756
 757                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX);
 758         }
 759
 760         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
 761                 qp_context->params2      |= get_hw_access_flags(qp, attr, attr_mask);
 762                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
 763                                                         MTHCA_QP_OPTPAR_RRE |
 764                                                         MTHCA_QP_OPTPAR_RAE);
 765         }
 766
 767         qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC);
 768
 769         if (ibqp->srq)
 770                 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RIC);
 771
 772         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
 773                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
 774                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT);
 775         }
 776         if (attr_mask & IB_QP_RQ_PSN)
 777                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
 778
 779         qp_context->ra_buff_indx =
 780                 cpu_to_be32(dev->qp_table.rdb_base +
 781                             ((qp->qpn & (dev->limits.num_qps - 1)) * MTHCA_RDB_ENTRY_SIZE <<
 782                              dev->qp_table.rdb_shift));
 783
 784         qp_context->cqn_rcv = cpu_to_be32(to_mcq(ibqp->recv_cq)->cqn);
 785
 786         if (mthca_is_memfree(dev))
 787                 qp_context->rcv_db_index   = cpu_to_be32(qp->rq.db_index);
 788
 789         if (attr_mask & IB_QP_QKEY) {
 790                 qp_context->qkey = cpu_to_be32(attr->qkey);
 791                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY);
 792         }
 793
 794         if (ibqp->srq)
 795                 qp_context->srqn = cpu_to_be32(1 << 24 |
 796                                                to_msrq(ibqp->srq)->srqn);
 797
 798         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
 799             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY               &&
 800             attr->en_sqd_async_notify)
 801                 sqd_event = 1 << 31;
 802
 803         err = mthca_MODIFY_QP(dev, cur_state, new_state, qp->qpn, 0,
 804                               mailbox, sqd_event, &status);
 805         if (err)
 806                 goto out_mailbox;
 807         if (status) {
 808                 mthca_warn(dev, "modify QP %d->%d returned status %02x.\n",
 809                            cur_state, new_state, status);
 810                 err = -EINVAL;
 811                 goto out_mailbox;
 812         }
 813
 814         qp->state = new_state;
 815         if (attr_mask & IB_QP_ACCESS_FLAGS)
 816                 qp->atomic_rd_en = attr->qp_access_flags;
 817         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
 818                 qp->resp_depth = attr->max_dest_rd_atomic;
 819         if (attr_mask & IB_QP_PORT)
 820                 qp->port = attr->port_num;
 821         if (attr_mask & IB_QP_ALT_PATH)
 822                 qp->alt_port = attr->alt_port_num;
 823
 824         if (is_sqp(dev, qp))
 825                 store_attrs(to_msqp(qp), attr, attr_mask);
 826
 827         /*
 828          * If we moved QP0 to RTR, bring the IB link up; if we moved
 829          * QP0 to RESET or ERROR, bring the link back down.
 830          */
 831         if (is_qp0(dev, qp)) {
 832                 if (cur_state != IB_QPS_RTR &&
 833                     new_state == IB_QPS_RTR)
 834                         init_port(dev, qp->port);
 835
 836                 if (cur_state != IB_QPS_RESET &&
 837                     cur_state != IB_QPS_ERR &&
 838                     (new_state == IB_QPS_RESET ||
 839                      new_state == IB_QPS_ERR))
 840                         mthca_CLOSE_IB(dev, qp->port, &status);
 841         }
 842
 843         /*
 844          * If we moved a kernel QP to RESET, clean up all old CQ
 845          * entries and reinitialize the QP.
 846          */
 847         if (new_state == IB_QPS_RESET && !qp->ibqp.uobject) {
 848                 mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq), qp->qpn,
 849                                qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
 850                 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
 851                         mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq), qp->qpn, NULL);
 852
 853                 mthca_wq_reset(&qp->sq);
 854                 qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
 855
 856                 mthca_wq_reset(&qp->rq);
 857                 qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
 858
 859                 if (mthca_is_memfree(dev)) {
 860                         *qp->sq.db = 0;
 861                         *qp->rq.db = 0;
 862                 }
 863         }
 864
 865 out_mailbox:
 866         mthca_free_mailbox(dev, mailbox);
 867
 868 out:
 869         mutex_unlock(&qp->mutex);
 870         return err;
 871 }
 872
 873 static int mthca_max_data_size(struct mthca_dev *dev, struct mthca_qp *qp, int desc_sz)
 874 {
 875         /*
 876          * Calculate the maximum size of WQE s/g segments, excluding
 877          * the next segment and other non-data segments.
 878          */
 879         int max_data_size = desc_sz - sizeof (struct mthca_next_seg);
 880
 881         switch (qp->transport) {
 882         case MLX:
 883                 max_data_size -= 2 * sizeof (struct mthca_data_seg);
 884                 break;
 885
 886         case UD:
 887                 if (mthca_is_memfree(dev))
 888                         max_data_size -= sizeof (struct mthca_arbel_ud_seg);
 889                 else
 890                         max_data_size -= sizeof (struct mthca_tavor_ud_seg);
 891                 break;
 892
 893         default:
 894                 max_data_size -= sizeof (struct mthca_raddr_seg);
 895                 break;
 896         }
 897
 898         return max_data_size;
 899 }
 900
 901 static inline int mthca_max_inline_data(struct mthca_pd *pd, int max_data_size)
 902 {
 903         /* We don't support inline data for kernel QPs (yet). */
 904         return pd->ibpd.uobject ? max_data_size - MTHCA_INLINE_HEADER_SIZE : 0;
 905 }
 906
 907 static void mthca_adjust_qp_caps(struct mthca_dev *dev,
 908                                  struct mthca_pd *pd,
 909                                  struct mthca_qp *qp)
 910 {
 911         int max_data_size = mthca_max_data_size(dev, qp,
 912                                                 min(dev->limits.max_desc_sz,
 913                                                     1 << qp->sq.wqe_shift));
 914
 915         qp->max_inline_data = mthca_max_inline_data(pd, max_data_size);
 916
 917         qp->sq.max_gs = min_t(int, dev->limits.max_sg,
 918                               max_data_size / sizeof (struct mthca_data_seg));
 919         qp->rq.max_gs = min_t(int, dev->limits.max_sg,
 920                                (min(dev->limits.max_desc_sz, 1 << qp->rq.wqe_shift) -
 921                                 sizeof (struct mthca_next_seg)) /
 922                                sizeof (struct mthca_data_seg));
 923 }
 924
 925 /*
 926  * Allocate and register buffer for WQEs.  qp->rq.max, sq.max,
 927  * rq.max_gs and sq.max_gs must all be assigned.
 928  * mthca_alloc_wqe_buf will calculate rq.wqe_shift and
 929  * sq.wqe_shift (as well as send_wqe_offset, is_direct, and
 930  * queue)
 931  */
 932 static int mthca_alloc_wqe_buf(struct mthca_dev *dev,
 933                                struct mthca_pd *pd,
 934                                struct mthca_qp *qp)
 935 {
 936         int size;
 937         int err = -ENOMEM;
 938
 939         size = sizeof (struct mthca_next_seg) +
 940                 qp->rq.max_gs * sizeof (struct mthca_data_seg);
 941
 942         if (size > dev->limits.max_desc_sz)
 943                 return -EINVAL;
 944
 945         for (qp->rq.wqe_shift = 6; 1 << qp->rq.wqe_shift < size;
 946              qp->rq.wqe_shift++)
 947                 ; /* nothing */
 948
 949         size = qp->sq.max_gs * sizeof (struct mthca_data_seg);
 950         switch (qp->transport) {
 951         case MLX:
 952                 size += 2 * sizeof (struct mthca_data_seg);
 953                 break;
 954
 955         case UD:
 956                 size += mthca_is_memfree(dev) ?
 957                         sizeof (struct mthca_arbel_ud_seg) :
 958                         sizeof (struct mthca_tavor_ud_seg);
 959                 break;
 960
 961         case UC:
 962                 size += sizeof (struct mthca_raddr_seg);
 963                 break;
 964
 965         case RC:
 966                 size += sizeof (struct mthca_raddr_seg);
 967                 /*
 968                  * An atomic op will require an atomic segment, a
 969                  * remote address segment and one scatter entry.
 970                  */
 971                 size = max_t(int, size,
 972                              sizeof (struct mthca_atomic_seg) +
 973                              sizeof (struct mthca_raddr_seg) +
 974                              sizeof (struct mthca_data_seg));
 975                 break;
 976
 977         default:
 978                 break;
 979         }
 980
 981         /* Make sure that we have enough space for a bind request */
 982         size = max_t(int, size, sizeof (struct mthca_bind_seg));
 983
 984         size += sizeof (struct mthca_next_seg);
 985
 986         if (size > dev->limits.max_desc_sz)
 987                 return -EINVAL;
 988
 989         for (qp->sq.wqe_shift = 6; 1 << qp->sq.wqe_shift < size;
 990              qp->sq.wqe_shift++)
 991                 ; /* nothing */
 992
 993         qp->send_wqe_offset = ALIGN(qp->rq.max << qp->rq.wqe_shift,
 994                                     1 << qp->sq.wqe_shift);
 995
 996         /*
 997          * If this is a userspace QP, we don't actually have to
 998          * allocate anything.  All we need is to calculate the WQE
 999          * sizes and the send_wqe_offset, so we're done now.
1000          */
1001         if (pd->ibpd.uobject)
1002                 return 0;
1003
1004         size = PAGE_ALIGN(qp->send_wqe_offset +
1005                           (qp->sq.max << qp->sq.wqe_shift));
1006
1007         qp->wrid = kmalloc((qp->rq.max + qp->sq.max) * sizeof (u64),
1008                            GFP_KERNEL);
1009         if (!qp->wrid)
1010                 goto err_out;
1011
1012         err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_QP_SIZE,
1013                               &qp->queue, &qp->is_direct, pd, 0, &qp->mr);
1014         if (err)
1015                 goto err_out;
1016
1017         return 0;
1018
1019 err_out:
1020         kfree(qp->wrid);
1021         return err;
1022 }
1023
1024 static void mthca_free_wqe_buf(struct mthca_dev *dev,
1025                                struct mthca_qp *qp)
1026 {
1027         mthca_buf_free(dev, PAGE_ALIGN(qp->send_wqe_offset +
1028                                        (qp->sq.max << qp->sq.wqe_shift)),
1029                        &qp->queue, qp->is_direct, &qp->mr);
1030         kfree(qp->wrid);
1031 }
1032
1033 static int mthca_map_memfree(struct mthca_dev *dev,
1034                              struct mthca_qp *qp)
1035 {
1036         int ret;
1037
1038         if (mthca_is_memfree(dev)) {
1039                 ret = mthca_table_get(dev, dev->qp_table.qp_table, qp->qpn);
1040                 if (ret)
1041                         return ret;
1042
1043                 ret = mthca_table_get(dev, dev->qp_table.eqp_table, qp->qpn);
1044                 if (ret)
1045                         goto err_qpc;
1046
1047                 ret = mthca_table_get(dev, dev->qp_table.rdb_table,
1048                                       qp->qpn << dev->qp_table.rdb_shift);
1049                 if (ret)
1050                         goto err_eqpc;
1051
1052         }
1053
1054         return 0;
1055
1056 err_eqpc:
1057         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1058
1059 err_qpc:
1060         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1061
1062         return ret;
1063 }
1064
1065 static void mthca_unmap_memfree(struct mthca_dev *dev,
1066                                 struct mthca_qp *qp)
1067 {
1068         mthca_table_put(dev, dev->qp_table.rdb_table,
1069                         qp->qpn << dev->qp_table.rdb_shift);
1070         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1071         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1072 }
1073
1074 static int mthca_alloc_memfree(struct mthca_dev *dev,
1075                                struct mthca_qp *qp)
1076 {
1077         int ret = 0;
1078
1079         if (mthca_is_memfree(dev)) {
1080                 qp->rq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_RQ,
1081                                                  qp->qpn, &qp->rq.db);
1082                 if (qp->rq.db_index < 0)
1083                         return ret;
1084
1085                 qp->sq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SQ,
1086                                                  qp->qpn, &qp->sq.db);
1087                 if (qp->sq.db_index < 0)
1088                         mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1089         }
1090
1091         return ret;
1092 }
1093
1094 static void mthca_free_memfree(struct mthca_dev *dev,
1095                                struct mthca_qp *qp)
1096 {
1097         if (mthca_is_memfree(dev)) {
1098                 mthca_free_db(dev, MTHCA_DB_TYPE_SQ, qp->sq.db_index);
1099                 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1100         }
1101 }
1102
1103 static int mthca_alloc_qp_common(struct mthca_dev *dev,
1104                                  struct mthca_pd *pd,
1105                                  struct mthca_cq *send_cq,
1106                                  struct mthca_cq *recv_cq,
1107                                  enum ib_sig_type send_policy,
1108                                  struct mthca_qp *qp)
1109 {
1110         int ret;
1111         int i;
1112
1113         qp->refcount = 1;
1114         init_waitqueue_head(&qp->wait);
1115         mutex_init(&qp->mutex);
1116         qp->state        = IB_QPS_RESET;
1117         qp->atomic_rd_en = 0;
1118         qp->resp_depth   = 0;
1119         qp->sq_policy    = send_policy;
1120         mthca_wq_reset(&qp->sq);
1121         mthca_wq_reset(&qp->rq);
1122
1123         spin_lock_init(&qp->sq.lock);
1124         spin_lock_init(&qp->rq.lock);
1125
1126         ret = mthca_map_memfree(dev, qp);
1127         if (ret)
1128                 return ret;
1129
1130         ret = mthca_alloc_wqe_buf(dev, pd, qp);
1131         if (ret) {
1132                 mthca_unmap_memfree(dev, qp);
1133                 return ret;
1134         }
1135
1136         mthca_adjust_qp_caps(dev, pd, qp);
1137
1138         /*
1139          * If this is a userspace QP, we're done now.  The doorbells
1140          * will be allocated and buffers will be initialized in
1141          * userspace.
1142          */
1143         if (pd->ibpd.uobject)
1144                 return 0;
1145
1146         ret = mthca_alloc_memfree(dev, qp);
1147         if (ret) {
1148                 mthca_free_wqe_buf(dev, qp);
1149                 mthca_unmap_memfree(dev, qp);
1150                 return ret;
1151         }
1152
1153         if (mthca_is_memfree(dev)) {
1154                 struct mthca_next_seg *next;
1155                 struct mthca_data_seg *scatter;
1156                 int size = (sizeof (struct mthca_next_seg) +
1157                             qp->rq.max_gs * sizeof (struct mthca_data_seg)) / 16;
1158
1159                 for (i = 0; i < qp->rq.max; ++i) {
1160                         next = get_recv_wqe(qp, i);
1161                         next->nda_op = cpu_to_be32(((i + 1) & (qp->rq.max - 1)) <<
1162                                                    qp->rq.wqe_shift);
1163                         next->ee_nds = cpu_to_be32(size);
1164
1165                         for (scatter = (void *) (next + 1);
1166                              (void *) scatter < (void *) next + (1 << qp->rq.wqe_shift);
1167                              ++scatter)
1168                                 scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
1169                 }
1170
1171                 for (i = 0; i < qp->sq.max; ++i) {
1172                         next = get_send_wqe(qp, i);
1173                         next->nda_op = cpu_to_be32((((i + 1) & (qp->sq.max - 1)) <<
1174                                                     qp->sq.wqe_shift) +
1175                                                    qp->send_wqe_offset);
1176                 }
1177         }
1178
1179         qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
1180         qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
1181
1182         return 0;
1183 }
1184
1185 static int mthca_set_qp_size(struct mthca_dev *dev, struct ib_qp_cap *cap,
1186                              struct mthca_pd *pd, struct mthca_qp *qp)
1187 {
1188         int max_data_size = mthca_max_data_size(dev, qp, dev->limits.max_desc_sz);
1189
1190         /* Sanity check QP size before proceeding */
1191         if (cap->max_send_wr     > dev->limits.max_wqes ||
1192             cap->max_recv_wr     > dev->limits.max_wqes ||
1193             cap->max_send_sge    > dev->limits.max_sg   ||
1194             cap->max_recv_sge    > dev->limits.max_sg   ||
1195             cap->max_inline_data > mthca_max_inline_data(pd, max_data_size))
1196                 return -EINVAL;
1197
1198         /*
1199          * For MLX transport we need 2 extra S/G entries:
1200          * one for the header and one for the checksum at the end
1201          */
1202         if (qp->transport == MLX && cap->max_recv_sge + 2 > dev->limits.max_sg)
1203                 return -EINVAL;
1204
1205         if (mthca_is_memfree(dev)) {
1206                 qp->rq.max = cap->max_recv_wr ?
1207                         roundup_pow_of_two(cap->max_recv_wr) : 0;
1208                 qp->sq.max = cap->max_send_wr ?
1209                         roundup_pow_of_two(cap->max_send_wr) : 0;
1210         } else {
1211                 qp->rq.max = cap->max_recv_wr;
1212                 qp->sq.max = cap->max_send_wr;
1213         }
1214
1215         qp->rq.max_gs = cap->max_recv_sge;
1216         qp->sq.max_gs = max_t(int, cap->max_send_sge,
1217                               ALIGN(cap->max_inline_data + MTHCA_INLINE_HEADER_SIZE,
1218                                     MTHCA_INLINE_CHUNK_SIZE) /
1219                               sizeof (struct mthca_data_seg));
1220
1221         return 0;
1222 }
1223
1224 int mthca_alloc_qp(struct mthca_dev *dev,
1225                    struct mthca_pd *pd,
1226                    struct mthca_cq *send_cq,
1227                    struct mthca_cq *recv_cq,
1228                    enum ib_qp_type type,
1229                    enum ib_sig_type send_policy,
1230                    struct ib_qp_cap *cap,
1231                    struct mthca_qp *qp)
1232 {
1233         int err;
1234
1235         switch (type) {
1236         case IB_QPT_RC: qp->transport = RC; break;
1237         case IB_QPT_UC: qp->transport = UC; break;
1238         case IB_QPT_UD: qp->transport = UD; break;
1239         default: return -EINVAL;
1240         }
1241
1242         err = mthca_set_qp_size(dev, cap, pd, qp);
1243         if (err)
1244                 return err;
1245
1246         qp->qpn = mthca_alloc(&dev->qp_table.alloc);
1247         if (qp->qpn == -1)
1248                 return -ENOMEM;
1249
1250         /* initialize port to zero for error-catching. */
1251         qp->port = 0;
1252
1253         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1254                                     send_policy, qp);
1255         if (err) {
1256                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1257                 return err;
1258         }
1259
1260         spin_lock_irq(&dev->qp_table.lock);
1261         mthca_array_set(&dev->qp_table.qp,
1262                         qp->qpn & (dev->limits.num_qps - 1), qp);
1263         spin_unlock_irq(&dev->qp_table.lock);
1264
1265         return 0;
1266 }
1267
1268 static void mthca_lock_cqs(struct mthca_cq *send_cq, struct mthca_cq *recv_cq)
1269 {
1270         if (send_cq == recv_cq)
1271                 spin_lock_irq(&send_cq->lock);
1272         else if (send_cq->cqn < recv_cq->cqn) {
1273                 spin_lock_irq(&send_cq->lock);
1274                 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
1275         } else {
1276                 spin_lock_irq(&recv_cq->lock);
1277                 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
1278         }
1279 }
1280
1281 static void mthca_unlock_cqs(struct mthca_cq *send_cq, struct mthca_cq *recv_cq)
1282 {
1283         if (send_cq == recv_cq)
1284                 spin_unlock_irq(&send_cq->lock);
1285         else if (send_cq->cqn < recv_cq->cqn) {
1286                 spin_unlock(&recv_cq->lock);
1287                 spin_unlock_irq(&send_cq->lock);
1288         } else {
1289                 spin_unlock(&send_cq->lock);
1290                 spin_unlock_irq(&recv_cq->lock);
1291         }
1292 }
1293
1294 int mthca_alloc_sqp(struct mthca_dev *dev,
1295                     struct mthca_pd *pd,
1296                     struct mthca_cq *send_cq,
1297                     struct mthca_cq *recv_cq,
1298                     enum ib_sig_type send_policy,
1299                     struct ib_qp_cap *cap,
1300                     int qpn,
1301                     int port,
1302                     struct mthca_sqp *sqp)
1303 {
1304         u32 mqpn = qpn * 2 + dev->qp_table.sqp_start + port - 1;
1305         int err;
1306
1307         sqp->qp.transport = MLX;
1308         err = mthca_set_qp_size(dev, cap, pd, &sqp->qp);
1309         if (err)
1310                 return err;
1311
1312         sqp->header_buf_size = sqp->qp.sq.max * MTHCA_UD_HEADER_SIZE;
1313         sqp->header_buf = dma_alloc_coherent(&dev->pdev->dev, sqp->header_buf_size,
1314                                              &sqp->header_dma, GFP_KERNEL);
1315         if (!sqp->header_buf)
1316                 return -ENOMEM;
1317
1318         spin_lock_irq(&dev->qp_table.lock);
1319         if (mthca_array_get(&dev->qp_table.qp, mqpn))
1320                 err = -EBUSY;
1321         else
1322                 mthca_array_set(&dev->qp_table.qp, mqpn, sqp);
1323         spin_unlock_irq(&dev->qp_table.lock);
1324
1325         if (err)
1326                 goto err_out;
1327
1328         sqp->qp.port      = port;
1329         sqp->qp.qpn       = mqpn;
1330         sqp->qp.transport = MLX;
1331
1332         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1333                                     send_policy, &sqp->qp);
1334         if (err)
1335                 goto err_out_free;
1336
1337         atomic_inc(&pd->sqp_count);
1338
1339         return 0;
1340
1341  err_out_free:
1342         /*
1343          * Lock CQs here, so that CQ polling code can do QP lookup
1344          * without taking a lock.
1345          */
1346         mthca_lock_cqs(send_cq, recv_cq);
1347
1348         spin_lock(&dev->qp_table.lock);
1349         mthca_array_clear(&dev->qp_table.qp, mqpn);
1350         spin_unlock(&dev->qp_table.lock);
1351
1352         mthca_unlock_cqs(send_cq, recv_cq);
1353
1354  err_out:
1355         dma_free_coherent(&dev->pdev->dev, sqp->header_buf_size,
1356                           sqp->header_buf, sqp->header_dma);
1357
1358         return err;
1359 }
1360
1361 static inline int get_qp_refcount(struct mthca_dev *dev, struct mthca_qp *qp)
1362 {
1363         int c;
1364
1365         spin_lock_irq(&dev->qp_table.lock);
1366         c = qp->refcount;
1367         spin_unlock_irq(&dev->qp_table.lock);
1368
1369         return c;
1370 }
1371
1372 void mthca_free_qp(struct mthca_dev *dev,
1373                    struct mthca_qp *qp)
1374 {
1375         u8 status;
1376         struct mthca_cq *send_cq;
1377         struct mthca_cq *recv_cq;
1378
1379         send_cq = to_mcq(qp->ibqp.send_cq);
1380         recv_cq = to_mcq(qp->ibqp.recv_cq);
1381
1382         /*
1383          * Lock CQs here, so that CQ polling code can do QP lookup
1384          * without taking a lock.
1385          */
1386         mthca_lock_cqs(send_cq, recv_cq);
1387
1388         spin_lock(&dev->qp_table.lock);
1389         mthca_array_clear(&dev->qp_table.qp,
1390                           qp->qpn & (dev->limits.num_qps - 1));
1391         --qp->refcount;
1392         spin_unlock(&dev->qp_table.lock);
1393
1394         mthca_unlock_cqs(send_cq, recv_cq);
1395
1396         wait_event(qp->wait, !get_qp_refcount(dev, qp));
1397
1398         if (qp->state != IB_QPS_RESET)
1399                 mthca_MODIFY_QP(dev, qp->state, IB_QPS_RESET, qp->qpn, 0,
1400                                 NULL, 0, &status);
1401
1402         /*
1403          * If this is a userspace QP, the buffers, MR, CQs and so on
1404          * will be cleaned up in userspace, so all we have to do is
1405          * unref the mem-free tables and free the QPN in our table.
1406          */
1407         if (!qp->ibqp.uobject) {
1408                 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq), qp->qpn,
1409                                qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1410                 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
1411                         mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq), qp->qpn,
1412                                        qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1413
1414                 mthca_free_memfree(dev, qp);
1415                 mthca_free_wqe_buf(dev, qp);
1416         }
1417
1418         mthca_unmap_memfree(dev, qp);
1419
1420         if (is_sqp(dev, qp)) {
1421                 atomic_dec(&(to_mpd(qp->ibqp.pd)->sqp_count));
1422                 dma_free_coherent(&dev->pdev->dev,
1423                                   to_msqp(qp)->header_buf_size,
1424                                   to_msqp(qp)->header_buf,
1425                                   to_msqp(qp)->header_dma);
1426         } else
1427                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1428 }
1429
1430 /* Create UD header for an MLX send and build a data segment for it */
1431 static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp,
1432                             int ind, struct ib_send_wr *wr,
1433                             struct mthca_mlx_seg *mlx,
1434                             struct mthca_data_seg *data)
1435 {
1436         int header_size;
1437         int err;
1438         u16 pkey;
1439
1440         ib_ud_header_init(256, /* assume a MAD */
1441                           mthca_ah_grh_present(to_mah(wr->wr.ud.ah)),
1442                           &sqp->ud_header);
1443
1444         err = mthca_read_ah(dev, to_mah(wr->wr.ud.ah), &sqp->ud_header);
1445         if (err)
1446                 return err;
1447         mlx->flags &= ~cpu_to_be32(MTHCA_NEXT_SOLICIT | 1);
1448         mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MTHCA_MLX_VL15 : 0) |
1449                                   (sqp->ud_header.lrh.destination_lid ==
1450                                    IB_LID_PERMISSIVE ? MTHCA_MLX_SLR : 0) |
1451                                   (sqp->ud_header.lrh.service_level << 8));
1452         mlx->rlid = sqp->ud_header.lrh.destination_lid;
1453         mlx->vcrc = 0;
1454
1455         switch (wr->opcode) {
1456         case IB_WR_SEND:
1457                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1458                 sqp->ud_header.immediate_present = 0;
1459                 break;
1460         case IB_WR_SEND_WITH_IMM:
1461                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1462                 sqp->ud_header.immediate_present = 1;
1463                 sqp->ud_header.immediate_data = wr->imm_data;
1464                 break;
1465         default:
1466                 return -EINVAL;
1467         }
1468
1469         sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
1470         if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1471                 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1472         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1473         if (!sqp->qp.ibqp.qp_num)
1474                 ib_get_cached_pkey(&dev->ib_dev, sqp->qp.port,
1475                                    sqp->pkey_index, &pkey);
1476         else
1477                 ib_get_cached_pkey(&dev->ib_dev, sqp->qp.port,
1478                                    wr->wr.ud.pkey_index, &pkey);
1479         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1480         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1481         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1482         sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1483                                                sqp->qkey : wr->wr.ud.remote_qkey);
1484         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1485
1486         header_size = ib_ud_header_pack(&sqp->ud_header,
1487                                         sqp->header_buf +
1488                                         ind * MTHCA_UD_HEADER_SIZE);
1489
1490         data->byte_count = cpu_to_be32(header_size);
1491         data->lkey       = cpu_to_be32(to_mpd(sqp->qp.ibqp.pd)->ntmr.ibmr.lkey);
1492         data->addr       = cpu_to_be64(sqp->header_dma +
1493                                        ind * MTHCA_UD_HEADER_SIZE);
1494
1495         return 0;
1496 }
1497
1498 static inline int mthca_wq_overflow(struct mthca_wq *wq, int nreq,
1499                                     struct ib_cq *ib_cq)
1500 {
1501         unsigned cur;
1502         struct mthca_cq *cq;
1503
1504         cur = wq->head - wq->tail;
1505         if (likely(cur + nreq < wq->max))
1506                 return 0;
1507
1508         cq = to_mcq(ib_cq);
1509         spin_lock(&cq->lock);
1510         cur = wq->head - wq->tail;
1511         spin_unlock(&cq->lock);
1512
1513         return cur + nreq >= wq->max;
1514 }
1515
1516 int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1517                           struct ib_send_wr **bad_wr)
1518 {
1519         struct mthca_dev *dev = to_mdev(ibqp->device);
1520         struct mthca_qp *qp = to_mqp(ibqp);
1521         void *wqe;
1522         void *prev_wqe;
1523         unsigned long flags;
1524         int err = 0;
1525         int nreq;
1526         int i;
1527         int size;
1528         int size0 = 0;
1529         u32 f0;
1530         int ind;
1531         u8 op0 = 0;
1532
1533         spin_lock_irqsave(&qp->sq.lock, flags);
1534
1535         /* XXX check that state is OK to post send */
1536
1537         ind = qp->sq.next_ind;
1538
1539         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1540                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1541                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1542                                         " %d max, %d nreq)\n", qp->qpn,
1543                                         qp->sq.head, qp->sq.tail,
1544                                         qp->sq.max, nreq);
1545                         err = -ENOMEM;
1546                         *bad_wr = wr;
1547                         goto out;
1548                 }
1549
1550                 wqe = get_send_wqe(qp, ind);
1551                 prev_wqe = qp->sq.last;
1552                 qp->sq.last = wqe;
1553
1554                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1555                 ((struct mthca_next_seg *) wqe)->ee_nds = 0;
1556                 ((struct mthca_next_seg *) wqe)->flags =
1557                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1558                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1559                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1560                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1561                         cpu_to_be32(1);
1562                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1563                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1564                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1565
1566                 wqe += sizeof (struct mthca_next_seg);
1567                 size = sizeof (struct mthca_next_seg) / 16;
1568
1569                 switch (qp->transport) {
1570                 case RC:
1571                         switch (wr->opcode) {
1572                         case IB_WR_ATOMIC_CMP_AND_SWP:
1573                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1574                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1575                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1576                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1577                                         cpu_to_be32(wr->wr.atomic.rkey);
1578                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1579
1580                                 wqe += sizeof (struct mthca_raddr_seg);
1581
1582                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1583                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1584                                                 cpu_to_be64(wr->wr.atomic.swap);
1585                                         ((struct mthca_atomic_seg *) wqe)->compare =
1586                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1587                                 } else {
1588                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1589                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1590                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1591                                 }
1592
1593                                 wqe += sizeof (struct mthca_atomic_seg);
1594                                 size += (sizeof (struct mthca_raddr_seg) +
1595                                          sizeof (struct mthca_atomic_seg)) / 16;
1596                                 break;
1597
1598                         case IB_WR_RDMA_WRITE:
1599                         case IB_WR_RDMA_WRITE_WITH_IMM:
1600                         case IB_WR_RDMA_READ:
1601                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1602                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1603                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1604                                         cpu_to_be32(wr->wr.rdma.rkey);
1605                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1606                                 wqe += sizeof (struct mthca_raddr_seg);
1607                                 size += sizeof (struct mthca_raddr_seg) / 16;
1608                                 break;
1609
1610                         default:
1611                                 /* No extra segments required for sends */
1612                                 break;
1613                         }
1614
1615                         break;
1616
1617                 case UC:
1618                         switch (wr->opcode) {
1619                         case IB_WR_RDMA_WRITE:
1620                         case IB_WR_RDMA_WRITE_WITH_IMM:
1621                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1622                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1623                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1624                                         cpu_to_be32(wr->wr.rdma.rkey);
1625                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1626                                 wqe += sizeof (struct mthca_raddr_seg);
1627                                 size += sizeof (struct mthca_raddr_seg) / 16;
1628                                 break;
1629
1630                         default:
1631                                 /* No extra segments required for sends */
1632                                 break;
1633                         }
1634
1635                         break;
1636
1637                 case UD:
1638                         ((struct mthca_tavor_ud_seg *) wqe)->lkey =
1639                                 cpu_to_be32(to_mah(wr->wr.ud.ah)->key);
1640                         ((struct mthca_tavor_ud_seg *) wqe)->av_addr =
1641                                 cpu_to_be64(to_mah(wr->wr.ud.ah)->avdma);
1642                         ((struct mthca_tavor_ud_seg *) wqe)->dqpn =
1643                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1644                         ((struct mthca_tavor_ud_seg *) wqe)->qkey =
1645                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1646
1647                         wqe += sizeof (struct mthca_tavor_ud_seg);
1648                         size += sizeof (struct mthca_tavor_ud_seg) / 16;
1649                         break;
1650
1651                 case MLX:
1652                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1653                                                wqe - sizeof (struct mthca_next_seg),
1654                                                wqe);
1655                         if (err) {
1656                                 *bad_wr = wr;
1657                                 goto out;
1658                         }
1659                         wqe += sizeof (struct mthca_data_seg);
1660                         size += sizeof (struct mthca_data_seg) / 16;
1661                         break;
1662                 }
1663
1664                 if (wr->num_sge > qp->sq.max_gs) {
1665                         mthca_err(dev, "too many gathers\n");
1666                         err = -EINVAL;
1667                         *bad_wr = wr;
1668                         goto out;
1669                 }
1670
1671                 for (i = 0; i < wr->num_sge; ++i) {
1672                         ((struct mthca_data_seg *) wqe)->byte_count =
1673                                 cpu_to_be32(wr->sg_list[i].length);
1674                         ((struct mthca_data_seg *) wqe)->lkey =
1675                                 cpu_to_be32(wr->sg_list[i].lkey);
1676                         ((struct mthca_data_seg *) wqe)->addr =
1677                                 cpu_to_be64(wr->sg_list[i].addr);
1678                         wqe += sizeof (struct mthca_data_seg);
1679                         size += sizeof (struct mthca_data_seg) / 16;
1680                 }
1681
1682                 /* Add one more inline data segment for ICRC */
1683                 if (qp->transport == MLX) {
1684                         ((struct mthca_data_seg *) wqe)->byte_count =
1685                                 cpu_to_be32((1 << 31) | 4);
1686                         ((u32 *) wqe)[1] = 0;
1687                         wqe += sizeof (struct mthca_data_seg);
1688                         size += sizeof (struct mthca_data_seg) / 16;
1689                 }
1690
1691                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1692
1693                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1694                         mthca_err(dev, "opcode invalid\n");
1695                         err = -EINVAL;
1696                         *bad_wr = wr;
1697                         goto out;
1698                 }
1699
1700                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1701                         cpu_to_be32(((ind << qp->sq.wqe_shift) +
1702                                      qp->send_wqe_offset) |
1703                                     mthca_opcode[wr->opcode]);
1704                 wmb();
1705                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1706                         cpu_to_be32((size0 ? 0 : MTHCA_NEXT_DBD) | size |
1707                                     ((wr->send_flags & IB_SEND_FENCE) ?
1708                                     MTHCA_NEXT_FENCE : 0));
1709
1710                 if (!size0) {
1711                         size0 = size;
1712                         op0   = mthca_opcode[wr->opcode];
1713                         f0    = wr->send_flags & IB_SEND_FENCE ?
1714                                 MTHCA_SEND_DOORBELL_FENCE : 0;
1715                 }
1716
1717                 ++ind;
1718                 if (unlikely(ind >= qp->sq.max))
1719                         ind -= qp->sq.max;
1720         }
1721
1722 out:
1723         if (likely(nreq)) {
1724                 __be32 doorbell[2];
1725
1726                 doorbell[0] = cpu_to_be32(((qp->sq.next_ind << qp->sq.wqe_shift) +
1727                                            qp->send_wqe_offset) | f0 | op0);
1728                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1729
1730                 wmb();
1731
1732                 mthca_write64(doorbell,
1733                               dev->kar + MTHCA_SEND_DOORBELL,
1734                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1735         }
1736
1737         qp->sq.next_ind = ind;
1738         qp->sq.head    += nreq;
1739
1740         spin_unlock_irqrestore(&qp->sq.lock, flags);
1741         return err;
1742 }
1743
1744 int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1745                              struct ib_recv_wr **bad_wr)
1746 {
1747         struct mthca_dev *dev = to_mdev(ibqp->device);
1748         struct mthca_qp *qp = to_mqp(ibqp);
1749         __be32 doorbell[2];
1750         unsigned long flags;
1751         int err = 0;
1752         int nreq;
1753         int i;
1754         int size;
1755         int size0 = 0;
1756         int ind;
1757         void *wqe;
1758         void *prev_wqe;
1759
1760         spin_lock_irqsave(&qp->rq.lock, flags);
1761
1762         /* XXX check that state is OK to post receive */
1763
1764         ind = qp->rq.next_ind;
1765
1766         for (nreq = 0; wr; wr = wr->next) {
1767                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1768                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
1769                                         " %d max, %d nreq)\n", qp->qpn,
1770                                         qp->rq.head, qp->rq.tail,
1771                                         qp->rq.max, nreq);
1772                         err = -ENOMEM;
1773                         *bad_wr = wr;
1774                         goto out;
1775                 }
1776
1777                 wqe = get_recv_wqe(qp, ind);
1778                 prev_wqe = qp->rq.last;
1779                 qp->rq.last = wqe;
1780
1781                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1782                 ((struct mthca_next_seg *) wqe)->ee_nds =
1783                         cpu_to_be32(MTHCA_NEXT_DBD);
1784                 ((struct mthca_next_seg *) wqe)->flags = 0;
1785
1786                 wqe += sizeof (struct mthca_next_seg);
1787                 size = sizeof (struct mthca_next_seg) / 16;
1788
1789                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1790                         err = -EINVAL;
1791                         *bad_wr = wr;
1792                         goto out;
1793                 }
1794
1795                 for (i = 0; i < wr->num_sge; ++i) {
1796                         ((struct mthca_data_seg *) wqe)->byte_count =
1797                                 cpu_to_be32(wr->sg_list[i].length);
1798                         ((struct mthca_data_seg *) wqe)->lkey =
1799                                 cpu_to_be32(wr->sg_list[i].lkey);
1800                         ((struct mthca_data_seg *) wqe)->addr =
1801                                 cpu_to_be64(wr->sg_list[i].addr);
1802                         wqe += sizeof (struct mthca_data_seg);
1803                         size += sizeof (struct mthca_data_seg) / 16;
1804                 }
1805
1806                 qp->wrid[ind] = wr->wr_id;
1807
1808                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1809                         cpu_to_be32((ind << qp->rq.wqe_shift) | 1);
1810                 wmb();
1811                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1812                         cpu_to_be32(MTHCA_NEXT_DBD | size);
1813
1814                 if (!size0)
1815                         size0 = size;
1816
1817                 ++ind;
1818                 if (unlikely(ind >= qp->rq.max))
1819                         ind -= qp->rq.max;
1820
1821                 ++nreq;
1822                 if (unlikely(nreq == MTHCA_TAVOR_MAX_WQES_PER_RECV_DB)) {
1823                         nreq = 0;
1824
1825                         doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1826                         doorbell[1] = cpu_to_be32(qp->qpn << 8);
1827
1828                         wmb();
1829
1830                         mthca_write64(doorbell,
1831                                       dev->kar + MTHCA_RECEIVE_DOORBELL,
1832                                       MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1833
1834                         qp->rq.head += MTHCA_TAVOR_MAX_WQES_PER_RECV_DB;
1835                         size0 = 0;
1836                 }
1837         }
1838
1839 out:
1840         if (likely(nreq)) {
1841                 doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1842                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | nreq);
1843
1844                 wmb();
1845
1846                 mthca_write64(doorbell,
1847                               dev->kar + MTHCA_RECEIVE_DOORBELL,
1848                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1849         }
1850
1851         qp->rq.next_ind = ind;
1852         qp->rq.head    += nreq;
1853
1854         spin_unlock_irqrestore(&qp->rq.lock, flags);
1855         return err;
1856 }
1857
1858 int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1859                           struct ib_send_wr **bad_wr)
1860 {
1861         struct mthca_dev *dev = to_mdev(ibqp->device);
1862         struct mthca_qp *qp = to_mqp(ibqp);
1863         __be32 doorbell[2];
1864         void *wqe;
1865         void *prev_wqe;
1866         unsigned long flags;
1867         int err = 0;
1868         int nreq;
1869         int i;
1870         int size;
1871         int size0 = 0;
1872         u32 f0;
1873         int ind;
1874         u8 op0 = 0;
1875
1876         spin_lock_irqsave(&qp->sq.lock, flags);
1877
1878         /* XXX check that state is OK to post send */
1879
1880         ind = qp->sq.head & (qp->sq.max - 1);
1881
1882         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1883                 if (unlikely(nreq == MTHCA_ARBEL_MAX_WQES_PER_SEND_DB)) {
1884                         nreq = 0;
1885
1886                         doorbell[0] = cpu_to_be32((MTHCA_ARBEL_MAX_WQES_PER_SEND_DB << 24) |
1887                                                   ((qp->sq.head & 0xffff) << 8) |
1888                                                   f0 | op0);
1889                         doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1890
1891                         qp->sq.head += MTHCA_ARBEL_MAX_WQES_PER_SEND_DB;
1892                         size0 = 0;
1893
1894                         /*
1895                          * Make sure that descriptors are written before
1896                          * doorbell record.
1897                          */
1898                         wmb();
1899                         *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
1900
1901                         /*
1902                          * Make sure doorbell record is written before we
1903                          * write MMIO send doorbell.
1904                          */
1905                         wmb();
1906                         mthca_write64(doorbell,
1907                                       dev->kar + MTHCA_SEND_DOORBELL,
1908                                       MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1909                 }
1910
1911                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1912                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1913                                         " %d max, %d nreq)\n", qp->qpn,
1914                                         qp->sq.head, qp->sq.tail,
1915                                         qp->sq.max, nreq);
1916                         err = -ENOMEM;
1917                         *bad_wr = wr;
1918                         goto out;
1919                 }
1920
1921                 wqe = get_send_wqe(qp, ind);
1922                 prev_wqe = qp->sq.last;
1923                 qp->sq.last = wqe;
1924
1925                 ((struct mthca_next_seg *) wqe)->flags =
1926                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1927                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1928                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1929                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1930                         cpu_to_be32(1);
1931                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1932                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1933                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1934
1935                 wqe += sizeof (struct mthca_next_seg);
1936                 size = sizeof (struct mthca_next_seg) / 16;
1937
1938                 switch (qp->transport) {
1939                 case RC:
1940                         switch (wr->opcode) {
1941                         case IB_WR_ATOMIC_CMP_AND_SWP:
1942                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1943                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1944                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1945                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1946                                         cpu_to_be32(wr->wr.atomic.rkey);
1947                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1948
1949                                 wqe += sizeof (struct mthca_raddr_seg);
1950
1951                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1952                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1953                                                 cpu_to_be64(wr->wr.atomic.swap);
1954                                         ((struct mthca_atomic_seg *) wqe)->compare =
1955                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1956                                 } else {
1957                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1958                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1959                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1960                                 }
1961
1962                                 wqe += sizeof (struct mthca_atomic_seg);
1963                                 size += (sizeof (struct mthca_raddr_seg) +
1964                                          sizeof (struct mthca_atomic_seg)) / 16;
1965                                 break;
1966
1967                         case IB_WR_RDMA_READ:
1968                         case IB_WR_RDMA_WRITE:
1969                         case IB_WR_RDMA_WRITE_WITH_IMM:
1970                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1971                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1972                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1973                                         cpu_to_be32(wr->wr.rdma.rkey);
1974                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1975                                 wqe += sizeof (struct mthca_raddr_seg);
1976                                 size += sizeof (struct mthca_raddr_seg) / 16;
1977                                 break;
1978
1979                         default:
1980                                 /* No extra segments required for sends */
1981                                 break;
1982                         }
1983
1984                         break;
1985
1986                 case UC:
1987                         switch (wr->opcode) {
1988                         case IB_WR_RDMA_WRITE:
1989                         case IB_WR_RDMA_WRITE_WITH_IMM:
1990                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1991                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1992                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1993                                         cpu_to_be32(wr->wr.rdma.rkey);
1994                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1995                                 wqe += sizeof (struct mthca_raddr_seg);
1996                                 size += sizeof (struct mthca_raddr_seg) / 16;
1997                                 break;
1998
1999                         default:
2000                                 /* No extra segments required for sends */
2001                                 break;
2002                         }
2003
2004                         break;
2005
2006                 case UD:
2007                         memcpy(((struct mthca_arbel_ud_seg *) wqe)->av,
2008                                to_mah(wr->wr.ud.ah)->av, MTHCA_AV_SIZE);
2009                         ((struct mthca_arbel_ud_seg *) wqe)->dqpn =
2010                                 cpu_to_be32(wr->wr.ud.remote_qpn);
2011                         ((struct mthca_arbel_ud_seg *) wqe)->qkey =
2012                                 cpu_to_be32(wr->wr.ud.remote_qkey);
2013
2014                         wqe += sizeof (struct mthca_arbel_ud_seg);
2015                         size += sizeof (struct mthca_arbel_ud_seg) / 16;
2016                         break;
2017
2018                 case MLX:
2019                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
2020                                                wqe - sizeof (struct mthca_next_seg),
2021                                                wqe);
2022                         if (err) {
2023                                 *bad_wr = wr;
2024                                 goto out;
2025                         }
2026                         wqe += sizeof (struct mthca_data_seg);
2027                         size += sizeof (struct mthca_data_seg) / 16;
2028                         break;
2029                 }
2030
2031                 if (wr->num_sge > qp->sq.max_gs) {
2032                         mthca_err(dev, "too many gathers\n");
2033                         err = -EINVAL;
2034                         *bad_wr = wr;
2035                         goto out;
2036                 }
2037
2038                 for (i = 0; i < wr->num_sge; ++i) {
2039                         ((struct mthca_data_seg *) wqe)->byte_count =
2040                                 cpu_to_be32(wr->sg_list[i].length);
2041                         ((struct mthca_data_seg *) wqe)->lkey =
2042                                 cpu_to_be32(wr->sg_list[i].lkey);
2043                         ((struct mthca_data_seg *) wqe)->addr =
2044                                 cpu_to_be64(wr->sg_list[i].addr);
2045                         wqe += sizeof (struct mthca_data_seg);
2046                         size += sizeof (struct mthca_data_seg) / 16;
2047                 }
2048
2049                 /* Add one more inline data segment for ICRC */
2050                 if (qp->transport == MLX) {
2051                         ((struct mthca_data_seg *) wqe)->byte_count =
2052                                 cpu_to_be32((1 << 31) | 4);
2053                         ((u32 *) wqe)[1] = 0;
2054                         wqe += sizeof (struct mthca_data_seg);
2055                         size += sizeof (struct mthca_data_seg) / 16;
2056                 }
2057
2058                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
2059
2060                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
2061                         mthca_err(dev, "opcode invalid\n");
2062                         err = -EINVAL;
2063                         *bad_wr = wr;
2064                         goto out;
2065                 }
2066
2067                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
2068                         cpu_to_be32(((ind << qp->sq.wqe_shift) +
2069                                      qp->send_wqe_offset) |
2070                                     mthca_opcode[wr->opcode]);
2071                 wmb();
2072                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
2073                         cpu_to_be32(MTHCA_NEXT_DBD | size |
2074                                     ((wr->send_flags & IB_SEND_FENCE) ?
2075                                      MTHCA_NEXT_FENCE : 0));
2076
2077                 if (!size0) {
2078                         size0 = size;
2079                         op0   = mthca_opcode[wr->opcode];
2080                         f0    = wr->send_flags & IB_SEND_FENCE ?
2081                                 MTHCA_SEND_DOORBELL_FENCE : 0;
2082                 }
2083
2084                 ++ind;
2085                 if (unlikely(ind >= qp->sq.max))
2086                         ind -= qp->sq.max;
2087         }
2088
2089 out:
2090         if (likely(nreq)) {
2091                 doorbell[0] = cpu_to_be32((nreq << 24)                  |
2092                                           ((qp->sq.head & 0xffff) << 8) |
2093                                           f0 | op0);
2094                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
2095
2096                 qp->sq.head += nreq;
2097
2098                 /*
2099                  * Make sure that descriptors are written before
2100                  * doorbell record.
2101                  */
2102                 wmb();
2103                 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
2104
2105                 /*
2106                  * Make sure doorbell record is written before we
2107                  * write MMIO send doorbell.
2108                  */
2109                 wmb();
2110                 mthca_write64(doorbell,
2111                               dev->kar + MTHCA_SEND_DOORBELL,
2112                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
2113         }
2114
2115         spin_unlock_irqrestore(&qp->sq.lock, flags);
2116         return err;
2117 }
2118
2119 int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2120                              struct ib_recv_wr **bad_wr)
2121 {
2122         struct mthca_dev *dev = to_mdev(ibqp->device);
2123         struct mthca_qp *qp = to_mqp(ibqp);
2124         unsigned long flags;
2125         int err = 0;
2126         int nreq;
2127         int ind;
2128         int i;
2129         void *wqe;
2130
2131         spin_lock_irqsave(&qp->rq.lock, flags);
2132
2133         /* XXX check that state is OK to post receive */
2134
2135         ind = qp->rq.head & (qp->rq.max - 1);
2136
2137         for (nreq = 0; wr; ++nreq, wr = wr->next) {
2138                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2139                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
2140                                         " %d max, %d nreq)\n", qp->qpn,
2141                                         qp->rq.head, qp->rq.tail,
2142                                         qp->rq.max, nreq);
2143                         err = -ENOMEM;
2144                         *bad_wr = wr;
2145                         goto out;
2146                 }
2147
2148                 wqe = get_recv_wqe(qp, ind);
2149
2150                 ((struct mthca_next_seg *) wqe)->flags = 0;
2151
2152                 wqe += sizeof (struct mthca_next_seg);
2153
2154                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2155                         err = -EINVAL;
2156                         *bad_wr = wr;
2157                         goto out;
2158                 }
2159
2160                 for (i = 0; i < wr->num_sge; ++i) {
2161                         ((struct mthca_data_seg *) wqe)->byte_count =
2162                                 cpu_to_be32(wr->sg_list[i].length);
2163                         ((struct mthca_data_seg *) wqe)->lkey =
2164                                 cpu_to_be32(wr->sg_list[i].lkey);
2165                         ((struct mthca_data_seg *) wqe)->addr =
2166                                 cpu_to_be64(wr->sg_list[i].addr);
2167                         wqe += sizeof (struct mthca_data_seg);
2168                 }
2169
2170                 if (i < qp->rq.max_gs) {
2171                         ((struct mthca_data_seg *) wqe)->byte_count = 0;
2172                         ((struct mthca_data_seg *) wqe)->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
2173                         ((struct mthca_data_seg *) wqe)->addr = 0;
2174                 }
2175
2176                 qp->wrid[ind] = wr->wr_id;
2177
2178                 ++ind;
2179                 if (unlikely(ind >= qp->rq.max))
2180                         ind -= qp->rq.max;
2181         }
2182 out:
2183         if (likely(nreq)) {
2184                 qp->rq.head += nreq;
2185
2186                 /*
2187                  * Make sure that descriptors are written before
2188                  * doorbell record.
2189                  */
2190                 wmb();
2191                 *qp->rq.db = cpu_to_be32(qp->rq.head & 0xffff);
2192         }
2193
2194         spin_unlock_irqrestore(&qp->rq.lock, flags);
2195         return err;
2196 }
2197
2198 void mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
2199                         int index, int *dbd, __be32 *new_wqe)
2200 {
2201         struct mthca_next_seg *next;
2202
2203         /*
2204          * For SRQs, all WQEs generate a CQE, so we're always at the
2205          * end of the doorbell chain.
2206          */
2207         if (qp->ibqp.srq) {
2208                 *new_wqe = 0;
2209                 return;
2210         }
2211
2212         if (is_send)
2213                 next = get_send_wqe(qp, index);
2214         else
2215                 next = get_recv_wqe(qp, index);
2216
2217         *dbd = !!(next->ee_nds & cpu_to_be32(MTHCA_NEXT_DBD));
2218         if (next->ee_nds & cpu_to_be32(0x3f))
2219                 *new_wqe = (next->nda_op & cpu_to_be32(~0x3f)) |
2220                         (next->ee_nds & cpu_to_be32(0x3f));
2221         else
2222                 *new_wqe = 0;
2223 }
2224
2225 int __devinit mthca_init_qp_table(struct mthca_dev *dev)
2226 {
2227         int err;
2228         u8 status;
2229         int i;
2230
2231         spin_lock_init(&dev->qp_table.lock);
2232
2233         /*
2234          * We reserve 2 extra QPs per port for the special QPs.  The
2235          * special QP for port 1 has to be even, so round up.
2236          */
2237         dev->qp_table.sqp_start = (dev->limits.reserved_qps + 1) & ~1UL;
2238         err = mthca_alloc_init(&dev->qp_table.alloc,
2239                                dev->limits.num_qps,
2240                                (1 << 24) - 1,
2241                                dev->qp_table.sqp_start +
2242                                MTHCA_MAX_PORTS * 2);
2243         if (err)
2244                 return err;
2245
2246         err = mthca_array_init(&dev->qp_table.qp,
2247                                dev->limits.num_qps);
2248         if (err) {
2249                 mthca_alloc_cleanup(&dev->qp_table.alloc);
2250                 return err;
2251         }
2252
2253         for (i = 0; i < 2; ++i) {
2254                 err = mthca_CONF_SPECIAL_QP(dev, i ? IB_QPT_GSI : IB_QPT_SMI,
2255                                             dev->qp_table.sqp_start + i * 2,
2256                                             &status);
2257                 if (err)
2258                         goto err_out;
2259                 if (status) {
2260                         mthca_warn(dev, "CONF_SPECIAL_QP returned "
2261                                    "status %02x, aborting.\n",
2262                                    status);
2263                         err = -EINVAL;
2264                         goto err_out;
2265                 }
2266         }
2267         return 0;
2268
2269  err_out:
2270         for (i = 0; i < 2; ++i)
2271                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2272
2273         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2274         mthca_alloc_cleanup(&dev->qp_table.alloc);
2275
2276         return err;
2277 }
2278
2279 void mthca_cleanup_qp_table(struct mthca_dev *dev)
2280 {
2281         int i;
2282         u8 status;
2283
2284         for (i = 0; i < 2; ++i)
2285                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2286
2287         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2288         mthca_alloc_cleanup(&dev->qp_table.alloc);
2289 }