drivers/infiniband/hw/mlx4/qp.c

   1 /*
   2  * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
   3  * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 #include <linux/log2.h>
  35 #include <linux/slab.h>
  36 #include <linux/netdevice.h>
  37
  38 #include <rdma/ib_cache.h>
  39 #include <rdma/ib_pack.h>
  40 #include <rdma/ib_addr.h>
  41
  42 #include <linux/mlx4/qp.h>
  43
  44 #include "mlx4_ib.h"
  45 #include "user.h"
  46
  47 enum {
  48         MLX4_IB_ACK_REQ_FREQ    = 8,
  49 };
  50
  51 enum {
  52         MLX4_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  53         MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  54         MLX4_IB_LINK_TYPE_IB            = 0,
  55         MLX4_IB_LINK_TYPE_ETH           = 1
  56 };
  57
  58 enum {
  59         /*
  60          * Largest possible UD header: send with GRH and immediate
  61          * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
  62          * tag.  (LRH would only use 8 bytes, so Ethernet is the
  63          * biggest case)
  64          */
  65         MLX4_IB_UD_HEADER_SIZE          = 82,
  66         MLX4_IB_LSO_HEADER_SPARE        = 128,
  67 };
  68
  69 enum {
  70         MLX4_IB_IBOE_ETHERTYPE          = 0x8915
  71 };
  72
  73 struct mlx4_ib_sqp {
  74         struct mlx4_ib_qp       qp;
  75         int                     pkey_index;
  76         u32                     qkey;
  77         u32                     send_psn;
  78         struct ib_ud_header     ud_header;
  79         u8                      header_buf[MLX4_IB_UD_HEADER_SIZE];
  80 };
  81
  82 enum {
  83         MLX4_IB_MIN_SQ_STRIDE   = 6,
  84         MLX4_IB_CACHE_LINE_SIZE = 64,
  85 };
  86
  87 static const __be32 mlx4_ib_opcode[] = {
  88         [IB_WR_SEND]                            = cpu_to_be32(MLX4_OPCODE_SEND),
  89         [IB_WR_LSO]                             = cpu_to_be32(MLX4_OPCODE_LSO),
  90         [IB_WR_SEND_WITH_IMM]                   = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
  91         [IB_WR_RDMA_WRITE]                      = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
  92         [IB_WR_RDMA_WRITE_WITH_IMM]             = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
  93         [IB_WR_RDMA_READ]                       = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
  94         [IB_WR_ATOMIC_CMP_AND_SWP]              = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
  95         [IB_WR_ATOMIC_FETCH_AND_ADD]            = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
  96         [IB_WR_SEND_WITH_INV]                   = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
  97         [IB_WR_LOCAL_INV]                       = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
  98         [IB_WR_FAST_REG_MR]                     = cpu_to_be32(MLX4_OPCODE_FMR),
  99         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
 100         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
 101 };
 102
 103 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
 104 {
 105         return container_of(mqp, struct mlx4_ib_sqp, qp);
 106 }
 107
 108 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 109 {
 110         return qp->mqp.qpn >= dev->dev->caps.sqp_start &&
 111                 qp->mqp.qpn <= dev->dev->caps.sqp_start + 3;
 112 }
 113
 114 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 115 {
 116         return qp->mqp.qpn >= dev->dev->caps.sqp_start &&
 117                 qp->mqp.qpn <= dev->dev->caps.sqp_start + 1;
 118 }
 119
 120 static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
 121 {
 122         return mlx4_buf_offset(&qp->buf, offset);
 123 }
 124
 125 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
 126 {
 127         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
 128 }
 129
 130 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
 131 {
 132         return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
 133 }
 134
 135 /*
 136  * Stamp a SQ WQE so that it is invalid if prefetched by marking the
 137  * first four bytes of every 64 byte chunk with
 138  *     0x7FFFFFF | (invalid_ownership_value << 31).
 139  *
 140  * When the max work request size is less than or equal to the WQE
 141  * basic block size, as an optimization, we can stamp all WQEs with
 142  * 0xffffffff, and skip the very first chunk of each WQE.
 143  */
 144 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
 145 {
 146         __be32 *wqe;
 147         int i;
 148         int s;
 149         int ind;
 150         void *buf;
 151         __be32 stamp;
 152         struct mlx4_wqe_ctrl_seg *ctrl;
 153
 154         if (qp->sq_max_wqes_per_wr > 1) {
 155                 s = roundup(size, 1U << qp->sq.wqe_shift);
 156                 for (i = 0; i < s; i += 64) {
 157                         ind = (i >> qp->sq.wqe_shift) + n;
 158                         stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
 159                                                        cpu_to_be32(0xffffffff);
 160                         buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
 161                         wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
 162                         *wqe = stamp;
 163                 }
 164         } else {
 165                 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
 166                 s = (ctrl->fence_size & 0x3f) << 4;
 167                 for (i = 64; i < s; i += 64) {
 168                         wqe = buf + i;
 169                         *wqe = cpu_to_be32(0xffffffff);
 170                 }
 171         }
 172 }
 173
 174 static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
 175 {
 176         struct mlx4_wqe_ctrl_seg *ctrl;
 177         struct mlx4_wqe_inline_seg *inl;
 178         void *wqe;
 179         int s;
 180
 181         ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
 182         s = sizeof(struct mlx4_wqe_ctrl_seg);
 183
 184         if (qp->ibqp.qp_type == IB_QPT_UD) {
 185                 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
 186                 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
 187                 memset(dgram, 0, sizeof *dgram);
 188                 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
 189                 s += sizeof(struct mlx4_wqe_datagram_seg);
 190         }
 191
 192         /* Pad the remainder of the WQE with an inline data segment. */
 193         if (size > s) {
 194                 inl = wqe + s;
 195                 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
 196         }
 197         ctrl->srcrb_flags = 0;
 198         ctrl->fence_size = size / 16;
 199         /*
 200          * Make sure descriptor is fully written before setting ownership bit
 201          * (because HW can start executing as soon as we do).
 202          */
 203         wmb();
 204
 205         ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
 206                 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
 207
 208         stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
 209 }
 210
 211 /* Post NOP WQE to prevent wrap-around in the middle of WR */
 212 static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
 213 {
 214         unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
 215         if (unlikely(s < qp->sq_max_wqes_per_wr)) {
 216                 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
 217                 ind += s;
 218         }
 219         return ind;
 220 }
 221
 222 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
 223 {
 224         struct ib_event event;
 225         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 226
 227         if (type == MLX4_EVENT_TYPE_PATH_MIG)
 228                 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
 229
 230         if (ibqp->event_handler) {
 231                 event.device     = ibqp->device;
 232                 event.element.qp = ibqp;
 233                 switch (type) {
 234                 case MLX4_EVENT_TYPE_PATH_MIG:
 235                         event.event = IB_EVENT_PATH_MIG;
 236                         break;
 237                 case MLX4_EVENT_TYPE_COMM_EST:
 238                         event.event = IB_EVENT_COMM_EST;
 239                         break;
 240                 case MLX4_EVENT_TYPE_SQ_DRAINED:
 241                         event.event = IB_EVENT_SQ_DRAINED;
 242                         break;
 243                 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
 244                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 245                         break;
 246                 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
 247                         event.event = IB_EVENT_QP_FATAL;
 248                         break;
 249                 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
 250                         event.event = IB_EVENT_PATH_MIG_ERR;
 251                         break;
 252                 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 253                         event.event = IB_EVENT_QP_REQ_ERR;
 254                         break;
 255                 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
 256                         event.event = IB_EVENT_QP_ACCESS_ERR;
 257                         break;
 258                 default:
 259                         printk(KERN_WARNING "mlx4_ib: Unexpected event type %d "
 260                                "on QP %06x\n", type, qp->qpn);
 261                         return;
 262                 }
 263
 264                 ibqp->event_handler(&event, ibqp->qp_context);
 265         }
 266 }
 267
 268 static int send_wqe_overhead(enum ib_qp_type type, u32 flags)
 269 {
 270         /*
 271          * UD WQEs must have a datagram segment.
 272          * RC and UC WQEs might have a remote address segment.
 273          * MLX WQEs need two extra inline data segments (for the UD
 274          * header and space for the ICRC).
 275          */
 276         switch (type) {
 277         case IB_QPT_UD:
 278                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 279                         sizeof (struct mlx4_wqe_datagram_seg) +
 280                         ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
 281         case IB_QPT_UC:
 282                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 283                         sizeof (struct mlx4_wqe_raddr_seg);
 284         case IB_QPT_RC:
 285                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 286                         sizeof (struct mlx4_wqe_atomic_seg) +
 287                         sizeof (struct mlx4_wqe_raddr_seg);
 288         case IB_QPT_SMI:
 289         case IB_QPT_GSI:
 290                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 291                         ALIGN(MLX4_IB_UD_HEADER_SIZE +
 292                               DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
 293                                            MLX4_INLINE_ALIGN) *
 294                               sizeof (struct mlx4_wqe_inline_seg),
 295                               sizeof (struct mlx4_wqe_data_seg)) +
 296                         ALIGN(4 +
 297                               sizeof (struct mlx4_wqe_inline_seg),
 298                               sizeof (struct mlx4_wqe_data_seg));
 299         default:
 300                 return sizeof (struct mlx4_wqe_ctrl_seg);
 301         }
 302 }
 303
 304 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 305                        int is_user, int has_rq, struct mlx4_ib_qp *qp)
 306 {
 307         /* Sanity check RQ size before proceeding */
 308         if (cap->max_recv_wr  > dev->dev->caps.max_wqes  ||
 309             cap->max_recv_sge > dev->dev->caps.max_rq_sg)
 310                 return -EINVAL;
 311
 312         if (!has_rq) {
 313                 if (cap->max_recv_wr)
 314                         return -EINVAL;
 315
 316                 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
 317         } else {
 318                 /* HW requires >= 1 RQ entry with >= 1 gather entry */
 319                 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
 320                         return -EINVAL;
 321
 322                 qp->rq.wqe_cnt   = roundup_pow_of_two(max(1U, cap->max_recv_wr));
 323                 qp->rq.max_gs    = roundup_pow_of_two(max(1U, cap->max_recv_sge));
 324                 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
 325         }
 326
 327         cap->max_recv_wr  = qp->rq.max_post = qp->rq.wqe_cnt;
 328         cap->max_recv_sge = qp->rq.max_gs;
 329
 330         return 0;
 331 }
 332
 333 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 334                               enum ib_qp_type type, struct mlx4_ib_qp *qp)
 335 {
 336         int s;
 337
 338         /* Sanity check SQ size before proceeding */
 339         if (cap->max_send_wr     > dev->dev->caps.max_wqes  ||
 340             cap->max_send_sge    > dev->dev->caps.max_sq_sg ||
 341             cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
 342             sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
 343                 return -EINVAL;
 344
 345         /*
 346          * For MLX transport we need 2 extra S/G entries:
 347          * one for the header and one for the checksum at the end
 348          */
 349         if ((type == IB_QPT_SMI || type == IB_QPT_GSI) &&
 350             cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
 351                 return -EINVAL;
 352
 353         s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
 354                 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
 355                 send_wqe_overhead(type, qp->flags);
 356
 357         if (s > dev->dev->caps.max_sq_desc_sz)
 358                 return -EINVAL;
 359
 360         /*
 361          * Hermon supports shrinking WQEs, such that a single work
 362          * request can include multiple units of 1 << wqe_shift.  This
 363          * way, work requests can differ in size, and do not have to
 364          * be a power of 2 in size, saving memory and speeding up send
 365          * WR posting.  Unfortunately, if we do this then the
 366          * wqe_index field in CQEs can't be used to look up the WR ID
 367          * anymore, so we do this only if selective signaling is off.
 368          *
 369          * Further, on 32-bit platforms, we can't use vmap() to make
 370          * the QP buffer virtually contiguous.  Thus we have to use
 371          * constant-sized WRs to make sure a WR is always fully within
 372          * a single page-sized chunk.
 373          *
 374          * Finally, we use NOP work requests to pad the end of the
 375          * work queue, to avoid wrap-around in the middle of WR.  We
 376          * set NEC bit to avoid getting completions with error for
 377          * these NOP WRs, but since NEC is only supported starting
 378          * with firmware 2.2.232, we use constant-sized WRs for older
 379          * firmware.
 380          *
 381          * And, since MLX QPs only support SEND, we use constant-sized
 382          * WRs in this case.
 383          *
 384          * We look for the smallest value of wqe_shift such that the
 385          * resulting number of wqes does not exceed device
 386          * capabilities.
 387          *
 388          * We set WQE size to at least 64 bytes, this way stamping
 389          * invalidates each WQE.
 390          */
 391         if (dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
 392             qp->sq_signal_bits && BITS_PER_LONG == 64 &&
 393             type != IB_QPT_SMI && type != IB_QPT_GSI)
 394                 qp->sq.wqe_shift = ilog2(64);
 395         else
 396                 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
 397
 398         for (;;) {
 399                 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
 400
 401                 /*
 402                  * We need to leave 2 KB + 1 WR of headroom in the SQ to
 403                  * allow HW to prefetch.
 404                  */
 405                 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
 406                 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
 407                                                     qp->sq_max_wqes_per_wr +
 408                                                     qp->sq_spare_wqes);
 409
 410                 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
 411                         break;
 412
 413                 if (qp->sq_max_wqes_per_wr <= 1)
 414                         return -EINVAL;
 415
 416                 ++qp->sq.wqe_shift;
 417         }
 418
 419         qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
 420                              (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
 421                          send_wqe_overhead(type, qp->flags)) /
 422                 sizeof (struct mlx4_wqe_data_seg);
 423
 424         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 425                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 426         if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
 427                 qp->rq.offset = 0;
 428                 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 429         } else {
 430                 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
 431                 qp->sq.offset = 0;
 432         }
 433
 434         cap->max_send_wr  = qp->sq.max_post =
 435                 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
 436         cap->max_send_sge = min(qp->sq.max_gs,
 437                                 min(dev->dev->caps.max_sq_sg,
 438                                     dev->dev->caps.max_rq_sg));
 439         /* We don't support inline sends for kernel QPs (yet) */
 440         cap->max_inline_data = 0;
 441
 442         return 0;
 443 }
 444
 445 static int set_user_sq_size(struct mlx4_ib_dev *dev,
 446                             struct mlx4_ib_qp *qp,
 447                             struct mlx4_ib_create_qp *ucmd)
 448 {
 449         /* Sanity check SQ size before proceeding */
 450         if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes       ||
 451             ucmd->log_sq_stride >
 452                 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
 453             ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
 454                 return -EINVAL;
 455
 456         qp->sq.wqe_cnt   = 1 << ucmd->log_sq_bb_count;
 457         qp->sq.wqe_shift = ucmd->log_sq_stride;
 458
 459         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 460                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 461
 462         return 0;
 463 }
 464
 465 static int qp_has_rq(struct ib_qp_init_attr *attr)
 466 {
 467         if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
 468                 return 0;
 469
 470         return !attr->srq;
 471 }
 472
 473 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
 474                             struct ib_qp_init_attr *init_attr,
 475                             struct ib_udata *udata, int sqpn, struct mlx4_ib_qp *qp)
 476 {
 477         int qpn;
 478         int err;
 479
 480         mutex_init(&qp->mutex);
 481         spin_lock_init(&qp->sq.lock);
 482         spin_lock_init(&qp->rq.lock);
 483         INIT_LIST_HEAD(&qp->gid_list);
 484
 485         qp->state        = IB_QPS_RESET;
 486         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
 487                 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
 488
 489         err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, qp_has_rq(init_attr), qp);
 490         if (err)
 491                 goto err;
 492
 493         if (pd->uobject) {
 494                 struct mlx4_ib_create_qp ucmd;
 495
 496                 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
 497                         err = -EFAULT;
 498                         goto err;
 499                 }
 500
 501                 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
 502
 503                 err = set_user_sq_size(dev, qp, &ucmd);
 504                 if (err)
 505                         goto err;
 506
 507                 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
 508                                        qp->buf_size, 0, 0);
 509                 if (IS_ERR(qp->umem)) {
 510                         err = PTR_ERR(qp->umem);
 511                         goto err;
 512                 }
 513
 514                 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
 515                                     ilog2(qp->umem->page_size), &qp->mtt);
 516                 if (err)
 517                         goto err_buf;
 518
 519                 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
 520                 if (err)
 521                         goto err_mtt;
 522
 523                 if (qp_has_rq(init_attr)) {
 524                         err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
 525                                                   ucmd.db_addr, &qp->db);
 526                         if (err)
 527                                 goto err_mtt;
 528                 }
 529         } else {
 530                 qp->sq_no_prefetch = 0;
 531
 532                 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
 533                         qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
 534
 535                 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
 536                         qp->flags |= MLX4_IB_QP_LSO;
 537
 538                 err = set_kernel_sq_size(dev, &init_attr->cap, init_attr->qp_type, qp);
 539                 if (err)
 540                         goto err;
 541
 542                 if (qp_has_rq(init_attr)) {
 543                         err = mlx4_db_alloc(dev->dev, &qp->db, 0);
 544                         if (err)
 545                                 goto err;
 546
 547                         *qp->db.db = 0;
 548                 }
 549
 550                 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf)) {
 551                         err = -ENOMEM;
 552                         goto err_db;
 553                 }
 554
 555                 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
 556                                     &qp->mtt);
 557                 if (err)
 558                         goto err_buf;
 559
 560                 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
 561                 if (err)
 562                         goto err_mtt;
 563
 564                 qp->sq.wrid  = kmalloc(qp->sq.wqe_cnt * sizeof (u64), GFP_KERNEL);
 565                 qp->rq.wrid  = kmalloc(qp->rq.wqe_cnt * sizeof (u64), GFP_KERNEL);
 566
 567                 if (!qp->sq.wrid || !qp->rq.wrid) {
 568                         err = -ENOMEM;
 569                         goto err_wrid;
 570                 }
 571         }
 572
 573         if (sqpn) {
 574                 qpn = sqpn;
 575         } else {
 576                 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn);
 577                 if (err)
 578                         goto err_wrid;
 579         }
 580
 581         err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
 582         if (err)
 583                 goto err_qpn;
 584
 585         if (init_attr->qp_type == IB_QPT_XRC_TGT)
 586                 qp->mqp.qpn |= (1 << 23);
 587
 588         /*
 589          * Hardware wants QPN written in big-endian order (after
 590          * shifting) for send doorbell.  Precompute this value to save
 591          * a little bit when posting sends.
 592          */
 593         qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
 594
 595         qp->mqp.event = mlx4_ib_qp_event;
 596
 597         return 0;
 598
 599 err_qpn:
 600         if (!sqpn)
 601                 mlx4_qp_release_range(dev->dev, qpn, 1);
 602
 603 err_wrid:
 604         if (pd->uobject) {
 605                 if (qp_has_rq(init_attr))
 606                         mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
 607         } else {
 608                 kfree(qp->sq.wrid);
 609                 kfree(qp->rq.wrid);
 610         }
 611
 612 err_mtt:
 613         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
 614
 615 err_buf:
 616         if (pd->uobject)
 617                 ib_umem_release(qp->umem);
 618         else
 619                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
 620
 621 err_db:
 622         if (!pd->uobject && qp_has_rq(init_attr))
 623                 mlx4_db_free(dev->dev, &qp->db);
 624
 625 err:
 626         return err;
 627 }
 628
 629 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
 630 {
 631         switch (state) {
 632         case IB_QPS_RESET:      return MLX4_QP_STATE_RST;
 633         case IB_QPS_INIT:       return MLX4_QP_STATE_INIT;
 634         case IB_QPS_RTR:        return MLX4_QP_STATE_RTR;
 635         case IB_QPS_RTS:        return MLX4_QP_STATE_RTS;
 636         case IB_QPS_SQD:        return MLX4_QP_STATE_SQD;
 637         case IB_QPS_SQE:        return MLX4_QP_STATE_SQER;
 638         case IB_QPS_ERR:        return MLX4_QP_STATE_ERR;
 639         default:                return -1;
 640         }
 641 }
 642
 643 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
 644         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
 645 {
 646         if (send_cq == recv_cq) {
 647                 spin_lock_irq(&send_cq->lock);
 648                 __acquire(&recv_cq->lock);
 649         } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
 650                 spin_lock_irq(&send_cq->lock);
 651                 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
 652         } else {
 653                 spin_lock_irq(&recv_cq->lock);
 654                 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
 655         }
 656 }
 657
 658 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
 659         __releases(&send_cq->lock) __releases(&recv_cq->lock)
 660 {
 661         if (send_cq == recv_cq) {
 662                 __release(&recv_cq->lock);
 663                 spin_unlock_irq(&send_cq->lock);
 664         } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
 665                 spin_unlock(&recv_cq->lock);
 666                 spin_unlock_irq(&send_cq->lock);
 667         } else {
 668                 spin_unlock(&send_cq->lock);
 669                 spin_unlock_irq(&recv_cq->lock);
 670         }
 671 }
 672
 673 static void del_gid_entries(struct mlx4_ib_qp *qp)
 674 {
 675         struct mlx4_ib_gid_entry *ge, *tmp;
 676
 677         list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
 678                 list_del(&ge->list);
 679                 kfree(ge);
 680         }
 681 }
 682
 683 static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
 684 {
 685         if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
 686                 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
 687         else
 688                 return to_mpd(qp->ibqp.pd);
 689 }
 690
 691 static void get_cqs(struct mlx4_ib_qp *qp,
 692                     struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
 693 {
 694         switch (qp->ibqp.qp_type) {
 695         case IB_QPT_XRC_TGT:
 696                 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
 697                 *recv_cq = *send_cq;
 698                 break;
 699         case IB_QPT_XRC_INI:
 700                 *send_cq = to_mcq(qp->ibqp.send_cq);
 701                 *recv_cq = *send_cq;
 702                 break;
 703         default:
 704                 *send_cq = to_mcq(qp->ibqp.send_cq);
 705                 *recv_cq = to_mcq(qp->ibqp.recv_cq);
 706                 break;
 707         }
 708 }
 709
 710 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
 711                               int is_user)
 712 {
 713         struct mlx4_ib_cq *send_cq, *recv_cq;
 714
 715         if (qp->state != IB_QPS_RESET)
 716                 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
 717                                    MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
 718                         printk(KERN_WARNING "mlx4_ib: modify QP %06x to RESET failed.\n",
 719                                qp->mqp.qpn);
 720
 721         get_cqs(qp, &send_cq, &recv_cq);
 722
 723         mlx4_ib_lock_cqs(send_cq, recv_cq);
 724
 725         if (!is_user) {
 726                 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
 727                                  qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
 728                 if (send_cq != recv_cq)
 729                         __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
 730         }
 731
 732         mlx4_qp_remove(dev->dev, &qp->mqp);
 733
 734         mlx4_ib_unlock_cqs(send_cq, recv_cq);
 735
 736         mlx4_qp_free(dev->dev, &qp->mqp);
 737
 738         if (!is_sqp(dev, qp))
 739                 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
 740
 741         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
 742
 743         if (is_user) {
 744                 if (qp->rq.wqe_cnt)
 745                         mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
 746                                               &qp->db);
 747                 ib_umem_release(qp->umem);
 748         } else {
 749                 kfree(qp->sq.wrid);
 750                 kfree(qp->rq.wrid);
 751                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
 752                 if (qp->rq.wqe_cnt)
 753                         mlx4_db_free(dev->dev, &qp->db);
 754         }
 755
 756         del_gid_entries(qp);
 757 }
 758
 759 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
 760                                 struct ib_qp_init_attr *init_attr,
 761                                 struct ib_udata *udata)
 762 {
 763         struct mlx4_ib_sqp *sqp;
 764         struct mlx4_ib_qp *qp;
 765         int err;
 766         u16 xrcdn = 0;
 767
 768         /*
 769          * We only support LSO and multicast loopback blocking, and
 770          * only for kernel UD QPs.
 771          */
 772         if (init_attr->create_flags & ~(IB_QP_CREATE_IPOIB_UD_LSO |
 773                                         IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK))
 774                 return ERR_PTR(-EINVAL);
 775
 776         if (init_attr->create_flags &&
 777             (udata || init_attr->qp_type != IB_QPT_UD))
 778                 return ERR_PTR(-EINVAL);
 779
 780         switch (init_attr->qp_type) {
 781         case IB_QPT_XRC_TGT:
 782                 pd = to_mxrcd(init_attr->xrcd)->pd;
 783                 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
 784                 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
 785                 /* fall through */
 786         case IB_QPT_XRC_INI:
 787                 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
 788                         return ERR_PTR(-ENOSYS);
 789                 init_attr->recv_cq = init_attr->send_cq;
 790                 /* fall through */
 791         case IB_QPT_RC:
 792         case IB_QPT_UC:
 793         case IB_QPT_UD:
 794         {
 795                 qp = kzalloc(sizeof *qp, GFP_KERNEL);
 796                 if (!qp)
 797                         return ERR_PTR(-ENOMEM);
 798
 799                 err = create_qp_common(to_mdev(pd->device), pd, init_attr, udata, 0, qp);
 800                 if (err) {
 801                         kfree(qp);
 802                         return ERR_PTR(err);
 803                 }
 804
 805                 qp->ibqp.qp_num = qp->mqp.qpn;
 806                 qp->xrcdn = xrcdn;
 807
 808                 break;
 809         }
 810         case IB_QPT_SMI:
 811         case IB_QPT_GSI:
 812         {
 813                 /* Userspace is not allowed to create special QPs: */
 814                 if (udata)
 815                         return ERR_PTR(-EINVAL);
 816
 817                 sqp = kzalloc(sizeof *sqp, GFP_KERNEL);
 818                 if (!sqp)
 819                         return ERR_PTR(-ENOMEM);
 820
 821                 qp = &sqp->qp;
 822
 823                 err = create_qp_common(to_mdev(pd->device), pd, init_attr, udata,
 824                                        to_mdev(pd->device)->dev->caps.sqp_start +
 825                                        (init_attr->qp_type == IB_QPT_SMI ? 0 : 2) +
 826                                        init_attr->port_num - 1,
 827                                        qp);
 828                 if (err) {
 829                         kfree(sqp);
 830                         return ERR_PTR(err);
 831                 }
 832
 833                 qp->port        = init_attr->port_num;
 834                 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
 835
 836                 break;
 837         }
 838         default:
 839                 /* Don't support raw QPs */
 840                 return ERR_PTR(-EINVAL);
 841         }
 842
 843         return &qp->ibqp;
 844 }
 845
 846 int mlx4_ib_destroy_qp(struct ib_qp *qp)
 847 {
 848         struct mlx4_ib_dev *dev = to_mdev(qp->device);
 849         struct mlx4_ib_qp *mqp = to_mqp(qp);
 850         struct mlx4_ib_pd *pd;
 851
 852         if (is_qp0(dev, mqp))
 853                 mlx4_CLOSE_PORT(dev->dev, mqp->port);
 854
 855         pd = get_pd(mqp);
 856         destroy_qp_common(dev, mqp, !!pd->ibpd.uobject);
 857
 858         if (is_sqp(dev, mqp))
 859                 kfree(to_msqp(mqp));
 860         else
 861                 kfree(mqp);
 862
 863         return 0;
 864 }
 865
 866 static int to_mlx4_st(enum ib_qp_type type)
 867 {
 868         switch (type) {
 869         case IB_QPT_RC:         return MLX4_QP_ST_RC;
 870         case IB_QPT_UC:         return MLX4_QP_ST_UC;
 871         case IB_QPT_UD:         return MLX4_QP_ST_UD;
 872         case IB_QPT_XRC_INI:
 873         case IB_QPT_XRC_TGT:    return MLX4_QP_ST_XRC;
 874         case IB_QPT_SMI:
 875         case IB_QPT_GSI:        return MLX4_QP_ST_MLX;
 876         default:                return -1;
 877         }
 878 }
 879
 880 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
 881                                    int attr_mask)
 882 {
 883         u8 dest_rd_atomic;
 884         u32 access_flags;
 885         u32 hw_access_flags = 0;
 886
 887         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
 888                 dest_rd_atomic = attr->max_dest_rd_atomic;
 889         else
 890                 dest_rd_atomic = qp->resp_depth;
 891
 892         if (attr_mask & IB_QP_ACCESS_FLAGS)
 893                 access_flags = attr->qp_access_flags;
 894         else
 895                 access_flags = qp->atomic_rd_en;
 896
 897         if (!dest_rd_atomic)
 898                 access_flags &= IB_ACCESS_REMOTE_WRITE;
 899
 900         if (access_flags & IB_ACCESS_REMOTE_READ)
 901                 hw_access_flags |= MLX4_QP_BIT_RRE;
 902         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
 903                 hw_access_flags |= MLX4_QP_BIT_RAE;
 904         if (access_flags & IB_ACCESS_REMOTE_WRITE)
 905                 hw_access_flags |= MLX4_QP_BIT_RWE;
 906
 907         return cpu_to_be32(hw_access_flags);
 908 }
 909
 910 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
 911                             int attr_mask)
 912 {
 913         if (attr_mask & IB_QP_PKEY_INDEX)
 914                 sqp->pkey_index = attr->pkey_index;
 915         if (attr_mask & IB_QP_QKEY)
 916                 sqp->qkey = attr->qkey;
 917         if (attr_mask & IB_QP_SQ_PSN)
 918                 sqp->send_psn = attr->sq_psn;
 919 }
 920
 921 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
 922 {
 923         path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
 924 }
 925
 926 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
 927                          struct mlx4_qp_path *path, u8 port)
 928 {
 929         int err;
 930         int is_eth = rdma_port_get_link_layer(&dev->ib_dev, port) ==
 931                 IB_LINK_LAYER_ETHERNET;
 932         u8 mac[6];
 933         int is_mcast;
 934         u16 vlan_tag;
 935         int vidx;
 936
 937         path->grh_mylmc     = ah->src_path_bits & 0x7f;
 938         path->rlid          = cpu_to_be16(ah->dlid);
 939         if (ah->static_rate) {
 940                 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
 941                 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
 942                        !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
 943                         --path->static_rate;
 944         } else
 945                 path->static_rate = 0;
 946
 947         if (ah->ah_flags & IB_AH_GRH) {
 948                 if (ah->grh.sgid_index >= dev->dev->caps.gid_table_len[port]) {
 949                         printk(KERN_ERR "sgid_index (%u) too large. max is %d\n",
 950                                ah->grh.sgid_index, dev->dev->caps.gid_table_len[port] - 1);
 951                         return -1;
 952                 }
 953
 954                 path->grh_mylmc |= 1 << 7;
 955                 path->mgid_index = ah->grh.sgid_index;
 956                 path->hop_limit  = ah->grh.hop_limit;
 957                 path->tclass_flowlabel =
 958                         cpu_to_be32((ah->grh.traffic_class << 20) |
 959                                     (ah->grh.flow_label));
 960                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
 961         }
 962
 963         if (is_eth) {
 964                 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
 965                         ((port - 1) << 6) | ((ah->sl & 7) << 3) | ((ah->sl & 8) >> 1);
 966
 967                 if (!(ah->ah_flags & IB_AH_GRH))
 968                         return -1;
 969
 970                 err = mlx4_ib_resolve_grh(dev, ah, mac, &is_mcast, port);
 971                 if (err)
 972                         return err;
 973
 974                 memcpy(path->dmac, mac, 6);
 975                 path->ackto = MLX4_IB_LINK_TYPE_ETH;
 976                 /* use index 0 into MAC table for IBoE */
 977                 path->grh_mylmc &= 0x80;
 978
 979                 vlan_tag = rdma_get_vlan_id(&dev->iboe.gid_table[port - 1][ah->grh.sgid_index]);
 980                 if (vlan_tag < 0x1000) {
 981                         if (mlx4_find_cached_vlan(dev->dev, port, vlan_tag, &vidx))
 982                                 return -ENOENT;
 983
 984                         path->vlan_index = vidx;
 985                         path->fl = 1 << 6;
 986                 }
 987         } else
 988                 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
 989                         ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
 990
 991         return 0;
 992 }
 993
 994 static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 995 {
 996         struct mlx4_ib_gid_entry *ge, *tmp;
 997
 998         list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
 999                 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1000                         ge->added = 1;
1001                         ge->port = qp->port;
1002                 }
1003         }
1004 }
1005
1006 static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
1007                                const struct ib_qp_attr *attr, int attr_mask,
1008                                enum ib_qp_state cur_state, enum ib_qp_state new_state)
1009 {
1010         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1011         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1012         struct mlx4_ib_pd *pd;
1013         struct mlx4_ib_cq *send_cq, *recv_cq;
1014         struct mlx4_qp_context *context;
1015         enum mlx4_qp_optpar optpar = 0;
1016         int sqd_event;
1017         int err = -EINVAL;
1018
1019         context = kzalloc(sizeof *context, GFP_KERNEL);
1020         if (!context)
1021                 return -ENOMEM;
1022
1023         context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
1024                                      (to_mlx4_st(ibqp->qp_type) << 16));
1025
1026         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
1027                 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1028         else {
1029                 optpar |= MLX4_QP_OPTPAR_PM_STATE;
1030                 switch (attr->path_mig_state) {
1031                 case IB_MIG_MIGRATED:
1032                         context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1033                         break;
1034                 case IB_MIG_REARM:
1035                         context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
1036                         break;
1037                 case IB_MIG_ARMED:
1038                         context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
1039                         break;
1040                 }
1041         }
1042
1043         if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
1044                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
1045         else if (ibqp->qp_type == IB_QPT_UD) {
1046                 if (qp->flags & MLX4_IB_QP_LSO)
1047                         context->mtu_msgmax = (IB_MTU_4096 << 5) |
1048                                               ilog2(dev->dev->caps.max_gso_sz);
1049                 else
1050                         context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
1051         } else if (attr_mask & IB_QP_PATH_MTU) {
1052                 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
1053                         printk(KERN_ERR "path MTU (%u) is invalid\n",
1054                                attr->path_mtu);
1055                         goto out;
1056                 }
1057                 context->mtu_msgmax = (attr->path_mtu << 5) |
1058                         ilog2(dev->dev->caps.max_msg_sz);
1059         }
1060
1061         if (qp->rq.wqe_cnt)
1062                 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
1063         context->rq_size_stride |= qp->rq.wqe_shift - 4;
1064
1065         if (qp->sq.wqe_cnt)
1066                 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
1067         context->sq_size_stride |= qp->sq.wqe_shift - 4;
1068
1069         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1070                 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
1071                 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
1072         }
1073
1074         if (qp->ibqp.uobject)
1075                 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
1076         else
1077                 context->usr_page = cpu_to_be32(dev->priv_uar.index);
1078
1079         if (attr_mask & IB_QP_DEST_QPN)
1080                 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
1081
1082         if (attr_mask & IB_QP_PORT) {
1083                 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
1084                     !(attr_mask & IB_QP_AV)) {
1085                         mlx4_set_sched(&context->pri_path, attr->port_num);
1086                         optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
1087                 }
1088         }
1089
1090         if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
1091                 if (dev->counters[qp->port - 1] != -1) {
1092                         context->pri_path.counter_index =
1093                                                 dev->counters[qp->port - 1];
1094                         optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
1095                 } else
1096                         context->pri_path.counter_index = 0xff;
1097         }
1098
1099         if (attr_mask & IB_QP_PKEY_INDEX) {
1100                 context->pri_path.pkey_index = attr->pkey_index;
1101                 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
1102         }
1103
1104         if (attr_mask & IB_QP_AV) {
1105                 if (mlx4_set_path(dev, &attr->ah_attr, &context->pri_path,
1106                                   attr_mask & IB_QP_PORT ? attr->port_num : qp->port))
1107                         goto out;
1108
1109                 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
1110                            MLX4_QP_OPTPAR_SCHED_QUEUE);
1111         }
1112
1113         if (attr_mask & IB_QP_TIMEOUT) {
1114                 context->pri_path.ackto |= attr->timeout << 3;
1115                 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
1116         }
1117
1118         if (attr_mask & IB_QP_ALT_PATH) {
1119                 if (attr->alt_port_num == 0 ||
1120                     attr->alt_port_num > dev->dev->caps.num_ports)
1121                         goto out;
1122
1123                 if (attr->alt_pkey_index >=
1124                     dev->dev->caps.pkey_table_len[attr->alt_port_num])
1125                         goto out;
1126
1127                 if (mlx4_set_path(dev, &attr->alt_ah_attr, &context->alt_path,
1128                                   attr->alt_port_num))
1129                         goto out;
1130
1131                 context->alt_path.pkey_index = attr->alt_pkey_index;
1132                 context->alt_path.ackto = attr->alt_timeout << 3;
1133                 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
1134         }
1135
1136         pd = get_pd(qp);
1137         get_cqs(qp, &send_cq, &recv_cq);
1138         context->pd       = cpu_to_be32(pd->pdn);
1139         context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
1140         context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
1141         context->params1  = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
1142
1143         /* Set "fast registration enabled" for all kernel QPs */
1144         if (!qp->ibqp.uobject)
1145                 context->params1 |= cpu_to_be32(1 << 11);
1146
1147         if (attr_mask & IB_QP_RNR_RETRY) {
1148                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1149                 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
1150         }
1151
1152         if (attr_mask & IB_QP_RETRY_CNT) {
1153                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1154                 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
1155         }
1156
1157         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1158                 if (attr->max_rd_atomic)
1159                         context->params1 |=
1160                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1161                 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
1162         }
1163
1164         if (attr_mask & IB_QP_SQ_PSN)
1165                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1166
1167         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1168                 if (attr->max_dest_rd_atomic)
1169                         context->params2 |=
1170                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1171                 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
1172         }
1173
1174         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
1175                 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
1176                 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
1177         }
1178
1179         if (ibqp->srq)
1180                 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
1181
1182         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1183                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1184                 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
1185         }
1186         if (attr_mask & IB_QP_RQ_PSN)
1187                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1188
1189         if (attr_mask & IB_QP_QKEY) {
1190                 context->qkey = cpu_to_be32(attr->qkey);
1191                 optpar |= MLX4_QP_OPTPAR_Q_KEY;
1192         }
1193
1194         if (ibqp->srq)
1195                 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
1196
1197         if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1198                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1199
1200         if (cur_state == IB_QPS_INIT &&
1201             new_state == IB_QPS_RTR  &&
1202             (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
1203              ibqp->qp_type == IB_QPT_UD)) {
1204                 context->pri_path.sched_queue = (qp->port - 1) << 6;
1205                 if (is_qp0(dev, qp))
1206                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1207                 else
1208                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1209         }
1210
1211         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
1212             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1213                 sqd_event = 1;
1214         else
1215                 sqd_event = 0;
1216
1217         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1218                 context->rlkey |= (1 << 4);
1219
1220         /*
1221          * Before passing a kernel QP to the HW, make sure that the
1222          * ownership bits of the send queue are set and the SQ
1223          * headroom is stamped so that the hardware doesn't start
1224          * processing stale work requests.
1225          */
1226         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1227                 struct mlx4_wqe_ctrl_seg *ctrl;
1228                 int i;
1229
1230                 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
1231                         ctrl = get_send_wqe(qp, i);
1232                         ctrl->owner_opcode = cpu_to_be32(1 << 31);
1233                         if (qp->sq_max_wqes_per_wr == 1)
1234                                 ctrl->fence_size = 1 << (qp->sq.wqe_shift - 4);
1235
1236                         stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
1237                 }
1238         }
1239
1240         err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
1241                              to_mlx4_state(new_state), context, optpar,
1242                              sqd_event, &qp->mqp);
1243         if (err)
1244                 goto out;
1245
1246         qp->state = new_state;
1247
1248         if (attr_mask & IB_QP_ACCESS_FLAGS)
1249                 qp->atomic_rd_en = attr->qp_access_flags;
1250         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1251                 qp->resp_depth = attr->max_dest_rd_atomic;
1252         if (attr_mask & IB_QP_PORT) {
1253                 qp->port = attr->port_num;
1254                 update_mcg_macs(dev, qp);
1255         }
1256         if (attr_mask & IB_QP_ALT_PATH)
1257                 qp->alt_port = attr->alt_port_num;
1258
1259         if (is_sqp(dev, qp))
1260                 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
1261
1262         /*
1263          * If we moved QP0 to RTR, bring the IB link up; if we moved
1264          * QP0 to RESET or ERROR, bring the link back down.
1265          */
1266         if (is_qp0(dev, qp)) {
1267                 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
1268                         if (mlx4_INIT_PORT(dev->dev, qp->port))
1269                                 printk(KERN_WARNING "INIT_PORT failed for port %d\n",
1270                                        qp->port);
1271
1272                 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
1273                     (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
1274                         mlx4_CLOSE_PORT(dev->dev, qp->port);
1275         }
1276
1277         /*
1278          * If we moved a kernel QP to RESET, clean up all old CQ
1279          * entries and reinitialize the QP.
1280          */
1281         if (new_state == IB_QPS_RESET && !ibqp->uobject) {
1282                 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1283                                  ibqp->srq ? to_msrq(ibqp->srq): NULL);
1284                 if (send_cq != recv_cq)
1285                         mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1286
1287                 qp->rq.head = 0;
1288                 qp->rq.tail = 0;
1289                 qp->sq.head = 0;
1290                 qp->sq.tail = 0;
1291                 qp->sq_next_wqe = 0;
1292                 if (qp->rq.wqe_cnt)
1293                         *qp->db.db  = 0;
1294         }
1295
1296 out:
1297         kfree(context);
1298         return err;
1299 }
1300
1301 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1302                       int attr_mask, struct ib_udata *udata)
1303 {
1304         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1305         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1306         enum ib_qp_state cur_state, new_state;
1307         int err = -EINVAL;
1308
1309         mutex_lock(&qp->mutex);
1310
1311         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
1312         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1313
1314         if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask))
1315                 goto out;
1316
1317         if ((attr_mask & IB_QP_PORT) &&
1318             (attr->port_num == 0 || attr->port_num > dev->dev->caps.num_ports)) {
1319                 goto out;
1320         }
1321
1322         if (attr_mask & IB_QP_PKEY_INDEX) {
1323                 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1324                 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p])
1325                         goto out;
1326         }
1327
1328         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
1329             attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
1330                 goto out;
1331         }
1332
1333         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
1334             attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
1335                 goto out;
1336         }
1337
1338         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1339                 err = 0;
1340                 goto out;
1341         }
1342
1343         err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
1344
1345 out:
1346         mutex_unlock(&qp->mutex);
1347         return err;
1348 }
1349
1350 static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_send_wr *wr,
1351                             void *wqe, unsigned *mlx_seg_len)
1352 {
1353         struct ib_device *ib_dev = sqp->qp.ibqp.device;
1354         struct mlx4_wqe_mlx_seg *mlx = wqe;
1355         struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
1356         struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
1357         union ib_gid sgid;
1358         u16 pkey;
1359         int send_size;
1360         int header_size;
1361         int spc;
1362         int i;
1363         int is_eth;
1364         int is_vlan = 0;
1365         int is_grh;
1366         u16 vlan;
1367
1368         send_size = 0;
1369         for (i = 0; i < wr->num_sge; ++i)
1370                 send_size += wr->sg_list[i].length;
1371
1372         is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
1373         is_grh = mlx4_ib_ah_grh_present(ah);
1374         if (is_eth) {
1375                 ib_get_cached_gid(ib_dev, be32_to_cpu(ah->av.ib.port_pd) >> 24,
1376                                   ah->av.ib.gid_index, &sgid);
1377                 vlan = rdma_get_vlan_id(&sgid);
1378                 is_vlan = vlan < 0x1000;
1379         }
1380         ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh, 0, &sqp->ud_header);
1381
1382         if (!is_eth) {
1383                 sqp->ud_header.lrh.service_level =
1384                         be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
1385                 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
1386                 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
1387         }
1388
1389         if (is_grh) {
1390                 sqp->ud_header.grh.traffic_class =
1391                         (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
1392                 sqp->ud_header.grh.flow_label    =
1393                         ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
1394                 sqp->ud_header.grh.hop_limit     = ah->av.ib.hop_limit;
1395                 ib_get_cached_gid(ib_dev, be32_to_cpu(ah->av.ib.port_pd) >> 24,
1396                                   ah->av.ib.gid_index, &sqp->ud_header.grh.source_gid);
1397                 memcpy(sqp->ud_header.grh.destination_gid.raw,
1398                        ah->av.ib.dgid, 16);
1399         }
1400
1401         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
1402
1403         if (!is_eth) {
1404                 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
1405                                           (sqp->ud_header.lrh.destination_lid ==
1406                                            IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
1407                                           (sqp->ud_header.lrh.service_level << 8));
1408                 mlx->rlid = sqp->ud_header.lrh.destination_lid;
1409         }
1410
1411         switch (wr->opcode) {
1412         case IB_WR_SEND:
1413                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
1414                 sqp->ud_header.immediate_present = 0;
1415                 break;
1416         case IB_WR_SEND_WITH_IMM:
1417                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1418                 sqp->ud_header.immediate_present = 1;
1419                 sqp->ud_header.immediate_data    = wr->ex.imm_data;
1420                 break;
1421         default:
1422                 return -EINVAL;
1423         }
1424
1425         if (is_eth) {
1426                 u8 *smac;
1427
1428                 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
1429                 /* FIXME: cache smac value? */
1430                 smac = to_mdev(sqp->qp.ibqp.device)->iboe.netdevs[sqp->qp.port - 1]->dev_addr;
1431                 memcpy(sqp->ud_header.eth.smac_h, smac, 6);
1432                 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
1433                         mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
1434                 if (!is_vlan) {
1435                         sqp->ud_header.eth.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
1436                 } else {
1437                         u16 pcp;
1438
1439                         sqp->ud_header.vlan.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
1440                         pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 27 & 3) << 13;
1441                         sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
1442                 }
1443         } else {
1444                 sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
1445                 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1446                         sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1447         }
1448         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1449         if (!sqp->qp.ibqp.qp_num)
1450                 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
1451         else
1452                 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->wr.ud.pkey_index, &pkey);
1453         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1454         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1455         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1456         sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1457                                                sqp->qkey : wr->wr.ud.remote_qkey);
1458         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1459
1460         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
1461
1462         if (0) {
1463                 printk(KERN_ERR "built UD header of size %d:\n", header_size);
1464                 for (i = 0; i < header_size / 4; ++i) {
1465                         if (i % 8 == 0)
1466                                 printk("  [%02x] ", i * 4);
1467                         printk(" %08x",
1468                                be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
1469                         if ((i + 1) % 8 == 0)
1470                                 printk("\n");
1471                 }
1472                 printk("\n");
1473         }
1474
1475         /*
1476          * Inline data segments may not cross a 64 byte boundary.  If
1477          * our UD header is bigger than the space available up to the
1478          * next 64 byte boundary in the WQE, use two inline data
1479          * segments to hold the UD header.
1480          */
1481         spc = MLX4_INLINE_ALIGN -
1482                 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
1483         if (header_size <= spc) {
1484                 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
1485                 memcpy(inl + 1, sqp->header_buf, header_size);
1486                 i = 1;
1487         } else {
1488                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
1489                 memcpy(inl + 1, sqp->header_buf, spc);
1490
1491                 inl = (void *) (inl + 1) + spc;
1492                 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
1493                 /*
1494                  * Need a barrier here to make sure all the data is
1495                  * visible before the byte_count field is set.
1496                  * Otherwise the HCA prefetcher could grab the 64-byte
1497                  * chunk with this inline segment and get a valid (!=
1498                  * 0xffffffff) byte count but stale data, and end up
1499                  * generating a packet with bad headers.
1500                  *
1501                  * The first inline segment's byte_count field doesn't
1502                  * need a barrier, because it comes after a
1503                  * control/MLX segment and therefore is at an offset
1504                  * of 16 mod 64.
1505                  */
1506                 wmb();
1507                 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
1508                 i = 2;
1509         }
1510
1511         *mlx_seg_len =
1512                 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
1513         return 0;
1514 }
1515
1516 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
1517 {
1518         unsigned cur;
1519         struct mlx4_ib_cq *cq;
1520
1521         cur = wq->head - wq->tail;
1522         if (likely(cur + nreq < wq->max_post))
1523                 return 0;
1524
1525         cq = to_mcq(ib_cq);
1526         spin_lock(&cq->lock);
1527         cur = wq->head - wq->tail;
1528         spin_unlock(&cq->lock);
1529
1530         return cur + nreq >= wq->max_post;
1531 }
1532
1533 static __be32 convert_access(int acc)
1534 {
1535         return (acc & IB_ACCESS_REMOTE_ATOMIC ? cpu_to_be32(MLX4_WQE_FMR_PERM_ATOMIC)       : 0) |
1536                (acc & IB_ACCESS_REMOTE_WRITE  ? cpu_to_be32(MLX4_WQE_FMR_PERM_REMOTE_WRITE) : 0) |
1537                (acc & IB_ACCESS_REMOTE_READ   ? cpu_to_be32(MLX4_WQE_FMR_PERM_REMOTE_READ)  : 0) |
1538                (acc & IB_ACCESS_LOCAL_WRITE   ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE)  : 0) |
1539                 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
1540 }
1541
1542 static void set_fmr_seg(struct mlx4_wqe_fmr_seg *fseg, struct ib_send_wr *wr)
1543 {
1544         struct mlx4_ib_fast_reg_page_list *mfrpl = to_mfrpl(wr->wr.fast_reg.page_list);
1545         int i;
1546
1547         for (i = 0; i < wr->wr.fast_reg.page_list_len; ++i)
1548                 mfrpl->mapped_page_list[i] =
1549                         cpu_to_be64(wr->wr.fast_reg.page_list->page_list[i] |
1550                                     MLX4_MTT_FLAG_PRESENT);
1551
1552         fseg->flags             = convert_access(wr->wr.fast_reg.access_flags);
1553         fseg->mem_key           = cpu_to_be32(wr->wr.fast_reg.rkey);
1554         fseg->buf_list          = cpu_to_be64(mfrpl->map);
1555         fseg->start_addr        = cpu_to_be64(wr->wr.fast_reg.iova_start);
1556         fseg->reg_len           = cpu_to_be64(wr->wr.fast_reg.length);
1557         fseg->offset            = 0; /* XXX -- is this just for ZBVA? */
1558         fseg->page_size         = cpu_to_be32(wr->wr.fast_reg.page_shift);
1559         fseg->reserved[0]       = 0;
1560         fseg->reserved[1]       = 0;
1561 }
1562
1563 static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
1564 {
1565         iseg->flags     = 0;
1566         iseg->mem_key   = cpu_to_be32(rkey);
1567         iseg->guest_id  = 0;
1568         iseg->pa        = 0;
1569 }
1570
1571 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
1572                                           u64 remote_addr, u32 rkey)
1573 {
1574         rseg->raddr    = cpu_to_be64(remote_addr);
1575         rseg->rkey     = cpu_to_be32(rkey);
1576         rseg->reserved = 0;
1577 }
1578
1579 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, struct ib_send_wr *wr)
1580 {
1581         if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1582                 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap);
1583                 aseg->compare  = cpu_to_be64(wr->wr.atomic.compare_add);
1584         } else if (wr->opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
1585                 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
1586                 aseg->compare  = cpu_to_be64(wr->wr.atomic.compare_add_mask);
1587         } else {
1588                 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
1589                 aseg->compare  = 0;
1590         }
1591
1592 }
1593
1594 static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
1595                                   struct ib_send_wr *wr)
1596 {
1597         aseg->swap_add          = cpu_to_be64(wr->wr.atomic.swap);
1598         aseg->swap_add_mask     = cpu_to_be64(wr->wr.atomic.swap_mask);
1599         aseg->compare           = cpu_to_be64(wr->wr.atomic.compare_add);
1600         aseg->compare_mask      = cpu_to_be64(wr->wr.atomic.compare_add_mask);
1601 }
1602
1603 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
1604                              struct ib_send_wr *wr)
1605 {
1606         memcpy(dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof (struct mlx4_av));
1607         dseg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1608         dseg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
1609         dseg->vlan = to_mah(wr->wr.ud.ah)->av.eth.vlan;
1610         memcpy(dseg->mac, to_mah(wr->wr.ud.ah)->av.eth.mac, 6);
1611 }
1612
1613 static void set_mlx_icrc_seg(void *dseg)
1614 {
1615         u32 *t = dseg;
1616         struct mlx4_wqe_inline_seg *iseg = dseg;
1617
1618         t[1] = 0;
1619
1620         /*
1621          * Need a barrier here before writing the byte_count field to
1622          * make sure that all the data is visible before the
1623          * byte_count field is set.  Otherwise, if the segment begins
1624          * a new cacheline, the HCA prefetcher could grab the 64-byte
1625          * chunk and get a valid (!= * 0xffffffff) byte count but
1626          * stale data, and end up sending the wrong data.
1627          */
1628         wmb();
1629
1630         iseg->byte_count = cpu_to_be32((1 << 31) | 4);
1631 }
1632
1633 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
1634 {
1635         dseg->lkey       = cpu_to_be32(sg->lkey);
1636         dseg->addr       = cpu_to_be64(sg->addr);
1637
1638         /*
1639          * Need a barrier here before writing the byte_count field to
1640          * make sure that all the data is visible before the
1641          * byte_count field is set.  Otherwise, if the segment begins
1642          * a new cacheline, the HCA prefetcher could grab the 64-byte
1643          * chunk and get a valid (!= * 0xffffffff) byte count but
1644          * stale data, and end up sending the wrong data.
1645          */
1646         wmb();
1647
1648         dseg->byte_count = cpu_to_be32(sg->length);
1649 }
1650
1651 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
1652 {
1653         dseg->byte_count = cpu_to_be32(sg->length);
1654         dseg->lkey       = cpu_to_be32(sg->lkey);
1655         dseg->addr       = cpu_to_be64(sg->addr);
1656 }
1657
1658 static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_send_wr *wr,
1659                          struct mlx4_ib_qp *qp, unsigned *lso_seg_len,
1660                          __be32 *lso_hdr_sz, __be32 *blh)
1661 {
1662         unsigned halign = ALIGN(sizeof *wqe + wr->wr.ud.hlen, 16);
1663
1664         if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
1665                 *blh = cpu_to_be32(1 << 6);
1666
1667         if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
1668                      wr->num_sge > qp->sq.max_gs - (halign >> 4)))
1669                 return -EINVAL;
1670
1671         memcpy(wqe->header, wr->wr.ud.header, wr->wr.ud.hlen);
1672
1673         *lso_hdr_sz  = cpu_to_be32((wr->wr.ud.mss - wr->wr.ud.hlen) << 16 |
1674                                    wr->wr.ud.hlen);
1675         *lso_seg_len = halign;
1676         return 0;
1677 }
1678
1679 static __be32 send_ieth(struct ib_send_wr *wr)
1680 {
1681         switch (wr->opcode) {
1682         case IB_WR_SEND_WITH_IMM:
1683         case IB_WR_RDMA_WRITE_WITH_IMM:
1684                 return wr->ex.imm_data;
1685
1686         case IB_WR_SEND_WITH_INV:
1687                 return cpu_to_be32(wr->ex.invalidate_rkey);
1688
1689         default:
1690                 return 0;
1691         }
1692 }
1693
1694 int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1695                       struct ib_send_wr **bad_wr)
1696 {
1697         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1698         void *wqe;
1699         struct mlx4_wqe_ctrl_seg *ctrl;
1700         struct mlx4_wqe_data_seg *dseg;
1701         unsigned long flags;
1702         int nreq;
1703         int err = 0;
1704         unsigned ind;
1705         int uninitialized_var(stamp);
1706         int uninitialized_var(size);
1707         unsigned uninitialized_var(seglen);
1708         __be32 dummy;
1709         __be32 *lso_wqe;
1710         __be32 uninitialized_var(lso_hdr_sz);
1711         __be32 blh;
1712         int i;
1713
1714         spin_lock_irqsave(&qp->sq.lock, flags);
1715
1716         ind = qp->sq_next_wqe;
1717
1718         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1719                 lso_wqe = &dummy;
1720                 blh = 0;
1721
1722                 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1723                         err = -ENOMEM;
1724                         *bad_wr = wr;
1725                         goto out;
1726                 }
1727
1728                 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
1729                         err = -EINVAL;
1730                         *bad_wr = wr;
1731                         goto out;
1732                 }
1733
1734                 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
1735                 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
1736
1737                 ctrl->srcrb_flags =
1738                         (wr->send_flags & IB_SEND_SIGNALED ?
1739                          cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
1740                         (wr->send_flags & IB_SEND_SOLICITED ?
1741                          cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
1742                         ((wr->send_flags & IB_SEND_IP_CSUM) ?
1743                          cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
1744                                      MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
1745                         qp->sq_signal_bits;
1746
1747                 ctrl->imm = send_ieth(wr);
1748
1749                 wqe += sizeof *ctrl;
1750                 size = sizeof *ctrl / 16;
1751
1752                 switch (ibqp->qp_type) {
1753                 case IB_QPT_RC:
1754                 case IB_QPT_UC:
1755                         switch (wr->opcode) {
1756                         case IB_WR_ATOMIC_CMP_AND_SWP:
1757                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1758                         case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
1759                                 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
1760                                               wr->wr.atomic.rkey);
1761                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
1762
1763                                 set_atomic_seg(wqe, wr);
1764                                 wqe  += sizeof (struct mlx4_wqe_atomic_seg);
1765
1766                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
1767                                          sizeof (struct mlx4_wqe_atomic_seg)) / 16;
1768
1769                                 break;
1770
1771                         case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
1772                                 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
1773                                               wr->wr.atomic.rkey);
1774                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
1775
1776                                 set_masked_atomic_seg(wqe, wr);
1777                                 wqe  += sizeof (struct mlx4_wqe_masked_atomic_seg);
1778
1779                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
1780                                          sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
1781
1782                                 break;
1783
1784                         case IB_WR_RDMA_READ:
1785                         case IB_WR_RDMA_WRITE:
1786                         case IB_WR_RDMA_WRITE_WITH_IMM:
1787                                 set_raddr_seg(wqe, wr->wr.rdma.remote_addr,
1788                                               wr->wr.rdma.rkey);
1789                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
1790                                 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
1791                                 break;
1792
1793                         case IB_WR_LOCAL_INV:
1794                                 ctrl->srcrb_flags |=
1795                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
1796                                 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
1797                                 wqe  += sizeof (struct mlx4_wqe_local_inval_seg);
1798                                 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
1799                                 break;
1800
1801                         case IB_WR_FAST_REG_MR:
1802                                 ctrl->srcrb_flags |=
1803                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
1804                                 set_fmr_seg(wqe, wr);
1805                                 wqe  += sizeof (struct mlx4_wqe_fmr_seg);
1806                                 size += sizeof (struct mlx4_wqe_fmr_seg) / 16;
1807                                 break;
1808
1809                         default:
1810                                 /* No extra segments required for sends */
1811                                 break;
1812                         }
1813                         break;
1814
1815                 case IB_QPT_UD:
1816                         set_datagram_seg(wqe, wr);
1817                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
1818                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
1819
1820                         if (wr->opcode == IB_WR_LSO) {
1821                                 err = build_lso_seg(wqe, wr, qp, &seglen, &lso_hdr_sz, &blh);
1822                                 if (unlikely(err)) {
1823                                         *bad_wr = wr;
1824                                         goto out;
1825                                 }
1826                                 lso_wqe = (__be32 *) wqe;
1827                                 wqe  += seglen;
1828                                 size += seglen / 16;
1829                         }
1830                         break;
1831
1832                 case IB_QPT_SMI:
1833                 case IB_QPT_GSI:
1834                         err = build_mlx_header(to_msqp(qp), wr, ctrl, &seglen);
1835                         if (unlikely(err)) {
1836                                 *bad_wr = wr;
1837                                 goto out;
1838                         }
1839                         wqe  += seglen;
1840                         size += seglen / 16;
1841                         break;
1842
1843                 default:
1844                         break;
1845                 }
1846
1847                 /*
1848                  * Write data segments in reverse order, so as to
1849                  * overwrite cacheline stamp last within each
1850                  * cacheline.  This avoids issues with WQE
1851                  * prefetching.
1852                  */
1853
1854                 dseg = wqe;
1855                 dseg += wr->num_sge - 1;
1856                 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
1857
1858                 /* Add one more inline data segment for ICRC for MLX sends */
1859                 if (unlikely(qp->ibqp.qp_type == IB_QPT_SMI ||
1860                              qp->ibqp.qp_type == IB_QPT_GSI)) {
1861                         set_mlx_icrc_seg(dseg + 1);
1862                         size += sizeof (struct mlx4_wqe_data_seg) / 16;
1863                 }
1864
1865                 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
1866                         set_data_seg(dseg, wr->sg_list + i);
1867
1868                 /*
1869                  * Possibly overwrite stamping in cacheline with LSO
1870                  * segment only after making sure all data segments
1871                  * are written.
1872                  */
1873                 wmb();
1874                 *lso_wqe = lso_hdr_sz;
1875
1876                 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
1877                                     MLX4_WQE_CTRL_FENCE : 0) | size;
1878
1879                 /*
1880                  * Make sure descriptor is fully written before
1881                  * setting ownership bit (because HW can start
1882                  * executing as soon as we do).
1883                  */
1884                 wmb();
1885
1886                 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
1887                         err = -EINVAL;
1888                         goto out;
1889                 }
1890
1891                 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
1892                         (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
1893
1894                 stamp = ind + qp->sq_spare_wqes;
1895                 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
1896
1897                 /*
1898                  * We can improve latency by not stamping the last
1899                  * send queue WQE until after ringing the doorbell, so
1900                  * only stamp here if there are still more WQEs to post.
1901                  *
1902                  * Same optimization applies to padding with NOP wqe
1903                  * in case of WQE shrinking (used to prevent wrap-around
1904                  * in the middle of WR).
1905                  */
1906                 if (wr->next) {
1907                         stamp_send_wqe(qp, stamp, size * 16);
1908                         ind = pad_wraparound(qp, ind);
1909                 }
1910         }
1911
1912 out:
1913         if (likely(nreq)) {
1914                 qp->sq.head += nreq;
1915
1916                 /*
1917                  * Make sure that descriptors are written before
1918                  * doorbell record.
1919                  */
1920                 wmb();
1921
1922                 writel(qp->doorbell_qpn,
1923                        to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
1924
1925                 /*
1926                  * Make sure doorbells don't leak out of SQ spinlock
1927                  * and reach the HCA out of order.
1928                  */
1929                 mmiowb();
1930
1931                 stamp_send_wqe(qp, stamp, size * 16);
1932
1933                 ind = pad_wraparound(qp, ind);
1934                 qp->sq_next_wqe = ind;
1935         }
1936
1937         spin_unlock_irqrestore(&qp->sq.lock, flags);
1938
1939         return err;
1940 }
1941
1942 int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1943                       struct ib_recv_wr **bad_wr)
1944 {
1945         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1946         struct mlx4_wqe_data_seg *scat;
1947         unsigned long flags;
1948         int err = 0;
1949         int nreq;
1950         int ind;
1951         int i;
1952
1953         spin_lock_irqsave(&qp->rq.lock, flags);
1954
1955         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
1956
1957         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1958                 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1959                         err = -ENOMEM;
1960                         *bad_wr = wr;
1961                         goto out;
1962                 }
1963
1964                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1965                         err = -EINVAL;
1966                         *bad_wr = wr;
1967                         goto out;
1968                 }
1969
1970                 scat = get_recv_wqe(qp, ind);
1971
1972                 for (i = 0; i < wr->num_sge; ++i)
1973                         __set_data_seg(scat + i, wr->sg_list + i);
1974
1975                 if (i < qp->rq.max_gs) {
1976                         scat[i].byte_count = 0;
1977                         scat[i].lkey       = cpu_to_be32(MLX4_INVALID_LKEY);
1978                         scat[i].addr       = 0;
1979                 }
1980
1981                 qp->rq.wrid[ind] = wr->wr_id;
1982
1983                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
1984         }
1985
1986 out:
1987         if (likely(nreq)) {
1988                 qp->rq.head += nreq;
1989
1990                 /*
1991                  * Make sure that descriptors are written before
1992                  * doorbell record.
1993                  */
1994                 wmb();
1995
1996                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
1997         }
1998
1999         spin_unlock_irqrestore(&qp->rq.lock, flags);
2000
2001         return err;
2002 }
2003
2004 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
2005 {
2006         switch (mlx4_state) {
2007         case MLX4_QP_STATE_RST:      return IB_QPS_RESET;
2008         case MLX4_QP_STATE_INIT:     return IB_QPS_INIT;
2009         case MLX4_QP_STATE_RTR:      return IB_QPS_RTR;
2010         case MLX4_QP_STATE_RTS:      return IB_QPS_RTS;
2011         case MLX4_QP_STATE_SQ_DRAINING:
2012         case MLX4_QP_STATE_SQD:      return IB_QPS_SQD;
2013         case MLX4_QP_STATE_SQER:     return IB_QPS_SQE;
2014         case MLX4_QP_STATE_ERR:      return IB_QPS_ERR;
2015         default:                     return -1;
2016         }
2017 }
2018
2019 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
2020 {
2021         switch (mlx4_mig_state) {
2022         case MLX4_QP_PM_ARMED:          return IB_MIG_ARMED;
2023         case MLX4_QP_PM_REARM:          return IB_MIG_REARM;
2024         case MLX4_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
2025         default: return -1;
2026         }
2027 }
2028
2029 static int to_ib_qp_access_flags(int mlx4_flags)
2030 {
2031         int ib_flags = 0;
2032
2033         if (mlx4_flags & MLX4_QP_BIT_RRE)
2034                 ib_flags |= IB_ACCESS_REMOTE_READ;
2035         if (mlx4_flags & MLX4_QP_BIT_RWE)
2036                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
2037         if (mlx4_flags & MLX4_QP_BIT_RAE)
2038                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
2039
2040         return ib_flags;
2041 }
2042
2043 static void to_ib_ah_attr(struct mlx4_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
2044                                 struct mlx4_qp_path *path)
2045 {
2046         struct mlx4_dev *dev = ibdev->dev;
2047         int is_eth;
2048
2049         memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
2050         ib_ah_attr->port_num      = path->sched_queue & 0x40 ? 2 : 1;
2051
2052         if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
2053                 return;
2054
2055         is_eth = rdma_port_get_link_layer(&ibdev->ib_dev, ib_ah_attr->port_num) ==
2056                 IB_LINK_LAYER_ETHERNET;
2057         if (is_eth)
2058                 ib_ah_attr->sl = ((path->sched_queue >> 3) & 0x7) |
2059                 ((path->sched_queue & 4) << 1);
2060         else
2061                 ib_ah_attr->sl = (path->sched_queue >> 2) & 0xf;
2062
2063         ib_ah_attr->dlid          = be16_to_cpu(path->rlid);
2064         ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f;
2065         ib_ah_attr->static_rate   = path->static_rate ? path->static_rate - 5 : 0;
2066         ib_ah_attr->ah_flags      = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
2067         if (ib_ah_attr->ah_flags) {
2068                 ib_ah_attr->grh.sgid_index = path->mgid_index;
2069                 ib_ah_attr->grh.hop_limit  = path->hop_limit;
2070                 ib_ah_attr->grh.traffic_class =
2071                         (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
2072                 ib_ah_attr->grh.flow_label =
2073                         be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
2074                 memcpy(ib_ah_attr->grh.dgid.raw,
2075                         path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
2076         }
2077 }
2078
2079 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
2080                      struct ib_qp_init_attr *qp_init_attr)
2081 {
2082         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
2083         struct mlx4_ib_qp *qp = to_mqp(ibqp);
2084         struct mlx4_qp_context context;
2085         int mlx4_state;
2086         int err = 0;
2087
2088         mutex_lock(&qp->mutex);
2089
2090         if (qp->state == IB_QPS_RESET) {
2091                 qp_attr->qp_state = IB_QPS_RESET;
2092                 goto done;
2093         }
2094
2095         err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
2096         if (err) {
2097                 err = -EINVAL;
2098                 goto out;
2099         }
2100
2101         mlx4_state = be32_to_cpu(context.flags) >> 28;
2102
2103         qp->state                    = to_ib_qp_state(mlx4_state);
2104         qp_attr->qp_state            = qp->state;
2105         qp_attr->path_mtu            = context.mtu_msgmax >> 5;
2106         qp_attr->path_mig_state      =
2107                 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
2108         qp_attr->qkey                = be32_to_cpu(context.qkey);
2109         qp_attr->rq_psn              = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
2110         qp_attr->sq_psn              = be32_to_cpu(context.next_send_psn) & 0xffffff;
2111         qp_attr->dest_qp_num         = be32_to_cpu(context.remote_qpn) & 0xffffff;
2112         qp_attr->qp_access_flags     =
2113                 to_ib_qp_access_flags(be32_to_cpu(context.params2));
2114
2115         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
2116                 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
2117                 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
2118                 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
2119                 qp_attr->alt_port_num   = qp_attr->alt_ah_attr.port_num;
2120         }
2121
2122         qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
2123         if (qp_attr->qp_state == IB_QPS_INIT)
2124                 qp_attr->port_num = qp->port;
2125         else
2126                 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
2127
2128         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
2129         qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
2130
2131         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
2132
2133         qp_attr->max_dest_rd_atomic =
2134                 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
2135         qp_attr->min_rnr_timer      =
2136                 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
2137         qp_attr->timeout            = context.pri_path.ackto >> 3;
2138         qp_attr->retry_cnt          = (be32_to_cpu(context.params1) >> 16) & 0x7;
2139         qp_attr->rnr_retry          = (be32_to_cpu(context.params1) >> 13) & 0x7;
2140         qp_attr->alt_timeout        = context.alt_path.ackto >> 3;
2141
2142 done:
2143         qp_attr->cur_qp_state        = qp_attr->qp_state;
2144         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
2145         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
2146
2147         if (!ibqp->uobject) {
2148                 qp_attr->cap.max_send_wr  = qp->sq.wqe_cnt;
2149                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
2150         } else {
2151                 qp_attr->cap.max_send_wr  = 0;
2152                 qp_attr->cap.max_send_sge = 0;
2153         }
2154
2155         /*
2156          * We don't support inline sends for kernel QPs (yet), and we
2157          * don't know what userspace's value should be.
2158          */
2159         qp_attr->cap.max_inline_data = 0;
2160
2161         qp_init_attr->cap            = qp_attr->cap;
2162
2163         qp_init_attr->create_flags = 0;
2164         if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
2165                 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
2166
2167         if (qp->flags & MLX4_IB_QP_LSO)
2168                 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
2169
2170 out:
2171         mutex_unlock(&qp->mutex);
2172         return err;
2173 }
2174