drivers/infiniband/hw/ipath/ipath_intr.c

   1 /*
   2  * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved.
   3  * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 #include <linux/pci.h>
  35
  36 #include "ipath_kernel.h"
  37 #include "ipath_verbs.h"
  38 #include "ipath_common.h"
  39
  40 /*
  41  * clear (write) a pio buffer, to clear a parity error.   This routine
  42  * should only be called when in freeze mode, and the buffer should be
  43  * canceled afterwards.
  44  */
  45 static void ipath_clrpiobuf(struct ipath_devdata *dd, u32 pnum)
  46 {
  47         u32 __iomem *pbuf;
  48         u32 dwcnt; /* dword count to write */
  49         if (pnum < dd->ipath_piobcnt2k) {
  50                 pbuf = (u32 __iomem *) (dd->ipath_pio2kbase + pnum *
  51                         dd->ipath_palign);
  52                 dwcnt = dd->ipath_piosize2k >> 2;
  53         }
  54         else {
  55                 pbuf = (u32 __iomem *) (dd->ipath_pio4kbase +
  56                         (pnum - dd->ipath_piobcnt2k) * dd->ipath_4kalign);
  57                 dwcnt = dd->ipath_piosize4k >> 2;
  58         }
  59         dev_info(&dd->pcidev->dev,
  60                 "Rewrite PIO buffer %u, to recover from parity error\n",
  61                 pnum);
  62         *pbuf = dwcnt+1; /* no flush required, since already in freeze */
  63         while(--dwcnt)
  64                 *pbuf++ = 0;
  65 }
  66
  67 /*
  68  * Called when we might have an error that is specific to a particular
  69  * PIO buffer, and may need to cancel that buffer, so it can be re-used.
  70  * If rewrite is true, and bits are set in the sendbufferror registers,
  71  * we'll write to the buffer, for error recovery on parity errors.
  72  */
  73 static void ipath_disarm_senderrbufs(struct ipath_devdata *dd, int rewrite)
  74 {
  75         u32 piobcnt;
  76         unsigned long sbuf[4];
  77         /*
  78          * it's possible that sendbuffererror could have bits set; might
  79          * have already done this as a result of hardware error handling
  80          */
  81         piobcnt = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k;
  82         /* read these before writing errorclear */
  83         sbuf[0] = ipath_read_kreg64(
  84                 dd, dd->ipath_kregs->kr_sendbuffererror);
  85         sbuf[1] = ipath_read_kreg64(
  86                 dd, dd->ipath_kregs->kr_sendbuffererror + 1);
  87         if (piobcnt > 128) {
  88                 sbuf[2] = ipath_read_kreg64(
  89                         dd, dd->ipath_kregs->kr_sendbuffererror + 2);
  90                 sbuf[3] = ipath_read_kreg64(
  91                         dd, dd->ipath_kregs->kr_sendbuffererror + 3);
  92         }
  93
  94         if (sbuf[0] || sbuf[1] || (piobcnt > 128 && (sbuf[2] || sbuf[3]))) {
  95                 int i;
  96                 if (ipath_debug & (__IPATH_PKTDBG|__IPATH_DBG) &&
  97                         dd->ipath_lastcancel > jiffies) {
  98                         __IPATH_DBG_WHICH(__IPATH_PKTDBG|__IPATH_DBG,
  99                                           "SendbufErrs %lx %lx", sbuf[0],
 100                                           sbuf[1]);
 101                         if (ipath_debug & __IPATH_PKTDBG && piobcnt > 128)
 102                                 printk(" %lx %lx ", sbuf[2], sbuf[3]);
 103                         printk("\n");
 104                 }
 105
 106                 for (i = 0; i < piobcnt; i++)
 107                         if (test_bit(i, sbuf)) {
 108                                 if (rewrite)
 109                                         ipath_clrpiobuf(dd, i);
 110                                 ipath_disarm_piobufs(dd, i, 1);
 111                         }
 112                 /* ignore armlaunch errs for a bit */
 113                 dd->ipath_lastcancel = jiffies+3;
 114         }
 115 }
 116
 117
 118 /* These are all rcv-related errors which we want to count for stats */
 119 #define E_SUM_PKTERRS \
 120         (INFINIPATH_E_RHDRLEN | INFINIPATH_E_RBADTID | \
 121          INFINIPATH_E_RBADVERSION | INFINIPATH_E_RHDR | \
 122          INFINIPATH_E_RLONGPKTLEN | INFINIPATH_E_RSHORTPKTLEN | \
 123          INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RMINPKTLEN | \
 124          INFINIPATH_E_RFORMATERR | INFINIPATH_E_RUNSUPVL | \
 125          INFINIPATH_E_RUNEXPCHAR | INFINIPATH_E_REBP)
 126
 127 /* These are all send-related errors which we want to count for stats */
 128 #define E_SUM_ERRS \
 129         (INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM | \
 130          INFINIPATH_E_SDROPPEDDATAPKT | INFINIPATH_E_SDROPPEDSMPPKT | \
 131          INFINIPATH_E_SMAXPKTLEN | INFINIPATH_E_SUNSUPVL | \
 132          INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SPKTLEN | \
 133          INFINIPATH_E_INVALIDADDR)
 134
 135 /*
 136  * this is similar to E_SUM_ERRS, but can't ignore armlaunch, don't ignore
 137  * errors not related to freeze and cancelling buffers.  Can't ignore
 138  * armlaunch because could get more while still cleaning up, and need
 139  * to cancel those as they happen.
 140  */
 141 #define E_SPKT_ERRS_IGNORE \
 142          (INFINIPATH_E_SDROPPEDDATAPKT | INFINIPATH_E_SDROPPEDSMPPKT | \
 143          INFINIPATH_E_SMAXPKTLEN | INFINIPATH_E_SMINPKTLEN | \
 144          INFINIPATH_E_SPKTLEN)
 145
 146 /*
 147  * these are errors that can occur when the link changes state while
 148  * a packet is being sent or received.  This doesn't cover things
 149  * like EBP or VCRC that can be the result of a sending having the
 150  * link change state, so we receive a "known bad" packet.
 151  */
 152 #define E_SUM_LINK_PKTERRS \
 153         (INFINIPATH_E_SDROPPEDDATAPKT | INFINIPATH_E_SDROPPEDSMPPKT | \
 154          INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SPKTLEN | \
 155          INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RMINPKTLEN | \
 156          INFINIPATH_E_RUNEXPCHAR)
 157
 158 static u64 handle_e_sum_errs(struct ipath_devdata *dd, ipath_err_t errs)
 159 {
 160         u64 ignore_this_time = 0;
 161
 162         ipath_disarm_senderrbufs(dd, 0);
 163         if ((errs & E_SUM_LINK_PKTERRS) &&
 164             !(dd->ipath_flags & IPATH_LINKACTIVE)) {
 165                 /*
 166                  * This can happen when SMA is trying to bring the link
 167                  * up, but the IB link changes state at the "wrong" time.
 168                  * The IB logic then complains that the packet isn't
 169                  * valid.  We don't want to confuse people, so we just
 170                  * don't print them, except at debug
 171                  */
 172                 ipath_dbg("Ignoring packet errors %llx, because link not "
 173                           "ACTIVE\n", (unsigned long long) errs);
 174                 ignore_this_time = errs & E_SUM_LINK_PKTERRS;
 175         }
 176
 177         return ignore_this_time;
 178 }
 179
 180 /* generic hw error messages... */
 181 #define INFINIPATH_HWE_TXEMEMPARITYERR_MSG(a) \
 182         { \
 183                 .mask = ( INFINIPATH_HWE_TXEMEMPARITYERR_##a <<    \
 184                           INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT ),   \
 185                 .msg = "TXE " #a " Memory Parity"            \
 186         }
 187 #define INFINIPATH_HWE_RXEMEMPARITYERR_MSG(a) \
 188         { \
 189                 .mask = ( INFINIPATH_HWE_RXEMEMPARITYERR_##a <<    \
 190                           INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT ),   \
 191                 .msg = "RXE " #a " Memory Parity"            \
 192         }
 193
 194 static const struct ipath_hwerror_msgs ipath_generic_hwerror_msgs[] = {
 195         INFINIPATH_HWE_MSG(IBCBUSFRSPCPARITYERR, "IPATH2IB Parity"),
 196         INFINIPATH_HWE_MSG(IBCBUSTOSPCPARITYERR, "IB2IPATH Parity"),
 197
 198         INFINIPATH_HWE_TXEMEMPARITYERR_MSG(PIOBUF),
 199         INFINIPATH_HWE_TXEMEMPARITYERR_MSG(PIOPBC),
 200         INFINIPATH_HWE_TXEMEMPARITYERR_MSG(PIOLAUNCHFIFO),
 201
 202         INFINIPATH_HWE_RXEMEMPARITYERR_MSG(RCVBUF),
 203         INFINIPATH_HWE_RXEMEMPARITYERR_MSG(LOOKUPQ),
 204         INFINIPATH_HWE_RXEMEMPARITYERR_MSG(EAGERTID),
 205         INFINIPATH_HWE_RXEMEMPARITYERR_MSG(EXPTID),
 206         INFINIPATH_HWE_RXEMEMPARITYERR_MSG(FLAGBUF),
 207         INFINIPATH_HWE_RXEMEMPARITYERR_MSG(DATAINFO),
 208         INFINIPATH_HWE_RXEMEMPARITYERR_MSG(HDRINFO),
 209 };
 210
 211 /**
 212  * ipath_format_hwmsg - format a single hwerror message
 213  * @msg message buffer
 214  * @msgl length of message buffer
 215  * @hwmsg message to add to message buffer
 216  */
 217 static void ipath_format_hwmsg(char *msg, size_t msgl, const char *hwmsg)
 218 {
 219         strlcat(msg, "[", msgl);
 220         strlcat(msg, hwmsg, msgl);
 221         strlcat(msg, "]", msgl);
 222 }
 223
 224 /**
 225  * ipath_format_hwerrors - format hardware error messages for display
 226  * @hwerrs hardware errors bit vector
 227  * @hwerrmsgs hardware error descriptions
 228  * @nhwerrmsgs number of hwerrmsgs
 229  * @msg message buffer
 230  * @msgl message buffer length
 231  */
 232 void ipath_format_hwerrors(u64 hwerrs,
 233                            const struct ipath_hwerror_msgs *hwerrmsgs,
 234                            size_t nhwerrmsgs,
 235                            char *msg, size_t msgl)
 236 {
 237         int i;
 238         const int glen =
 239             sizeof(ipath_generic_hwerror_msgs) /
 240             sizeof(ipath_generic_hwerror_msgs[0]);
 241
 242         for (i=0; i<glen; i++) {
 243                 if (hwerrs & ipath_generic_hwerror_msgs[i].mask) {
 244                         ipath_format_hwmsg(msg, msgl,
 245                                            ipath_generic_hwerror_msgs[i].msg);
 246                 }
 247         }
 248
 249         for (i=0; i<nhwerrmsgs; i++) {
 250                 if (hwerrs & hwerrmsgs[i].mask) {
 251                         ipath_format_hwmsg(msg, msgl, hwerrmsgs[i].msg);
 252                 }
 253         }
 254 }
 255
 256 /* return the strings for the most common link states */
 257 static char *ib_linkstate(u32 linkstate)
 258 {
 259         char *ret;
 260
 261         switch (linkstate) {
 262         case IPATH_IBSTATE_INIT:
 263                 ret = "Init";
 264                 break;
 265         case IPATH_IBSTATE_ARM:
 266                 ret = "Arm";
 267                 break;
 268         case IPATH_IBSTATE_ACTIVE:
 269                 ret = "Active";
 270                 break;
 271         default:
 272                 ret = "Down";
 273         }
 274
 275         return ret;
 276 }
 277
 278 static void handle_e_ibstatuschanged(struct ipath_devdata *dd,
 279                                      ipath_err_t errs, int noprint)
 280 {
 281         u64 val;
 282         u32 ltstate, lstate;
 283
 284         /*
 285          * even if diags are enabled, we want to notice LINKINIT, etc.
 286          * We just don't want to change the LED state, or
 287          * dd->ipath_kregs->kr_ibcctrl
 288          */
 289         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus);
 290         lstate = val & IPATH_IBSTATE_MASK;
 291
 292         /*
 293          * this is confusing enough when it happens that I want to always put it
 294          * on the console and in the logs.  If it was a requested state change,
 295          * we'll have already cleared the flags, so we won't print this warning
 296          */
 297         if ((lstate != IPATH_IBSTATE_ARM && lstate != IPATH_IBSTATE_ACTIVE)
 298                 && (dd->ipath_flags & (IPATH_LINKARMED | IPATH_LINKACTIVE))) {
 299                 dev_info(&dd->pcidev->dev, "Link state changed from %s to %s\n",
 300                                  (dd->ipath_flags & IPATH_LINKARMED) ? "ARM" : "ACTIVE",
 301                                  ib_linkstate(lstate));
 302                 /*
 303                  * Flush all queued sends when link went to DOWN or INIT,
 304                  * to be sure that they don't block SMA and other MAD packets
 305                  */
 306                 ipath_cancel_sends(dd);
 307         }
 308         else if (lstate == IPATH_IBSTATE_INIT || lstate == IPATH_IBSTATE_ARM ||
 309             lstate == IPATH_IBSTATE_ACTIVE) {
 310                 /*
 311                  * only print at SMA if there is a change, debug if not
 312                  * (sometimes we want to know that, usually not).
 313                  */
 314                 if (lstate == ((unsigned) dd->ipath_lastibcstat
 315                                & IPATH_IBSTATE_MASK)) {
 316                         ipath_dbg("Status change intr but no change (%s)\n",
 317                                   ib_linkstate(lstate));
 318                 }
 319                 else
 320                         ipath_cdbg(VERBOSE, "Unit %u link state %s, last "
 321                                    "was %s\n", dd->ipath_unit,
 322                                    ib_linkstate(lstate),
 323                                    ib_linkstate((unsigned)
 324                                                 dd->ipath_lastibcstat
 325                                                 & IPATH_IBSTATE_MASK));
 326         }
 327         else {
 328                 lstate = dd->ipath_lastibcstat & IPATH_IBSTATE_MASK;
 329                 if (lstate == IPATH_IBSTATE_INIT ||
 330                     lstate == IPATH_IBSTATE_ARM ||
 331                     lstate == IPATH_IBSTATE_ACTIVE)
 332                         ipath_cdbg(VERBOSE, "Unit %u link state down"
 333                                    " (state 0x%x), from %s\n",
 334                                    dd->ipath_unit,
 335                                    (u32)val & IPATH_IBSTATE_MASK,
 336                                    ib_linkstate(lstate));
 337                 else
 338                         ipath_cdbg(VERBOSE, "Unit %u link state changed "
 339                                    "to 0x%x from down (%x)\n",
 340                                    dd->ipath_unit, (u32) val, lstate);
 341         }
 342         ltstate = (val >> INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) &
 343                 INFINIPATH_IBCS_LINKTRAININGSTATE_MASK;
 344         lstate = (val >> INFINIPATH_IBCS_LINKSTATE_SHIFT) &
 345                 INFINIPATH_IBCS_LINKSTATE_MASK;
 346
 347         if (ltstate == INFINIPATH_IBCS_LT_STATE_POLLACTIVE ||
 348             ltstate == INFINIPATH_IBCS_LT_STATE_POLLQUIET) {
 349                 u32 last_ltstate;
 350
 351                 /*
 352                  * Ignore cycling back and forth from Polling.Active
 353                  * to Polling.Quiet while waiting for the other end of
 354                  * the link to come up. We will cycle back and forth
 355                  * between them if no cable is plugged in,
 356                  * the other device is powered off or disabled, etc.
 357                  */
 358                 last_ltstate = (dd->ipath_lastibcstat >>
 359                                 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT)
 360                         & INFINIPATH_IBCS_LINKTRAININGSTATE_MASK;
 361                 if (last_ltstate == INFINIPATH_IBCS_LT_STATE_POLLACTIVE
 362                     || last_ltstate ==
 363                     INFINIPATH_IBCS_LT_STATE_POLLQUIET) {
 364                         if (dd->ipath_ibpollcnt > 40) {
 365                                 dd->ipath_flags |= IPATH_NOCABLE;
 366                                 *dd->ipath_statusp |=
 367                                         IPATH_STATUS_IB_NOCABLE;
 368                         } else
 369                                 dd->ipath_ibpollcnt++;
 370                         goto skip_ibchange;
 371                 }
 372         }
 373         dd->ipath_ibpollcnt = 0;        /* some state other than 2 or 3 */
 374         ipath_stats.sps_iblink++;
 375         if (ltstate != INFINIPATH_IBCS_LT_STATE_LINKUP) {
 376                 dd->ipath_flags |= IPATH_LINKDOWN;
 377                 dd->ipath_flags &= ~(IPATH_LINKUNK | IPATH_LINKINIT
 378                                      | IPATH_LINKACTIVE |
 379                                      IPATH_LINKARMED);
 380                 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
 381                 dd->ipath_lli_counter = 0;
 382                 if (!noprint) {
 383                         if (((dd->ipath_lastibcstat >>
 384                               INFINIPATH_IBCS_LINKSTATE_SHIFT) &
 385                              INFINIPATH_IBCS_LINKSTATE_MASK)
 386                             == INFINIPATH_IBCS_L_STATE_ACTIVE)
 387                                 /* if from up to down be more vocal */
 388                                 ipath_cdbg(VERBOSE,
 389                                            "Unit %u link now down (%s)\n",
 390                                            dd->ipath_unit,
 391                                            ipath_ibcstatus_str[ltstate]);
 392                         else
 393                                 ipath_cdbg(VERBOSE, "Unit %u link is "
 394                                            "down (%s)\n", dd->ipath_unit,
 395                                            ipath_ibcstatus_str[ltstate]);
 396                 }
 397
 398                 dd->ipath_f_setextled(dd, lstate, ltstate);
 399         } else if ((val & IPATH_IBSTATE_MASK) == IPATH_IBSTATE_ACTIVE) {
 400                 dd->ipath_flags |= IPATH_LINKACTIVE;
 401                 dd->ipath_flags &=
 402                         ~(IPATH_LINKUNK | IPATH_LINKINIT | IPATH_LINKDOWN |
 403                           IPATH_LINKARMED | IPATH_NOCABLE);
 404                 *dd->ipath_statusp &= ~IPATH_STATUS_IB_NOCABLE;
 405                 *dd->ipath_statusp |=
 406                         IPATH_STATUS_IB_READY | IPATH_STATUS_IB_CONF;
 407                 dd->ipath_f_setextled(dd, lstate, ltstate);
 408         } else if ((val & IPATH_IBSTATE_MASK) == IPATH_IBSTATE_INIT) {
 409                 /*
 410                  * set INIT and DOWN.  Down is checked by most of the other
 411                  * code, but INIT is useful to know in a few places.
 412                  */
 413                 dd->ipath_flags |= IPATH_LINKINIT | IPATH_LINKDOWN;
 414                 dd->ipath_flags &=
 415                         ~(IPATH_LINKUNK | IPATH_LINKACTIVE | IPATH_LINKARMED
 416                           | IPATH_NOCABLE);
 417                 *dd->ipath_statusp &= ~(IPATH_STATUS_IB_NOCABLE
 418                                         | IPATH_STATUS_IB_READY);
 419                 dd->ipath_f_setextled(dd, lstate, ltstate);
 420         } else if ((val & IPATH_IBSTATE_MASK) == IPATH_IBSTATE_ARM) {
 421                 dd->ipath_flags |= IPATH_LINKARMED;
 422                 dd->ipath_flags &=
 423                         ~(IPATH_LINKUNK | IPATH_LINKDOWN | IPATH_LINKINIT |
 424                           IPATH_LINKACTIVE | IPATH_NOCABLE);
 425                 *dd->ipath_statusp &= ~(IPATH_STATUS_IB_NOCABLE
 426                                         | IPATH_STATUS_IB_READY);
 427                 dd->ipath_f_setextled(dd, lstate, ltstate);
 428         } else {
 429                 if (!noprint)
 430                         ipath_dbg("IBstatuschange unit %u: %s (%x)\n",
 431                                   dd->ipath_unit,
 432                                   ipath_ibcstatus_str[ltstate], ltstate);
 433         }
 434 skip_ibchange:
 435         dd->ipath_lastibcstat = val;
 436 }
 437
 438 static void handle_supp_msgs(struct ipath_devdata *dd,
 439                              unsigned supp_msgs, char msg[512])
 440 {
 441         /*
 442          * Print the message unless it's ibc status change only, which
 443          * happens so often we never want to count it.
 444          */
 445         if (dd->ipath_lasterror & ~INFINIPATH_E_IBSTATUSCHANGED) {
 446                 int iserr;
 447                 iserr = ipath_decode_err(msg, sizeof msg,
 448                                 dd->ipath_lasterror &
 449                                 ~INFINIPATH_E_IBSTATUSCHANGED);
 450                 if (dd->ipath_lasterror &
 451                         ~(INFINIPATH_E_RRCVEGRFULL |
 452                         INFINIPATH_E_RRCVHDRFULL | INFINIPATH_E_PKTERRS))
 453                         ipath_dev_err(dd, "Suppressed %u messages for "
 454                                       "fast-repeating errors (%s) (%llx)\n",
 455                                       supp_msgs, msg,
 456                                       (unsigned long long)
 457                                       dd->ipath_lasterror);
 458                 else {
 459                         /*
 460                          * rcvegrfull and rcvhdrqfull are "normal", for some
 461                          * types of processes (mostly benchmarks) that send
 462                          * huge numbers of messages, while not processing
 463                          * them. So only complain about these at debug
 464                          * level.
 465                          */
 466                         if (iserr)
 467                                 ipath_dbg("Suppressed %u messages for %s\n",
 468                                           supp_msgs, msg);
 469                         else
 470                                 ipath_cdbg(ERRPKT,
 471                                         "Suppressed %u messages for %s\n",
 472                                           supp_msgs, msg);
 473                 }
 474         }
 475 }
 476
 477 static unsigned handle_frequent_errors(struct ipath_devdata *dd,
 478                                        ipath_err_t errs, char msg[512],
 479                                        int *noprint)
 480 {
 481         unsigned long nc;
 482         static unsigned long nextmsg_time;
 483         static unsigned nmsgs, supp_msgs;
 484
 485         /*
 486          * Throttle back "fast" messages to no more than 10 per 5 seconds.
 487          * This isn't perfect, but it's a reasonable heuristic. If we get
 488          * more than 10, give a 6x longer delay.
 489          */
 490         nc = jiffies;
 491         if (nmsgs > 10) {
 492                 if (time_before(nc, nextmsg_time)) {
 493                         *noprint = 1;
 494                         if (!supp_msgs++)
 495                                 nextmsg_time = nc + HZ * 3;
 496                 }
 497                 else if (supp_msgs) {
 498                         handle_supp_msgs(dd, supp_msgs, msg);
 499                         supp_msgs = 0;
 500                         nmsgs = 0;
 501                 }
 502         }
 503         else if (!nmsgs++ || time_after(nc, nextmsg_time))
 504                 nextmsg_time = nc + HZ / 2;
 505
 506         return supp_msgs;
 507 }
 508
 509 static int handle_errors(struct ipath_devdata *dd, ipath_err_t errs)
 510 {
 511         char msg[512];
 512         u64 ignore_this_time = 0;
 513         int i, iserr = 0;
 514         int chkerrpkts = 0, noprint = 0;
 515         unsigned supp_msgs;
 516         int log_idx;
 517
 518         supp_msgs = handle_frequent_errors(dd, errs, msg, &noprint);
 519
 520         /*
 521          * don't report errors that are masked (includes those always
 522          * ignored)
 523          */
 524         errs &= ~dd->ipath_maskederrs;
 525
 526         /* do these first, they are most important */
 527         if (errs & INFINIPATH_E_HARDWARE) {
 528                 /* reuse same msg buf */
 529                 dd->ipath_f_handle_hwerrors(dd, msg, sizeof msg);
 530         } else {
 531                 u64 mask;
 532                 for (log_idx = 0; log_idx < IPATH_EEP_LOG_CNT; ++log_idx) {
 533                         mask = dd->ipath_eep_st_masks[log_idx].errs_to_log;
 534                         if (errs & mask)
 535                                 ipath_inc_eeprom_err(dd, log_idx, 1);
 536                 }
 537         }
 538
 539         if (!noprint && (errs & ~dd->ipath_e_bitsextant))
 540                 ipath_dev_err(dd, "error interrupt with unknown errors "
 541                               "%llx set\n", (unsigned long long)
 542                               (errs & ~dd->ipath_e_bitsextant));
 543
 544         if (errs & E_SUM_ERRS)
 545                 ignore_this_time = handle_e_sum_errs(dd, errs);
 546         else if ((errs & E_SUM_LINK_PKTERRS) &&
 547             !(dd->ipath_flags & IPATH_LINKACTIVE)) {
 548                 /*
 549                  * This can happen when SMA is trying to bring the link
 550                  * up, but the IB link changes state at the "wrong" time.
 551                  * The IB logic then complains that the packet isn't
 552                  * valid.  We don't want to confuse people, so we just
 553                  * don't print them, except at debug
 554                  */
 555                 ipath_dbg("Ignoring packet errors %llx, because link not "
 556                           "ACTIVE\n", (unsigned long long) errs);
 557                 ignore_this_time = errs & E_SUM_LINK_PKTERRS;
 558         }
 559
 560         if (supp_msgs == 250000) {
 561                 int s_iserr;
 562                 /*
 563                  * It's not entirely reasonable assuming that the errors set
 564                  * in the last clear period are all responsible for the
 565                  * problem, but the alternative is to assume it's the only
 566                  * ones on this particular interrupt, which also isn't great
 567                  */
 568                 dd->ipath_maskederrs |= dd->ipath_lasterror | errs;
 569                 ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
 570                                  ~dd->ipath_maskederrs);
 571                 s_iserr = ipath_decode_err(msg, sizeof msg,
 572                                  (dd->ipath_maskederrs & ~dd->
 573                                   ipath_ignorederrs));
 574
 575                 if ((dd->ipath_maskederrs & ~dd->ipath_ignorederrs) &
 576                         ~(INFINIPATH_E_RRCVEGRFULL |
 577                         INFINIPATH_E_RRCVHDRFULL | INFINIPATH_E_PKTERRS))
 578                         ipath_dev_err(dd, "Temporarily disabling "
 579                             "error(s) %llx reporting; too frequent (%s)\n",
 580                                 (unsigned long long) (dd->ipath_maskederrs &
 581                                 ~dd->ipath_ignorederrs), msg);
 582                 else {
 583                         /*
 584                          * rcvegrfull and rcvhdrqfull are "normal",
 585                          * for some types of processes (mostly benchmarks)
 586                          * that send huge numbers of messages, while not
 587                          * processing them.  So only complain about
 588                          * these at debug level.
 589                          */
 590                         if (s_iserr)
 591                                 ipath_dbg("Temporarily disabling reporting "
 592                                     "too frequent queue full errors (%s)\n",
 593                                     msg);
 594                         else
 595                                 ipath_cdbg(ERRPKT,
 596                                     "Temporarily disabling reporting too"
 597                                     " frequent packet errors (%s)\n",
 598                                     msg);
 599                 }
 600
 601                 /*
 602                  * Re-enable the masked errors after around 3 minutes.  in
 603                  * ipath_get_faststats().  If we have a series of fast
 604                  * repeating but different errors, the interval will keep
 605                  * stretching out, but that's OK, as that's pretty
 606                  * catastrophic.
 607                  */
 608                 dd->ipath_unmasktime = jiffies + HZ * 180;
 609         }
 610
 611         ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, errs);
 612         if (ignore_this_time)
 613                 errs &= ~ignore_this_time;
 614         if (errs & ~dd->ipath_lasterror) {
 615                 errs &= ~dd->ipath_lasterror;
 616                 /* never suppress duplicate hwerrors or ibstatuschange */
 617                 dd->ipath_lasterror |= errs &
 618                         ~(INFINIPATH_E_HARDWARE |
 619                           INFINIPATH_E_IBSTATUSCHANGED);
 620         }
 621
 622         /* likely due to cancel, so suppress */
 623         if ((errs & (INFINIPATH_E_SPKTLEN | INFINIPATH_E_SPIOARMLAUNCH)) &&
 624                 dd->ipath_lastcancel > jiffies) {
 625                 ipath_dbg("Suppressed armlaunch/spktlen after error send cancel\n");
 626                 errs &= ~(INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SPKTLEN);
 627         }
 628
 629         if (!errs)
 630                 return 0;
 631
 632         if (!noprint)
 633                 /*
 634                  * the ones we mask off are handled specially below or above
 635                  */
 636                 ipath_decode_err(msg, sizeof msg,
 637                                  errs & ~(INFINIPATH_E_IBSTATUSCHANGED |
 638                                           INFINIPATH_E_RRCVEGRFULL |
 639                                           INFINIPATH_E_RRCVHDRFULL |
 640                                           INFINIPATH_E_HARDWARE));
 641         else
 642                 /* so we don't need if (!noprint) at strlcat's below */
 643                 *msg = 0;
 644
 645         if (errs & E_SUM_PKTERRS) {
 646                 ipath_stats.sps_pkterrs++;
 647                 chkerrpkts = 1;
 648         }
 649         if (errs & E_SUM_ERRS)
 650                 ipath_stats.sps_errs++;
 651
 652         if (errs & (INFINIPATH_E_RICRC | INFINIPATH_E_RVCRC)) {
 653                 ipath_stats.sps_crcerrs++;
 654                 chkerrpkts = 1;
 655         }
 656         iserr = errs & ~(E_SUM_PKTERRS | INFINIPATH_E_PKTERRS);
 657
 658
 659         /*
 660          * We don't want to print these two as they happen, or we can make
 661          * the situation even worse, because it takes so long to print
 662          * messages to serial consoles.  Kernel ports get printed from
 663          * fast_stats, no more than every 5 seconds, user ports get printed
 664          * on close
 665          */
 666         if (errs & INFINIPATH_E_RRCVHDRFULL) {
 667                 u32 hd, tl;
 668                 ipath_stats.sps_hdrqfull++;
 669                 for (i = 0; i < dd->ipath_cfgports; i++) {
 670                         struct ipath_portdata *pd = dd->ipath_pd[i];
 671                         if (i == 0) {
 672                                 hd = dd->ipath_port0head;
 673                                 tl = (u32) le64_to_cpu(
 674                                         *dd->ipath_hdrqtailptr);
 675                         } else if (pd && pd->port_cnt &&
 676                                    pd->port_rcvhdrtail_kvaddr) {
 677                                 /*
 678                                  * don't report same point multiple times,
 679                                  * except kernel
 680                                  */
 681                                 tl = *(u64 *) pd->port_rcvhdrtail_kvaddr;
 682                                 if (tl == dd->ipath_lastrcvhdrqtails[i])
 683                                         continue;
 684                                 hd = ipath_read_ureg32(dd, ur_rcvhdrhead,
 685                                                        i);
 686                         } else
 687                                 continue;
 688                         if (hd == (tl + 1) ||
 689                             (!hd && tl == dd->ipath_hdrqlast)) {
 690                                 if (i == 0)
 691                                         chkerrpkts = 1;
 692                                 dd->ipath_lastrcvhdrqtails[i] = tl;
 693                                 pd->port_hdrqfull++;
 694                                 if (test_bit(IPATH_PORT_WAITING_OVERFLOW,
 695                                              &pd->port_flag)) {
 696                                         clear_bit(
 697                                           IPATH_PORT_WAITING_OVERFLOW,
 698                                           &pd->port_flag);
 699                                         set_bit(
 700                                           IPATH_PORT_WAITING_OVERFLOW,
 701                                           &pd->int_flag);
 702                                         wake_up_interruptible(
 703                                           &pd->port_wait);
 704                                 }
 705                         }
 706                 }
 707         }
 708         if (errs & INFINIPATH_E_RRCVEGRFULL) {
 709                 /*
 710                  * since this is of less importance and not likely to
 711                  * happen without also getting hdrfull, only count
 712                  * occurrences; don't check each port (or even the kernel
 713                  * vs user)
 714                  */
 715                 ipath_stats.sps_etidfull++;
 716                 if (dd->ipath_port0head !=
 717                     (u32) le64_to_cpu(*dd->ipath_hdrqtailptr))
 718                         chkerrpkts = 1;
 719         }
 720
 721         /*
 722          * do this before IBSTATUSCHANGED, in case both bits set in a single
 723          * interrupt; we want the STATUSCHANGE to "win", so we do our
 724          * internal copy of state machine correctly
 725          */
 726         if (errs & INFINIPATH_E_RIBLOSTLINK) {
 727                 /*
 728                  * force through block below
 729                  */
 730                 errs |= INFINIPATH_E_IBSTATUSCHANGED;
 731                 ipath_stats.sps_iblink++;
 732                 dd->ipath_flags |= IPATH_LINKDOWN;
 733                 dd->ipath_flags &= ~(IPATH_LINKUNK | IPATH_LINKINIT
 734                                      | IPATH_LINKARMED | IPATH_LINKACTIVE);
 735                 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
 736                 if (!noprint) {
 737                         u64 st = ipath_read_kreg64(
 738                                 dd, dd->ipath_kregs->kr_ibcstatus);
 739
 740                         ipath_dbg("Lost link, link now down (%s)\n",
 741                                   ipath_ibcstatus_str[st & 0xf]);
 742                 }
 743         }
 744         if (errs & INFINIPATH_E_IBSTATUSCHANGED)
 745                 handle_e_ibstatuschanged(dd, errs, noprint);
 746
 747         if (errs & INFINIPATH_E_RESET) {
 748                 if (!noprint)
 749                         ipath_dev_err(dd, "Got reset, requires re-init "
 750                                       "(unload and reload driver)\n");
 751                 dd->ipath_flags &= ~IPATH_INITTED;      /* needs re-init */
 752                 /* mark as having had error */
 753                 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
 754                 *dd->ipath_statusp &= ~IPATH_STATUS_IB_CONF;
 755         }
 756
 757         if (!noprint && *msg) {
 758                 if (iserr)
 759                         ipath_dev_err(dd, "%s error\n", msg);
 760                 else
 761                         dev_info(&dd->pcidev->dev, "%s packet problems\n",
 762                                 msg);
 763         }
 764         if (dd->ipath_state_wanted & dd->ipath_flags) {
 765                 ipath_cdbg(VERBOSE, "driver wanted state %x, iflags now %x, "
 766                            "waking\n", dd->ipath_state_wanted,
 767                            dd->ipath_flags);
 768                 wake_up_interruptible(&ipath_state_wait);
 769         }
 770
 771         return chkerrpkts;
 772 }
 773
 774
 775 /*
 776  * try to cleanup as much as possible for anything that might have gone
 777  * wrong while in freeze mode, such as pio buffers being written by user
 778  * processes (causing armlaunch), send errors due to going into freeze mode,
 779  * etc., and try to avoid causing extra interrupts while doing so.
 780  * Forcibly update the in-memory pioavail register copies after cleanup
 781  * because the chip won't do it for anything changing while in freeze mode
 782  * (we don't want to wait for the next pio buffer state change).
 783  * Make sure that we don't lose any important interrupts by using the chip
 784  * feature that says that writing 0 to a bit in *clear that is set in
 785  * *status will cause an interrupt to be generated again (if allowed by
 786  * the *mask value).
 787  */
 788 void ipath_clear_freeze(struct ipath_devdata *dd)
 789 {
 790         int i, im;
 791         __le64 val;
 792
 793         /* disable error interrupts, to avoid confusion */
 794         ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask, 0ULL);
 795
 796         /*
 797          * clear all sends, because they have may been
 798          * completed by usercode while in freeze mode, and
 799          * therefore would not be sent, and eventually
 800          * might cause the process to run out of bufs
 801          */
 802         ipath_cancel_sends(dd);
 803         ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
 804                          dd->ipath_control);
 805
 806         /* ensure pio avail updates continue */
 807         ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
 808                  dd->ipath_sendctrl & ~IPATH_S_PIOBUFAVAILUPD);
 809         ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 810         ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
 811                  dd->ipath_sendctrl);
 812
 813         /*
 814          * We just enabled pioavailupdate, so dma copy is almost certainly
 815          * not yet right, so read the registers directly.  Similar to init
 816          */
 817         for (i = 0; i < dd->ipath_pioavregs; i++) {
 818                 /* deal with 6110 chip bug */
 819                 im = i > 3 ? ((i&1) ? i-1 : i+1) : i;
 820                 val = ipath_read_kreg64(dd, 0x1000+(im*sizeof(u64)));
 821                 dd->ipath_pioavailregs_dma[i] = dd->ipath_pioavailshadow[i]
 822                         = le64_to_cpu(val);
 823         }
 824
 825         /*
 826          * force new interrupt if any hwerr, error or interrupt bits are
 827          * still set, and clear "safe" send packet errors related to freeze
 828          * and cancelling sends.  Re-enable error interrupts before possible
 829          * force of re-interrupt on pending interrupts.
 830          */
 831         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear, 0ULL);
 832         ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear,
 833                 E_SPKT_ERRS_IGNORE);
 834         ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
 835                 ~dd->ipath_maskederrs);
 836         ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, 0ULL);
 837 }
 838
 839
 840 /* this is separate to allow for better optimization of ipath_intr() */
 841
 842 static void ipath_bad_intr(struct ipath_devdata *dd, u32 * unexpectp)
 843 {
 844         /*
 845          * sometimes happen during driver init and unload, don't want
 846          * to process any interrupts at that point
 847          */
 848
 849         /* this is just a bandaid, not a fix, if something goes badly
 850          * wrong */
 851         if (++*unexpectp > 100) {
 852                 if (++*unexpectp > 105) {
 853                         /*
 854                          * ok, we must be taking somebody else's interrupts,
 855                          * due to a messed up mptable and/or PIRQ table, so
 856                          * unregister the interrupt.  We've seen this during
 857                          * linuxbios development work, and it may happen in
 858                          * the future again.
 859                          */
 860                         if (dd->pcidev && dd->ipath_irq) {
 861                                 ipath_dev_err(dd, "Now %u unexpected "
 862                                               "interrupts, unregistering "
 863                                               "interrupt handler\n",
 864                                               *unexpectp);
 865                                 ipath_dbg("free_irq of irq %d\n",
 866                                           dd->ipath_irq);
 867                                 dd->ipath_f_free_irq(dd);
 868                         }
 869                 }
 870                 if (ipath_read_kreg32(dd, dd->ipath_kregs->kr_intmask)) {
 871                         ipath_dev_err(dd, "%u unexpected interrupts, "
 872                                       "disabling interrupts completely\n",
 873                                       *unexpectp);
 874                         /*
 875                          * disable all interrupts, something is very wrong
 876                          */
 877                         ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask,
 878                                          0ULL);
 879                 }
 880         } else if (*unexpectp > 1)
 881                 ipath_dbg("Interrupt when not ready, should not happen, "
 882                           "ignoring\n");
 883 }
 884
 885 static void ipath_bad_regread(struct ipath_devdata *dd)
 886 {
 887         static int allbits;
 888
 889         /* separate routine, for better optimization of ipath_intr() */
 890
 891         /*
 892          * We print the message and disable interrupts, in hope of
 893          * having a better chance of debugging the problem.
 894          */
 895         ipath_dev_err(dd,
 896                       "Read of interrupt status failed (all bits set)\n");
 897         if (allbits++) {
 898                 /* disable all interrupts, something is very wrong */
 899                 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 0ULL);
 900                 if (allbits == 2) {
 901                         ipath_dev_err(dd, "Still bad interrupt status, "
 902                                       "unregistering interrupt\n");
 903                         dd->ipath_f_free_irq(dd);
 904                 } else if (allbits > 2) {
 905                         if ((allbits % 10000) == 0)
 906                                 printk(".");
 907                 } else
 908                         ipath_dev_err(dd, "Disabling interrupts, "
 909                                       "multiple errors\n");
 910         }
 911 }
 912
 913 static void handle_port_pioavail(struct ipath_devdata *dd)
 914 {
 915         u32 i;
 916         /*
 917          * start from port 1, since for now port 0  is never using
 918          * wait_event for PIO
 919          */
 920         for (i = 1; dd->ipath_portpiowait && i < dd->ipath_cfgports; i++) {
 921                 struct ipath_portdata *pd = dd->ipath_pd[i];
 922
 923                 if (pd && pd->port_cnt &&
 924                     dd->ipath_portpiowait & (1U << i)) {
 925                         clear_bit(i, &dd->ipath_portpiowait);
 926                         if (test_bit(IPATH_PORT_WAITING_PIO,
 927                                      &pd->port_flag)) {
 928                                 clear_bit(IPATH_PORT_WAITING_PIO,
 929                                           &pd->port_flag);
 930                                 wake_up_interruptible(&pd->port_wait);
 931                         }
 932                 }
 933         }
 934 }
 935
 936 static void handle_layer_pioavail(struct ipath_devdata *dd)
 937 {
 938         int ret;
 939
 940         ret = ipath_ib_piobufavail(dd->verbs_dev);
 941         if (ret > 0)
 942                 goto set;
 943
 944         return;
 945 set:
 946         set_bit(IPATH_S_PIOINTBUFAVAIL, &dd->ipath_sendctrl);
 947         ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
 948                          dd->ipath_sendctrl);
 949 }
 950
 951 /*
 952  * Handle receive interrupts for user ports; this means a user
 953  * process was waiting for a packet to arrive, and didn't want
 954  * to poll
 955  */
 956 static void handle_urcv(struct ipath_devdata *dd, u32 istat)
 957 {
 958         u64 portr;
 959         int i;
 960         int rcvdint = 0;
 961
 962         portr = ((istat >> INFINIPATH_I_RCVAVAIL_SHIFT) &
 963                  dd->ipath_i_rcvavail_mask)
 964                 | ((istat >> INFINIPATH_I_RCVURG_SHIFT) &
 965                    dd->ipath_i_rcvurg_mask);
 966         for (i = 1; i < dd->ipath_cfgports; i++) {
 967                 struct ipath_portdata *pd = dd->ipath_pd[i];
 968                 if (portr & (1 << i) && pd && pd->port_cnt) {
 969                         if (test_bit(IPATH_PORT_WAITING_RCV,
 970                                      &pd->port_flag)) {
 971                                 clear_bit(IPATH_PORT_WAITING_RCV,
 972                                           &pd->port_flag);
 973                                 set_bit(IPATH_PORT_WAITING_RCV,
 974                                         &pd->int_flag);
 975                                 clear_bit(i + INFINIPATH_R_INTRAVAIL_SHIFT,
 976                                           &dd->ipath_rcvctrl);
 977                                 wake_up_interruptible(&pd->port_wait);
 978                                 rcvdint = 1;
 979                         } else if (test_bit(IPATH_PORT_WAITING_URG,
 980                                             &pd->port_flag)) {
 981                                 clear_bit(IPATH_PORT_WAITING_URG,
 982                                           &pd->port_flag);
 983                                 set_bit(IPATH_PORT_WAITING_URG,
 984                                         &pd->int_flag);
 985                                 wake_up_interruptible(&pd->port_wait);
 986                         }
 987                 }
 988         }
 989         if (rcvdint) {
 990                 /* only want to take one interrupt, so turn off the rcv
 991                  * interrupt for all the ports that we did the wakeup on
 992                  * (but never for kernel port)
 993                  */
 994                 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
 995                                  dd->ipath_rcvctrl);
 996         }
 997 }
 998
 999 irqreturn_t ipath_intr(int irq, void *data)
1000 {
1001         struct ipath_devdata *dd = data;
1002         u32 istat, chk0rcv = 0;
1003         ipath_err_t estat = 0;
1004         irqreturn_t ret;
1005         u32 oldhead, curtail;
1006         static unsigned unexpected = 0;
1007         static const u32 port0rbits = (1U<<INFINIPATH_I_RCVAVAIL_SHIFT) |
1008                  (1U<<INFINIPATH_I_RCVURG_SHIFT);
1009
1010         ipath_stats.sps_ints++;
1011
1012         if (dd->ipath_int_counter != (u32) -1)
1013                 dd->ipath_int_counter++;
1014
1015         if (!(dd->ipath_flags & IPATH_PRESENT)) {
1016                 /*
1017                  * This return value is not great, but we do not want the
1018                  * interrupt core code to remove our interrupt handler
1019                  * because we don't appear to be handling an interrupt
1020                  * during a chip reset.
1021                  */
1022                 return IRQ_HANDLED;
1023         }
1024
1025         /*
1026          * this needs to be flags&initted, not statusp, so we keep
1027          * taking interrupts even after link goes down, etc.
1028          * Also, we *must* clear the interrupt at some point, or we won't
1029          * take it again, which can be real bad for errors, etc...
1030          */
1031
1032         if (!(dd->ipath_flags & IPATH_INITTED)) {
1033                 ipath_bad_intr(dd, &unexpected);
1034                 ret = IRQ_NONE;
1035                 goto bail;
1036         }
1037
1038         /*
1039          * We try to avoid reading the interrupt status register, since
1040          * that's a PIO read, and stalls the processor for up to about
1041          * ~0.25 usec. The idea is that if we processed a port0 packet,
1042          * we blindly clear the  port 0 receive interrupt bits, and nothing
1043          * else, then return.  If other interrupts are pending, the chip
1044          * will re-interrupt us as soon as we write the intclear register.
1045          * We then won't process any more kernel packets (if not the 2nd
1046          * time, then the 3rd or 4th) and we'll then handle the other
1047          * interrupts.   We clear the interrupts first so that we don't
1048          * lose intr for later packets that arrive while we are processing.
1049          */
1050         oldhead = dd->ipath_port0head;
1051         curtail = (u32)le64_to_cpu(*dd->ipath_hdrqtailptr);
1052         if (oldhead != curtail) {
1053                 if (dd->ipath_flags & IPATH_GPIO_INTR) {
1054                         ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_clear,
1055                                          (u64) (1 << IPATH_GPIO_PORT0_BIT));
1056                         istat = port0rbits | INFINIPATH_I_GPIO;
1057                 }
1058                 else
1059                         istat = port0rbits;
1060                 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, istat);
1061                 ipath_kreceive(dd);
1062                 if (oldhead != dd->ipath_port0head) {
1063                         ipath_stats.sps_fastrcvint++;
1064                         goto done;
1065                 }
1066         }
1067
1068         istat = ipath_read_kreg32(dd, dd->ipath_kregs->kr_intstatus);
1069
1070         if (unlikely(!istat)) {
1071                 ipath_stats.sps_nullintr++;
1072                 ret = IRQ_NONE; /* not our interrupt, or already handled */
1073                 goto bail;
1074         }
1075         if (unlikely(istat == -1)) {
1076                 ipath_bad_regread(dd);
1077                 /* don't know if it was our interrupt or not */
1078                 ret = IRQ_NONE;
1079                 goto bail;
1080         }
1081
1082         if (unexpected)
1083                 unexpected = 0;
1084
1085         if (unlikely(istat & ~dd->ipath_i_bitsextant))
1086                 ipath_dev_err(dd,
1087                               "interrupt with unknown interrupts %x set\n",
1088                               istat & (u32) ~ dd->ipath_i_bitsextant);
1089         else
1090                 ipath_cdbg(VERBOSE, "intr stat=0x%x\n", istat);
1091
1092         if (unlikely(istat & INFINIPATH_I_ERROR)) {
1093                 ipath_stats.sps_errints++;
1094                 estat = ipath_read_kreg64(dd,
1095                                           dd->ipath_kregs->kr_errorstatus);
1096                 if (!estat)
1097                         dev_info(&dd->pcidev->dev, "error interrupt (%x), "
1098                                  "but no error bits set!\n", istat);
1099                 else if (estat == -1LL)
1100                         /*
1101                          * should we try clearing all, or hope next read
1102                          * works?
1103                          */
1104                         ipath_dev_err(dd, "Read of error status failed "
1105                                       "(all bits set); ignoring\n");
1106                 else
1107                         if (handle_errors(dd, estat))
1108                                 /* force calling ipath_kreceive() */
1109                                 chk0rcv = 1;
1110         }
1111
1112         if (istat & INFINIPATH_I_GPIO) {
1113                 /*
1114                  * GPIO interrupts fall in two broad classes:
1115                  * GPIO_2 indicates (on some HT4xx boards) that a packet
1116                  *        has arrived for Port 0. Checking for this
1117                  *        is controlled by flag IPATH_GPIO_INTR.
1118                  * GPIO_3..5 on IBA6120 Rev2 chips indicate errors
1119                  *        that we need to count. Checking for this
1120                  *        is controlled by flag IPATH_GPIO_ERRINTRS.
1121                  */
1122                 u32 gpiostatus;
1123                 u32 to_clear = 0;
1124
1125                 gpiostatus = ipath_read_kreg32(
1126                         dd, dd->ipath_kregs->kr_gpio_status);
1127                 /* First the error-counter case.
1128                  */
1129                 if ((gpiostatus & IPATH_GPIO_ERRINTR_MASK) &&
1130                     (dd->ipath_flags & IPATH_GPIO_ERRINTRS)) {
1131                         /* want to clear the bits we see asserted. */
1132                         to_clear |= (gpiostatus & IPATH_GPIO_ERRINTR_MASK);
1133
1134                         /*
1135                          * Count appropriately, clear bits out of our copy,
1136                          * as they have been "handled".
1137                          */
1138                         if (gpiostatus & (1 << IPATH_GPIO_RXUVL_BIT)) {
1139                                 ipath_dbg("FlowCtl on UnsupVL\n");
1140                                 dd->ipath_rxfc_unsupvl_errs++;
1141                         }
1142                         if (gpiostatus & (1 << IPATH_GPIO_OVRUN_BIT)) {
1143                                 ipath_dbg("Overrun Threshold exceeded\n");
1144                                 dd->ipath_overrun_thresh_errs++;
1145                         }
1146                         if (gpiostatus & (1 << IPATH_GPIO_LLI_BIT)) {
1147                                 ipath_dbg("Local Link Integrity error\n");
1148                                 dd->ipath_lli_errs++;
1149                         }
1150                         gpiostatus &= ~IPATH_GPIO_ERRINTR_MASK;
1151                 }
1152                 /* Now the Port0 Receive case */
1153                 if ((gpiostatus & (1 << IPATH_GPIO_PORT0_BIT)) &&
1154                     (dd->ipath_flags & IPATH_GPIO_INTR)) {
1155                         /*
1156                          * GPIO status bit 2 is set, and we expected it.
1157                          * clear it and indicate in p0bits.
1158                          * This probably only happens if a Port0 pkt
1159                          * arrives at _just_ the wrong time, and we
1160                          * handle that by seting chk0rcv;
1161                          */
1162                         to_clear |= (1 << IPATH_GPIO_PORT0_BIT);
1163                         gpiostatus &= ~(1 << IPATH_GPIO_PORT0_BIT);
1164                         chk0rcv = 1;
1165                 }
1166                 if (gpiostatus) {
1167                         /*
1168                          * Some unexpected bits remain. If they could have
1169                          * caused the interrupt, complain and clear.
1170                          * MEA: this is almost certainly non-ideal.
1171                          * we should look into auto-disable of unexpected
1172                          * GPIO interrupts, possibly on a "three strikes"
1173                          * basis.
1174                          */
1175                         const u32 mask = (u32) dd->ipath_gpio_mask;
1176
1177                         if (mask & gpiostatus) {
1178                                 ipath_dbg("Unexpected GPIO IRQ bits %x\n",
1179                                   gpiostatus & mask);
1180                                 to_clear |= (gpiostatus & mask);
1181                         }
1182                 }
1183                 if (to_clear) {
1184                         ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_clear,
1185                                         (u64) to_clear);
1186                 }
1187         }
1188         chk0rcv |= istat & port0rbits;
1189
1190         /*
1191          * Clear the interrupt bits we found set, unless they are receive
1192          * related, in which case we already cleared them above, and don't
1193          * want to clear them again, because we might lose an interrupt.
1194          * Clear it early, so we "know" know the chip will have seen this by
1195          * the time we process the queue, and will re-interrupt if necessary.
1196          * The processor itself won't take the interrupt again until we return.
1197          */
1198         ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, istat);
1199
1200         /*
1201          * handle port0 receive  before checking for pio buffers available,
1202          * since receives can overflow; piobuf waiters can afford a few
1203          * extra cycles, since they were waiting anyway, and user's waiting
1204          * for receive are at the bottom.
1205          */
1206         if (chk0rcv) {
1207                 ipath_kreceive(dd);
1208                 istat &= ~port0rbits;
1209         }
1210
1211         if (istat & ((dd->ipath_i_rcvavail_mask <<
1212                       INFINIPATH_I_RCVAVAIL_SHIFT)
1213                      | (dd->ipath_i_rcvurg_mask <<
1214                         INFINIPATH_I_RCVURG_SHIFT)))
1215                 handle_urcv(dd, istat);
1216
1217         if (istat & INFINIPATH_I_SPIOBUFAVAIL) {
1218                 clear_bit(IPATH_S_PIOINTBUFAVAIL, &dd->ipath_sendctrl);
1219                 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1220                                  dd->ipath_sendctrl);
1221
1222                 if (dd->ipath_portpiowait)
1223                         handle_port_pioavail(dd);
1224
1225                 handle_layer_pioavail(dd);
1226         }
1227
1228 done:
1229         ret = IRQ_HANDLED;
1230
1231 bail:
1232         return ret;
1233 }