drivers/infiniband/hw/ipath/ipath_init_chip.c

   1 /*
   2  * Copyright (c) 2006, 2007, 2008 QLogic Corporation. All rights reserved.
   3  * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 #include <linux/pci.h>
  35 #include <linux/netdevice.h>
  36 #include <linux/slab.h>
  37 #include <linux/vmalloc.h>
  38
  39 #include "ipath_kernel.h"
  40 #include "ipath_common.h"
  41
  42 /*
  43  * min buffers we want to have per port, after driver
  44  */
  45 #define IPATH_MIN_USER_PORT_BUFCNT 7
  46
  47 /*
  48  * Number of ports we are configured to use (to allow for more pio
  49  * buffers per port, etc.)  Zero means use chip value.
  50  */
  51 static ushort ipath_cfgports;
  52
  53 module_param_named(cfgports, ipath_cfgports, ushort, S_IRUGO);
  54 MODULE_PARM_DESC(cfgports, "Set max number of ports to use");
  55
  56 /*
  57  * Number of buffers reserved for driver (verbs and layered drivers.)
  58  * Initialized based on number of PIO buffers if not set via module interface.
  59  * The problem with this is that it's global, but we'll use different
  60  * numbers for different chip types.
  61  */
  62 static ushort ipath_kpiobufs;
  63
  64 static int ipath_set_kpiobufs(const char *val, struct kernel_param *kp);
  65
  66 module_param_call(kpiobufs, ipath_set_kpiobufs, param_get_ushort,
  67                   &ipath_kpiobufs, S_IWUSR | S_IRUGO);
  68 MODULE_PARM_DESC(kpiobufs, "Set number of PIO buffers for driver");
  69
  70 /**
  71  * create_port0_egr - allocate the eager TID buffers
  72  * @dd: the infinipath device
  73  *
  74  * This code is now quite different for user and kernel, because
  75  * the kernel uses skb's, for the accelerated network performance.
  76  * This is the kernel (port0) version.
  77  *
  78  * Allocate the eager TID buffers and program them into infinipath.
  79  * We use the network layer alloc_skb() allocator to allocate the
  80  * memory, and either use the buffers as is for things like verbs
  81  * packets, or pass the buffers up to the ipath layered driver and
  82  * thence the network layer, replacing them as we do so (see
  83  * ipath_rcv_layer()).
  84  */
  85 static int create_port0_egr(struct ipath_devdata *dd)
  86 {
  87         unsigned e, egrcnt;
  88         struct ipath_skbinfo *skbinfo;
  89         int ret;
  90
  91         egrcnt = dd->ipath_p0_rcvegrcnt;
  92
  93         skbinfo = vmalloc(sizeof(*dd->ipath_port0_skbinfo) * egrcnt);
  94         if (skbinfo == NULL) {
  95                 ipath_dev_err(dd, "allocation error for eager TID "
  96                               "skb array\n");
  97                 ret = -ENOMEM;
  98                 goto bail;
  99         }
 100         for (e = 0; e < egrcnt; e++) {
 101                 /*
 102                  * This is a bit tricky in that we allocate extra
 103                  * space for 2 bytes of the 14 byte ethernet header.
 104                  * These two bytes are passed in the ipath header so
 105                  * the rest of the data is word aligned.  We allocate
 106                  * 4 bytes so that the data buffer stays word aligned.
 107                  * See ipath_kreceive() for more details.
 108                  */
 109                 skbinfo[e].skb = ipath_alloc_skb(dd, GFP_KERNEL);
 110                 if (!skbinfo[e].skb) {
 111                         ipath_dev_err(dd, "SKB allocation error for "
 112                                       "eager TID %u\n", e);
 113                         while (e != 0)
 114                                 dev_kfree_skb(skbinfo[--e].skb);
 115                         vfree(skbinfo);
 116                         ret = -ENOMEM;
 117                         goto bail;
 118                 }
 119         }
 120         /*
 121          * After loop above, so we can test non-NULL to see if ready
 122          * to use at receive, etc.
 123          */
 124         dd->ipath_port0_skbinfo = skbinfo;
 125
 126         for (e = 0; e < egrcnt; e++) {
 127                 dd->ipath_port0_skbinfo[e].phys =
 128                   ipath_map_single(dd->pcidev,
 129                                    dd->ipath_port0_skbinfo[e].skb->data,
 130                                    dd->ipath_ibmaxlen, PCI_DMA_FROMDEVICE);
 131                 dd->ipath_f_put_tid(dd, e + (u64 __iomem *)
 132                                     ((char __iomem *) dd->ipath_kregbase +
 133                                      dd->ipath_rcvegrbase),
 134                                     RCVHQ_RCV_TYPE_EAGER,
 135                                     dd->ipath_port0_skbinfo[e].phys);
 136         }
 137
 138         ret = 0;
 139
 140 bail:
 141         return ret;
 142 }
 143
 144 static int bringup_link(struct ipath_devdata *dd)
 145 {
 146         u64 val, ibc;
 147         int ret = 0;
 148
 149         /* hold IBC in reset */
 150         dd->ipath_control &= ~INFINIPATH_C_LINKENABLE;
 151         ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
 152                          dd->ipath_control);
 153
 154         /*
 155          * set initial max size pkt IBC will send, including ICRC; it's the
 156          * PIO buffer size in dwords, less 1; also see ipath_set_mtu()
 157          */
 158         val = (dd->ipath_ibmaxlen >> 2) + 1;
 159         ibc = val << dd->ibcc_mpl_shift;
 160
 161         /* flowcontrolwatermark is in units of KBytes */
 162         ibc |= 0x5ULL << INFINIPATH_IBCC_FLOWCTRLWATERMARK_SHIFT;
 163         /*
 164          * How often flowctrl sent.  More or less in usecs; balance against
 165          * watermark value, so that in theory senders always get a flow
 166          * control update in time to not let the IB link go idle.
 167          */
 168         ibc |= 0x3ULL << INFINIPATH_IBCC_FLOWCTRLPERIOD_SHIFT;
 169         /* max error tolerance */
 170         ibc |= 0xfULL << INFINIPATH_IBCC_PHYERRTHRESHOLD_SHIFT;
 171         /* use "real" buffer space for */
 172         ibc |= 4ULL << INFINIPATH_IBCC_CREDITSCALE_SHIFT;
 173         /* IB credit flow control. */
 174         ibc |= 0xfULL << INFINIPATH_IBCC_OVERRUNTHRESHOLD_SHIFT;
 175         /* initially come up waiting for TS1, without sending anything. */
 176         dd->ipath_ibcctrl = ibc;
 177         /*
 178          * Want to start out with both LINKCMD and LINKINITCMD in NOP
 179          * (0 and 0).  Don't put linkinitcmd in ipath_ibcctrl, want that
 180          * to stay a NOP. Flag that we are disabled, for the (unlikely)
 181          * case that some recovery path is trying to bring the link up
 182          * before we are ready.
 183          */
 184         ibc |= INFINIPATH_IBCC_LINKINITCMD_DISABLE <<
 185                 INFINIPATH_IBCC_LINKINITCMD_SHIFT;
 186         dd->ipath_flags |= IPATH_IB_LINK_DISABLED;
 187         ipath_cdbg(VERBOSE, "Writing 0x%llx to ibcctrl\n",
 188                    (unsigned long long) ibc);
 189         ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl, ibc);
 190
 191         // be sure chip saw it
 192         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 193
 194         ret = dd->ipath_f_bringup_serdes(dd);
 195
 196         if (ret)
 197                 dev_info(&dd->pcidev->dev, "Could not initialize SerDes, "
 198                          "not usable\n");
 199         else {
 200                 /* enable IBC */
 201                 dd->ipath_control |= INFINIPATH_C_LINKENABLE;
 202                 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
 203                                  dd->ipath_control);
 204         }
 205
 206         return ret;
 207 }
 208
 209 static struct ipath_portdata *create_portdata0(struct ipath_devdata *dd)
 210 {
 211         struct ipath_portdata *pd = NULL;
 212
 213         pd = kzalloc(sizeof(*pd), GFP_KERNEL);
 214         if (pd) {
 215                 pd->port_dd = dd;
 216                 pd->port_cnt = 1;
 217                 /* The port 0 pkey table is used by the layer interface. */
 218                 pd->port_pkeys[0] = IPATH_DEFAULT_P_KEY;
 219                 pd->port_seq_cnt = 1;
 220         }
 221         return pd;
 222 }
 223
 224 static int init_chip_first(struct ipath_devdata *dd)
 225 {
 226         struct ipath_portdata *pd;
 227         int ret = 0;
 228         u64 val;
 229
 230         spin_lock_init(&dd->ipath_kernel_tid_lock);
 231         spin_lock_init(&dd->ipath_user_tid_lock);
 232         spin_lock_init(&dd->ipath_sendctrl_lock);
 233         spin_lock_init(&dd->ipath_uctxt_lock);
 234         spin_lock_init(&dd->ipath_sdma_lock);
 235         spin_lock_init(&dd->ipath_gpio_lock);
 236         spin_lock_init(&dd->ipath_eep_st_lock);
 237         spin_lock_init(&dd->ipath_sdepb_lock);
 238         mutex_init(&dd->ipath_eep_lock);
 239
 240         /*
 241          * skip cfgports stuff because we are not allocating memory,
 242          * and we don't want problems if the portcnt changed due to
 243          * cfgports.  We do still check and report a difference, if
 244          * not same (should be impossible).
 245          */
 246         dd->ipath_f_config_ports(dd, ipath_cfgports);
 247         if (!ipath_cfgports)
 248                 dd->ipath_cfgports = dd->ipath_portcnt;
 249         else if (ipath_cfgports <= dd->ipath_portcnt) {
 250                 dd->ipath_cfgports = ipath_cfgports;
 251                 ipath_dbg("Configured to use %u ports out of %u in chip\n",
 252                           dd->ipath_cfgports, ipath_read_kreg32(dd,
 253                           dd->ipath_kregs->kr_portcnt));
 254         } else {
 255                 dd->ipath_cfgports = dd->ipath_portcnt;
 256                 ipath_dbg("Tried to configured to use %u ports; chip "
 257                           "only supports %u\n", ipath_cfgports,
 258                           ipath_read_kreg32(dd,
 259                                   dd->ipath_kregs->kr_portcnt));
 260         }
 261         /*
 262          * Allocate full portcnt array, rather than just cfgports, because
 263          * cleanup iterates across all possible ports.
 264          */
 265         dd->ipath_pd = kzalloc(sizeof(*dd->ipath_pd) * dd->ipath_portcnt,
 266                                GFP_KERNEL);
 267
 268         if (!dd->ipath_pd) {
 269                 ipath_dev_err(dd, "Unable to allocate portdata array, "
 270                               "failing\n");
 271                 ret = -ENOMEM;
 272                 goto done;
 273         }
 274
 275         pd = create_portdata0(dd);
 276         if (!pd) {
 277                 ipath_dev_err(dd, "Unable to allocate portdata for port "
 278                               "0, failing\n");
 279                 ret = -ENOMEM;
 280                 goto done;
 281         }
 282         dd->ipath_pd[0] = pd;
 283
 284         dd->ipath_rcvtidcnt =
 285                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidcnt);
 286         dd->ipath_rcvtidbase =
 287                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidbase);
 288         dd->ipath_rcvegrcnt =
 289                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt);
 290         dd->ipath_rcvegrbase =
 291                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrbase);
 292         dd->ipath_palign =
 293                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_pagealign);
 294         dd->ipath_piobufbase =
 295                 ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiobufbase);
 296         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiosize);
 297         dd->ipath_piosize2k = val & ~0U;
 298         dd->ipath_piosize4k = val >> 32;
 299         if (dd->ipath_piosize4k == 0 && ipath_mtu4096)
 300                 ipath_mtu4096 = 0; /* 4KB not supported by this chip */
 301         dd->ipath_ibmtu = ipath_mtu4096 ? 4096 : 2048;
 302         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiobufcnt);
 303         dd->ipath_piobcnt2k = val & ~0U;
 304         dd->ipath_piobcnt4k = val >> 32;
 305         dd->ipath_pio2kbase =
 306                 (u32 __iomem *) (((char __iomem *) dd->ipath_kregbase) +
 307                                  (dd->ipath_piobufbase & 0xffffffff));
 308         if (dd->ipath_piobcnt4k) {
 309                 dd->ipath_pio4kbase = (u32 __iomem *)
 310                         (((char __iomem *) dd->ipath_kregbase) +
 311                          (dd->ipath_piobufbase >> 32));
 312                 /*
 313                  * 4K buffers take 2 pages; we use roundup just to be
 314                  * paranoid; we calculate it once here, rather than on
 315                  * ever buf allocate
 316                  */
 317                 dd->ipath_4kalign = ALIGN(dd->ipath_piosize4k,
 318                                           dd->ipath_palign);
 319                 ipath_dbg("%u 2k(%x) piobufs @ %p, %u 4k(%x) @ %p "
 320                           "(%x aligned)\n",
 321                           dd->ipath_piobcnt2k, dd->ipath_piosize2k,
 322                           dd->ipath_pio2kbase, dd->ipath_piobcnt4k,
 323                           dd->ipath_piosize4k, dd->ipath_pio4kbase,
 324                           dd->ipath_4kalign);
 325         }
 326         else ipath_dbg("%u 2k piobufs @ %p\n",
 327                        dd->ipath_piobcnt2k, dd->ipath_pio2kbase);
 328
 329 done:
 330         return ret;
 331 }
 332
 333 /**
 334  * init_chip_reset - re-initialize after a reset, or enable
 335  * @dd: the infinipath device
 336  *
 337  * sanity check at least some of the values after reset, and
 338  * ensure no receive or transmit (explicitly, in case reset
 339  * failed
 340  */
 341 static int init_chip_reset(struct ipath_devdata *dd)
 342 {
 343         u32 rtmp;
 344         int i;
 345         unsigned long flags;
 346
 347         /*
 348          * ensure chip does no sends or receives, tail updates, or
 349          * pioavail updates while we re-initialize
 350          */
 351         dd->ipath_rcvctrl &= ~(1ULL << dd->ipath_r_tailupd_shift);
 352         for (i = 0; i < dd->ipath_portcnt; i++) {
 353                 clear_bit(dd->ipath_r_portenable_shift + i,
 354                           &dd->ipath_rcvctrl);
 355                 clear_bit(dd->ipath_r_intravail_shift + i,
 356                           &dd->ipath_rcvctrl);
 357         }
 358         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
 359                 dd->ipath_rcvctrl);
 360
 361         spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
 362         dd->ipath_sendctrl = 0U; /* no sdma, etc */
 363         ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
 364         ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 365         spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
 366
 367         ipath_write_kreg(dd, dd->ipath_kregs->kr_control, 0ULL);
 368
 369         rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidcnt);
 370         if (rtmp != dd->ipath_rcvtidcnt)
 371                 dev_info(&dd->pcidev->dev, "tidcnt was %u before "
 372                          "reset, now %u, using original\n",
 373                          dd->ipath_rcvtidcnt, rtmp);
 374         rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidbase);
 375         if (rtmp != dd->ipath_rcvtidbase)
 376                 dev_info(&dd->pcidev->dev, "tidbase was %u before "
 377                          "reset, now %u, using original\n",
 378                          dd->ipath_rcvtidbase, rtmp);
 379         rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt);
 380         if (rtmp != dd->ipath_rcvegrcnt)
 381                 dev_info(&dd->pcidev->dev, "egrcnt was %u before "
 382                          "reset, now %u, using original\n",
 383                          dd->ipath_rcvegrcnt, rtmp);
 384         rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrbase);
 385         if (rtmp != dd->ipath_rcvegrbase)
 386                 dev_info(&dd->pcidev->dev, "egrbase was %u before "
 387                          "reset, now %u, using original\n",
 388                          dd->ipath_rcvegrbase, rtmp);
 389
 390         return 0;
 391 }
 392
 393 static int init_pioavailregs(struct ipath_devdata *dd)
 394 {
 395         int ret;
 396
 397         dd->ipath_pioavailregs_dma = dma_alloc_coherent(
 398                 &dd->pcidev->dev, PAGE_SIZE, &dd->ipath_pioavailregs_phys,
 399                 GFP_KERNEL);
 400         if (!dd->ipath_pioavailregs_dma) {
 401                 ipath_dev_err(dd, "failed to allocate PIOavail reg area "
 402                               "in memory\n");
 403                 ret = -ENOMEM;
 404                 goto done;
 405         }
 406
 407         /*
 408          * we really want L2 cache aligned, but for current CPUs of
 409          * interest, they are the same.
 410          */
 411         dd->ipath_statusp = (u64 *)
 412                 ((char *)dd->ipath_pioavailregs_dma +
 413                  ((2 * L1_CACHE_BYTES +
 414                    dd->ipath_pioavregs * sizeof(u64)) & ~L1_CACHE_BYTES));
 415         /* copy the current value now that it's really allocated */
 416         *dd->ipath_statusp = dd->_ipath_status;
 417         /*
 418          * setup buffer to hold freeze msg, accessible to apps,
 419          * following statusp
 420          */
 421         dd->ipath_freezemsg = (char *)&dd->ipath_statusp[1];
 422         /* and its length */
 423         dd->ipath_freezelen = L1_CACHE_BYTES - sizeof(dd->ipath_statusp[0]);
 424
 425         ret = 0;
 426
 427 done:
 428         return ret;
 429 }
 430
 431 /**
 432  * init_shadow_tids - allocate the shadow TID array
 433  * @dd: the infinipath device
 434  *
 435  * allocate the shadow TID array, so we can ipath_munlock previous
 436  * entries.  It may make more sense to move the pageshadow to the
 437  * port data structure, so we only allocate memory for ports actually
 438  * in use, since we at 8k per port, now.
 439  */
 440 static void init_shadow_tids(struct ipath_devdata *dd)
 441 {
 442         struct page **pages;
 443         dma_addr_t *addrs;
 444
 445         pages = vzalloc(dd->ipath_cfgports * dd->ipath_rcvtidcnt *
 446                         sizeof(struct page *));
 447         if (!pages) {
 448                 ipath_dev_err(dd, "failed to allocate shadow page * "
 449                               "array, no expected sends!\n");
 450                 dd->ipath_pageshadow = NULL;
 451                 return;
 452         }
 453
 454         addrs = vmalloc(dd->ipath_cfgports * dd->ipath_rcvtidcnt *
 455                         sizeof(dma_addr_t));
 456         if (!addrs) {
 457                 ipath_dev_err(dd, "failed to allocate shadow dma handle "
 458                               "array, no expected sends!\n");
 459                 vfree(pages);
 460                 dd->ipath_pageshadow = NULL;
 461                 return;
 462         }
 463
 464         dd->ipath_pageshadow = pages;
 465         dd->ipath_physshadow = addrs;
 466 }
 467
 468 static void enable_chip(struct ipath_devdata *dd, int reinit)
 469 {
 470         u32 val;
 471         u64 rcvmask;
 472         unsigned long flags;
 473         int i;
 474
 475         if (!reinit)
 476                 init_waitqueue_head(&ipath_state_wait);
 477
 478         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
 479                          dd->ipath_rcvctrl);
 480
 481         spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
 482         /* Enable PIO send, and update of PIOavail regs to memory. */
 483         dd->ipath_sendctrl = INFINIPATH_S_PIOENABLE |
 484                 INFINIPATH_S_PIOBUFAVAILUPD;
 485
 486         /*
 487          * Set the PIO avail update threshold to host memory
 488          * on chips that support it.
 489          */
 490         if (dd->ipath_pioupd_thresh)
 491                 dd->ipath_sendctrl |= dd->ipath_pioupd_thresh
 492                         << INFINIPATH_S_UPDTHRESH_SHIFT;
 493         ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
 494         ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 495         spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
 496
 497         /*
 498          * Enable kernel ports' receive and receive interrupt.
 499          * Other ports done as user opens and inits them.
 500          */
 501         rcvmask = 1ULL;
 502         dd->ipath_rcvctrl |= (rcvmask << dd->ipath_r_portenable_shift) |
 503                 (rcvmask << dd->ipath_r_intravail_shift);
 504         if (!(dd->ipath_flags & IPATH_NODMA_RTAIL))
 505                 dd->ipath_rcvctrl |= (1ULL << dd->ipath_r_tailupd_shift);
 506
 507         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
 508                          dd->ipath_rcvctrl);
 509
 510         /*
 511          * now ready for use.  this should be cleared whenever we
 512          * detect a reset, or initiate one.
 513          */
 514         dd->ipath_flags |= IPATH_INITTED;
 515
 516         /*
 517          * Init our shadow copies of head from tail values,
 518          * and write head values to match.
 519          */
 520         val = ipath_read_ureg32(dd, ur_rcvegrindextail, 0);
 521         ipath_write_ureg(dd, ur_rcvegrindexhead, val, 0);
 522
 523         /* Initialize so we interrupt on next packet received */
 524         ipath_write_ureg(dd, ur_rcvhdrhead,
 525                          dd->ipath_rhdrhead_intr_off |
 526                          dd->ipath_pd[0]->port_head, 0);
 527
 528         /*
 529          * by now pioavail updates to memory should have occurred, so
 530          * copy them into our working/shadow registers; this is in
 531          * case something went wrong with abort, but mostly to get the
 532          * initial values of the generation bit correct.
 533          */
 534         for (i = 0; i < dd->ipath_pioavregs; i++) {
 535                 __le64 pioavail;
 536
 537                 /*
 538                  * Chip Errata bug 6641; even and odd qwords>3 are swapped.
 539                  */
 540                 if (i > 3 && (dd->ipath_flags & IPATH_SWAP_PIOBUFS))
 541                         pioavail = dd->ipath_pioavailregs_dma[i ^ 1];
 542                 else
 543                         pioavail = dd->ipath_pioavailregs_dma[i];
 544                 /*
 545                  * don't need to worry about ipath_pioavailkernel here
 546                  * because we will call ipath_chg_pioavailkernel() later
 547                  * in initialization, to busy out buffers as needed
 548                  */
 549                 dd->ipath_pioavailshadow[i] = le64_to_cpu(pioavail);
 550         }
 551         /* can get counters, stats, etc. */
 552         dd->ipath_flags |= IPATH_PRESENT;
 553 }
 554
 555 static int init_housekeeping(struct ipath_devdata *dd, int reinit)
 556 {
 557         char boardn[40];
 558         int ret = 0;
 559
 560         /*
 561          * have to clear shadow copies of registers at init that are
 562          * not otherwise set here, or all kinds of bizarre things
 563          * happen with driver on chip reset
 564          */
 565         dd->ipath_rcvhdrsize = 0;
 566
 567         /*
 568          * Don't clear ipath_flags as 8bit mode was set before
 569          * entering this func. However, we do set the linkstate to
 570          * unknown, so we can watch for a transition.
 571          * PRESENT is set because we want register reads to work,
 572          * and the kernel infrastructure saw it in config space;
 573          * We clear it if we have failures.
 574          */
 575         dd->ipath_flags |= IPATH_LINKUNK | IPATH_PRESENT;
 576         dd->ipath_flags &= ~(IPATH_LINKACTIVE | IPATH_LINKARMED |
 577                              IPATH_LINKDOWN | IPATH_LINKINIT);
 578
 579         ipath_cdbg(VERBOSE, "Try to read spc chip revision\n");
 580         dd->ipath_revision =
 581                 ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision);
 582
 583         /*
 584          * set up fundamental info we need to use the chip; we assume
 585          * if the revision reg and these regs are OK, we don't need to
 586          * special case the rest
 587          */
 588         dd->ipath_sregbase =
 589                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_sendregbase);
 590         dd->ipath_cregbase =
 591                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_counterregbase);
 592         dd->ipath_uregbase =
 593                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_userregbase);
 594         ipath_cdbg(VERBOSE, "ipath_kregbase %p, sendbase %x usrbase %x, "
 595                    "cntrbase %x\n", dd->ipath_kregbase, dd->ipath_sregbase,
 596                    dd->ipath_uregbase, dd->ipath_cregbase);
 597         if ((dd->ipath_revision & 0xffffffff) == 0xffffffff
 598             || (dd->ipath_sregbase & 0xffffffff) == 0xffffffff
 599             || (dd->ipath_cregbase & 0xffffffff) == 0xffffffff
 600             || (dd->ipath_uregbase & 0xffffffff) == 0xffffffff) {
 601                 ipath_dev_err(dd, "Register read failures from chip, "
 602                               "giving up initialization\n");
 603                 dd->ipath_flags &= ~IPATH_PRESENT;
 604                 ret = -ENODEV;
 605                 goto done;
 606         }
 607
 608
 609         /* clear diagctrl register, in case diags were running and crashed */
 610         ipath_write_kreg (dd, dd->ipath_kregs->kr_hwdiagctrl, 0);
 611
 612         /* clear the initial reset flag, in case first driver load */
 613         ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear,
 614                          INFINIPATH_E_RESET);
 615
 616         ipath_cdbg(VERBOSE, "Revision %llx (PCI %x)\n",
 617                    (unsigned long long) dd->ipath_revision,
 618                    dd->ipath_pcirev);
 619
 620         if (((dd->ipath_revision >> INFINIPATH_R_SOFTWARE_SHIFT) &
 621              INFINIPATH_R_SOFTWARE_MASK) != IPATH_CHIP_SWVERSION) {
 622                 ipath_dev_err(dd, "Driver only handles version %d, "
 623                               "chip swversion is %d (%llx), failng\n",
 624                               IPATH_CHIP_SWVERSION,
 625                               (int)(dd->ipath_revision >>
 626                                     INFINIPATH_R_SOFTWARE_SHIFT) &
 627                               INFINIPATH_R_SOFTWARE_MASK,
 628                               (unsigned long long) dd->ipath_revision);
 629                 ret = -ENOSYS;
 630                 goto done;
 631         }
 632         dd->ipath_majrev = (u8) ((dd->ipath_revision >>
 633                                   INFINIPATH_R_CHIPREVMAJOR_SHIFT) &
 634                                  INFINIPATH_R_CHIPREVMAJOR_MASK);
 635         dd->ipath_minrev = (u8) ((dd->ipath_revision >>
 636                                   INFINIPATH_R_CHIPREVMINOR_SHIFT) &
 637                                  INFINIPATH_R_CHIPREVMINOR_MASK);
 638         dd->ipath_boardrev = (u8) ((dd->ipath_revision >>
 639                                     INFINIPATH_R_BOARDID_SHIFT) &
 640                                    INFINIPATH_R_BOARDID_MASK);
 641
 642         ret = dd->ipath_f_get_boardname(dd, boardn, sizeof boardn);
 643
 644         snprintf(dd->ipath_boardversion, sizeof(dd->ipath_boardversion),
 645                  "ChipABI %u.%u, %s, InfiniPath%u %u.%u, PCI %u, "
 646                  "SW Compat %u\n",
 647                  IPATH_CHIP_VERS_MAJ, IPATH_CHIP_VERS_MIN, boardn,
 648                  (unsigned)(dd->ipath_revision >> INFINIPATH_R_ARCH_SHIFT) &
 649                  INFINIPATH_R_ARCH_MASK,
 650                  dd->ipath_majrev, dd->ipath_minrev, dd->ipath_pcirev,
 651                  (unsigned)(dd->ipath_revision >>
 652                             INFINIPATH_R_SOFTWARE_SHIFT) &
 653                  INFINIPATH_R_SOFTWARE_MASK);
 654
 655         ipath_dbg("%s", dd->ipath_boardversion);
 656
 657         if (ret)
 658                 goto done;
 659
 660         if (reinit)
 661                 ret = init_chip_reset(dd);
 662         else
 663                 ret = init_chip_first(dd);
 664
 665 done:
 666         return ret;
 667 }
 668
 669 static void verify_interrupt(unsigned long opaque)
 670 {
 671         struct ipath_devdata *dd = (struct ipath_devdata *) opaque;
 672
 673         if (!dd)
 674                 return; /* being torn down */
 675
 676         /*
 677          * If we don't have any interrupts, let the user know and
 678          * don't bother checking again.
 679          */
 680         if (dd->ipath_int_counter == 0) {
 681                 if (!dd->ipath_f_intr_fallback(dd))
 682                         dev_err(&dd->pcidev->dev, "No interrupts detected, "
 683                                 "not usable.\n");
 684                 else /* re-arm the timer to see if fallback works */
 685                         mod_timer(&dd->ipath_intrchk_timer, jiffies + HZ/2);
 686         } else
 687                 ipath_cdbg(VERBOSE, "%u interrupts at timer check\n",
 688                         dd->ipath_int_counter);
 689 }
 690
 691 /**
 692  * ipath_init_chip - do the actual initialization sequence on the chip
 693  * @dd: the infinipath device
 694  * @reinit: reinitializing, so don't allocate new memory
 695  *
 696  * Do the actual initialization sequence on the chip.  This is done
 697  * both from the init routine called from the PCI infrastructure, and
 698  * when we reset the chip, or detect that it was reset internally,
 699  * or it's administratively re-enabled.
 700  *
 701  * Memory allocation here and in called routines is only done in
 702  * the first case (reinit == 0).  We have to be careful, because even
 703  * without memory allocation, we need to re-write all the chip registers
 704  * TIDs, etc. after the reset or enable has completed.
 705  */
 706 int ipath_init_chip(struct ipath_devdata *dd, int reinit)
 707 {
 708         int ret = 0;
 709         u32 kpiobufs, defkbufs;
 710         u32 piobufs, uports;
 711         u64 val;
 712         struct ipath_portdata *pd;
 713         gfp_t gfp_flags = GFP_USER | __GFP_COMP;
 714
 715         ret = init_housekeeping(dd, reinit);
 716         if (ret)
 717                 goto done;
 718
 719         /*
 720          * we ignore most issues after reporting them, but have to specially
 721          * handle hardware-disabled chips.
 722          */
 723         if (ret == 2) {
 724                 /* unique error, known to ipath_init_one */
 725                 ret = -EPERM;
 726                 goto done;
 727         }
 728
 729         /*
 730          * We could bump this to allow for full rcvegrcnt + rcvtidcnt,
 731          * but then it no longer nicely fits power of two, and since
 732          * we now use routines that backend onto __get_free_pages, the
 733          * rest would be wasted.
 734          */
 735         dd->ipath_rcvhdrcnt = max(dd->ipath_p0_rcvegrcnt, dd->ipath_rcvegrcnt);
 736         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrcnt,
 737                          dd->ipath_rcvhdrcnt);
 738
 739         /*
 740          * Set up the shadow copies of the piobufavail registers,
 741          * which we compare against the chip registers for now, and
 742          * the in memory DMA'ed copies of the registers.  This has to
 743          * be done early, before we calculate lastport, etc.
 744          */
 745         piobufs = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k;
 746         /*
 747          * calc number of pioavail registers, and save it; we have 2
 748          * bits per buffer.
 749          */
 750         dd->ipath_pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2)
 751                 / (sizeof(u64) * BITS_PER_BYTE / 2);
 752         uports = dd->ipath_cfgports ? dd->ipath_cfgports - 1 : 0;
 753         if (piobufs > 144)
 754                 defkbufs = 32 + dd->ipath_pioreserved;
 755         else
 756                 defkbufs = 16 + dd->ipath_pioreserved;
 757
 758         if (ipath_kpiobufs && (ipath_kpiobufs +
 759                 (uports * IPATH_MIN_USER_PORT_BUFCNT)) > piobufs) {
 760                 int i = (int) piobufs -
 761                         (int) (uports * IPATH_MIN_USER_PORT_BUFCNT);
 762                 if (i < 1)
 763                         i = 1;
 764                 dev_info(&dd->pcidev->dev, "Allocating %d PIO bufs of "
 765                          "%d for kernel leaves too few for %d user ports "
 766                          "(%d each); using %u\n", ipath_kpiobufs,
 767                          piobufs, uports, IPATH_MIN_USER_PORT_BUFCNT, i);
 768                 /*
 769                  * shouldn't change ipath_kpiobufs, because could be
 770                  * different for different devices...
 771                  */
 772                 kpiobufs = i;
 773         } else if (ipath_kpiobufs)
 774                 kpiobufs = ipath_kpiobufs;
 775         else
 776                 kpiobufs = defkbufs;
 777         dd->ipath_lastport_piobuf = piobufs - kpiobufs;
 778         dd->ipath_pbufsport =
 779                 uports ? dd->ipath_lastport_piobuf / uports : 0;
 780         /* if not an even divisor, some user ports get extra buffers */
 781         dd->ipath_ports_extrabuf = dd->ipath_lastport_piobuf -
 782                 (dd->ipath_pbufsport * uports);
 783         if (dd->ipath_ports_extrabuf)
 784                 ipath_dbg("%u pbufs/port leaves some unused, add 1 buffer to "
 785                         "ports <= %u\n", dd->ipath_pbufsport,
 786                         dd->ipath_ports_extrabuf);
 787         dd->ipath_lastpioindex = 0;
 788         dd->ipath_lastpioindexl = dd->ipath_piobcnt2k;
 789         /* ipath_pioavailshadow initialized earlier */
 790         ipath_cdbg(VERBOSE, "%d PIO bufs for kernel out of %d total %u "
 791                    "each for %u user ports\n", kpiobufs,
 792                    piobufs, dd->ipath_pbufsport, uports);
 793         ret = dd->ipath_f_early_init(dd);
 794         if (ret) {
 795                 ipath_dev_err(dd, "Early initialization failure\n");
 796                 goto done;
 797         }
 798
 799         /*
 800          * Early_init sets rcvhdrentsize and rcvhdrsize, so this must be
 801          * done after early_init.
 802          */
 803         dd->ipath_hdrqlast =
 804                 dd->ipath_rcvhdrentsize * (dd->ipath_rcvhdrcnt - 1);
 805         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrentsize,
 806                          dd->ipath_rcvhdrentsize);
 807         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrsize,
 808                          dd->ipath_rcvhdrsize);
 809
 810         if (!reinit) {
 811                 ret = init_pioavailregs(dd);
 812                 init_shadow_tids(dd);
 813                 if (ret)
 814                         goto done;
 815         }
 816
 817         ipath_write_kreg(dd, dd->ipath_kregs->kr_sendpioavailaddr,
 818                          dd->ipath_pioavailregs_phys);
 819
 820         /*
 821          * this is to detect s/w errors, which the h/w works around by
 822          * ignoring the low 6 bits of address, if it wasn't aligned.
 823          */
 824         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpioavailaddr);
 825         if (val != dd->ipath_pioavailregs_phys) {
 826                 ipath_dev_err(dd, "Catastrophic software error, "
 827                               "SendPIOAvailAddr written as %lx, "
 828                               "read back as %llx\n",
 829                               (unsigned long) dd->ipath_pioavailregs_phys,
 830                               (unsigned long long) val);
 831                 ret = -EINVAL;
 832                 goto done;
 833         }
 834
 835         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvbthqp, IPATH_KD_QP);
 836
 837         /*
 838          * make sure we are not in freeze, and PIO send enabled, so
 839          * writes to pbc happen
 840          */
 841         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask, 0ULL);
 842         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
 843                          ~0ULL&~INFINIPATH_HWE_MEMBISTFAILED);
 844         ipath_write_kreg(dd, dd->ipath_kregs->kr_control, 0ULL);
 845
 846         /*
 847          * before error clears, since we expect serdes pll errors during
 848          * this, the first time after reset
 849          */
 850         if (bringup_link(dd)) {
 851                 dev_info(&dd->pcidev->dev, "Failed to bringup IB link\n");
 852                 ret = -ENETDOWN;
 853                 goto done;
 854         }
 855
 856         /*
 857          * clear any "expected" hwerrs from reset and/or initialization
 858          * clear any that aren't enabled (at least this once), and then
 859          * set the enable mask
 860          */
 861         dd->ipath_f_init_hwerrors(dd);
 862         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
 863                          ~0ULL&~INFINIPATH_HWE_MEMBISTFAILED);
 864         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 865                          dd->ipath_hwerrmask);
 866
 867         /* clear all */
 868         ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, -1LL);
 869         /* enable errors that are masked, at least this first time. */
 870         ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
 871                          ~dd->ipath_maskederrs);
 872         dd->ipath_maskederrs = 0; /* don't re-enable ignored in timer */
 873         dd->ipath_errormask =
 874                 ipath_read_kreg64(dd, dd->ipath_kregs->kr_errormask);
 875         /* clear any interrupts up to this point (ints still not enabled) */
 876         ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, -1LL);
 877
 878         dd->ipath_f_tidtemplate(dd);
 879
 880         /*
 881          * Set up the port 0 (kernel) rcvhdr q and egr TIDs.  If doing
 882          * re-init, the simplest way to handle this is to free
 883          * existing, and re-allocate.
 884          * Need to re-create rest of port 0 portdata as well.
 885          */
 886         pd = dd->ipath_pd[0];
 887         if (reinit) {
 888                 struct ipath_portdata *npd;
 889
 890                 /*
 891                  * Alloc and init new ipath_portdata for port0,
 892                  * Then free old pd. Could lead to fragmentation, but also
 893                  * makes later support for hot-swap easier.
 894                  */
 895                 npd = create_portdata0(dd);
 896                 if (npd) {
 897                         ipath_free_pddata(dd, pd);
 898                         dd->ipath_pd[0] = npd;
 899                         pd = npd;
 900                 } else {
 901                         ipath_dev_err(dd, "Unable to allocate portdata"
 902                                       " for port 0, failing\n");
 903                         ret = -ENOMEM;
 904                         goto done;
 905                 }
 906         }
 907         ret = ipath_create_rcvhdrq(dd, pd);
 908         if (!ret)
 909                 ret = create_port0_egr(dd);
 910         if (ret) {
 911                 ipath_dev_err(dd, "failed to allocate kernel port's "
 912                               "rcvhdrq and/or egr bufs\n");
 913                 goto done;
 914         }
 915         else
 916                 enable_chip(dd, reinit);
 917
 918         /* after enable_chip, so pioavailshadow setup */
 919         ipath_chg_pioavailkernel(dd, 0, piobufs, 1);
 920
 921         /*
 922          * Cancel any possible active sends from early driver load.
 923          * Follows early_init because some chips have to initialize
 924          * PIO buffers in early_init to avoid false parity errors.
 925          * After enable and ipath_chg_pioavailkernel so we can safely
 926          * enable pioavail updates and PIOENABLE; packets are now
 927          * ready to go out.
 928          */
 929         ipath_cancel_sends(dd, 1);
 930
 931         if (!reinit) {
 932                 /*
 933                  * Used when we close a port, for DMA already in flight
 934                  * at close.
 935                  */
 936                 dd->ipath_dummy_hdrq = dma_alloc_coherent(
 937                         &dd->pcidev->dev, dd->ipath_pd[0]->port_rcvhdrq_size,
 938                         &dd->ipath_dummy_hdrq_phys,
 939                         gfp_flags);
 940                 if (!dd->ipath_dummy_hdrq) {
 941                         dev_info(&dd->pcidev->dev,
 942                                 "Couldn't allocate 0x%lx bytes for dummy hdrq\n",
 943                                 dd->ipath_pd[0]->port_rcvhdrq_size);
 944                         /* fallback to just 0'ing */
 945                         dd->ipath_dummy_hdrq_phys = 0UL;
 946                 }
 947         }
 948
 949         /*
 950          * cause retrigger of pending interrupts ignored during init,
 951          * even if we had errors
 952          */
 953         ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, 0ULL);
 954
 955         if (!dd->ipath_stats_timer_active) {
 956                 /*
 957                  * first init, or after an admin disable/enable
 958                  * set up stats retrieval timer, even if we had errors
 959                  * in last portion of setup
 960                  */
 961                 init_timer(&dd->ipath_stats_timer);
 962                 dd->ipath_stats_timer.function = ipath_get_faststats;
 963                 dd->ipath_stats_timer.data = (unsigned long) dd;
 964                 /* every 5 seconds; */
 965                 dd->ipath_stats_timer.expires = jiffies + 5 * HZ;
 966                 /* takes ~16 seconds to overflow at full IB 4x bandwdith */
 967                 add_timer(&dd->ipath_stats_timer);
 968                 dd->ipath_stats_timer_active = 1;
 969         }
 970
 971         /* Set up SendDMA if chip supports it */
 972         if (dd->ipath_flags & IPATH_HAS_SEND_DMA)
 973                 ret = setup_sdma(dd);
 974
 975         /* Set up HoL state */
 976         init_timer(&dd->ipath_hol_timer);
 977         dd->ipath_hol_timer.function = ipath_hol_event;
 978         dd->ipath_hol_timer.data = (unsigned long)dd;
 979         dd->ipath_hol_state = IPATH_HOL_UP;
 980
 981 done:
 982         if (!ret) {
 983                 *dd->ipath_statusp |= IPATH_STATUS_CHIP_PRESENT;
 984                 if (!dd->ipath_f_intrsetup(dd)) {
 985                         /* now we can enable all interrupts from the chip */
 986                         ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask,
 987                                          -1LL);
 988                         /* force re-interrupt of any pending interrupts. */
 989                         ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear,
 990                                          0ULL);
 991                         /* chip is usable; mark it as initialized */
 992                         *dd->ipath_statusp |= IPATH_STATUS_INITTED;
 993
 994                         /*
 995                          * setup to verify we get an interrupt, and fallback
 996                          * to an alternate if necessary and possible
 997                          */
 998                         if (!reinit) {
 999                                 init_timer(&dd->ipath_intrchk_timer);
1000                                 dd->ipath_intrchk_timer.function =
1001                                         verify_interrupt;
1002                                 dd->ipath_intrchk_timer.data =
1003                                         (unsigned long) dd;
1004                         }
1005                         dd->ipath_intrchk_timer.expires = jiffies + HZ/2;
1006                         add_timer(&dd->ipath_intrchk_timer);
1007                 } else
1008                         ipath_dev_err(dd, "No interrupts enabled, couldn't "
1009                                       "setup interrupt address\n");
1010
1011                 if (dd->ipath_cfgports > ipath_stats.sps_nports)
1012                         /*
1013                          * sps_nports is a global, so, we set it to
1014                          * the highest number of ports of any of the
1015                          * chips we find; we never decrement it, at
1016                          * least for now.  Since this might have changed
1017                          * over disable/enable or prior to reset, always
1018                          * do the check and potentially adjust.
1019                          */
1020                         ipath_stats.sps_nports = dd->ipath_cfgports;
1021         } else
1022                 ipath_dbg("Failed (%d) to initialize chip\n", ret);
1023
1024         /* if ret is non-zero, we probably should do some cleanup
1025            here... */
1026         return ret;
1027 }
1028
1029 static int ipath_set_kpiobufs(const char *str, struct kernel_param *kp)
1030 {
1031         struct ipath_devdata *dd;
1032         unsigned long flags;
1033         unsigned short val;
1034         int ret;
1035
1036         ret = ipath_parse_ushort(str, &val);
1037
1038         spin_lock_irqsave(&ipath_devs_lock, flags);
1039
1040         if (ret < 0)
1041                 goto bail;
1042
1043         if (val == 0) {
1044                 ret = -EINVAL;
1045                 goto bail;
1046         }
1047
1048         list_for_each_entry(dd, &ipath_dev_list, ipath_list) {
1049                 if (dd->ipath_kregbase)
1050                         continue;
1051                 if (val > (dd->ipath_piobcnt2k + dd->ipath_piobcnt4k -
1052                            (dd->ipath_cfgports *
1053                             IPATH_MIN_USER_PORT_BUFCNT)))
1054                 {
1055                         ipath_dev_err(
1056                                 dd,
1057                                 "Allocating %d PIO bufs for kernel leaves "
1058                                 "too few for %d user ports (%d each)\n",
1059                                 val, dd->ipath_cfgports - 1,
1060                                 IPATH_MIN_USER_PORT_BUFCNT);
1061                         ret = -EINVAL;
1062                         goto bail;
1063                 }
1064                 dd->ipath_lastport_piobuf =
1065                         dd->ipath_piobcnt2k + dd->ipath_piobcnt4k - val;
1066         }
1067
1068         ipath_kpiobufs = val;
1069         ret = 0;
1070 bail:
1071         spin_unlock_irqrestore(&ipath_devs_lock, flags);
1072
1073         return ret;
1074 }