drivers/infiniband/hw/cxgb3/cxio_hal.c

   1 /*
   2  * Copyright (c) 2006 Chelsio, Inc. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32 #include <asm/delay.h>
  33
  34 #include <linux/mutex.h>
  35 #include <linux/netdevice.h>
  36 #include <linux/sched.h>
  37 #include <linux/spinlock.h>
  38 #include <linux/pci.h>
  39 #include <linux/dma-mapping.h>
  40
  41 #include "cxio_resource.h"
  42 #include "cxio_hal.h"
  43 #include "cxgb3_offload.h"
  44 #include "sge_defs.h"
  45
  46 static LIST_HEAD(rdev_list);
  47 static cxio_hal_ev_callback_func_t cxio_ev_cb = NULL;
  48
  49 static struct cxio_rdev *cxio_hal_find_rdev_by_name(char *dev_name)
  50 {
  51         struct cxio_rdev *rdev;
  52
  53         list_for_each_entry(rdev, &rdev_list, entry)
  54                 if (!strcmp(rdev->dev_name, dev_name))
  55                         return rdev;
  56         return NULL;
  57 }
  58
  59 static struct cxio_rdev *cxio_hal_find_rdev_by_t3cdev(struct t3cdev *tdev)
  60 {
  61         struct cxio_rdev *rdev;
  62
  63         list_for_each_entry(rdev, &rdev_list, entry)
  64                 if (rdev->t3cdev_p == tdev)
  65                         return rdev;
  66         return NULL;
  67 }
  68
  69 int cxio_hal_cq_op(struct cxio_rdev *rdev_p, struct t3_cq *cq,
  70                    enum t3_cq_opcode op, u32 credit)
  71 {
  72         int ret;
  73         struct t3_cqe *cqe;
  74         u32 rptr;
  75
  76         struct rdma_cq_op setup;
  77         setup.id = cq->cqid;
  78         setup.credits = (op == CQ_CREDIT_UPDATE) ? credit : 0;
  79         setup.op = op;
  80         ret = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_OP, &setup);
  81
  82         if ((ret < 0) || (op == CQ_CREDIT_UPDATE))
  83                 return ret;
  84
  85         /*
  86          * If the rearm returned an index other than our current index,
  87          * then there might be CQE's in flight (being DMA'd).  We must wait
  88          * here for them to complete or the consumer can miss a notification.
  89          */
  90         if (Q_PTR2IDX((cq->rptr), cq->size_log2) != ret) {
  91                 int i=0;
  92
  93                 rptr = cq->rptr;
  94
  95                 /*
  96                  * Keep the generation correct by bumping rptr until it
  97                  * matches the index returned by the rearm - 1.
  98                  */
  99                 while (Q_PTR2IDX((rptr+1), cq->size_log2) != ret)
 100                         rptr++;
 101
 102                 /*
 103                  * Now rptr is the index for the (last) cqe that was
 104                  * in-flight at the time the HW rearmed the CQ.  We
 105                  * spin until that CQE is valid.
 106                  */
 107                 cqe = cq->queue + Q_PTR2IDX(rptr, cq->size_log2);
 108                 while (!CQ_VLD_ENTRY(rptr, cq->size_log2, cqe)) {
 109                         udelay(1);
 110                         if (i++ > 1000000) {
 111                                 BUG_ON(1);
 112                                 printk(KERN_ERR "%s: stalled rnic\n",
 113                                        rdev_p->dev_name);
 114                                 return -EIO;
 115                         }
 116                 }
 117         }
 118         return 0;
 119 }
 120
 121 static int cxio_hal_clear_cq_ctx(struct cxio_rdev *rdev_p, u32 cqid)
 122 {
 123         struct rdma_cq_setup setup;
 124         setup.id = cqid;
 125         setup.base_addr = 0;    /* NULL address */
 126         setup.size = 0;         /* disaable the CQ */
 127         setup.credits = 0;
 128         setup.credit_thres = 0;
 129         setup.ovfl_mode = 0;
 130         return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
 131 }
 132
 133 static int cxio_hal_clear_qp_ctx(struct cxio_rdev *rdev_p, u32 qpid)
 134 {
 135         u64 sge_cmd;
 136         struct t3_modify_qp_wr *wqe;
 137         struct sk_buff *skb = alloc_skb(sizeof(*wqe), GFP_KERNEL);
 138         if (!skb) {
 139                 PDBG("%s alloc_skb failed\n", __FUNCTION__);
 140                 return -ENOMEM;
 141         }
 142         wqe = (struct t3_modify_qp_wr *) skb_put(skb, sizeof(*wqe));
 143         memset(wqe, 0, sizeof(*wqe));
 144         build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_QP_MOD, 3, 1, qpid, 7);
 145         wqe->flags = cpu_to_be32(MODQP_WRITE_EC);
 146         sge_cmd = qpid << 8 | 3;
 147         wqe->sge_cmd = cpu_to_be64(sge_cmd);
 148         skb->priority = CPL_PRIORITY_CONTROL;
 149         return (cxgb3_ofld_send(rdev_p->t3cdev_p, skb));
 150 }
 151
 152 int cxio_create_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq)
 153 {
 154         struct rdma_cq_setup setup;
 155         int size = (1UL << (cq->size_log2)) * sizeof(struct t3_cqe);
 156
 157         cq->cqid = cxio_hal_get_cqid(rdev_p->rscp);
 158         if (!cq->cqid)
 159                 return -ENOMEM;
 160         cq->sw_queue = kzalloc(size, GFP_KERNEL);
 161         if (!cq->sw_queue)
 162                 return -ENOMEM;
 163         cq->queue = dma_alloc_coherent(&(rdev_p->rnic_info.pdev->dev),
 164                                              (1UL << (cq->size_log2)) *
 165                                              sizeof(struct t3_cqe),
 166                                              &(cq->dma_addr), GFP_KERNEL);
 167         if (!cq->queue) {
 168                 kfree(cq->sw_queue);
 169                 return -ENOMEM;
 170         }
 171         pci_unmap_addr_set(cq, mapping, cq->dma_addr);
 172         memset(cq->queue, 0, size);
 173         setup.id = cq->cqid;
 174         setup.base_addr = (u64) (cq->dma_addr);
 175         setup.size = 1UL << cq->size_log2;
 176         setup.credits = 65535;
 177         setup.credit_thres = 1;
 178         if (rdev_p->t3cdev_p->type == T3B)
 179                 setup.ovfl_mode = 0;
 180         else
 181                 setup.ovfl_mode = 1;
 182         return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
 183 }
 184
 185 int cxio_resize_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq)
 186 {
 187         struct rdma_cq_setup setup;
 188         setup.id = cq->cqid;
 189         setup.base_addr = (u64) (cq->dma_addr);
 190         setup.size = 1UL << cq->size_log2;
 191         setup.credits = setup.size;
 192         setup.credit_thres = setup.size;        /* TBD: overflow recovery */
 193         setup.ovfl_mode = 1;
 194         return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
 195 }
 196
 197 static u32 get_qpid(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
 198 {
 199         struct cxio_qpid_list *entry;
 200         u32 qpid;
 201         int i;
 202
 203         mutex_lock(&uctx->lock);
 204         if (!list_empty(&uctx->qpids)) {
 205                 entry = list_entry(uctx->qpids.next, struct cxio_qpid_list,
 206                                    entry);
 207                 list_del(&entry->entry);
 208                 qpid = entry->qpid;
 209                 kfree(entry);
 210         } else {
 211                 qpid = cxio_hal_get_qpid(rdev_p->rscp);
 212                 if (!qpid)
 213                         goto out;
 214                 for (i = qpid+1; i & rdev_p->qpmask; i++) {
 215                         entry = kmalloc(sizeof *entry, GFP_KERNEL);
 216                         if (!entry)
 217                                 break;
 218                         entry->qpid = i;
 219                         list_add_tail(&entry->entry, &uctx->qpids);
 220                 }
 221         }
 222 out:
 223         mutex_unlock(&uctx->lock);
 224         PDBG("%s qpid 0x%x\n", __FUNCTION__, qpid);
 225         return qpid;
 226 }
 227
 228 static void put_qpid(struct cxio_rdev *rdev_p, u32 qpid,
 229                      struct cxio_ucontext *uctx)
 230 {
 231         struct cxio_qpid_list *entry;
 232
 233         entry = kmalloc(sizeof *entry, GFP_KERNEL);
 234         if (!entry)
 235                 return;
 236         PDBG("%s qpid 0x%x\n", __FUNCTION__, qpid);
 237         entry->qpid = qpid;
 238         mutex_lock(&uctx->lock);
 239         list_add_tail(&entry->entry, &uctx->qpids);
 240         mutex_unlock(&uctx->lock);
 241 }
 242
 243 void cxio_release_ucontext(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
 244 {
 245         struct list_head *pos, *nxt;
 246         struct cxio_qpid_list *entry;
 247
 248         mutex_lock(&uctx->lock);
 249         list_for_each_safe(pos, nxt, &uctx->qpids) {
 250                 entry = list_entry(pos, struct cxio_qpid_list, entry);
 251                 list_del_init(&entry->entry);
 252                 if (!(entry->qpid & rdev_p->qpmask))
 253                         cxio_hal_put_qpid(rdev_p->rscp, entry->qpid);
 254                 kfree(entry);
 255         }
 256         mutex_unlock(&uctx->lock);
 257 }
 258
 259 void cxio_init_ucontext(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
 260 {
 261         INIT_LIST_HEAD(&uctx->qpids);
 262         mutex_init(&uctx->lock);
 263 }
 264
 265 int cxio_create_qp(struct cxio_rdev *rdev_p, u32 kernel_domain,
 266                    struct t3_wq *wq, struct cxio_ucontext *uctx)
 267 {
 268         int depth = 1UL << wq->size_log2;
 269         int rqsize = 1UL << wq->rq_size_log2;
 270
 271         wq->qpid = get_qpid(rdev_p, uctx);
 272         if (!wq->qpid)
 273                 return -ENOMEM;
 274
 275         wq->rq = kzalloc(depth * sizeof(u64), GFP_KERNEL);
 276         if (!wq->rq)
 277                 goto err1;
 278
 279         wq->rq_addr = cxio_hal_rqtpool_alloc(rdev_p, rqsize);
 280         if (!wq->rq_addr)
 281                 goto err2;
 282
 283         wq->sq = kzalloc(depth * sizeof(struct t3_swsq), GFP_KERNEL);
 284         if (!wq->sq)
 285                 goto err3;
 286
 287         wq->queue = dma_alloc_coherent(&(rdev_p->rnic_info.pdev->dev),
 288                                              depth * sizeof(union t3_wr),
 289                                              &(wq->dma_addr), GFP_KERNEL);
 290         if (!wq->queue)
 291                 goto err4;
 292
 293         memset(wq->queue, 0, depth * sizeof(union t3_wr));
 294         pci_unmap_addr_set(wq, mapping, wq->dma_addr);
 295         wq->doorbell = (void __iomem *)rdev_p->rnic_info.kdb_addr;
 296         if (!kernel_domain)
 297                 wq->udb = (u64)rdev_p->rnic_info.udbell_physbase +
 298                                         (wq->qpid << rdev_p->qpshift);
 299         PDBG("%s qpid 0x%x doorbell 0x%p udb 0x%llx\n", __FUNCTION__,
 300              wq->qpid, wq->doorbell, (unsigned long long) wq->udb);
 301         return 0;
 302 err4:
 303         kfree(wq->sq);
 304 err3:
 305         cxio_hal_rqtpool_free(rdev_p, wq->rq_addr, rqsize);
 306 err2:
 307         kfree(wq->rq);
 308 err1:
 309         put_qpid(rdev_p, wq->qpid, uctx);
 310         return -ENOMEM;
 311 }
 312
 313 int cxio_destroy_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq)
 314 {
 315         int err;
 316         err = cxio_hal_clear_cq_ctx(rdev_p, cq->cqid);
 317         kfree(cq->sw_queue);
 318         dma_free_coherent(&(rdev_p->rnic_info.pdev->dev),
 319                           (1UL << (cq->size_log2))
 320                           * sizeof(struct t3_cqe), cq->queue,
 321                           pci_unmap_addr(cq, mapping));
 322         cxio_hal_put_cqid(rdev_p->rscp, cq->cqid);
 323         return err;
 324 }
 325
 326 int cxio_destroy_qp(struct cxio_rdev *rdev_p, struct t3_wq *wq,
 327                     struct cxio_ucontext *uctx)
 328 {
 329         dma_free_coherent(&(rdev_p->rnic_info.pdev->dev),
 330                           (1UL << (wq->size_log2))
 331                           * sizeof(union t3_wr), wq->queue,
 332                           pci_unmap_addr(wq, mapping));
 333         kfree(wq->sq);
 334         cxio_hal_rqtpool_free(rdev_p, wq->rq_addr, (1UL << wq->rq_size_log2));
 335         kfree(wq->rq);
 336         put_qpid(rdev_p, wq->qpid, uctx);
 337         return 0;
 338 }
 339
 340 static void insert_recv_cqe(struct t3_wq *wq, struct t3_cq *cq)
 341 {
 342         struct t3_cqe cqe;
 343
 344         PDBG("%s wq %p cq %p sw_rptr 0x%x sw_wptr 0x%x\n", __FUNCTION__,
 345              wq, cq, cq->sw_rptr, cq->sw_wptr);
 346         memset(&cqe, 0, sizeof(cqe));
 347         cqe.header = cpu_to_be32(V_CQE_STATUS(TPT_ERR_SWFLUSH) |
 348                                  V_CQE_OPCODE(T3_SEND) |
 349                                  V_CQE_TYPE(0) |
 350                                  V_CQE_SWCQE(1) |
 351                                  V_CQE_QPID(wq->qpid) |
 352                                  V_CQE_GENBIT(Q_GENBIT(cq->sw_wptr,
 353                                                        cq->size_log2)));
 354         *(cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2)) = cqe;
 355         cq->sw_wptr++;
 356 }
 357
 358 void cxio_flush_rq(struct t3_wq *wq, struct t3_cq *cq, int count)
 359 {
 360         u32 ptr;
 361
 362         PDBG("%s wq %p cq %p\n", __FUNCTION__, wq, cq);
 363
 364         /* flush RQ */
 365         PDBG("%s rq_rptr %u rq_wptr %u skip count %u\n", __FUNCTION__,
 366             wq->rq_rptr, wq->rq_wptr, count);
 367         ptr = wq->rq_rptr + count;
 368         while (ptr++ != wq->rq_wptr)
 369                 insert_recv_cqe(wq, cq);
 370 }
 371
 372 static void insert_sq_cqe(struct t3_wq *wq, struct t3_cq *cq,
 373                           struct t3_swsq *sqp)
 374 {
 375         struct t3_cqe cqe;
 376
 377         PDBG("%s wq %p cq %p sw_rptr 0x%x sw_wptr 0x%x\n", __FUNCTION__,
 378              wq, cq, cq->sw_rptr, cq->sw_wptr);
 379         memset(&cqe, 0, sizeof(cqe));
 380         cqe.header = cpu_to_be32(V_CQE_STATUS(TPT_ERR_SWFLUSH) |
 381                                  V_CQE_OPCODE(sqp->opcode) |
 382                                  V_CQE_TYPE(1) |
 383                                  V_CQE_SWCQE(1) |
 384                                  V_CQE_QPID(wq->qpid) |
 385                                  V_CQE_GENBIT(Q_GENBIT(cq->sw_wptr,
 386                                                        cq->size_log2)));
 387         cqe.u.scqe.wrid_hi = sqp->sq_wptr;
 388
 389         *(cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2)) = cqe;
 390         cq->sw_wptr++;
 391 }
 392
 393 void cxio_flush_sq(struct t3_wq *wq, struct t3_cq *cq, int count)
 394 {
 395         __u32 ptr;
 396         struct t3_swsq *sqp = wq->sq + Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2);
 397
 398         ptr = wq->sq_rptr + count;
 399         sqp += count;
 400         while (ptr != wq->sq_wptr) {
 401                 insert_sq_cqe(wq, cq, sqp);
 402                 sqp++;
 403                 ptr++;
 404         }
 405 }
 406
 407 /*
 408  * Move all CQEs from the HWCQ into the SWCQ.
 409  */
 410 void cxio_flush_hw_cq(struct t3_cq *cq)
 411 {
 412         struct t3_cqe *cqe, *swcqe;
 413
 414         PDBG("%s cq %p cqid 0x%x\n", __FUNCTION__, cq, cq->cqid);
 415         cqe = cxio_next_hw_cqe(cq);
 416         while (cqe) {
 417                 PDBG("%s flushing hwcq rptr 0x%x to swcq wptr 0x%x\n",
 418                      __FUNCTION__, cq->rptr, cq->sw_wptr);
 419                 swcqe = cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2);
 420                 *swcqe = *cqe;
 421                 swcqe->header |= cpu_to_be32(V_CQE_SWCQE(1));
 422                 cq->sw_wptr++;
 423                 cq->rptr++;
 424                 cqe = cxio_next_hw_cqe(cq);
 425         }
 426 }
 427
 428 static int cqe_completes_wr(struct t3_cqe *cqe, struct t3_wq *wq)
 429 {
 430         if (CQE_OPCODE(*cqe) == T3_TERMINATE)
 431                 return 0;
 432
 433         if ((CQE_OPCODE(*cqe) == T3_RDMA_WRITE) && RQ_TYPE(*cqe))
 434                 return 0;
 435
 436         if ((CQE_OPCODE(*cqe) == T3_READ_RESP) && SQ_TYPE(*cqe))
 437                 return 0;
 438
 439         if ((CQE_OPCODE(*cqe) == T3_SEND) && RQ_TYPE(*cqe) &&
 440             Q_EMPTY(wq->rq_rptr, wq->rq_wptr))
 441                 return 0;
 442
 443         return 1;
 444 }
 445
 446 void cxio_count_scqes(struct t3_cq *cq, struct t3_wq *wq, int *count)
 447 {
 448         struct t3_cqe *cqe;
 449         u32 ptr;
 450
 451         *count = 0;
 452         ptr = cq->sw_rptr;
 453         while (!Q_EMPTY(ptr, cq->sw_wptr)) {
 454                 cqe = cq->sw_queue + (Q_PTR2IDX(ptr, cq->size_log2));
 455                 if ((SQ_TYPE(*cqe) || (CQE_OPCODE(*cqe) == T3_READ_RESP)) &&
 456                     (CQE_QPID(*cqe) == wq->qpid))
 457                         (*count)++;
 458                 ptr++;
 459         }
 460         PDBG("%s cq %p count %d\n", __FUNCTION__, cq, *count);
 461 }
 462
 463 void cxio_count_rcqes(struct t3_cq *cq, struct t3_wq *wq, int *count)
 464 {
 465         struct t3_cqe *cqe;
 466         u32 ptr;
 467
 468         *count = 0;
 469         PDBG("%s count zero %d\n", __FUNCTION__, *count);
 470         ptr = cq->sw_rptr;
 471         while (!Q_EMPTY(ptr, cq->sw_wptr)) {
 472                 cqe = cq->sw_queue + (Q_PTR2IDX(ptr, cq->size_log2));
 473                 if (RQ_TYPE(*cqe) && (CQE_OPCODE(*cqe) != T3_READ_RESP) &&
 474                     (CQE_QPID(*cqe) == wq->qpid) && cqe_completes_wr(cqe, wq))
 475                         (*count)++;
 476                 ptr++;
 477         }
 478         PDBG("%s cq %p count %d\n", __FUNCTION__, cq, *count);
 479 }
 480
 481 static int cxio_hal_init_ctrl_cq(struct cxio_rdev *rdev_p)
 482 {
 483         struct rdma_cq_setup setup;
 484         setup.id = 0;
 485         setup.base_addr = 0;    /* NULL address */
 486         setup.size = 1;         /* enable the CQ */
 487         setup.credits = 0;
 488
 489         /* force SGE to redirect to RspQ and interrupt */
 490         setup.credit_thres = 0;
 491         setup.ovfl_mode = 1;
 492         return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
 493 }
 494
 495 static int cxio_hal_init_ctrl_qp(struct cxio_rdev *rdev_p)
 496 {
 497         int err;
 498         u64 sge_cmd, ctx0, ctx1;
 499         u64 base_addr;
 500         struct t3_modify_qp_wr *wqe;
 501         struct sk_buff *skb;
 502
 503         skb = alloc_skb(sizeof(*wqe), GFP_KERNEL);
 504         if (!skb) {
 505                 PDBG("%s alloc_skb failed\n", __FUNCTION__);
 506                 return -ENOMEM;
 507         }
 508         err = cxio_hal_init_ctrl_cq(rdev_p);
 509         if (err) {
 510                 PDBG("%s err %d initializing ctrl_cq\n", __FUNCTION__, err);
 511                 goto err;
 512         }
 513         rdev_p->ctrl_qp.workq = dma_alloc_coherent(
 514                                         &(rdev_p->rnic_info.pdev->dev),
 515                                         (1 << T3_CTRL_QP_SIZE_LOG2) *
 516                                         sizeof(union t3_wr),
 517                                         &(rdev_p->ctrl_qp.dma_addr),
 518                                         GFP_KERNEL);
 519         if (!rdev_p->ctrl_qp.workq) {
 520                 PDBG("%s dma_alloc_coherent failed\n", __FUNCTION__);
 521                 err = -ENOMEM;
 522                 goto err;
 523         }
 524         pci_unmap_addr_set(&rdev_p->ctrl_qp, mapping,
 525                            rdev_p->ctrl_qp.dma_addr);
 526         rdev_p->ctrl_qp.doorbell = (void __iomem *)rdev_p->rnic_info.kdb_addr;
 527         memset(rdev_p->ctrl_qp.workq, 0,
 528                (1 << T3_CTRL_QP_SIZE_LOG2) * sizeof(union t3_wr));
 529
 530         mutex_init(&rdev_p->ctrl_qp.lock);
 531         init_waitqueue_head(&rdev_p->ctrl_qp.waitq);
 532
 533         /* update HW Ctrl QP context */
 534         base_addr = rdev_p->ctrl_qp.dma_addr;
 535         base_addr >>= 12;
 536         ctx0 = (V_EC_SIZE((1 << T3_CTRL_QP_SIZE_LOG2)) |
 537                 V_EC_BASE_LO((u32) base_addr & 0xffff));
 538         ctx0 <<= 32;
 539         ctx0 |= V_EC_CREDITS(FW_WR_NUM);
 540         base_addr >>= 16;
 541         ctx1 = (u32) base_addr;
 542         base_addr >>= 32;
 543         ctx1 |= ((u64) (V_EC_BASE_HI((u32) base_addr & 0xf) | V_EC_RESPQ(0) |
 544                         V_EC_TYPE(0) | V_EC_GEN(1) |
 545                         V_EC_UP_TOKEN(T3_CTL_QP_TID) | F_EC_VALID)) << 32;
 546         wqe = (struct t3_modify_qp_wr *) skb_put(skb, sizeof(*wqe));
 547         memset(wqe, 0, sizeof(*wqe));
 548         build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_QP_MOD, 0, 1,
 549                        T3_CTL_QP_TID, 7);
 550         wqe->flags = cpu_to_be32(MODQP_WRITE_EC);
 551         sge_cmd = (3ULL << 56) | FW_RI_SGEEC_START << 8 | 3;
 552         wqe->sge_cmd = cpu_to_be64(sge_cmd);
 553         wqe->ctx1 = cpu_to_be64(ctx1);
 554         wqe->ctx0 = cpu_to_be64(ctx0);
 555         PDBG("CtrlQP dma_addr 0x%llx workq %p size %d\n",
 556              (unsigned long long) rdev_p->ctrl_qp.dma_addr,
 557              rdev_p->ctrl_qp.workq, 1 << T3_CTRL_QP_SIZE_LOG2);
 558         skb->priority = CPL_PRIORITY_CONTROL;
 559         return (cxgb3_ofld_send(rdev_p->t3cdev_p, skb));
 560 err:
 561         kfree_skb(skb);
 562         return err;
 563 }
 564
 565 static int cxio_hal_destroy_ctrl_qp(struct cxio_rdev *rdev_p)
 566 {
 567         dma_free_coherent(&(rdev_p->rnic_info.pdev->dev),
 568                           (1UL << T3_CTRL_QP_SIZE_LOG2)
 569                           * sizeof(union t3_wr), rdev_p->ctrl_qp.workq,
 570                           pci_unmap_addr(&rdev_p->ctrl_qp, mapping));
 571         return cxio_hal_clear_qp_ctx(rdev_p, T3_CTRL_QP_ID);
 572 }
 573
 574 /* write len bytes of data into addr (32B aligned address)
 575  * If data is NULL, clear len byte of memory to zero.
 576  * caller aquires the ctrl_qp lock before the call
 577  */
 578 static int cxio_hal_ctrl_qp_write_mem(struct cxio_rdev *rdev_p, u32 addr,
 579                                       u32 len, void *data, int completion)
 580 {
 581         u32 i, nr_wqe, copy_len;
 582         u8 *copy_data;
 583         u8 wr_len, utx_len;     /* lenght in 8 byte flit */
 584         enum t3_wr_flags flag;
 585         __be64 *wqe;
 586         u64 utx_cmd;
 587         addr &= 0x7FFFFFF;
 588         nr_wqe = len % 96 ? len / 96 + 1 : len / 96;    /* 96B max per WQE */
 589         PDBG("%s wptr 0x%x rptr 0x%x len %d, nr_wqe %d data %p addr 0x%0x\n",
 590              __FUNCTION__, rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, len,
 591              nr_wqe, data, addr);
 592         utx_len = 3;            /* in 32B unit */
 593         for (i = 0; i < nr_wqe; i++) {
 594                 if (Q_FULL(rdev_p->ctrl_qp.rptr, rdev_p->ctrl_qp.wptr,
 595                            T3_CTRL_QP_SIZE_LOG2)) {
 596                         PDBG("%s ctrl_qp full wtpr 0x%0x rptr 0x%0x, "
 597                              "wait for more space i %d\n", __FUNCTION__,
 598                              rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, i);
 599                         if (wait_event_interruptible(rdev_p->ctrl_qp.waitq,
 600                                              !Q_FULL(rdev_p->ctrl_qp.rptr,
 601                                                      rdev_p->ctrl_qp.wptr,
 602                                                      T3_CTRL_QP_SIZE_LOG2))) {
 603                                 PDBG("%s ctrl_qp workq interrupted\n",
 604                                      __FUNCTION__);
 605                                 return -ERESTARTSYS;
 606                         }
 607                         PDBG("%s ctrl_qp wakeup, continue posting work request "
 608                              "i %d\n", __FUNCTION__, i);
 609                 }
 610                 wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr %
 611                                                 (1 << T3_CTRL_QP_SIZE_LOG2)));
 612                 flag = 0;
 613                 if (i == (nr_wqe - 1)) {
 614                         /* last WQE */
 615                         flag = completion ? T3_COMPLETION_FLAG : 0;
 616                         if (len % 32)
 617                                 utx_len = len / 32 + 1;
 618                         else
 619                                 utx_len = len / 32;
 620                 }
 621
 622                 /*
 623                  * Force a CQE to return the credit to the workq in case
 624                  * we posted more than half the max QP size of WRs
 625                  */
 626                 if ((i != 0) &&
 627                     (i % (((1 << T3_CTRL_QP_SIZE_LOG2)) >> 1) == 0)) {
 628                         flag = T3_COMPLETION_FLAG;
 629                         PDBG("%s force completion at i %d\n", __FUNCTION__, i);
 630                 }
 631
 632                 /* build the utx mem command */
 633                 wqe += (sizeof(struct t3_bypass_wr) >> 3);
 634                 utx_cmd = (T3_UTX_MEM_WRITE << 28) | (addr + i * 3);
 635                 utx_cmd <<= 32;
 636                 utx_cmd |= (utx_len << 28) | ((utx_len << 2) + 1);
 637                 *wqe = cpu_to_be64(utx_cmd);
 638                 wqe++;
 639                 copy_data = (u8 *) data + i * 96;
 640                 copy_len = len > 96 ? 96 : len;
 641
 642                 /* clear memory content if data is NULL */
 643                 if (data)
 644                         memcpy(wqe, copy_data, copy_len);
 645                 else
 646                         memset(wqe, 0, copy_len);
 647                 if (copy_len % 32)
 648                         memset(((u8 *) wqe) + copy_len, 0,
 649                                32 - (copy_len % 32));
 650                 wr_len = ((sizeof(struct t3_bypass_wr)) >> 3) + 1 +
 651                          (utx_len << 2);
 652                 wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr %
 653                               (1 << T3_CTRL_QP_SIZE_LOG2)));
 654
 655                 /* wptr in the WRID[31:0] */
 656                 ((union t3_wrid *)(wqe+1))->id0.low = rdev_p->ctrl_qp.wptr;
 657
 658                 /*
 659                  * This must be the last write with a memory barrier
 660                  * for the genbit
 661                  */
 662                 build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_BP, flag,
 663                                Q_GENBIT(rdev_p->ctrl_qp.wptr,
 664                                         T3_CTRL_QP_SIZE_LOG2), T3_CTRL_QP_ID,
 665                                wr_len);
 666                 if (flag == T3_COMPLETION_FLAG)
 667                         ring_doorbell(rdev_p->ctrl_qp.doorbell, T3_CTRL_QP_ID);
 668                 len -= 96;
 669                 rdev_p->ctrl_qp.wptr++;
 670         }
 671         return 0;
 672 }
 673
 674 /* IN: stag key, pdid, perm, zbva, to, len, page_size, pbl, and pbl_size
 675  * OUT: stag index, actual pbl_size, pbl_addr allocated.
 676  * TBD: shared memory region support
 677  */
 678 static int __cxio_tpt_op(struct cxio_rdev *rdev_p, u32 reset_tpt_entry,
 679                          u32 *stag, u8 stag_state, u32 pdid,
 680                          enum tpt_mem_type type, enum tpt_mem_perm perm,
 681                          u32 zbva, u64 to, u32 len, u8 page_size, __be64 *pbl,
 682                          u32 *pbl_size, u32 *pbl_addr)
 683 {
 684         int err;
 685         struct tpt_entry tpt;
 686         u32 stag_idx;
 687         u32 wptr;
 688         int rereg = (*stag != T3_STAG_UNSET);
 689
 690         stag_state = stag_state > 0;
 691         stag_idx = (*stag) >> 8;
 692
 693         if ((!reset_tpt_entry) && !(*stag != T3_STAG_UNSET)) {
 694                 stag_idx = cxio_hal_get_stag(rdev_p->rscp);
 695                 if (!stag_idx)
 696                         return -ENOMEM;
 697                 *stag = (stag_idx << 8) | ((*stag) & 0xFF);
 698         }
 699         PDBG("%s stag_state 0x%0x type 0x%0x pdid 0x%0x, stag_idx 0x%x\n",
 700              __FUNCTION__, stag_state, type, pdid, stag_idx);
 701
 702         if (reset_tpt_entry)
 703                 cxio_hal_pblpool_free(rdev_p, *pbl_addr, *pbl_size << 3);
 704         else if (!rereg) {
 705                 *pbl_addr = cxio_hal_pblpool_alloc(rdev_p, *pbl_size << 3);
 706                 if (!*pbl_addr) {
 707                         return -ENOMEM;
 708                 }
 709         }
 710
 711         mutex_lock(&rdev_p->ctrl_qp.lock);
 712
 713         /* write PBL first if any - update pbl only if pbl list exist */
 714         if (pbl) {
 715
 716                 PDBG("%s *pdb_addr 0x%x, pbl_base 0x%x, pbl_size %d\n",
 717                      __FUNCTION__, *pbl_addr, rdev_p->rnic_info.pbl_base,
 718                      *pbl_size);
 719                 err = cxio_hal_ctrl_qp_write_mem(rdev_p,
 720                                 (*pbl_addr >> 5),
 721                                 (*pbl_size << 3), pbl, 0);
 722                 if (err)
 723                         goto ret;
 724         }
 725
 726         /* write TPT entry */
 727         if (reset_tpt_entry)
 728                 memset(&tpt, 0, sizeof(tpt));
 729         else {
 730                 tpt.valid_stag_pdid = cpu_to_be32(F_TPT_VALID |
 731                                 V_TPT_STAG_KEY((*stag) & M_TPT_STAG_KEY) |
 732                                 V_TPT_STAG_STATE(stag_state) |
 733                                 V_TPT_STAG_TYPE(type) | V_TPT_PDID(pdid));
 734                 BUG_ON(page_size >= 28);
 735                 tpt.flags_pagesize_qpid = cpu_to_be32(V_TPT_PERM(perm) |
 736                                 F_TPT_MW_BIND_ENABLE |
 737                                 V_TPT_ADDR_TYPE((zbva ? TPT_ZBTO : TPT_VATO)) |
 738                                 V_TPT_PAGE_SIZE(page_size));
 739                 tpt.rsvd_pbl_addr = reset_tpt_entry ? 0 :
 740                                     cpu_to_be32(V_TPT_PBL_ADDR(PBL_OFF(rdev_p, *pbl_addr)>>3));
 741                 tpt.len = cpu_to_be32(len);
 742                 tpt.va_hi = cpu_to_be32((u32) (to >> 32));
 743                 tpt.va_low_or_fbo = cpu_to_be32((u32) (to & 0xFFFFFFFFULL));
 744                 tpt.rsvd_bind_cnt_or_pstag = 0;
 745                 tpt.rsvd_pbl_size = reset_tpt_entry ? 0 :
 746                                   cpu_to_be32(V_TPT_PBL_SIZE((*pbl_size) >> 2));
 747         }
 748         err = cxio_hal_ctrl_qp_write_mem(rdev_p,
 749                                        stag_idx +
 750                                        (rdev_p->rnic_info.tpt_base >> 5),
 751                                        sizeof(tpt), &tpt, 1);
 752
 753         /* release the stag index to free pool */
 754         if (reset_tpt_entry)
 755                 cxio_hal_put_stag(rdev_p->rscp, stag_idx);
 756 ret:
 757         wptr = rdev_p->ctrl_qp.wptr;
 758         mutex_unlock(&rdev_p->ctrl_qp.lock);
 759         if (!err)
 760                 if (wait_event_interruptible(rdev_p->ctrl_qp.waitq,
 761                                              SEQ32_GE(rdev_p->ctrl_qp.rptr,
 762                                                       wptr)))
 763                         return -ERESTARTSYS;
 764         return err;
 765 }
 766
 767 int cxio_register_phys_mem(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid,
 768                            enum tpt_mem_perm perm, u32 zbva, u64 to, u32 len,
 769                            u8 page_size, __be64 *pbl, u32 *pbl_size,
 770                            u32 *pbl_addr)
 771 {
 772         *stag = T3_STAG_UNSET;
 773         return __cxio_tpt_op(rdev_p, 0, stag, 1, pdid, TPT_NON_SHARED_MR, perm,
 774                              zbva, to, len, page_size, pbl, pbl_size, pbl_addr);
 775 }
 776
 777 int cxio_reregister_phys_mem(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid,
 778                            enum tpt_mem_perm perm, u32 zbva, u64 to, u32 len,
 779                            u8 page_size, __be64 *pbl, u32 *pbl_size,
 780                            u32 *pbl_addr)
 781 {
 782         return __cxio_tpt_op(rdev_p, 0, stag, 1, pdid, TPT_NON_SHARED_MR, perm,
 783                              zbva, to, len, page_size, pbl, pbl_size, pbl_addr);
 784 }
 785
 786 int cxio_dereg_mem(struct cxio_rdev *rdev_p, u32 stag, u32 pbl_size,
 787                    u32 pbl_addr)
 788 {
 789         return __cxio_tpt_op(rdev_p, 1, &stag, 0, 0, 0, 0, 0, 0ULL, 0, 0, NULL,
 790                              &pbl_size, &pbl_addr);
 791 }
 792
 793 int cxio_allocate_window(struct cxio_rdev *rdev_p, u32 * stag, u32 pdid)
 794 {
 795         u32 pbl_size = 0;
 796         *stag = T3_STAG_UNSET;
 797         return __cxio_tpt_op(rdev_p, 0, stag, 0, pdid, TPT_MW, 0, 0, 0ULL, 0, 0,
 798                              NULL, &pbl_size, NULL);
 799 }
 800
 801 int cxio_deallocate_window(struct cxio_rdev *rdev_p, u32 stag)
 802 {
 803         return __cxio_tpt_op(rdev_p, 1, &stag, 0, 0, 0, 0, 0, 0ULL, 0, 0, NULL,
 804                              NULL, NULL);
 805 }
 806
 807 int cxio_rdma_init(struct cxio_rdev *rdev_p, struct t3_rdma_init_attr *attr)
 808 {
 809         struct t3_rdma_init_wr *wqe;
 810         struct sk_buff *skb = alloc_skb(sizeof(*wqe), GFP_ATOMIC);
 811         if (!skb)
 812                 return -ENOMEM;
 813         PDBG("%s rdev_p %p\n", __FUNCTION__, rdev_p);
 814         wqe = (struct t3_rdma_init_wr *) __skb_put(skb, sizeof(*wqe));
 815         wqe->wrh.op_seop_flags = cpu_to_be32(V_FW_RIWR_OP(T3_WR_INIT));
 816         wqe->wrh.gen_tid_len = cpu_to_be32(V_FW_RIWR_TID(attr->tid) |
 817                                            V_FW_RIWR_LEN(sizeof(*wqe) >> 3));
 818         wqe->wrid.id1 = 0;
 819         wqe->qpid = cpu_to_be32(attr->qpid);
 820         wqe->pdid = cpu_to_be32(attr->pdid);
 821         wqe->scqid = cpu_to_be32(attr->scqid);
 822         wqe->rcqid = cpu_to_be32(attr->rcqid);
 823         wqe->rq_addr = cpu_to_be32(attr->rq_addr - rdev_p->rnic_info.rqt_base);
 824         wqe->rq_size = cpu_to_be32(attr->rq_size);
 825         wqe->mpaattrs = attr->mpaattrs;
 826         wqe->qpcaps = attr->qpcaps;
 827         wqe->ulpdu_size = cpu_to_be16(attr->tcp_emss);
 828         wqe->flags = cpu_to_be32(attr->flags);
 829         wqe->ord = cpu_to_be32(attr->ord);
 830         wqe->ird = cpu_to_be32(attr->ird);
 831         wqe->qp_dma_addr = cpu_to_be64(attr->qp_dma_addr);
 832         wqe->qp_dma_size = cpu_to_be32(attr->qp_dma_size);
 833         wqe->rsvd = 0;
 834         skb->priority = 0;      /* 0=>ToeQ; 1=>CtrlQ */
 835         return (cxgb3_ofld_send(rdev_p->t3cdev_p, skb));
 836 }
 837
 838 void cxio_register_ev_cb(cxio_hal_ev_callback_func_t ev_cb)
 839 {
 840         cxio_ev_cb = ev_cb;
 841 }
 842
 843 void cxio_unregister_ev_cb(cxio_hal_ev_callback_func_t ev_cb)
 844 {
 845         cxio_ev_cb = NULL;
 846 }
 847
 848 static int cxio_hal_ev_handler(struct t3cdev *t3cdev_p, struct sk_buff *skb)
 849 {
 850         static int cnt;
 851         struct cxio_rdev *rdev_p = NULL;
 852         struct respQ_msg_t *rsp_msg = (struct respQ_msg_t *) skb->data;
 853         PDBG("%d: %s cq_id 0x%x cq_ptr 0x%x genbit %0x overflow %0x an %0x"
 854              " se %0x notify %0x cqbranch %0x creditth %0x\n",
 855              cnt, __FUNCTION__, RSPQ_CQID(rsp_msg), RSPQ_CQPTR(rsp_msg),
 856              RSPQ_GENBIT(rsp_msg), RSPQ_OVERFLOW(rsp_msg), RSPQ_AN(rsp_msg),
 857              RSPQ_SE(rsp_msg), RSPQ_NOTIFY(rsp_msg), RSPQ_CQBRANCH(rsp_msg),
 858              RSPQ_CREDIT_THRESH(rsp_msg));
 859         PDBG("CQE: QPID 0x%0x genbit %0x type 0x%0x status 0x%0x opcode %d "
 860              "len 0x%0x wrid_hi_stag 0x%x wrid_low_msn 0x%x\n",
 861              CQE_QPID(rsp_msg->cqe), CQE_GENBIT(rsp_msg->cqe),
 862              CQE_TYPE(rsp_msg->cqe), CQE_STATUS(rsp_msg->cqe),
 863              CQE_OPCODE(rsp_msg->cqe), CQE_LEN(rsp_msg->cqe),
 864              CQE_WRID_HI(rsp_msg->cqe), CQE_WRID_LOW(rsp_msg->cqe));
 865         rdev_p = (struct cxio_rdev *)t3cdev_p->ulp;
 866         if (!rdev_p) {
 867                 PDBG("%s called by t3cdev %p with null ulp\n", __FUNCTION__,
 868                      t3cdev_p);
 869                 return 0;
 870         }
 871         if (CQE_QPID(rsp_msg->cqe) == T3_CTRL_QP_ID) {
 872                 rdev_p->ctrl_qp.rptr = CQE_WRID_LOW(rsp_msg->cqe) + 1;
 873                 wake_up_interruptible(&rdev_p->ctrl_qp.waitq);
 874                 dev_kfree_skb_irq(skb);
 875         } else if (CQE_QPID(rsp_msg->cqe) == 0xfff8)
 876                 dev_kfree_skb_irq(skb);
 877         else if (cxio_ev_cb)
 878                 (*cxio_ev_cb) (rdev_p, skb);
 879         else
 880                 dev_kfree_skb_irq(skb);
 881         cnt++;
 882         return 0;
 883 }
 884
 885 /* Caller takes care of locking if needed */
 886 int cxio_rdev_open(struct cxio_rdev *rdev_p)
 887 {
 888         struct net_device *netdev_p = NULL;
 889         int err = 0;
 890         if (strlen(rdev_p->dev_name)) {
 891                 if (cxio_hal_find_rdev_by_name(rdev_p->dev_name)) {
 892                         return -EBUSY;
 893                 }
 894                 netdev_p = dev_get_by_name(rdev_p->dev_name);
 895                 if (!netdev_p) {
 896                         return -EINVAL;
 897                 }
 898                 dev_put(netdev_p);
 899         } else if (rdev_p->t3cdev_p) {
 900                 if (cxio_hal_find_rdev_by_t3cdev(rdev_p->t3cdev_p)) {
 901                         return -EBUSY;
 902                 }
 903                 netdev_p = rdev_p->t3cdev_p->lldev;
 904                 strncpy(rdev_p->dev_name, rdev_p->t3cdev_p->name,
 905                         T3_MAX_DEV_NAME_LEN);
 906         } else {
 907                 PDBG("%s t3cdev_p or dev_name must be set\n", __FUNCTION__);
 908                 return -EINVAL;
 909         }
 910
 911         list_add_tail(&rdev_p->entry, &rdev_list);
 912
 913         PDBG("%s opening rnic dev %s\n", __FUNCTION__, rdev_p->dev_name);
 914         memset(&rdev_p->ctrl_qp, 0, sizeof(rdev_p->ctrl_qp));
 915         if (!rdev_p->t3cdev_p)
 916                 rdev_p->t3cdev_p = T3CDEV(netdev_p);
 917         rdev_p->t3cdev_p->ulp = (void *) rdev_p;
 918         err = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_GET_PARAMS,
 919                                          &(rdev_p->rnic_info));
 920         if (err) {
 921                 printk(KERN_ERR "%s t3cdev_p(%p)->ctl returned error %d.\n",
 922                      __FUNCTION__, rdev_p->t3cdev_p, err);
 923                 goto err1;
 924         }
 925         err = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, GET_PORTS,
 926                                     &(rdev_p->port_info));
 927         if (err) {
 928                 printk(KERN_ERR "%s t3cdev_p(%p)->ctl returned error %d.\n",
 929                      __FUNCTION__, rdev_p->t3cdev_p, err);
 930                 goto err1;
 931         }
 932
 933         /*
 934          * qpshift is the number of bits to shift the qpid left in order
 935          * to get the correct address of the doorbell for that qp.
 936          */
 937         cxio_init_ucontext(rdev_p, &rdev_p->uctx);
 938         rdev_p->qpshift = PAGE_SHIFT -
 939                           ilog2(65536 >>
 940                                     ilog2(rdev_p->rnic_info.udbell_len >>
 941                                               PAGE_SHIFT));
 942         rdev_p->qpnr = rdev_p->rnic_info.udbell_len >> PAGE_SHIFT;
 943         rdev_p->qpmask = (65536 >> ilog2(rdev_p->qpnr)) - 1;
 944         PDBG("%s rnic %s info: tpt_base 0x%0x tpt_top 0x%0x num stags %d "
 945              "pbl_base 0x%0x pbl_top 0x%0x rqt_base 0x%0x, rqt_top 0x%0x\n",
 946              __FUNCTION__, rdev_p->dev_name, rdev_p->rnic_info.tpt_base,
 947              rdev_p->rnic_info.tpt_top, cxio_num_stags(rdev_p),
 948              rdev_p->rnic_info.pbl_base,
 949              rdev_p->rnic_info.pbl_top, rdev_p->rnic_info.rqt_base,
 950              rdev_p->rnic_info.rqt_top);
 951         PDBG("udbell_len 0x%0x udbell_physbase 0x%lx kdb_addr %p qpshift %lu "
 952              "qpnr %d qpmask 0x%x\n",
 953              rdev_p->rnic_info.udbell_len,
 954              rdev_p->rnic_info.udbell_physbase, rdev_p->rnic_info.kdb_addr,
 955              rdev_p->qpshift, rdev_p->qpnr, rdev_p->qpmask);
 956
 957         err = cxio_hal_init_ctrl_qp(rdev_p);
 958         if (err) {
 959                 printk(KERN_ERR "%s error %d initializing ctrl_qp.\n",
 960                        __FUNCTION__, err);
 961                 goto err1;
 962         }
 963         err = cxio_hal_init_resource(rdev_p, cxio_num_stags(rdev_p), 0,
 964                                      0, T3_MAX_NUM_QP, T3_MAX_NUM_CQ,
 965                                      T3_MAX_NUM_PD);
 966         if (err) {
 967                 printk(KERN_ERR "%s error %d initializing hal resources.\n",
 968                        __FUNCTION__, err);
 969                 goto err2;
 970         }
 971         err = cxio_hal_pblpool_create(rdev_p);
 972         if (err) {
 973                 printk(KERN_ERR "%s error %d initializing pbl mem pool.\n",
 974                        __FUNCTION__, err);
 975                 goto err3;
 976         }
 977         err = cxio_hal_rqtpool_create(rdev_p);
 978         if (err) {
 979                 printk(KERN_ERR "%s error %d initializing rqt mem pool.\n",
 980                        __FUNCTION__, err);
 981                 goto err4;
 982         }
 983         return 0;
 984 err4:
 985         cxio_hal_pblpool_destroy(rdev_p);
 986 err3:
 987         cxio_hal_destroy_resource(rdev_p->rscp);
 988 err2:
 989         cxio_hal_destroy_ctrl_qp(rdev_p);
 990 err1:
 991         list_del(&rdev_p->entry);
 992         return err;
 993 }
 994
 995 void cxio_rdev_close(struct cxio_rdev *rdev_p)
 996 {
 997         if (rdev_p) {
 998                 cxio_hal_pblpool_destroy(rdev_p);
 999                 cxio_hal_rqtpool_destroy(rdev_p);
1000                 list_del(&rdev_p->entry);
1001                 rdev_p->t3cdev_p->ulp = NULL;
1002                 cxio_hal_destroy_ctrl_qp(rdev_p);
1003                 cxio_hal_destroy_resource(rdev_p->rscp);
1004         }
1005 }
1006
1007 int __init cxio_hal_init(void)
1008 {
1009         if (cxio_hal_init_rhdl_resource(T3_MAX_NUM_RI))
1010                 return -ENOMEM;
1011         t3_register_cpl_handler(CPL_ASYNC_NOTIF, cxio_hal_ev_handler);
1012         return 0;
1013 }
1014
1015 void __exit cxio_hal_exit(void)
1016 {
1017         struct cxio_rdev *rdev, *tmp;
1018
1019         t3_register_cpl_handler(CPL_ASYNC_NOTIF, NULL);
1020         list_for_each_entry_safe(rdev, tmp, &rdev_list, entry)
1021                 cxio_rdev_close(rdev);
1022         cxio_hal_destroy_rhdl_resource();
1023 }
1024
1025 static void flush_completed_wrs(struct t3_wq *wq, struct t3_cq *cq)
1026 {
1027         struct t3_swsq *sqp;
1028         __u32 ptr = wq->sq_rptr;
1029         int count = Q_COUNT(wq->sq_rptr, wq->sq_wptr);
1030
1031         sqp = wq->sq + Q_PTR2IDX(ptr, wq->sq_size_log2);
1032         while (count--)
1033                 if (!sqp->signaled) {
1034                         ptr++;
1035                         sqp = wq->sq + Q_PTR2IDX(ptr,  wq->sq_size_log2);
1036                 } else if (sqp->complete) {
1037
1038                         /*
1039                          * Insert this completed cqe into the swcq.
1040                          */
1041                         PDBG("%s moving cqe into swcq sq idx %ld cq idx %ld\n",
1042                              __FUNCTION__, Q_PTR2IDX(ptr,  wq->sq_size_log2),
1043                              Q_PTR2IDX(cq->sw_wptr, cq->size_log2));
1044                         sqp->cqe.header |= htonl(V_CQE_SWCQE(1));
1045                         *(cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2))
1046                                 = sqp->cqe;
1047                         cq->sw_wptr++;
1048                         sqp->signaled = 0;
1049                         break;
1050                 } else
1051                         break;
1052 }
1053
1054 static void create_read_req_cqe(struct t3_wq *wq, struct t3_cqe *hw_cqe,
1055                                 struct t3_cqe *read_cqe)
1056 {
1057         read_cqe->u.scqe.wrid_hi = wq->oldest_read->sq_wptr;
1058         read_cqe->len = wq->oldest_read->read_len;
1059         read_cqe->header = htonl(V_CQE_QPID(CQE_QPID(*hw_cqe)) |
1060                                  V_CQE_SWCQE(SW_CQE(*hw_cqe)) |
1061                                  V_CQE_OPCODE(T3_READ_REQ) |
1062                                  V_CQE_TYPE(1));
1063 }
1064
1065 /*
1066  * Return a ptr to the next read wr in the SWSQ or NULL.
1067  */
1068 static void advance_oldest_read(struct t3_wq *wq)
1069 {
1070
1071         u32 rptr = wq->oldest_read - wq->sq + 1;
1072         u32 wptr = Q_PTR2IDX(wq->sq_wptr, wq->sq_size_log2);
1073
1074         while (Q_PTR2IDX(rptr, wq->sq_size_log2) != wptr) {
1075                 wq->oldest_read = wq->sq + Q_PTR2IDX(rptr, wq->sq_size_log2);
1076
1077                 if (wq->oldest_read->opcode == T3_READ_REQ)
1078                         return;
1079                 rptr++;
1080         }
1081         wq->oldest_read = NULL;
1082 }
1083
1084 /*
1085  * cxio_poll_cq
1086  *
1087  * Caller must:
1088  *     check the validity of the first CQE,
1089  *     supply the wq assicated with the qpid.
1090  *
1091  * credit: cq credit to return to sge.
1092  * cqe_flushed: 1 iff the CQE is flushed.
1093  * cqe: copy of the polled CQE.
1094  *
1095  * return value:
1096  *     0       CQE returned,
1097  *    -1       CQE skipped, try again.
1098  */
1099 int cxio_poll_cq(struct t3_wq *wq, struct t3_cq *cq, struct t3_cqe *cqe,
1100                      u8 *cqe_flushed, u64 *cookie, u32 *credit)
1101 {
1102         int ret = 0;
1103         struct t3_cqe *hw_cqe, read_cqe;
1104
1105         *cqe_flushed = 0;
1106         *credit = 0;
1107         hw_cqe = cxio_next_cqe(cq);
1108
1109         PDBG("%s CQE OOO %d qpid 0x%0x genbit %d type %d status 0x%0x"
1110              " opcode 0x%0x len 0x%0x wrid_hi_stag 0x%x wrid_low_msn 0x%x\n",
1111              __FUNCTION__, CQE_OOO(*hw_cqe), CQE_QPID(*hw_cqe),
1112              CQE_GENBIT(*hw_cqe), CQE_TYPE(*hw_cqe), CQE_STATUS(*hw_cqe),
1113              CQE_OPCODE(*hw_cqe), CQE_LEN(*hw_cqe), CQE_WRID_HI(*hw_cqe),
1114              CQE_WRID_LOW(*hw_cqe));
1115
1116         /*
1117          * skip cqe's not affiliated with a QP.
1118          */
1119         if (wq == NULL) {
1120                 ret = -1;
1121                 goto skip_cqe;
1122         }
1123
1124         /*
1125          * Gotta tweak READ completions:
1126          *      1) the cqe doesn't contain the sq_wptr from the wr.
1127          *      2) opcode not reflected from the wr.
1128          *      3) read_len not reflected from the wr.
1129          *      4) cq_type is RQ_TYPE not SQ_TYPE.
1130          */
1131         if (RQ_TYPE(*hw_cqe) && (CQE_OPCODE(*hw_cqe) == T3_READ_RESP)) {
1132
1133                 /*
1134                  * Don't write to the HWCQ, so create a new read req CQE
1135                  * in local memory.
1136                  */
1137                 create_read_req_cqe(wq, hw_cqe, &read_cqe);
1138                 hw_cqe = &read_cqe;
1139                 advance_oldest_read(wq);
1140         }
1141
1142         /*
1143          * T3A: Discard TERMINATE CQEs.
1144          */
1145         if (CQE_OPCODE(*hw_cqe) == T3_TERMINATE) {
1146                 ret = -1;
1147                 wq->error = 1;
1148                 goto skip_cqe;
1149         }
1150
1151         if (CQE_STATUS(*hw_cqe) || wq->error) {
1152                 *cqe_flushed = wq->error;
1153                 wq->error = 1;
1154
1155                 /*
1156                  * T3A inserts errors into the CQE.  We cannot return
1157                  * these as work completions.
1158                  */
1159                 /* incoming write failures */
1160                 if ((CQE_OPCODE(*hw_cqe) == T3_RDMA_WRITE)
1161                      && RQ_TYPE(*hw_cqe)) {
1162                         ret = -1;
1163                         goto skip_cqe;
1164                 }
1165                 /* incoming read request failures */
1166                 if ((CQE_OPCODE(*hw_cqe) == T3_READ_RESP) && SQ_TYPE(*hw_cqe)) {
1167                         ret = -1;
1168                         goto skip_cqe;
1169                 }
1170
1171                 /* incoming SEND with no receive posted failures */
1172                 if ((CQE_OPCODE(*hw_cqe) == T3_SEND) && RQ_TYPE(*hw_cqe) &&
1173                     Q_EMPTY(wq->rq_rptr, wq->rq_wptr)) {
1174                         ret = -1;
1175                         goto skip_cqe;
1176                 }
1177                 goto proc_cqe;
1178         }
1179
1180         /*
1181          * RECV completion.
1182          */
1183         if (RQ_TYPE(*hw_cqe)) {
1184
1185                 /*
1186                  * HW only validates 4 bits of MSN.  So we must validate that
1187                  * the MSN in the SEND is the next expected MSN.  If its not,
1188                  * then we complete this with TPT_ERR_MSN and mark the wq in
1189                  * error.
1190                  */
1191                 if (unlikely((CQE_WRID_MSN(*hw_cqe) != (wq->rq_rptr + 1)))) {
1192                         wq->error = 1;
1193                         hw_cqe->header |= htonl(V_CQE_STATUS(TPT_ERR_MSN));
1194                         goto proc_cqe;
1195                 }
1196                 goto proc_cqe;
1197         }
1198
1199         /*
1200          * If we get here its a send completion.
1201          *
1202          * Handle out of order completion. These get stuffed
1203          * in the SW SQ. Then the SW SQ is walked to move any
1204          * now in-order completions into the SW CQ.  This handles
1205          * 2 cases:
1206          *      1) reaping unsignaled WRs when the first subsequent
1207          *         signaled WR is completed.
1208          *      2) out of order read completions.
1209          */
1210         if (!SW_CQE(*hw_cqe) && (CQE_WRID_SQ_WPTR(*hw_cqe) != wq->sq_rptr)) {
1211                 struct t3_swsq *sqp;
1212
1213                 PDBG("%s out of order completion going in swsq at idx %ld\n",
1214                      __FUNCTION__,
1215                      Q_PTR2IDX(CQE_WRID_SQ_WPTR(*hw_cqe), wq->sq_size_log2));
1216                 sqp = wq->sq +
1217                       Q_PTR2IDX(CQE_WRID_SQ_WPTR(*hw_cqe), wq->sq_size_log2);
1218                 sqp->cqe = *hw_cqe;
1219                 sqp->complete = 1;
1220                 ret = -1;
1221                 goto flush_wq;
1222         }
1223
1224 proc_cqe:
1225         *cqe = *hw_cqe;
1226
1227         /*
1228          * Reap the associated WR(s) that are freed up with this
1229          * completion.
1230          */
1231         if (SQ_TYPE(*hw_cqe)) {
1232                 wq->sq_rptr = CQE_WRID_SQ_WPTR(*hw_cqe);
1233                 PDBG("%s completing sq idx %ld\n", __FUNCTION__,
1234                      Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2));
1235                 *cookie = (wq->sq +
1236                            Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2))->wr_id;
1237                 wq->sq_rptr++;
1238         } else {
1239                 PDBG("%s completing rq idx %ld\n", __FUNCTION__,
1240                      Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2));
1241                 *cookie = *(wq->rq + Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2));
1242                 wq->rq_rptr++;
1243         }
1244
1245 flush_wq:
1246         /*
1247          * Flush any completed cqes that are now in-order.
1248          */
1249         flush_completed_wrs(wq, cq);
1250
1251 skip_cqe:
1252         if (SW_CQE(*hw_cqe)) {
1253                 PDBG("%s cq %p cqid 0x%x skip sw cqe sw_rptr 0x%x\n",
1254                      __FUNCTION__, cq, cq->cqid, cq->sw_rptr);
1255                 ++cq->sw_rptr;
1256         } else {
1257                 PDBG("%s cq %p cqid 0x%x skip hw cqe rptr 0x%x\n",
1258                      __FUNCTION__, cq, cq->cqid, cq->rptr);
1259                 ++cq->rptr;
1260
1261                 /*
1262                  * T3A: compute credits.
1263                  */
1264                 if (((cq->rptr - cq->wptr) > (1 << (cq->size_log2 - 1)))
1265                     || ((cq->rptr - cq->wptr) >= 128)) {
1266                         *credit = cq->rptr - cq->wptr;
1267                         cq->wptr = cq->rptr;
1268                 }
1269         }
1270         return ret;
1271 }