drivers/ieee1394/ohci1394.c

   1 /*
   2  * ohci1394.c - driver for OHCI 1394 boards
   3  * Copyright (C)1999,2000 Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>
   4  *                        Gord Peters <GordPeters@smarttech.com>
   5  *              2001      Ben Collins <bcollins@debian.org>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software Foundation,
  19  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20  */
  21
  22 /*
  23  * Things known to be working:
  24  * . Async Request Transmit
  25  * . Async Response Receive
  26  * . Async Request Receive
  27  * . Async Response Transmit
  28  * . Iso Receive
  29  * . DMA mmap for iso receive
  30  * . Config ROM generation
  31  *
  32  * Things implemented, but still in test phase:
  33  * . Iso Transmit
  34  * . Async Stream Packets Transmit (Receive done via Iso interface)
  35  *
  36  * Things not implemented:
  37  * . DMA error recovery
  38  *
  39  * Known bugs:
  40  * . devctl BUS_RESET arg confusion (reset type or root holdoff?)
  41  *   added LONG_RESET_ROOT and SHORT_RESET_ROOT for root holdoff --kk
  42  */
  43
  44 /*
  45  * Acknowledgments:
  46  *
  47  * Adam J Richter <adam@yggdrasil.com>
  48  *  . Use of pci_class to find device
  49  *
  50  * Emilie Chung <emilie.chung@axis.com>
  51  *  . Tip on Async Request Filter
  52  *
  53  * Pascal Drolet <pascal.drolet@informission.ca>
  54  *  . Various tips for optimization and functionnalities
  55  *
  56  * Robert Ficklin <rficklin@westengineering.com>
  57  *  . Loop in irq_handler
  58  *
  59  * James Goodwin <jamesg@Filanet.com>
  60  *  . Various tips on initialization, self-id reception, etc.
  61  *
  62  * Albrecht Dress <ad@mpifr-bonn.mpg.de>
  63  *  . Apple PowerBook detection
  64  *
  65  * Daniel Kobras <daniel.kobras@student.uni-tuebingen.de>
  66  *  . Reset the board properly before leaving + misc cleanups
  67  *
  68  * Leon van Stuivenberg <leonvs@iae.nl>
  69  *  . Bug fixes
  70  *
  71  * Ben Collins <bcollins@debian.org>
  72  *  . Working big-endian support
  73  *  . Updated to 2.4.x module scheme (PCI aswell)
  74  *  . Config ROM generation
  75  *
  76  * Manfred Weihs <weihs@ict.tuwien.ac.at>
  77  *  . Reworked code for initiating bus resets
  78  *    (long, short, with or without hold-off)
  79  *
  80  * Nandu Santhi <contactnandu@users.sourceforge.net>
  81  *  . Added support for nVidia nForce2 onboard Firewire chipset
  82  *
  83  */
  84
  85 #include <linux/kernel.h>
  86 #include <linux/list.h>
  87 #include <linux/slab.h>
  88 #include <linux/interrupt.h>
  89 #include <linux/wait.h>
  90 #include <linux/errno.h>
  91 #include <linux/module.h>
  92 #include <linux/moduleparam.h>
  93 #include <linux/pci.h>
  94 #include <linux/fs.h>
  95 #include <linux/poll.h>
  96 #include <asm/byteorder.h>
  97 #include <asm/atomic.h>
  98 #include <asm/uaccess.h>
  99 #include <linux/delay.h>
 100 #include <linux/spinlock.h>
 101
 102 #include <asm/pgtable.h>
 103 #include <asm/page.h>
 104 #include <asm/irq.h>
 105 #include <linux/sched.h>
 106 #include <linux/types.h>
 107 #include <linux/vmalloc.h>
 108 #include <linux/init.h>
 109
 110 #ifdef CONFIG_PPC_PMAC
 111 #include <asm/machdep.h>
 112 #include <asm/pmac_feature.h>
 113 #include <asm/prom.h>
 114 #include <asm/pci-bridge.h>
 115 #endif
 116
 117 #include "csr1212.h"
 118 #include "ieee1394.h"
 119 #include "ieee1394_types.h"
 120 #include "hosts.h"
 121 #include "dma.h"
 122 #include "iso.h"
 123 #include "ieee1394_core.h"
 124 #include "highlevel.h"
 125 #include "ohci1394.h"
 126
 127 #ifdef CONFIG_IEEE1394_VERBOSEDEBUG
 128 #define OHCI1394_DEBUG
 129 #endif
 130
 131 #ifdef DBGMSG
 132 #undef DBGMSG
 133 #endif
 134
 135 #ifdef OHCI1394_DEBUG
 136 #define DBGMSG(fmt, args...) \
 137 printk(KERN_INFO "%s: fw-host%d: " fmt "\n" , OHCI1394_DRIVER_NAME, ohci->host->id , ## args)
 138 #else
 139 #define DBGMSG(fmt, args...) do {} while (0)
 140 #endif
 141
 142 #ifdef CONFIG_IEEE1394_OHCI_DMA_DEBUG
 143 #define OHCI_DMA_ALLOC(fmt, args...) \
 144         HPSB_ERR("%s(%s)alloc(%d): "fmt, OHCI1394_DRIVER_NAME, __FUNCTION__, \
 145                 ++global_outstanding_dmas, ## args)
 146 #define OHCI_DMA_FREE(fmt, args...) \
 147         HPSB_ERR("%s(%s)free(%d): "fmt, OHCI1394_DRIVER_NAME, __FUNCTION__, \
 148                 --global_outstanding_dmas, ## args)
 149 static int global_outstanding_dmas = 0;
 150 #else
 151 #define OHCI_DMA_ALLOC(fmt, args...) do {} while (0)
 152 #define OHCI_DMA_FREE(fmt, args...) do {} while (0)
 153 #endif
 154
 155 /* print general (card independent) information */
 156 #define PRINT_G(level, fmt, args...) \
 157 printk(level "%s: " fmt "\n" , OHCI1394_DRIVER_NAME , ## args)
 158
 159 /* print card specific information */
 160 #define PRINT(level, fmt, args...) \
 161 printk(level "%s: fw-host%d: " fmt "\n" , OHCI1394_DRIVER_NAME, ohci->host->id , ## args)
 162
 163 /* Module Parameters */
 164 static int phys_dma = 1;
 165 module_param(phys_dma, int, 0444);
 166 MODULE_PARM_DESC(phys_dma, "Enable physical dma (default = 1).");
 167
 168 static void dma_trm_tasklet(unsigned long data);
 169 static void dma_trm_reset(struct dma_trm_ctx *d);
 170
 171 static int alloc_dma_rcv_ctx(struct ti_ohci *ohci, struct dma_rcv_ctx *d,
 172                              enum context_type type, int ctx, int num_desc,
 173                              int buf_size, int split_buf_size, int context_base);
 174 static void stop_dma_rcv_ctx(struct dma_rcv_ctx *d);
 175 static void free_dma_rcv_ctx(struct dma_rcv_ctx *d);
 176
 177 static int alloc_dma_trm_ctx(struct ti_ohci *ohci, struct dma_trm_ctx *d,
 178                              enum context_type type, int ctx, int num_desc,
 179                              int context_base);
 180
 181 static void ohci1394_pci_remove(struct pci_dev *pdev);
 182
 183 #ifndef __LITTLE_ENDIAN
 184 const static size_t hdr_sizes[] = {
 185         3,      /* TCODE_WRITEQ */
 186         4,      /* TCODE_WRITEB */
 187         3,      /* TCODE_WRITE_RESPONSE */
 188         0,      /* reserved */
 189         3,      /* TCODE_READQ */
 190         4,      /* TCODE_READB */
 191         3,      /* TCODE_READQ_RESPONSE */
 192         4,      /* TCODE_READB_RESPONSE */
 193         1,      /* TCODE_CYCLE_START */
 194         4,      /* TCODE_LOCK_REQUEST */
 195         2,      /* TCODE_ISO_DATA */
 196         4,      /* TCODE_LOCK_RESPONSE */
 197                 /* rest is reserved or link-internal */
 198 };
 199
 200 static inline void header_le32_to_cpu(quadlet_t *data, unsigned char tcode)
 201 {
 202         size_t size;
 203
 204         if (unlikely(tcode >= ARRAY_SIZE(hdr_sizes)))
 205                 return;
 206
 207         size = hdr_sizes[tcode];
 208         while (size--)
 209                 data[size] = le32_to_cpu(data[size]);
 210 }
 211 #else
 212 #define header_le32_to_cpu(w,x) do {} while (0)
 213 #endif /* !LITTLE_ENDIAN */
 214
 215 /***********************************
 216  * IEEE-1394 functionality section *
 217  ***********************************/
 218
 219 static u8 get_phy_reg(struct ti_ohci *ohci, u8 addr)
 220 {
 221         int i;
 222         unsigned long flags;
 223         quadlet_t r;
 224
 225         spin_lock_irqsave (&ohci->phy_reg_lock, flags);
 226
 227         reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | 0x00008000);
 228
 229         for (i = 0; i < OHCI_LOOP_COUNT; i++) {
 230                 if (reg_read(ohci, OHCI1394_PhyControl) & 0x80000000)
 231                         break;
 232
 233                 mdelay(1);
 234         }
 235
 236         r = reg_read(ohci, OHCI1394_PhyControl);
 237
 238         if (i >= OHCI_LOOP_COUNT)
 239                 PRINT (KERN_ERR, "Get PHY Reg timeout [0x%08x/0x%08x/%d]",
 240                        r, r & 0x80000000, i);
 241
 242         spin_unlock_irqrestore (&ohci->phy_reg_lock, flags);
 243
 244         return (r & 0x00ff0000) >> 16;
 245 }
 246
 247 static void set_phy_reg(struct ti_ohci *ohci, u8 addr, u8 data)
 248 {
 249         int i;
 250         unsigned long flags;
 251         u32 r = 0;
 252
 253         spin_lock_irqsave (&ohci->phy_reg_lock, flags);
 254
 255         reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | data | 0x00004000);
 256
 257         for (i = 0; i < OHCI_LOOP_COUNT; i++) {
 258                 r = reg_read(ohci, OHCI1394_PhyControl);
 259                 if (!(r & 0x00004000))
 260                         break;
 261
 262                 mdelay(1);
 263         }
 264
 265         if (i == OHCI_LOOP_COUNT)
 266                 PRINT (KERN_ERR, "Set PHY Reg timeout [0x%08x/0x%08x/%d]",
 267                        r, r & 0x00004000, i);
 268
 269         spin_unlock_irqrestore (&ohci->phy_reg_lock, flags);
 270
 271         return;
 272 }
 273
 274 /* Or's our value into the current value */
 275 static void set_phy_reg_mask(struct ti_ohci *ohci, u8 addr, u8 data)
 276 {
 277         u8 old;
 278
 279         old = get_phy_reg (ohci, addr);
 280         old |= data;
 281         set_phy_reg (ohci, addr, old);
 282
 283         return;
 284 }
 285
 286 static void handle_selfid(struct ti_ohci *ohci, struct hpsb_host *host,
 287                                 int phyid, int isroot)
 288 {
 289         quadlet_t *q = ohci->selfid_buf_cpu;
 290         quadlet_t self_id_count=reg_read(ohci, OHCI1394_SelfIDCount);
 291         size_t size;
 292         quadlet_t q0, q1;
 293
 294         /* Check status of self-id reception */
 295
 296         if (ohci->selfid_swap)
 297                 q0 = le32_to_cpu(q[0]);
 298         else
 299                 q0 = q[0];
 300
 301         if ((self_id_count & 0x80000000) ||
 302             ((self_id_count & 0x00FF0000) != (q0 & 0x00FF0000))) {
 303                 PRINT(KERN_ERR,
 304                       "Error in reception of SelfID packets [0x%08x/0x%08x] (count: %d)",
 305                       self_id_count, q0, ohci->self_id_errors);
 306
 307                 /* Tip by James Goodwin <jamesg@Filanet.com>:
 308                  * We had an error, generate another bus reset in response.  */
 309                 if (ohci->self_id_errors<OHCI1394_MAX_SELF_ID_ERRORS) {
 310                         set_phy_reg_mask (ohci, 1, 0x40);
 311                         ohci->self_id_errors++;
 312                 } else {
 313                         PRINT(KERN_ERR,
 314                               "Too many errors on SelfID error reception, giving up!");
 315                 }
 316                 return;
 317         }
 318
 319         /* SelfID Ok, reset error counter. */
 320         ohci->self_id_errors = 0;
 321
 322         size = ((self_id_count & 0x00001FFC) >> 2) - 1;
 323         q++;
 324
 325         while (size > 0) {
 326                 if (ohci->selfid_swap) {
 327                         q0 = le32_to_cpu(q[0]);
 328                         q1 = le32_to_cpu(q[1]);
 329                 } else {
 330                         q0 = q[0];
 331                         q1 = q[1];
 332                 }
 333
 334                 if (q0 == ~q1) {
 335                         DBGMSG ("SelfID packet 0x%x received", q0);
 336                         hpsb_selfid_received(host, cpu_to_be32(q0));
 337                         if (((q0 & 0x3f000000) >> 24) == phyid)
 338                                 DBGMSG ("SelfID for this node is 0x%08x", q0);
 339                 } else {
 340                         PRINT(KERN_ERR,
 341                               "SelfID is inconsistent [0x%08x/0x%08x]", q0, q1);
 342                 }
 343                 q += 2;
 344                 size -= 2;
 345         }
 346
 347         DBGMSG("SelfID complete");
 348
 349         return;
 350 }
 351
 352 static void ohci_soft_reset(struct ti_ohci *ohci) {
 353         int i;
 354
 355         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
 356
 357         for (i = 0; i < OHCI_LOOP_COUNT; i++) {
 358                 if (!(reg_read(ohci, OHCI1394_HCControlSet) & OHCI1394_HCControl_softReset))
 359                         break;
 360                 mdelay(1);
 361         }
 362         DBGMSG ("Soft reset finished");
 363 }
 364
 365
 366 /* Generate the dma receive prgs and start the context */
 367 static void initialize_dma_rcv_ctx(struct dma_rcv_ctx *d, int generate_irq)
 368 {
 369         struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
 370         int i;
 371
 372         ohci1394_stop_context(ohci, d->ctrlClear, NULL);
 373
 374         for (i=0; i<d->num_desc; i++) {
 375                 u32 c;
 376
 377                 c = DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE | DMA_CTL_BRANCH;
 378                 if (generate_irq)
 379                         c |= DMA_CTL_IRQ;
 380
 381                 d->prg_cpu[i]->control = cpu_to_le32(c | d->buf_size);
 382
 383                 /* End of descriptor list? */
 384                 if (i + 1 < d->num_desc) {
 385                         d->prg_cpu[i]->branchAddress =
 386                                 cpu_to_le32((d->prg_bus[i+1] & 0xfffffff0) | 0x1);
 387                 } else {
 388                         d->prg_cpu[i]->branchAddress =
 389                                 cpu_to_le32((d->prg_bus[0] & 0xfffffff0));
 390                 }
 391
 392                 d->prg_cpu[i]->address = cpu_to_le32(d->buf_bus[i]);
 393                 d->prg_cpu[i]->status = cpu_to_le32(d->buf_size);
 394         }
 395
 396         d->buf_ind = 0;
 397         d->buf_offset = 0;
 398
 399         if (d->type == DMA_CTX_ISO) {
 400                 /* Clear contextControl */
 401                 reg_write(ohci, d->ctrlClear, 0xffffffff);
 402
 403                 /* Set bufferFill, isochHeader, multichannel for IR context */
 404                 reg_write(ohci, d->ctrlSet, 0xd0000000);
 405
 406                 /* Set the context match register to match on all tags */
 407                 reg_write(ohci, d->ctxtMatch, 0xf0000000);
 408
 409                 /* Clear the multi channel mask high and low registers */
 410                 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, 0xffffffff);
 411                 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, 0xffffffff);
 412
 413                 /* Set up isoRecvIntMask to generate interrupts */
 414                 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << d->ctx);
 415         }
 416
 417         /* Tell the controller where the first AR program is */
 418         reg_write(ohci, d->cmdPtr, d->prg_bus[0] | 0x1);
 419
 420         /* Run context */
 421         reg_write(ohci, d->ctrlSet, 0x00008000);
 422
 423         DBGMSG("Receive DMA ctx=%d initialized", d->ctx);
 424 }
 425
 426 /* Initialize the dma transmit context */
 427 static void initialize_dma_trm_ctx(struct dma_trm_ctx *d)
 428 {
 429         struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
 430
 431         /* Stop the context */
 432         ohci1394_stop_context(ohci, d->ctrlClear, NULL);
 433
 434         d->prg_ind = 0;
 435         d->sent_ind = 0;
 436         d->free_prgs = d->num_desc;
 437         d->branchAddrPtr = NULL;
 438         INIT_LIST_HEAD(&d->fifo_list);
 439         INIT_LIST_HEAD(&d->pending_list);
 440
 441         if (d->type == DMA_CTX_ISO) {
 442                 /* enable interrupts */
 443                 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << d->ctx);
 444         }
 445
 446         DBGMSG("Transmit DMA ctx=%d initialized", d->ctx);
 447 }
 448
 449 /* Count the number of available iso contexts */
 450 static int get_nb_iso_ctx(struct ti_ohci *ohci, int reg)
 451 {
 452         int i,ctx=0;
 453         u32 tmp;
 454
 455         reg_write(ohci, reg, 0xffffffff);
 456         tmp = reg_read(ohci, reg);
 457
 458         DBGMSG("Iso contexts reg: %08x implemented: %08x", reg, tmp);
 459
 460         /* Count the number of contexts */
 461         for (i=0; i<32; i++) {
 462                 if (tmp & 1) ctx++;
 463                 tmp >>= 1;
 464         }
 465         return ctx;
 466 }
 467
 468 /* Global initialization */
 469 static void ohci_initialize(struct ti_ohci *ohci)
 470 {
 471         quadlet_t buf;
 472         int num_ports, i;
 473
 474         spin_lock_init(&ohci->phy_reg_lock);
 475
 476         /* Put some defaults to these undefined bus options */
 477         buf = reg_read(ohci, OHCI1394_BusOptions);
 478         buf |=  0x60000000; /* Enable CMC and ISC */
 479         if (hpsb_disable_irm)
 480                 buf &= ~0x80000000;
 481         else
 482                 buf |=  0x80000000; /* Enable IRMC */
 483         buf &= ~0x00ff0000; /* XXX: Set cyc_clk_acc to zero for now */
 484         buf &= ~0x18000000; /* Disable PMC and BMC */
 485         reg_write(ohci, OHCI1394_BusOptions, buf);
 486
 487         /* Set the bus number */
 488         reg_write(ohci, OHCI1394_NodeID, 0x0000ffc0);
 489
 490         /* Enable posted writes */
 491         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_postedWriteEnable);
 492
 493         /* Clear link control register */
 494         reg_write(ohci, OHCI1394_LinkControlClear, 0xffffffff);
 495
 496         /* Enable cycle timer and cycle master and set the IRM
 497          * contender bit in our self ID packets if appropriate. */
 498         reg_write(ohci, OHCI1394_LinkControlSet,
 499                   OHCI1394_LinkControl_CycleTimerEnable |
 500                   OHCI1394_LinkControl_CycleMaster);
 501         i = get_phy_reg(ohci, 4) | PHY_04_LCTRL;
 502         if (hpsb_disable_irm)
 503                 i &= ~PHY_04_CONTENDER;
 504         else
 505                 i |= PHY_04_CONTENDER;
 506         set_phy_reg(ohci, 4, i);
 507
 508         /* Set up self-id dma buffer */
 509         reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->selfid_buf_bus);
 510
 511         /* enable self-id and phys */
 512         reg_write(ohci, OHCI1394_LinkControlSet, OHCI1394_LinkControl_RcvSelfID |
 513                   OHCI1394_LinkControl_RcvPhyPkt);
 514
 515         /* Set the Config ROM mapping register */
 516         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->csr_config_rom_bus);
 517
 518         /* Now get our max packet size */
 519         ohci->max_packet_size =
 520                 1<<(((reg_read(ohci, OHCI1394_BusOptions)>>12)&0xf)+1);
 521
 522         /* Don't accept phy packets into AR request context */
 523         reg_write(ohci, OHCI1394_LinkControlClear, 0x00000400);
 524
 525         /* Clear the interrupt mask */
 526         reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 0xffffffff);
 527         reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 0xffffffff);
 528
 529         /* Clear the interrupt mask */
 530         reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 0xffffffff);
 531         reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 0xffffffff);
 532
 533         /* Initialize AR dma */
 534         initialize_dma_rcv_ctx(&ohci->ar_req_context, 0);
 535         initialize_dma_rcv_ctx(&ohci->ar_resp_context, 0);
 536
 537         /* Initialize AT dma */
 538         initialize_dma_trm_ctx(&ohci->at_req_context);
 539         initialize_dma_trm_ctx(&ohci->at_resp_context);
 540
 541         /* Initialize IR Legacy DMA channel mask */
 542         ohci->ir_legacy_channels = 0;
 543
 544         /* Accept AR requests from all nodes */
 545         reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
 546
 547         /* Set the address range of the physical response unit.
 548          * Most controllers do not implement it as a writable register though.
 549          * They will keep a hardwired offset of 0x00010000 and show 0x0 as
 550          * register content.
 551          * To actually enable physical responses is the job of our interrupt
 552          * handler which programs the physical request filter. */
 553         reg_write(ohci, OHCI1394_PhyUpperBound,
 554                   OHCI1394_PHYS_UPPER_BOUND_PROGRAMMED >> 16);
 555
 556         DBGMSG("physUpperBoundOffset=%08x",
 557                reg_read(ohci, OHCI1394_PhyUpperBound));
 558
 559         /* Specify AT retries */
 560         reg_write(ohci, OHCI1394_ATRetries,
 561                   OHCI1394_MAX_AT_REQ_RETRIES |
 562                   (OHCI1394_MAX_AT_RESP_RETRIES<<4) |
 563                   (OHCI1394_MAX_PHYS_RESP_RETRIES<<8));
 564
 565         /* We don't want hardware swapping */
 566         reg_write(ohci, OHCI1394_HCControlClear, OHCI1394_HCControl_noByteSwap);
 567
 568         /* Enable interrupts */
 569         reg_write(ohci, OHCI1394_IntMaskSet,
 570                   OHCI1394_unrecoverableError |
 571                   OHCI1394_masterIntEnable |
 572                   OHCI1394_busReset |
 573                   OHCI1394_selfIDComplete |
 574                   OHCI1394_RSPkt |
 575                   OHCI1394_RQPkt |
 576                   OHCI1394_respTxComplete |
 577                   OHCI1394_reqTxComplete |
 578                   OHCI1394_isochRx |
 579                   OHCI1394_isochTx |
 580                   OHCI1394_postedWriteErr |
 581                   OHCI1394_cycleTooLong |
 582                   OHCI1394_cycleInconsistent);
 583
 584         /* Enable link */
 585         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_linkEnable);
 586
 587         buf = reg_read(ohci, OHCI1394_Version);
 588         PRINT(KERN_INFO, "OHCI-1394 %d.%d (PCI): IRQ=[%d]  "
 589               "MMIO=[%llx-%llx]  Max Packet=[%d]  IR/IT contexts=[%d/%d]",
 590               ((((buf) >> 16) & 0xf) + (((buf) >> 20) & 0xf) * 10),
 591               ((((buf) >> 4) & 0xf) + ((buf) & 0xf) * 10), ohci->dev->irq,
 592               (unsigned long long)pci_resource_start(ohci->dev, 0),
 593               (unsigned long long)pci_resource_start(ohci->dev, 0) + OHCI1394_REGISTER_SIZE - 1,
 594               ohci->max_packet_size,
 595               ohci->nb_iso_rcv_ctx, ohci->nb_iso_xmit_ctx);
 596
 597         /* Check all of our ports to make sure that if anything is
 598          * connected, we enable that port. */
 599         num_ports = get_phy_reg(ohci, 2) & 0xf;
 600         for (i = 0; i < num_ports; i++) {
 601                 unsigned int status;
 602
 603                 set_phy_reg(ohci, 7, i);
 604                 status = get_phy_reg(ohci, 8);
 605
 606                 if (status & 0x20)
 607                         set_phy_reg(ohci, 8, status & ~1);
 608         }
 609
 610         /* Serial EEPROM Sanity check. */
 611         if ((ohci->max_packet_size < 512) ||
 612             (ohci->max_packet_size > 4096)) {
 613                 /* Serial EEPROM contents are suspect, set a sane max packet
 614                  * size and print the raw contents for bug reports if verbose
 615                  * debug is enabled. */
 616 #ifdef CONFIG_IEEE1394_VERBOSEDEBUG
 617                 int i;
 618 #endif
 619
 620                 PRINT(KERN_DEBUG, "Serial EEPROM has suspicious values, "
 621                       "attempting to setting max_packet_size to 512 bytes");
 622                 reg_write(ohci, OHCI1394_BusOptions,
 623                           (reg_read(ohci, OHCI1394_BusOptions) & 0xf007) | 0x8002);
 624                 ohci->max_packet_size = 512;
 625 #ifdef CONFIG_IEEE1394_VERBOSEDEBUG
 626                 PRINT(KERN_DEBUG, "    EEPROM Present: %d",
 627                       (reg_read(ohci, OHCI1394_Version) >> 24) & 0x1);
 628                 reg_write(ohci, OHCI1394_GUID_ROM, 0x80000000);
 629
 630                 for (i = 0;
 631                      ((i < 1000) &&
 632                       (reg_read(ohci, OHCI1394_GUID_ROM) & 0x80000000)); i++)
 633                         udelay(10);
 634
 635                 for (i = 0; i < 0x20; i++) {
 636                         reg_write(ohci, OHCI1394_GUID_ROM, 0x02000000);
 637                         PRINT(KERN_DEBUG, "    EEPROM %02x: %02x", i,
 638                               (reg_read(ohci, OHCI1394_GUID_ROM) >> 16) & 0xff);
 639                 }
 640 #endif
 641         }
 642 }
 643
 644 /*
 645  * Insert a packet in the DMA fifo and generate the DMA prg
 646  * FIXME: rewrite the program in order to accept packets crossing
 647  *        page boundaries.
 648  *        check also that a single dma descriptor doesn't cross a
 649  *        page boundary.
 650  */
 651 static void insert_packet(struct ti_ohci *ohci,
 652                           struct dma_trm_ctx *d, struct hpsb_packet *packet)
 653 {
 654         u32 cycleTimer;
 655         int idx = d->prg_ind;
 656
 657         DBGMSG("Inserting packet for node " NODE_BUS_FMT
 658                ", tlabel=%d, tcode=0x%x, speed=%d",
 659                NODE_BUS_ARGS(ohci->host, packet->node_id), packet->tlabel,
 660                packet->tcode, packet->speed_code);
 661
 662         d->prg_cpu[idx]->begin.address = 0;
 663         d->prg_cpu[idx]->begin.branchAddress = 0;
 664
 665         if (d->type == DMA_CTX_ASYNC_RESP) {
 666                 /*
 667                  * For response packets, we need to put a timeout value in
 668                  * the 16 lower bits of the status... let's try 1 sec timeout
 669                  */
 670                 cycleTimer = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
 671                 d->prg_cpu[idx]->begin.status = cpu_to_le32(
 672                         (((((cycleTimer>>25)&0x7)+1)&0x7)<<13) |
 673                         ((cycleTimer&0x01fff000)>>12));
 674
 675                 DBGMSG("cycleTimer: %08x timeStamp: %08x",
 676                        cycleTimer, d->prg_cpu[idx]->begin.status);
 677         } else
 678                 d->prg_cpu[idx]->begin.status = 0;
 679
 680         if ( (packet->type == hpsb_async) || (packet->type == hpsb_raw) ) {
 681
 682                 if (packet->type == hpsb_raw) {
 683                         d->prg_cpu[idx]->data[0] = cpu_to_le32(OHCI1394_TCODE_PHY<<4);
 684                         d->prg_cpu[idx]->data[1] = cpu_to_le32(packet->header[0]);
 685                         d->prg_cpu[idx]->data[2] = cpu_to_le32(packet->header[1]);
 686                 } else {
 687                         d->prg_cpu[idx]->data[0] = packet->speed_code<<16 |
 688                                 (packet->header[0] & 0xFFFF);
 689
 690                         if (packet->tcode == TCODE_ISO_DATA) {
 691                                 /* Sending an async stream packet */
 692                                 d->prg_cpu[idx]->data[1] = packet->header[0] & 0xFFFF0000;
 693                         } else {
 694                                 /* Sending a normal async request or response */
 695                                 d->prg_cpu[idx]->data[1] =
 696                                         (packet->header[1] & 0xFFFF) |
 697                                         (packet->header[0] & 0xFFFF0000);
 698                                 d->prg_cpu[idx]->data[2] = packet->header[2];
 699                                 d->prg_cpu[idx]->data[3] = packet->header[3];
 700                         }
 701                         header_le32_to_cpu(d->prg_cpu[idx]->data, packet->tcode);
 702                 }
 703
 704                 if (packet->data_size) { /* block transmit */
 705                         if (packet->tcode == TCODE_STREAM_DATA){
 706                                 d->prg_cpu[idx]->begin.control =
 707                                         cpu_to_le32(DMA_CTL_OUTPUT_MORE |
 708                                                     DMA_CTL_IMMEDIATE | 0x8);
 709                         } else {
 710                                 d->prg_cpu[idx]->begin.control =
 711                                         cpu_to_le32(DMA_CTL_OUTPUT_MORE |
 712                                                     DMA_CTL_IMMEDIATE | 0x10);
 713                         }
 714                         d->prg_cpu[idx]->end.control =
 715                                 cpu_to_le32(DMA_CTL_OUTPUT_LAST |
 716                                             DMA_CTL_IRQ |
 717                                             DMA_CTL_BRANCH |
 718                                             packet->data_size);
 719                         /*
 720                          * Check that the packet data buffer
 721                          * does not cross a page boundary.
 722                          *
 723                          * XXX Fix this some day. eth1394 seems to trigger
 724                          * it, but ignoring it doesn't seem to cause a
 725                          * problem.
 726                          */
 727 #if 0
 728                         if (cross_bound((unsigned long)packet->data,
 729                                         packet->data_size)>0) {
 730                                 /* FIXME: do something about it */
 731                                 PRINT(KERN_ERR,
 732                                       "%s: packet data addr: %p size %Zd bytes "
 733                                       "cross page boundary", __FUNCTION__,
 734                                       packet->data, packet->data_size);
 735                         }
 736 #endif
 737                         d->prg_cpu[idx]->end.address = cpu_to_le32(
 738                                 pci_map_single(ohci->dev, packet->data,
 739                                                packet->data_size,
 740                                                PCI_DMA_TODEVICE));
 741                         OHCI_DMA_ALLOC("single, block transmit packet");
 742
 743                         d->prg_cpu[idx]->end.branchAddress = 0;
 744                         d->prg_cpu[idx]->end.status = 0;
 745                         if (d->branchAddrPtr)
 746                                 *(d->branchAddrPtr) =
 747                                         cpu_to_le32(d->prg_bus[idx] | 0x3);
 748                         d->branchAddrPtr =
 749                                 &(d->prg_cpu[idx]->end.branchAddress);
 750                 } else { /* quadlet transmit */
 751                         if (packet->type == hpsb_raw)
 752                                 d->prg_cpu[idx]->begin.control =
 753                                         cpu_to_le32(DMA_CTL_OUTPUT_LAST |
 754                                                     DMA_CTL_IMMEDIATE |
 755                                                     DMA_CTL_IRQ |
 756                                                     DMA_CTL_BRANCH |
 757                                                     (packet->header_size + 4));
 758                         else
 759                                 d->prg_cpu[idx]->begin.control =
 760                                         cpu_to_le32(DMA_CTL_OUTPUT_LAST |
 761                                                     DMA_CTL_IMMEDIATE |
 762                                                     DMA_CTL_IRQ |
 763                                                     DMA_CTL_BRANCH |
 764                                                     packet->header_size);
 765
 766                         if (d->branchAddrPtr)
 767                                 *(d->branchAddrPtr) =
 768                                         cpu_to_le32(d->prg_bus[idx] | 0x2);
 769                         d->branchAddrPtr =
 770                                 &(d->prg_cpu[idx]->begin.branchAddress);
 771                 }
 772
 773         } else { /* iso packet */
 774                 d->prg_cpu[idx]->data[0] = packet->speed_code<<16 |
 775                         (packet->header[0] & 0xFFFF);
 776                 d->prg_cpu[idx]->data[1] = packet->header[0] & 0xFFFF0000;
 777                 header_le32_to_cpu(d->prg_cpu[idx]->data, packet->tcode);
 778
 779                 d->prg_cpu[idx]->begin.control =
 780                         cpu_to_le32(DMA_CTL_OUTPUT_MORE |
 781                                     DMA_CTL_IMMEDIATE | 0x8);
 782                 d->prg_cpu[idx]->end.control =
 783                         cpu_to_le32(DMA_CTL_OUTPUT_LAST |
 784                                     DMA_CTL_UPDATE |
 785                                     DMA_CTL_IRQ |
 786                                     DMA_CTL_BRANCH |
 787                                     packet->data_size);
 788                 d->prg_cpu[idx]->end.address = cpu_to_le32(
 789                                 pci_map_single(ohci->dev, packet->data,
 790                                 packet->data_size, PCI_DMA_TODEVICE));
 791                 OHCI_DMA_ALLOC("single, iso transmit packet");
 792
 793                 d->prg_cpu[idx]->end.branchAddress = 0;
 794                 d->prg_cpu[idx]->end.status = 0;
 795                 DBGMSG("Iso xmit context info: header[%08x %08x]\n"
 796                        "                       begin=%08x %08x %08x %08x\n"
 797                        "                             %08x %08x %08x %08x\n"
 798                        "                       end  =%08x %08x %08x %08x",
 799                        d->prg_cpu[idx]->data[0], d->prg_cpu[idx]->data[1],
 800                        d->prg_cpu[idx]->begin.control,
 801                        d->prg_cpu[idx]->begin.address,
 802                        d->prg_cpu[idx]->begin.branchAddress,
 803                        d->prg_cpu[idx]->begin.status,
 804                        d->prg_cpu[idx]->data[0],
 805                        d->prg_cpu[idx]->data[1],
 806                        d->prg_cpu[idx]->data[2],
 807                        d->prg_cpu[idx]->data[3],
 808                        d->prg_cpu[idx]->end.control,
 809                        d->prg_cpu[idx]->end.address,
 810                        d->prg_cpu[idx]->end.branchAddress,
 811                        d->prg_cpu[idx]->end.status);
 812                 if (d->branchAddrPtr)
 813                         *(d->branchAddrPtr) = cpu_to_le32(d->prg_bus[idx] | 0x3);
 814                 d->branchAddrPtr = &(d->prg_cpu[idx]->end.branchAddress);
 815         }
 816         d->free_prgs--;
 817
 818         /* queue the packet in the appropriate context queue */
 819         list_add_tail(&packet->driver_list, &d->fifo_list);
 820         d->prg_ind = (d->prg_ind + 1) % d->num_desc;
 821 }
 822
 823 /*
 824  * This function fills the FIFO with the (eventual) pending packets
 825  * and runs or wakes up the DMA prg if necessary.
 826  *
 827  * The function MUST be called with the d->lock held.
 828  */
 829 static void dma_trm_flush(struct ti_ohci *ohci, struct dma_trm_ctx *d)
 830 {
 831         struct hpsb_packet *packet, *ptmp;
 832         int idx = d->prg_ind;
 833         int z = 0;
 834
 835         /* insert the packets into the dma fifo */
 836         list_for_each_entry_safe(packet, ptmp, &d->pending_list, driver_list) {
 837                 if (!d->free_prgs)
 838                         break;
 839
 840                 /* For the first packet only */
 841                 if (!z)
 842                         z = (packet->data_size) ? 3 : 2;
 843
 844                 /* Insert the packet */
 845                 list_del_init(&packet->driver_list);
 846                 insert_packet(ohci, d, packet);
 847         }
 848
 849         /* Nothing must have been done, either no free_prgs or no packets */
 850         if (z == 0)
 851                 return;
 852
 853         /* Is the context running ? (should be unless it is
 854            the first packet to be sent in this context) */
 855         if (!(reg_read(ohci, d->ctrlSet) & 0x8000)) {
 856                 u32 nodeId = reg_read(ohci, OHCI1394_NodeID);
 857
 858                 DBGMSG("Starting transmit DMA ctx=%d",d->ctx);
 859                 reg_write(ohci, d->cmdPtr, d->prg_bus[idx] | z);
 860
 861                 /* Check that the node id is valid, and not 63 */
 862                 if (!(nodeId & 0x80000000) || (nodeId & 0x3f) == 63)
 863                         PRINT(KERN_ERR, "Running dma failed because Node ID is not valid");
 864                 else
 865                         reg_write(ohci, d->ctrlSet, 0x8000);
 866         } else {
 867                 /* Wake up the dma context if necessary */
 868                 if (!(reg_read(ohci, d->ctrlSet) & 0x400))
 869                         DBGMSG("Waking transmit DMA ctx=%d",d->ctx);
 870
 871                 /* do this always, to avoid race condition */
 872                 reg_write(ohci, d->ctrlSet, 0x1000);
 873         }
 874
 875         return;
 876 }
 877
 878 /* Transmission of an async or iso packet */
 879 static int ohci_transmit(struct hpsb_host *host, struct hpsb_packet *packet)
 880 {
 881         struct ti_ohci *ohci = host->hostdata;
 882         struct dma_trm_ctx *d;
 883         unsigned long flags;
 884
 885         if (packet->data_size > ohci->max_packet_size) {
 886                 PRINT(KERN_ERR,
 887                       "Transmit packet size %Zd is too big",
 888                       packet->data_size);
 889                 return -EOVERFLOW;
 890         }
 891
 892         /* Decide whether we have an iso, a request, or a response packet */
 893         if (packet->type == hpsb_raw)
 894                 d = &ohci->at_req_context;
 895         else if ((packet->tcode == TCODE_ISO_DATA) && (packet->type == hpsb_iso)) {
 896                 /* The legacy IT DMA context is initialized on first
 897                  * use.  However, the alloc cannot be run from
 898                  * interrupt context, so we bail out if that is the
 899                  * case. I don't see anyone sending ISO packets from
 900                  * interrupt context anyway... */
 901
 902                 if (ohci->it_legacy_context.ohci == NULL) {
 903                         if (in_interrupt()) {
 904                                 PRINT(KERN_ERR,
 905                                       "legacy IT context cannot be initialized during interrupt");
 906                                 return -EINVAL;
 907                         }
 908
 909                         if (alloc_dma_trm_ctx(ohci, &ohci->it_legacy_context,
 910                                               DMA_CTX_ISO, 0, IT_NUM_DESC,
 911                                               OHCI1394_IsoXmitContextBase) < 0) {
 912                                 PRINT(KERN_ERR,
 913                                       "error initializing legacy IT context");
 914                                 return -ENOMEM;
 915                         }
 916
 917                         initialize_dma_trm_ctx(&ohci->it_legacy_context);
 918                 }
 919
 920                 d = &ohci->it_legacy_context;
 921         } else if ((packet->tcode & 0x02) && (packet->tcode != TCODE_ISO_DATA))
 922                 d = &ohci->at_resp_context;
 923         else
 924                 d = &ohci->at_req_context;
 925
 926         spin_lock_irqsave(&d->lock,flags);
 927
 928         list_add_tail(&packet->driver_list, &d->pending_list);
 929
 930         dma_trm_flush(ohci, d);
 931
 932         spin_unlock_irqrestore(&d->lock,flags);
 933
 934         return 0;
 935 }
 936
 937 static int ohci_devctl(struct hpsb_host *host, enum devctl_cmd cmd, int arg)
 938 {
 939         struct ti_ohci *ohci = host->hostdata;
 940         int retval = 0;
 941         unsigned long flags;
 942         int phy_reg;
 943
 944         switch (cmd) {
 945         case RESET_BUS:
 946                 switch (arg) {
 947                 case SHORT_RESET:
 948                         phy_reg = get_phy_reg(ohci, 5);
 949                         phy_reg |= 0x40;
 950                         set_phy_reg(ohci, 5, phy_reg); /* set ISBR */
 951                         break;
 952                 case LONG_RESET:
 953                         phy_reg = get_phy_reg(ohci, 1);
 954                         phy_reg |= 0x40;
 955                         set_phy_reg(ohci, 1, phy_reg); /* set IBR */
 956                         break;
 957                 case SHORT_RESET_NO_FORCE_ROOT:
 958                         phy_reg = get_phy_reg(ohci, 1);
 959                         if (phy_reg & 0x80) {
 960                                 phy_reg &= ~0x80;
 961                                 set_phy_reg(ohci, 1, phy_reg); /* clear RHB */
 962                         }
 963
 964                         phy_reg = get_phy_reg(ohci, 5);
 965                         phy_reg |= 0x40;
 966                         set_phy_reg(ohci, 5, phy_reg); /* set ISBR */
 967                         break;
 968                 case LONG_RESET_NO_FORCE_ROOT:
 969                         phy_reg = get_phy_reg(ohci, 1);
 970                         phy_reg &= ~0x80;
 971                         phy_reg |= 0x40;
 972                         set_phy_reg(ohci, 1, phy_reg); /* clear RHB, set IBR */
 973                         break;
 974                 case SHORT_RESET_FORCE_ROOT:
 975                         phy_reg = get_phy_reg(ohci, 1);
 976                         if (!(phy_reg & 0x80)) {
 977                                 phy_reg |= 0x80;
 978                                 set_phy_reg(ohci, 1, phy_reg); /* set RHB */
 979                         }
 980
 981                         phy_reg = get_phy_reg(ohci, 5);
 982                         phy_reg |= 0x40;
 983                         set_phy_reg(ohci, 5, phy_reg); /* set ISBR */
 984                         break;
 985                 case LONG_RESET_FORCE_ROOT:
 986                         phy_reg = get_phy_reg(ohci, 1);
 987                         phy_reg |= 0xc0;
 988                         set_phy_reg(ohci, 1, phy_reg); /* set RHB and IBR */
 989                         break;
 990                 default:
 991                         retval = -1;
 992                 }
 993                 break;
 994
 995         case GET_CYCLE_COUNTER:
 996                 retval = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
 997                 break;
 998
 999         case SET_CYCLE_COUNTER:
1000                 reg_write(ohci, OHCI1394_IsochronousCycleTimer, arg);
1001                 break;
1002
1003         case SET_BUS_ID:
1004                 PRINT(KERN_ERR, "devctl command SET_BUS_ID err");
1005                 break;
1006
1007         case ACT_CYCLE_MASTER:
1008                 if (arg) {
1009                         /* check if we are root and other nodes are present */
1010                         u32 nodeId = reg_read(ohci, OHCI1394_NodeID);
1011                         if ((nodeId & (1<<30)) && (nodeId & 0x3f)) {
1012                                 /*
1013                                  * enable cycleTimer, cycleMaster
1014                                  */
1015                                 DBGMSG("Cycle master enabled");
1016                                 reg_write(ohci, OHCI1394_LinkControlSet,
1017                                           OHCI1394_LinkControl_CycleTimerEnable |
1018                                           OHCI1394_LinkControl_CycleMaster);
1019                         }
1020                 } else {
1021                         /* disable cycleTimer, cycleMaster, cycleSource */
1022                         reg_write(ohci, OHCI1394_LinkControlClear,
1023                                   OHCI1394_LinkControl_CycleTimerEnable |
1024                                   OHCI1394_LinkControl_CycleMaster |
1025                                   OHCI1394_LinkControl_CycleSource);
1026                 }
1027                 break;
1028
1029         case CANCEL_REQUESTS:
1030                 DBGMSG("Cancel request received");
1031                 dma_trm_reset(&ohci->at_req_context);
1032                 dma_trm_reset(&ohci->at_resp_context);
1033                 break;
1034
1035         case ISO_LISTEN_CHANNEL:
1036         {
1037                 u64 mask;
1038                 struct dma_rcv_ctx *d = &ohci->ir_legacy_context;
1039                 int ir_legacy_active;
1040
1041                 if (arg<0 || arg>63) {
1042                         PRINT(KERN_ERR,
1043                               "%s: IS0 listen channel %d is out of range",
1044                               __FUNCTION__, arg);
1045                         return -EFAULT;
1046                 }
1047
1048                 mask = (u64)0x1<<arg;
1049
1050                 spin_lock_irqsave(&ohci->IR_channel_lock, flags);
1051
1052                 if (ohci->ISO_channel_usage & mask) {
1053                         PRINT(KERN_ERR,
1054                               "%s: IS0 listen channel %d is already used",
1055                               __FUNCTION__, arg);
1056                         spin_unlock_irqrestore(&ohci->IR_channel_lock, flags);
1057                         return -EFAULT;
1058                 }
1059
1060                 ir_legacy_active = ohci->ir_legacy_channels;
1061
1062                 ohci->ISO_channel_usage |= mask;
1063                 ohci->ir_legacy_channels |= mask;
1064
1065                 spin_unlock_irqrestore(&ohci->IR_channel_lock, flags);
1066
1067                 if (!ir_legacy_active) {
1068                         if (ohci1394_register_iso_tasklet(ohci,
1069                                           &ohci->ir_legacy_tasklet) < 0) {
1070                                 PRINT(KERN_ERR, "No IR DMA context available");
1071                                 return -EBUSY;
1072                         }
1073
1074                         /* the IR context can be assigned to any DMA context
1075                          * by ohci1394_register_iso_tasklet */
1076                         d->ctx = ohci->ir_legacy_tasklet.context;
1077                         d->ctrlSet = OHCI1394_IsoRcvContextControlSet +
1078                                 32*d->ctx;
1079                         d->ctrlClear = OHCI1394_IsoRcvContextControlClear +
1080                                 32*d->ctx;
1081                         d->cmdPtr = OHCI1394_IsoRcvCommandPtr + 32*d->ctx;
1082                         d->ctxtMatch = OHCI1394_IsoRcvContextMatch + 32*d->ctx;
1083
1084                         initialize_dma_rcv_ctx(&ohci->ir_legacy_context, 1);
1085
1086                         if (printk_ratelimit())
1087                                 DBGMSG("IR legacy activated");
1088                 }
1089
1090                 spin_lock_irqsave(&ohci->IR_channel_lock, flags);
1091
1092                 if (arg>31)
1093                         reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet,
1094                                   1<<(arg-32));
1095                 else
1096                         reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet,
1097                                   1<<arg);
1098
1099                 spin_unlock_irqrestore(&ohci->IR_channel_lock, flags);
1100                 DBGMSG("Listening enabled on channel %d", arg);
1101                 break;
1102         }
1103         case ISO_UNLISTEN_CHANNEL:
1104         {
1105                 u64 mask;
1106
1107                 if (arg<0 || arg>63) {
1108                         PRINT(KERN_ERR,
1109                               "%s: IS0 unlisten channel %d is out of range",
1110                               __FUNCTION__, arg);
1111                         return -EFAULT;
1112                 }
1113
1114                 mask = (u64)0x1<<arg;
1115
1116                 spin_lock_irqsave(&ohci->IR_channel_lock, flags);
1117
1118                 if (!(ohci->ISO_channel_usage & mask)) {
1119                         PRINT(KERN_ERR,
1120                               "%s: IS0 unlisten channel %d is not used",
1121                               __FUNCTION__, arg);
1122                         spin_unlock_irqrestore(&ohci->IR_channel_lock, flags);
1123                         return -EFAULT;
1124                 }
1125
1126                 ohci->ISO_channel_usage &= ~mask;
1127                 ohci->ir_legacy_channels &= ~mask;
1128
1129                 if (arg>31)
1130                         reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear,
1131                                   1<<(arg-32));
1132                 else
1133                         reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear,
1134                                   1<<arg);
1135
1136                 spin_unlock_irqrestore(&ohci->IR_channel_lock, flags);
1137                 DBGMSG("Listening disabled on channel %d", arg);
1138
1139                 if (ohci->ir_legacy_channels == 0) {
1140                         stop_dma_rcv_ctx(&ohci->ir_legacy_context);
1141                         DBGMSG("ISO legacy receive context stopped");
1142                 }
1143
1144                 break;
1145         }
1146         default:
1147                 PRINT_G(KERN_ERR, "ohci_devctl cmd %d not implemented yet",
1148                         cmd);
1149                 break;
1150         }
1151         return retval;
1152 }
1153
1154 /***********************************
1155  * rawiso ISO reception            *
1156  ***********************************/
1157
1158 /*
1159   We use either buffer-fill or packet-per-buffer DMA mode. The DMA
1160   buffer is split into "blocks" (regions described by one DMA
1161   descriptor). Each block must be one page or less in size, and
1162   must not cross a page boundary.
1163
1164   There is one little wrinkle with buffer-fill mode: a packet that
1165   starts in the final block may wrap around into the first block. But
1166   the user API expects all packets to be contiguous. Our solution is
1167   to keep the very last page of the DMA buffer in reserve - if a
1168   packet spans the gap, we copy its tail into this page.
1169 */
1170
1171 struct ohci_iso_recv {
1172         struct ti_ohci *ohci;
1173
1174         struct ohci1394_iso_tasklet task;
1175         int task_active;
1176
1177         enum { BUFFER_FILL_MODE = 0,
1178                PACKET_PER_BUFFER_MODE = 1 } dma_mode;
1179
1180         /* memory and PCI mapping for the DMA descriptors */
1181         struct dma_prog_region prog;
1182         struct dma_cmd *block; /* = (struct dma_cmd*) prog.virt */
1183
1184         /* how many DMA blocks fit in the buffer */
1185         unsigned int nblocks;
1186
1187         /* stride of DMA blocks */
1188         unsigned int buf_stride;
1189
1190         /* number of blocks to batch between interrupts */
1191         int block_irq_interval;
1192
1193         /* block that DMA will finish next */
1194         int block_dma;
1195
1196         /* (buffer-fill only) block that the reader will release next */
1197         int block_reader;
1198
1199         /* (buffer-fill only) bytes of buffer the reader has released,
1200            less than one block */
1201         int released_bytes;
1202
1203         /* (buffer-fill only) buffer offset at which the next packet will appear */
1204         int dma_offset;
1205
1206         /* OHCI DMA context control registers */
1207         u32 ContextControlSet;
1208         u32 ContextControlClear;
1209         u32 CommandPtr;
1210         u32 ContextMatch;
1211 };
1212
1213 static void ohci_iso_recv_task(unsigned long data);
1214 static void ohci_iso_recv_stop(struct hpsb_iso *iso);
1215 static void ohci_iso_recv_shutdown(struct hpsb_iso *iso);
1216 static int  ohci_iso_recv_start(struct hpsb_iso *iso, int cycle, int tag_mask, int sync);
1217 static void ohci_iso_recv_program(struct hpsb_iso *iso);
1218
1219 static int ohci_iso_recv_init(struct hpsb_iso *iso)
1220 {
1221         struct ti_ohci *ohci = iso->host->hostdata;
1222         struct ohci_iso_recv *recv;
1223         int ctx;
1224         int ret = -ENOMEM;
1225
1226         recv = kmalloc(sizeof(*recv), GFP_KERNEL);
1227         if (!recv)
1228                 return -ENOMEM;
1229
1230         iso->hostdata = recv;
1231         recv->ohci = ohci;
1232         recv->task_active = 0;
1233         dma_prog_region_init(&recv->prog);
1234         recv->block = NULL;
1235
1236         /* use buffer-fill mode, unless irq_interval is 1
1237            (note: multichannel requires buffer-fill) */
1238
1239         if (((iso->irq_interval == 1 && iso->dma_mode == HPSB_ISO_DMA_OLD_ABI) ||
1240              iso->dma_mode == HPSB_ISO_DMA_PACKET_PER_BUFFER) && iso->channel != -1) {
1241                 recv->dma_mode = PACKET_PER_BUFFER_MODE;
1242         } else {
1243                 recv->dma_mode = BUFFER_FILL_MODE;
1244         }
1245
1246         /* set nblocks, buf_stride, block_irq_interval */
1247
1248         if (recv->dma_mode == BUFFER_FILL_MODE) {
1249                 recv->buf_stride = PAGE_SIZE;
1250
1251                 /* one block per page of data in the DMA buffer, minus the final guard page */
1252                 recv->nblocks = iso->buf_size/PAGE_SIZE - 1;
1253                 if (recv->nblocks < 3) {
1254                         DBGMSG("ohci_iso_recv_init: DMA buffer too small");
1255                         goto err;
1256                 }
1257
1258                 /* iso->irq_interval is in packets - translate that to blocks */
1259                 if (iso->irq_interval == 1)
1260                         recv->block_irq_interval = 1;
1261                 else
1262                         recv->block_irq_interval = iso->irq_interval *
1263                                                         ((recv->nblocks+1)/iso->buf_packets);
1264                 if (recv->block_irq_interval*4 > recv->nblocks)
1265                         recv->block_irq_interval = recv->nblocks/4;
1266                 if (recv->block_irq_interval < 1)
1267                         recv->block_irq_interval = 1;
1268
1269         } else {
1270                 int max_packet_size;
1271
1272                 recv->nblocks = iso->buf_packets;
1273                 recv->block_irq_interval = iso->irq_interval;
1274                 if (recv->block_irq_interval * 4 > iso->buf_packets)
1275                         recv->block_irq_interval = iso->buf_packets / 4;
1276                 if (recv->block_irq_interval < 1)
1277                 recv->block_irq_interval = 1;
1278
1279                 /* choose a buffer stride */
1280                 /* must be a power of 2, and <= PAGE_SIZE */
1281
1282                 max_packet_size = iso->buf_size / iso->buf_packets;
1283
1284                 for (recv->buf_stride = 8; recv->buf_stride < max_packet_size;
1285                     recv->buf_stride *= 2);
1286
1287                 if (recv->buf_stride*iso->buf_packets > iso->buf_size ||
1288                    recv->buf_stride > PAGE_SIZE) {
1289                         /* this shouldn't happen, but anyway... */
1290                         DBGMSG("ohci_iso_recv_init: problem choosing a buffer stride");
1291                         goto err;
1292                 }
1293         }
1294
1295         recv->block_reader = 0;
1296         recv->released_bytes = 0;
1297         recv->block_dma = 0;
1298         recv->dma_offset = 0;
1299
1300         /* size of DMA program = one descriptor per block */
1301         if (dma_prog_region_alloc(&recv->prog,
1302                                  sizeof(struct dma_cmd) * recv->nblocks,
1303                                  recv->ohci->dev))
1304                 goto err;
1305
1306         recv->block = (struct dma_cmd*) recv->prog.kvirt;
1307
1308         ohci1394_init_iso_tasklet(&recv->task,
1309                                   iso->channel == -1 ? OHCI_ISO_MULTICHANNEL_RECEIVE :
1310                                                        OHCI_ISO_RECEIVE,
1311                                   ohci_iso_recv_task, (unsigned long) iso);
1312
1313         if (ohci1394_register_iso_tasklet(recv->ohci, &recv->task) < 0) {
1314                 ret = -EBUSY;
1315                 goto err;
1316         }
1317
1318         recv->task_active = 1;
1319
1320         /* recv context registers are spaced 32 bytes apart */
1321         ctx = recv->task.context;
1322         recv->ContextControlSet = OHCI1394_IsoRcvContextControlSet + 32 * ctx;
1323         recv->ContextControlClear = OHCI1394_IsoRcvContextControlClear + 32 * ctx;
1324         recv->CommandPtr = OHCI1394_IsoRcvCommandPtr + 32 * ctx;
1325         recv->ContextMatch = OHCI1394_IsoRcvContextMatch + 32 * ctx;
1326
1327         if (iso->channel == -1) {
1328                 /* clear multi-channel selection mask */
1329                 reg_write(recv->ohci, OHCI1394_IRMultiChanMaskHiClear, 0xFFFFFFFF);
1330                 reg_write(recv->ohci, OHCI1394_IRMultiChanMaskLoClear, 0xFFFFFFFF);
1331         }
1332
1333         /* write the DMA program */
1334         ohci_iso_recv_program(iso);
1335
1336         DBGMSG("ohci_iso_recv_init: %s mode, DMA buffer is %lu pages"
1337                " (%u bytes), using %u blocks, buf_stride %u, block_irq_interval %d",
1338                recv->dma_mode == BUFFER_FILL_MODE ?
1339                "buffer-fill" : "packet-per-buffer",
1340                iso->buf_size/PAGE_SIZE, iso->buf_size,
1341                recv->nblocks, recv->buf_stride, recv->block_irq_interval);
1342
1343         return 0;
1344
1345 err:
1346         ohci_iso_recv_shutdown(iso);
1347         return ret;
1348 }
1349
1350 static void ohci_iso_recv_stop(struct hpsb_iso *iso)
1351 {
1352         struct ohci_iso_recv *recv = iso->hostdata;
1353
1354         /* disable interrupts */
1355         reg_write(recv->ohci, OHCI1394_IsoRecvIntMaskClear, 1 << recv->task.context);
1356
1357         /* halt DMA */
1358         ohci1394_stop_context(recv->ohci, recv->ContextControlClear, NULL);
1359 }
1360
1361 static void ohci_iso_recv_shutdown(struct hpsb_iso *iso)
1362 {
1363         struct ohci_iso_recv *recv = iso->hostdata;
1364
1365         if (recv->task_active) {
1366                 ohci_iso_recv_stop(iso);
1367                 ohci1394_unregister_iso_tasklet(recv->ohci, &recv->task);
1368                 recv->task_active = 0;
1369         }
1370
1371         dma_prog_region_free(&recv->prog);
1372         kfree(recv);
1373         iso->hostdata = NULL;
1374 }
1375
1376 /* set up a "gapped" ring buffer DMA program */
1377 static void ohci_iso_recv_program(struct hpsb_iso *iso)
1378 {
1379         struct ohci_iso_recv *recv = iso->hostdata;
1380         int blk;
1381
1382         /* address of 'branch' field in previous DMA descriptor */
1383         u32 *prev_branch = NULL;
1384
1385         for (blk = 0; blk < recv->nblocks; blk++) {
1386                 u32 control;
1387
1388                 /* the DMA descriptor */
1389                 struct dma_cmd *cmd = &recv->block[blk];
1390
1391                 /* offset of the DMA descriptor relative to the DMA prog buffer */
1392                 unsigned long prog_offset = blk * sizeof(struct dma_cmd);
1393
1394                 /* offset of this packet's data within the DMA buffer */
1395                 unsigned long buf_offset = blk * recv->buf_stride;
1396
1397                 if (recv->dma_mode == BUFFER_FILL_MODE) {
1398                         control = 2 << 28; /* INPUT_MORE */
1399                 } else {
1400                         control = 3 << 28; /* INPUT_LAST */
1401                 }
1402
1403                 control |= 8 << 24; /* s = 1, update xferStatus and resCount */
1404
1405                 /* interrupt on last block, and at intervals */
1406                 if (blk == recv->nblocks-1 || (blk % recv->block_irq_interval) == 0) {
1407                         control |= 3 << 20; /* want interrupt */
1408                 }
1409
1410                 control |= 3 << 18; /* enable branch to address */
1411                 control |= recv->buf_stride;
1412
1413                 cmd->control = cpu_to_le32(control);
1414                 cmd->address = cpu_to_le32(dma_region_offset_to_bus(&iso->data_buf, buf_offset));
1415                 cmd->branchAddress = 0; /* filled in on next loop */
1416                 cmd->status = cpu_to_le32(recv->buf_stride);
1417
1418                 /* link the previous descriptor to this one */
1419                 if (prev_branch) {
1420                         *prev_branch = cpu_to_le32(dma_prog_region_offset_to_bus(&recv->prog, prog_offset) | 1);
1421                 }
1422
1423                 prev_branch = &cmd->branchAddress;
1424         }
1425
1426         /* the final descriptor's branch address and Z should be left at 0 */
1427 }
1428
1429 /* listen or unlisten to a specific channel (multi-channel mode only) */
1430 static void ohci_iso_recv_change_channel(struct hpsb_iso *iso, unsigned char channel, int listen)
1431 {
1432         struct ohci_iso_recv *recv = iso->hostdata;
1433         int reg, i;
1434
1435         if (channel < 32) {
1436                 reg = listen ? OHCI1394_IRMultiChanMaskLoSet : OHCI1394_IRMultiChanMaskLoClear;
1437                 i = channel;
1438         } else {
1439                 reg = listen ? OHCI1394_IRMultiChanMaskHiSet : OHCI1394_IRMultiChanMaskHiClear;
1440                 i = channel - 32;
1441         }
1442
1443         reg_write(recv->ohci, reg, (1 << i));
1444
1445         /* issue a dummy read to force all PCI writes to be posted immediately */
1446         mb();
1447         reg_read(recv->ohci, OHCI1394_IsochronousCycleTimer);
1448 }
1449
1450 static void ohci_iso_recv_set_channel_mask(struct hpsb_iso *iso, u64 mask)
1451 {
1452         struct ohci_iso_recv *recv = iso->hostdata;
1453         int i;
1454
1455         for (i = 0; i < 64; i++) {
1456                 if (mask & (1ULL << i)) {
1457                         if (i < 32)
1458                                 reg_write(recv->ohci, OHCI1394_IRMultiChanMaskLoSet, (1 << i));
1459                         else
1460                                 reg_write(recv->ohci, OHCI1394_IRMultiChanMaskHiSet, (1 << (i-32)));
1461                 } else {
1462                         if (i < 32)
1463                                 reg_write(recv->ohci, OHCI1394_IRMultiChanMaskLoClear, (1 << i));
1464                         else
1465                                 reg_write(recv->ohci, OHCI1394_IRMultiChanMaskHiClear, (1 << (i-32)));
1466                 }
1467         }
1468
1469         /* issue a dummy read to force all PCI writes to be posted immediately */
1470         mb();
1471         reg_read(recv->ohci, OHCI1394_IsochronousCycleTimer);
1472 }
1473
1474 static int ohci_iso_recv_start(struct hpsb_iso *iso, int cycle, int tag_mask, int sync)
1475 {
1476         struct ohci_iso_recv *recv = iso->hostdata;
1477         struct ti_ohci *ohci = recv->ohci;
1478         u32 command, contextMatch;
1479
1480         reg_write(recv->ohci, recv->ContextControlClear, 0xFFFFFFFF);
1481         wmb();
1482
1483         /* always keep ISO headers */
1484         command = (1 << 30);
1485
1486         if (recv->dma_mode == BUFFER_FILL_MODE)
1487                 command |= (1 << 31);
1488
1489         reg_write(recv->ohci, recv->ContextControlSet, command);
1490
1491         /* match on specified tags */
1492         contextMatch = tag_mask << 28;
1493
1494         if (iso->channel == -1) {
1495                 /* enable multichannel reception */
1496                 reg_write(recv->ohci, recv->ContextControlSet, (1 << 28));
1497         } else {
1498                 /* listen on channel */
1499                 contextMatch |= iso->channel;
1500         }
1501
1502         if (cycle != -1) {
1503                 u32 seconds;
1504
1505                 /* enable cycleMatch */
1506                 reg_write(recv->ohci, recv->ContextControlSet, (1 << 29));
1507
1508                 /* set starting cycle */
1509                 cycle &= 0x1FFF;
1510
1511                 /* 'cycle' is only mod 8000, but we also need two 'seconds' bits -
1512                    just snarf them from the current time */
1513                 seconds = reg_read(recv->ohci, OHCI1394_IsochronousCycleTimer) >> 25;
1514
1515                 /* advance one second to give some extra time for DMA to start */
1516                 seconds += 1;
1517
1518                 cycle |= (seconds & 3) << 13;
1519
1520                 contextMatch |= cycle << 12;
1521         }
1522
1523         if (sync != -1) {
1524                 /* set sync flag on first DMA descriptor */
1525                 struct dma_cmd *cmd = &recv->block[recv->block_dma];
1526                 cmd->control |= cpu_to_le32(DMA_CTL_WAIT);
1527
1528                 /* match sync field */
1529                 contextMatch |= (sync&0xf)<<8;
1530         }
1531
1532         reg_write(recv->ohci, recv->ContextMatch, contextMatch);
1533
1534         /* address of first descriptor block */
1535         command = dma_prog_region_offset_to_bus(&recv->prog,
1536                                                 recv->block_dma * sizeof(struct dma_cmd));
1537         command |= 1; /* Z=1 */
1538
1539         reg_write(recv->ohci, recv->CommandPtr, command);
1540
1541         /* enable interrupts */
1542         reg_write(recv->ohci, OHCI1394_IsoRecvIntMaskSet, 1 << recv->task.context);
1543
1544         wmb();
1545
1546         /* run */
1547         reg_write(recv->ohci, recv->ContextControlSet, 0x8000);
1548
1549         /* issue a dummy read of the cycle timer register to force
1550            all PCI writes to be posted immediately */
1551         mb();
1552         reg_read(recv->ohci, OHCI1394_IsochronousCycleTimer);
1553
1554         /* check RUN */
1555         if (!(reg_read(recv->ohci, recv->ContextControlSet) & 0x8000)) {
1556                 PRINT(KERN_ERR,
1557                       "Error starting IR DMA (ContextControl 0x%08x)\n",
1558                       reg_read(recv->ohci, recv->ContextControlSet));
1559                 return -1;
1560         }
1561
1562         return 0;
1563 }
1564
1565 static void ohci_iso_recv_release_block(struct ohci_iso_recv *recv, int block)
1566 {
1567         /* re-use the DMA descriptor for the block */
1568         /* by linking the previous descriptor to it */
1569
1570         int next_i = block;
1571         int prev_i = (next_i == 0) ? (recv->nblocks - 1) : (next_i - 1);
1572
1573         struct dma_cmd *next = &recv->block[next_i];
1574         struct dma_cmd *prev = &recv->block[prev_i];
1575
1576         /* ignore out-of-range requests */
1577         if ((block < 0) || (block > recv->nblocks))
1578                 return;
1579
1580         /* 'next' becomes the new end of the DMA chain,
1581            so disable branch and enable interrupt */
1582         next->branchAddress = 0;
1583         next->control |= cpu_to_le32(3 << 20);
1584         next->status = cpu_to_le32(recv->buf_stride);
1585
1586         /* link prev to next */
1587         prev->branchAddress = cpu_to_le32(dma_prog_region_offset_to_bus(&recv->prog,
1588                                                                         sizeof(struct dma_cmd) * next_i)
1589                                           | 1); /* Z=1 */
1590
1591         /* disable interrupt on previous DMA descriptor, except at intervals */
1592         if ((prev_i % recv->block_irq_interval) == 0) {
1593                 prev->control |= cpu_to_le32(3 << 20); /* enable interrupt */
1594         } else {
1595                 prev->control &= cpu_to_le32(~(3<<20)); /* disable interrupt */
1596         }
1597         wmb();
1598
1599         /* wake up DMA in case it fell asleep */
1600         reg_write(recv->ohci, recv->ContextControlSet, (1 << 12));
1601 }
1602
1603 static void ohci_iso_recv_bufferfill_release(struct ohci_iso_recv *recv,
1604                                              struct hpsb_iso_packet_info *info)
1605 {
1606         /* release the memory where the packet was */
1607         recv->released_bytes += info->total_len;
1608
1609         /* have we released enough memory for one block? */
1610         while (recv->released_bytes > recv->buf_stride) {
1611                 ohci_iso_recv_release_block(recv, recv->block_reader);
1612                 recv->block_reader = (recv->block_reader + 1) % recv->nblocks;
1613                 recv->released_bytes -= recv->buf_stride;
1614         }
1615 }
1616
1617 static inline void ohci_iso_recv_release(struct hpsb_iso *iso, struct hpsb_iso_packet_info *info)
1618 {
1619         struct ohci_iso_recv *recv = iso->hostdata;
1620         if (recv->dma_mode == BUFFER_FILL_MODE) {
1621                 ohci_iso_recv_bufferfill_release(recv, info);
1622         } else {
1623                 ohci_iso_recv_release_block(recv, info - iso->infos);
1624         }
1625 }
1626
1627 /* parse all packets from blocks that have been fully received */
1628 static void ohci_iso_recv_bufferfill_parse(struct hpsb_iso *iso, struct ohci_iso_recv *recv)
1629 {
1630         int wake = 0;
1631         int runaway = 0;
1632         struct ti_ohci *ohci = recv->ohci;
1633
1634         while (1) {
1635                 /* we expect the next parsable packet to begin at recv->dma_offset */
1636                 /* note: packet layout is as shown in section 10.6.1.1 of the OHCI spec */
1637
1638                 unsigned int offset;
1639                 unsigned short len, cycle, total_len;
1640                 unsigned char channel, tag, sy;
1641
1642                 unsigned char *p = iso->data_buf.kvirt;
1643
1644                 unsigned int this_block = recv->dma_offset/recv->buf_stride;
1645
1646                 /* don't loop indefinitely */
1647                 if (runaway++ > 100000) {
1648                         atomic_inc(&iso->overflows);
1649                         PRINT(KERN_ERR,
1650                               "IR DMA error - Runaway during buffer parsing!\n");
1651                         break;
1652                 }
1653
1654                 /* stop parsing once we arrive at block_dma (i.e. don't get ahead of DMA) */
1655                 if (this_block == recv->block_dma)
1656                         break;
1657
1658                 wake = 1;
1659
1660                 /* parse data length, tag, channel, and sy */
1661
1662                 /* note: we keep our own local copies of 'len' and 'offset'
1663                    so the user can't mess with them by poking in the mmap area */
1664
1665                 len = p[recv->dma_offset+2] | (p[recv->dma_offset+3] << 8);
1666
1667                 if (len > 4096) {
1668                         PRINT(KERN_ERR,
1669                               "IR DMA error - bogus 'len' value %u\n", len);
1670                 }
1671
1672                 channel = p[recv->dma_offset+1] & 0x3F;
1673                 tag = p[recv->dma_offset+1] >> 6;
1674                 sy = p[recv->dma_offset+0] & 0xF;
1675
1676                 /* advance to data payload */
1677                 recv->dma_offset += 4;
1678
1679                 /* check for wrap-around */
1680                 if (recv->dma_offset >= recv->buf_stride*recv->nblocks) {
1681                         recv->dma_offset -= recv->buf_stride*recv->nblocks;
1682                 }
1683
1684                 /* dma_offset now points to the first byte of the data payload */
1685                 offset = recv->dma_offset;
1686
1687                 /* advance to xferStatus/timeStamp */
1688                 recv->dma_offset += len;
1689
1690                 total_len = len + 8; /* 8 bytes header+trailer in OHCI packet */
1691                 /* payload is padded to 4 bytes */
1692                 if (len % 4) {
1693                         recv->dma_offset += 4 - (len%4);
1694                         total_len += 4 - (len%4);
1695                 }
1696
1697                 /* check for wrap-around */
1698                 if (recv->dma_offset >= recv->buf_stride*recv->nblocks) {
1699                         /* uh oh, the packet data wraps from the last
1700                            to the first DMA block - make the packet
1701                            contiguous by copying its "tail" into the
1702                            guard page */
1703
1704                         int guard_off = recv->buf_stride*recv->nblocks;
1705                         int tail_len = len - (guard_off - offset);
1706
1707                         if (tail_len > 0  && tail_len < recv->buf_stride) {
1708                                 memcpy(iso->data_buf.kvirt + guard_off,
1709                                        iso->data_buf.kvirt,
1710                                        tail_len);
1711                         }
1712
1713                         recv->dma_offset -= recv->buf_stride*recv->nblocks;
1714                 }
1715
1716                 /* parse timestamp */
1717                 cycle = p[recv->dma_offset+0] | (p[recv->dma_offset+1]<<8);
1718                 cycle &= 0x1FFF;
1719
1720                 /* advance to next packet */
1721                 recv->dma_offset += 4;
1722
1723                 /* check for wrap-around */
1724                 if (recv->dma_offset >= recv->buf_stride*recv->nblocks) {
1725                         recv->dma_offset -= recv->buf_stride*recv->nblocks;
1726                 }
1727
1728                 hpsb_iso_packet_received(iso, offset, len, total_len, cycle, channel, tag, sy);
1729         }
1730
1731         if (wake)
1732                 hpsb_iso_wake(iso);
1733 }
1734
1735 static void ohci_iso_recv_bufferfill_task(struct hpsb_iso *iso, struct ohci_iso_recv *recv)
1736 {
1737         int loop;
1738         struct ti_ohci *ohci = recv->ohci;
1739
1740         /* loop over all blocks */
1741         for (loop = 0; loop < recv->nblocks; loop++) {
1742
1743                 /* check block_dma to see if it's done */
1744                 struct dma_cmd *im = &recv->block[recv->block_dma];
1745
1746                 /* check the DMA descriptor for new writes to xferStatus */
1747                 u16 xferstatus = le32_to_cpu(im->status) >> 16;
1748
1749                 /* rescount is the number of bytes *remaining to be written* in the block */
1750                 u16 rescount = le32_to_cpu(im->status) & 0xFFFF;
1751
1752                 unsigned char event = xferstatus & 0x1F;
1753
1754                 if (!event) {
1755                         /* nothing has happened to this block yet */
1756                         break;
1757                 }
1758
1759                 if (event != 0x11) {
1760                         atomic_inc(&iso->overflows);
1761                         PRINT(KERN_ERR,
1762                               "IR DMA error - OHCI error code 0x%02x\n", event);
1763                 }
1764
1765                 if (rescount != 0) {
1766                         /* the card is still writing to this block;
1767                            we can't touch it until it's done */
1768                         break;
1769                 }
1770
1771                 /* OK, the block is finished... */
1772
1773                 /* sync our view of the block */
1774                 dma_region_sync_for_cpu(&iso->data_buf, recv->block_dma*recv->buf_stride, recv->buf_stride);
1775
1776                 /* reset the DMA descriptor */
1777                 im->status = recv->buf_stride;
1778
1779                 /* advance block_dma */
1780                 recv->block_dma = (recv->block_dma + 1) % recv->nblocks;
1781
1782                 if ((recv->block_dma+1) % recv->nblocks == recv->block_reader) {
1783                         atomic_inc(&iso->overflows);
1784                         DBGMSG("ISO reception overflow - "
1785                                "ran out of DMA blocks");
1786                 }
1787         }
1788
1789         /* parse any packets that have arrived */
1790         ohci_iso_recv_bufferfill_parse(iso, recv);
1791 }
1792
1793 static void ohci_iso_recv_packetperbuf_task(struct hpsb_iso *iso, struct ohci_iso_recv *recv)
1794 {
1795         int count;
1796         int wake = 0;
1797         struct ti_ohci *ohci = recv->ohci;
1798
1799         /* loop over the entire buffer */
1800         for (count = 0; count < recv->nblocks; count++) {
1801                 u32 packet_len = 0;
1802
1803                 /* pointer to the DMA descriptor */
1804                 struct dma_cmd *il = ((struct dma_cmd*) recv->prog.kvirt) + iso->pkt_dma;
1805
1806                 /* check the DMA descriptor for new writes to xferStatus */
1807                 u16 xferstatus = le32_to_cpu(il->status) >> 16;
1808                 u16 rescount = le32_to_cpu(il->status) & 0xFFFF;
1809
1810                 unsigned char event = xferstatus & 0x1F;
1811
1812                 if (!event) {
1813                         /* this packet hasn't come in yet; we are done for now */
1814                         goto out;
1815                 }
1816
1817                 if (event == 0x11) {
1818                         /* packet received successfully! */
1819
1820                         /* rescount is the number of bytes *remaining* in the packet buffer,
1821                            after the packet was written */
1822                         packet_len = recv->buf_stride - rescount;
1823
1824                 } else if (event == 0x02) {
1825                         PRINT(KERN_ERR, "IR DMA error - packet too long for buffer\n");
1826                 } else if (event) {
1827                         PRINT(KERN_ERR, "IR DMA error - OHCI error code 0x%02x\n", event);
1828                 }
1829
1830                 /* sync our view of the buffer */
1831                 dma_region_sync_for_cpu(&iso->data_buf, iso->pkt_dma * recv->buf_stride, recv->buf_stride);
1832
1833                 /* record the per-packet info */
1834                 {
1835                         /* iso header is 8 bytes ahead of the data payload */
1836                         unsigned char *hdr;
1837
1838                         unsigned int offset;
1839                         unsigned short cycle;
1840                         unsigned char channel, tag, sy;
1841
1842                         offset = iso->pkt_dma * recv->buf_stride;
1843                         hdr = iso->data_buf.kvirt + offset;
1844
1845                         /* skip iso header */
1846                         offset += 8;
1847                         packet_len -= 8;
1848
1849                         cycle = (hdr[0] | (hdr[1] << 8)) & 0x1FFF;
1850                         channel = hdr[5] & 0x3F;
1851                         tag = hdr[5] >> 6;
1852                         sy = hdr[4] & 0xF;
1853
1854                         hpsb_iso_packet_received(iso, offset, packet_len,
1855                                         recv->buf_stride, cycle, channel, tag, sy);
1856                 }
1857
1858                 /* reset the DMA descriptor */
1859                 il->status = recv->buf_stride;
1860
1861                 wake = 1;
1862                 recv->block_dma = iso->pkt_dma;
1863         }
1864
1865 out:
1866         if (wake)
1867                 hpsb_iso_wake(iso);
1868 }
1869
1870 static void ohci_iso_recv_task(unsigned long data)
1871 {
1872         struct hpsb_iso *iso = (struct hpsb_iso*) data;
1873         struct ohci_iso_recv *recv = iso->hostdata;
1874
1875         if (recv->dma_mode == BUFFER_FILL_MODE)
1876                 ohci_iso_recv_bufferfill_task(iso, recv);
1877         else
1878                 ohci_iso_recv_packetperbuf_task(iso, recv);
1879 }
1880
1881 /***********************************
1882  * rawiso ISO transmission         *
1883  ***********************************/
1884
1885 struct ohci_iso_xmit {
1886         struct ti_ohci *ohci;
1887         struct dma_prog_region prog;
1888         struct ohci1394_iso_tasklet task;
1889         int task_active;
1890
1891         u32 ContextControlSet;
1892         u32 ContextControlClear;
1893         u32 CommandPtr;
1894 };
1895
1896 /* transmission DMA program:
1897    one OUTPUT_MORE_IMMEDIATE for the IT header
1898    one OUTPUT_LAST for the buffer data */
1899
1900 struct iso_xmit_cmd {
1901         struct dma_cmd output_more_immediate;
1902         u8 iso_hdr[8];
1903         u32 unused[2];
1904         struct dma_cmd output_last;
1905 };
1906
1907 static int ohci_iso_xmit_init(struct hpsb_iso *iso);
1908 static int ohci_iso_xmit_start(struct hpsb_iso *iso, int cycle);
1909 static void ohci_iso_xmit_shutdown(struct hpsb_iso *iso);
1910 static void ohci_iso_xmit_task(unsigned long data);
1911
1912 static int ohci_iso_xmit_init(struct hpsb_iso *iso)
1913 {
1914         struct ohci_iso_xmit *xmit;
1915         unsigned int prog_size;
1916         int ctx;
1917         int ret = -ENOMEM;
1918
1919         xmit = kmalloc(sizeof(*xmit), GFP_KERNEL);
1920         if (!xmit)
1921                 return -ENOMEM;
1922
1923         iso->hostdata = xmit;
1924         xmit->ohci = iso->host->hostdata;
1925         xmit->task_active = 0;
1926
1927         dma_prog_region_init(&xmit->prog);
1928
1929         prog_size = sizeof(struct iso_xmit_cmd) * iso->buf_packets;
1930
1931         if (dma_prog_region_alloc(&xmit->prog, prog_size, xmit->ohci->dev))
1932                 goto err;
1933
1934         ohci1394_init_iso_tasklet(&xmit->task, OHCI_ISO_TRANSMIT,
1935                                   ohci_iso_xmit_task, (unsigned long) iso);
1936
1937         if (ohci1394_register_iso_tasklet(xmit->ohci, &xmit->task) < 0) {
1938                 ret = -EBUSY;
1939                 goto err;
1940         }
1941
1942         xmit->task_active = 1;
1943
1944         /* xmit context registers are spaced 16 bytes apart */
1945         ctx = xmit->task.context;
1946         xmit->ContextControlSet = OHCI1394_IsoXmitContextControlSet + 16 * ctx;
1947         xmit->ContextControlClear = OHCI1394_IsoXmitContextControlClear + 16 * ctx;
1948         xmit->CommandPtr = OHCI1394_IsoXmitCommandPtr + 16 * ctx;
1949
1950         return 0;
1951
1952 err:
1953         ohci_iso_xmit_shutdown(iso);
1954         return ret;
1955 }
1956
1957 static void ohci_iso_xmit_stop(struct hpsb_iso *iso)
1958 {
1959         struct ohci_iso_xmit *xmit = iso->hostdata;
1960         struct ti_ohci *ohci = xmit->ohci;
1961
1962         /* disable interrupts */
1963         reg_write(xmit->ohci, OHCI1394_IsoXmitIntMaskClear, 1 << xmit->task.context);
1964
1965         /* halt DMA */
1966         if (ohci1394_stop_context(xmit->ohci, xmit->ContextControlClear, NULL)) {
1967                 /* XXX the DMA context will lock up if you try to send too much data! */
1968                 PRINT(KERN_ERR,
1969                       "you probably exceeded the OHCI card's bandwidth limit - "
1970                       "reload the module and reduce xmit bandwidth");
1971         }
1972 }
1973
1974 static void ohci_iso_xmit_shutdown(struct hpsb_iso *iso)
1975 {
1976         struct ohci_iso_xmit *xmit = iso->hostdata;
1977
1978         if (xmit->task_active) {
1979                 ohci_iso_xmit_stop(iso);
1980                 ohci1394_unregister_iso_tasklet(xmit->ohci, &xmit->task);
1981                 xmit->task_active = 0;
1982         }
1983
1984         dma_prog_region_free(&xmit->prog);
1985         kfree(xmit);
1986         iso->hostdata = NULL;
1987 }
1988
1989 static void ohci_iso_xmit_task(unsigned long data)
1990 {
1991         struct hpsb_iso *iso = (struct hpsb_iso*) data;
1992         struct ohci_iso_xmit *xmit = iso->hostdata;
1993         struct ti_ohci *ohci = xmit->ohci;
1994         int wake = 0;
1995         int count;
1996
1997         /* check the whole buffer if necessary, starting at pkt_dma */
1998         for (count = 0; count < iso->buf_packets; count++) {
1999                 int cycle;
2000
2001                 /* DMA descriptor */
2002                 struct iso_xmit_cmd *cmd = dma_region_i(&xmit->prog, struct iso_xmit_cmd, iso->pkt_dma);
2003
2004                 /* check for new writes to xferStatus */
2005                 u16 xferstatus = le32_to_cpu(cmd->output_last.status) >> 16;
2006                 u8  event = xferstatus & 0x1F;
2007
2008                 if (!event) {
2009                         /* packet hasn't been sent yet; we are done for now */
2010                         break;
2011                 }
2012
2013                 if (event != 0x11)
2014                         PRINT(KERN_ERR,
2015                               "IT DMA error - OHCI error code 0x%02x\n", event);
2016
2017                 /* at least one packet went out, so wake up the writer */
2018                 wake = 1;
2019
2020                 /* parse cycle */
2021                 cycle = le32_to_cpu(cmd->output_last.status) & 0x1FFF;
2022
2023                 /* tell the subsystem the packet has gone out */
2024                 hpsb_iso_packet_sent(iso, cycle, event != 0x11);
2025
2026                 /* reset the DMA descriptor for next time */
2027                 cmd->output_last.status = 0;
2028         }
2029
2030         if (wake)
2031                 hpsb_iso_wake(iso);
2032 }
2033
2034 static int ohci_iso_xmit_queue(struct hpsb_iso *iso, struct hpsb_iso_packet_info *info)
2035 {
2036         struct ohci_iso_xmit *xmit = iso->hostdata;
2037         struct ti_ohci *ohci = xmit->ohci;
2038
2039         int next_i, prev_i;
2040         struct iso_xmit_cmd *next, *prev;
2041
2042         unsigned int offset;
2043         unsigned short len;
2044         unsigned char tag, sy;
2045
2046         /* check that the packet doesn't cross a page boundary
2047            (we could allow this if we added OUTPUT_MORE descriptor support) */
2048         if (cross_bound(info->offset, info->len)) {
2049                 PRINT(KERN_ERR,
2050                       "rawiso xmit: packet %u crosses a page boundary",
2051                       iso->first_packet);
2052                 return -EINVAL;
2053         }
2054
2055         offset = info->offset;
2056         len = info->len;
2057         tag = info->tag;
2058         sy = info->sy;
2059
2060         /* sync up the card's view of the buffer */
2061         dma_region_sync_for_device(&iso->data_buf, offset, len);
2062
2063         /* append first_packet to the DMA chain */
2064         /* by linking the previous descriptor to it */
2065         /* (next will become the new end of the DMA chain) */
2066
2067         next_i = iso->first_packet;
2068         prev_i = (next_i == 0) ? (iso->buf_packets - 1) : (next_i - 1);
2069
2070         next = dma_region_i(&xmit->prog, struct iso_xmit_cmd, next_i);
2071         prev = dma_region_i(&xmit->prog, struct iso_xmit_cmd, prev_i);
2072
2073         /* set up the OUTPUT_MORE_IMMEDIATE descriptor */
2074         memset(next, 0, sizeof(struct iso_xmit_cmd));
2075         next->output_more_immediate.control = cpu_to_le32(0x02000008);
2076
2077         /* ISO packet header is embedded in the OUTPUT_MORE_IMMEDIATE */
2078
2079         /* tcode = 0xA, and sy */
2080         next->iso_hdr[0] = 0xA0 | (sy & 0xF);
2081
2082         /* tag and channel number */
2083         next->iso_hdr[1] = (tag << 6) | (iso->channel & 0x3F);
2084
2085         /* transmission speed */
2086         next->iso_hdr[2] = iso->speed & 0x7;
2087
2088         /* payload size */
2089         next->iso_hdr[6] = len & 0xFF;
2090         next->iso_hdr[7] = len >> 8;
2091
2092         /* set up the OUTPUT_LAST */
2093         next->output_last.control = cpu_to_le32(1 << 28);
2094         next->output_last.control |= cpu_to_le32(1 << 27); /* update timeStamp */
2095         next->output_last.control |= cpu_to_le32(3 << 20); /* want interrupt */
2096         next->output_last.control |= cpu_to_le32(3 << 18); /* enable branch */
2097         next->output_last.control |= cpu_to_le32(len);
2098
2099         /* payload bus address */
2100         next->output_last.address = cpu_to_le32(dma_region_offset_to_bus(&iso->data_buf, offset));
2101
2102         /* leave branchAddress at zero for now */
2103
2104         /* re-write the previous DMA descriptor to chain to this one */
2105
2106         /* set prev branch address to point to next (Z=3) */
2107         prev->output_last.branchAddress = cpu_to_le32(
2108                 dma_prog_region_offset_to_bus(&xmit->prog, sizeof(struct iso_xmit_cmd) * next_i) | 3);
2109
2110         /* disable interrupt, unless required by the IRQ interval */
2111         if (prev_i % iso->irq_interval) {
2112                 prev->output_last.control &= cpu_to_le32(~(3 << 20)); /* no interrupt */
2113         } else {
2114                 prev->output_last.control |= cpu_to_le32(3 << 20); /* enable interrupt */
2115         }
2116
2117         wmb();
2118
2119         /* wake DMA in case it is sleeping */
2120         reg_write(xmit->ohci, xmit->ContextControlSet, 1 << 12);
2121
2122         /* issue a dummy read of the cycle timer to force all PCI
2123            writes to be posted immediately */
2124         mb();
2125         reg_read(xmit->ohci, OHCI1394_IsochronousCycleTimer);
2126
2127         return 0;
2128 }
2129
2130 static int ohci_iso_xmit_start(struct hpsb_iso *iso, int cycle)
2131 {
2132         struct ohci_iso_xmit *xmit = iso->hostdata;
2133         struct ti_ohci *ohci = xmit->ohci;
2134
2135         /* clear out the control register */
2136         reg_write(xmit->ohci, xmit->ContextControlClear, 0xFFFFFFFF);
2137         wmb();
2138
2139         /* address and length of first descriptor block (Z=3) */
2140         reg_write(xmit->ohci, xmit->CommandPtr,
2141                   dma_prog_region_offset_to_bus(&xmit->prog, iso->pkt_dma * sizeof(struct iso_xmit_cmd)) | 3);
2142
2143         /* cycle match */
2144         if (cycle != -1) {
2145                 u32 start = cycle & 0x1FFF;
2146
2147                 /* 'cycle' is only mod 8000, but we also need two 'seconds' bits -
2148                    just snarf them from the current time */
2149                 u32 seconds = reg_read(xmit->ohci, OHCI1394_IsochronousCycleTimer) >> 25;
2150
2151                 /* advance one second to give some extra time for DMA to start */
2152                 seconds += 1;
2153
2154                 start |= (seconds & 3) << 13;
2155
2156                 reg_write(xmit->ohci, xmit->ContextControlSet, 0x80000000 | (start << 16));
2157         }
2158
2159         /* enable interrupts */
2160         reg_write(xmit->ohci, OHCI1394_IsoXmitIntMaskSet, 1 << xmit->task.context);
2161
2162         /* run */
2163         reg_write(xmit->ohci, xmit->ContextControlSet, 0x8000);
2164         mb();
2165
2166         /* wait 100 usec to give the card time to go active */
2167         udelay(100);
2168
2169         /* check the RUN bit */
2170         if (!(reg_read(xmit->ohci, xmit->ContextControlSet) & 0x8000)) {
2171                 PRINT(KERN_ERR, "Error starting IT DMA (ContextControl 0x%08x)\n",
2172                       reg_read(xmit->ohci, xmit->ContextControlSet));
2173                 return -1;
2174         }
2175
2176         return 0;
2177 }
2178
2179 static int ohci_isoctl(struct hpsb_iso *iso, enum isoctl_cmd cmd, unsigned long arg)
2180 {
2181
2182         switch(cmd) {
2183         case XMIT_INIT:
2184                 return ohci_iso_xmit_init(iso);
2185         case XMIT_START:
2186                 return ohci_iso_xmit_start(iso, arg);
2187         case XMIT_STOP:
2188                 ohci_iso_xmit_stop(iso);
2189                 return 0;
2190         case XMIT_QUEUE:
2191                 return ohci_iso_xmit_queue(iso, (struct hpsb_iso_packet_info*) arg);
2192         case XMIT_SHUTDOWN:
2193                 ohci_iso_xmit_shutdown(iso);
2194                 return 0;
2195
2196         case RECV_INIT:
2197                 return ohci_iso_recv_init(iso);
2198         case RECV_START: {
2199                 int *args = (int*) arg;
2200                 return ohci_iso_recv_start(iso, args[0], args[1], args[2]);
2201         }
2202         case RECV_STOP:
2203                 ohci_iso_recv_stop(iso);
2204                 return 0;
2205         case RECV_RELEASE:
2206                 ohci_iso_recv_release(iso, (struct hpsb_iso_packet_info*) arg);
2207                 return 0;
2208         case RECV_FLUSH:
2209                 ohci_iso_recv_task((unsigned long) iso);
2210                 return 0;
2211         case RECV_SHUTDOWN:
2212                 ohci_iso_recv_shutdown(iso);
2213                 return 0;
2214         case RECV_LISTEN_CHANNEL:
2215                 ohci_iso_recv_change_channel(iso, arg, 1);
2216                 return 0;
2217         case RECV_UNLISTEN_CHANNEL:
2218                 ohci_iso_recv_change_channel(iso, arg, 0);
2219                 return 0;
2220         case RECV_SET_CHANNEL_MASK:
2221                 ohci_iso_recv_set_channel_mask(iso, *((u64*) arg));
2222                 return 0;
2223
2224         default:
2225                 PRINT_G(KERN_ERR, "ohci_isoctl cmd %d not implemented yet",
2226                         cmd);
2227                 break;
2228         }
2229         return -EINVAL;
2230 }
2231
2232 /***************************************
2233  * IEEE-1394 functionality section END *
2234  ***************************************/
2235
2236
2237 /********************************************************
2238  * Global stuff (interrupt handler, init/shutdown code) *
2239  ********************************************************/
2240
2241 static void dma_trm_reset(struct dma_trm_ctx *d)
2242 {
2243         unsigned long flags;
2244         LIST_HEAD(packet_list);
2245         struct ti_ohci *ohci = d->ohci;
2246         struct hpsb_packet *packet, *ptmp;
2247
2248         ohci1394_stop_context(ohci, d->ctrlClear, NULL);
2249
2250         /* Lock the context, reset it and release it. Move the packets
2251          * that were pending in the context to packet_list and free
2252          * them after releasing the lock. */
2253
2254         spin_lock_irqsave(&d->lock, flags);
2255
2256         list_splice(&d->fifo_list, &packet_list);
2257         list_splice(&d->pending_list, &packet_list);
2258         INIT_LIST_HEAD(&d->fifo_list);
2259         INIT_LIST_HEAD(&d->pending_list);
2260
2261         d->branchAddrPtr = NULL;
2262         d->sent_ind = d->prg_ind;
2263         d->free_prgs = d->num_desc;
2264
2265         spin_unlock_irqrestore(&d->lock, flags);
2266
2267         if (list_empty(&packet_list))
2268                 return;
2269
2270         PRINT(KERN_INFO, "AT dma reset ctx=%d, aborting transmission", d->ctx);
2271
2272         /* Now process subsystem callbacks for the packets from this
2273          * context. */
2274         list_for_each_entry_safe(packet, ptmp, &packet_list, driver_list) {
2275                 list_del_init(&packet->driver_list);
2276                 hpsb_packet_sent(ohci->host, packet, ACKX_ABORTED);
2277         }
2278 }
2279
2280 static void ohci_schedule_iso_tasklets(struct ti_ohci *ohci,
2281                                        quadlet_t rx_event,
2282                                        quadlet_t tx_event)
2283 {
2284         struct ohci1394_iso_tasklet *t;
2285         unsigned long mask;
2286         unsigned long flags;
2287
2288         spin_lock_irqsave(&ohci->iso_tasklet_list_lock, flags);
2289
2290         list_for_each_entry(t, &ohci->iso_tasklet_list, link) {
2291                 mask = 1 << t->context;
2292
2293                 if (t->type == OHCI_ISO_TRANSMIT && tx_event & mask)
2294                         tasklet_schedule(&t->tasklet);
2295                 else if (rx_event & mask)
2296                         tasklet_schedule(&t->tasklet);
2297         }
2298
2299         spin_unlock_irqrestore(&ohci->iso_tasklet_list_lock, flags);
2300 }
2301
2302 static irqreturn_t ohci_irq_handler(int irq, void *dev_id)
2303 {
2304         quadlet_t event, node_id;
2305         struct ti_ohci *ohci = (struct ti_ohci *)dev_id;
2306         struct hpsb_host *host = ohci->host;
2307         int phyid = -1, isroot = 0;
2308         unsigned long flags;
2309
2310         /* Read and clear the interrupt event register.  Don't clear
2311          * the busReset event, though. This is done when we get the
2312          * selfIDComplete interrupt. */
2313         spin_lock_irqsave(&ohci->event_lock, flags);
2314         event = reg_read(ohci, OHCI1394_IntEventClear);
2315         reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
2316         spin_unlock_irqrestore(&ohci->event_lock, flags);
2317
2318         if (!event)
2319                 return IRQ_NONE;
2320
2321         /* If event is ~(u32)0 cardbus card was ejected.  In this case
2322          * we just return, and clean up in the ohci1394_pci_remove
2323          * function. */
2324         if (event == ~(u32) 0) {
2325                 DBGMSG("Device removed.");
2326                 return IRQ_NONE;
2327         }
2328
2329         DBGMSG("IntEvent: %08x", event);
2330
2331         if (event & OHCI1394_unrecoverableError) {
2332                 int ctx;
2333                 PRINT(KERN_ERR, "Unrecoverable error!");
2334
2335                 if (reg_read(ohci, OHCI1394_AsReqTrContextControlSet) & 0x800)
2336                         PRINT(KERN_ERR, "Async Req Tx Context died: "
2337                                 "ctrl[%08x] cmdptr[%08x]",
2338                                 reg_read(ohci, OHCI1394_AsReqTrContextControlSet),
2339                                 reg_read(ohci, OHCI1394_AsReqTrCommandPtr));
2340
2341                 if (reg_read(ohci, OHCI1394_AsRspTrContextControlSet) & 0x800)
2342                         PRINT(KERN_ERR, "Async Rsp Tx Context died: "
2343                                 "ctrl[%08x] cmdptr[%08x]",
2344                                 reg_read(ohci, OHCI1394_AsRspTrContextControlSet),
2345                                 reg_read(ohci, OHCI1394_AsRspTrCommandPtr));
2346
2347                 if (reg_read(ohci, OHCI1394_AsReqRcvContextControlSet) & 0x800)
2348                         PRINT(KERN_ERR, "Async Req Rcv Context died: "
2349                                 "ctrl[%08x] cmdptr[%08x]",
2350                                 reg_read(ohci, OHCI1394_AsReqRcvContextControlSet),
2351                                 reg_read(ohci, OHCI1394_AsReqRcvCommandPtr));
2352
2353                 if (reg_read(ohci, OHCI1394_AsRspRcvContextControlSet) & 0x800)
2354                         PRINT(KERN_ERR, "Async Rsp Rcv Context died: "
2355                                 "ctrl[%08x] cmdptr[%08x]",
2356                                 reg_read(ohci, OHCI1394_AsRspRcvContextControlSet),
2357                                 reg_read(ohci, OHCI1394_AsRspRcvCommandPtr));
2358
2359                 for (ctx = 0; ctx < ohci->nb_iso_xmit_ctx; ctx++) {
2360                         if (reg_read(ohci, OHCI1394_IsoXmitContextControlSet + (16 * ctx)) & 0x800)
2361                                 PRINT(KERN_ERR, "Iso Xmit %d Context died: "
2362                                         "ctrl[%08x] cmdptr[%08x]", ctx,
2363                                         reg_read(ohci, OHCI1394_IsoXmitContextControlSet + (16 * ctx)),
2364                                         reg_read(ohci, OHCI1394_IsoXmitCommandPtr + (16 * ctx)));
2365                 }
2366
2367                 for (ctx = 0; ctx < ohci->nb_iso_rcv_ctx; ctx++) {
2368                         if (reg_read(ohci, OHCI1394_IsoRcvContextControlSet + (32 * ctx)) & 0x800)
2369                                 PRINT(KERN_ERR, "Iso Recv %d Context died: "
2370                                         "ctrl[%08x] cmdptr[%08x] match[%08x]", ctx,
2371                                         reg_read(ohci, OHCI1394_IsoRcvContextControlSet + (32 * ctx)),
2372                                         reg_read(ohci, OHCI1394_IsoRcvCommandPtr + (32 * ctx)),
2373                                         reg_read(ohci, OHCI1394_IsoRcvContextMatch + (32 * ctx)));
2374                 }
2375
2376                 event &= ~OHCI1394_unrecoverableError;
2377         }
2378         if (event & OHCI1394_postedWriteErr) {
2379                 PRINT(KERN_ERR, "physical posted write error");
2380                 /* no recovery strategy yet, had to involve protocol drivers */
2381         }
2382         if (event & OHCI1394_cycleTooLong) {
2383                 if(printk_ratelimit())
2384                         PRINT(KERN_WARNING, "isochronous cycle too long");
2385                 else
2386                         DBGMSG("OHCI1394_cycleTooLong");
2387                 reg_write(ohci, OHCI1394_LinkControlSet,
2388                           OHCI1394_LinkControl_CycleMaster);
2389                 event &= ~OHCI1394_cycleTooLong;
2390         }
2391         if (event & OHCI1394_cycleInconsistent) {
2392                 /* We subscribe to the cycleInconsistent event only to
2393                  * clear the corresponding event bit... otherwise,
2394                  * isochronous cycleMatch DMA won't work. */
2395                 DBGMSG("OHCI1394_cycleInconsistent");
2396                 event &= ~OHCI1394_cycleInconsistent;
2397         }
2398         if (event & OHCI1394_busReset) {
2399                 /* The busReset event bit can't be cleared during the
2400                  * selfID phase, so we disable busReset interrupts, to
2401                  * avoid burying the cpu in interrupt requests. */
2402                 spin_lock_irqsave(&ohci->event_lock, flags);
2403                 reg_write(ohci, OHCI1394_IntMaskClear, OHCI1394_busReset);
2404
2405                 if (ohci->check_busreset) {
2406                         int loop_count = 0;
2407
2408                         udelay(10);
2409
2410                         while (reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
2411                                 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
2412
2413                                 spin_unlock_irqrestore(&ohci->event_lock, flags);
2414                                 udelay(10);
2415                                 spin_lock_irqsave(&ohci->event_lock, flags);
2416
2417                                 /* The loop counter check is to prevent the driver
2418                                  * from remaining in this state forever. For the
2419                                  * initial bus reset, the loop continues for ever
2420                                  * and the system hangs, until some device is plugged-in
2421                                  * or out manually into a port! The forced reset seems
2422                                  * to solve this problem. This mainly effects nForce2. */
2423                                 if (loop_count > 10000) {
2424                                         ohci_devctl(host, RESET_BUS, LONG_RESET);
2425                                         DBGMSG("Detected bus-reset loop. Forced a bus reset!");
2426                                         loop_count = 0;
2427                                 }
2428
2429                                 loop_count++;
2430                         }
2431                 }
2432                 spin_unlock_irqrestore(&ohci->event_lock, flags);
2433                 if (!host->in_bus_reset) {
2434                         DBGMSG("irq_handler: Bus reset requested");
2435
2436                         /* Subsystem call */
2437                         hpsb_bus_reset(ohci->host);
2438                 }
2439                 event &= ~OHCI1394_busReset;
2440         }
2441         if (event & OHCI1394_reqTxComplete) {
2442                 struct dma_trm_ctx *d = &ohci->at_req_context;
2443                 DBGMSG("Got reqTxComplete interrupt "
2444                        "status=0x%08X", reg_read(ohci, d->ctrlSet));
2445                 if (reg_read(ohci, d->ctrlSet) & 0x800)
2446                         ohci1394_stop_context(ohci, d->ctrlClear,
2447                                               "reqTxComplete");
2448                 else
2449                         dma_trm_tasklet((unsigned long)d);
2450                         //tasklet_schedule(&d->task);
2451                 event &= ~OHCI1394_reqTxComplete;
2452         }
2453         if (event & OHCI1394_respTxComplete) {
2454                 struct dma_trm_ctx *d = &ohci->at_resp_context;
2455                 DBGMSG("Got respTxComplete interrupt "
2456                        "status=0x%08X", reg_read(ohci, d->ctrlSet));
2457                 if (reg_read(ohci, d->ctrlSet) & 0x800)
2458                         ohci1394_stop_context(ohci, d->ctrlClear,
2459                                               "respTxComplete");
2460                 else
2461                         tasklet_schedule(&d->task);
2462                 event &= ~OHCI1394_respTxComplete;
2463         }
2464         if (event & OHCI1394_RQPkt) {
2465                 struct dma_rcv_ctx *d = &ohci->ar_req_context;
2466                 DBGMSG("Got RQPkt interrupt status=0x%08X",
2467                        reg_read(ohci, d->ctrlSet));
2468                 if (reg_read(ohci, d->ctrlSet) & 0x800)
2469                         ohci1394_stop_context(ohci, d->ctrlClear, "RQPkt");
2470                 else
2471                         tasklet_schedule(&d->task);
2472                 event &= ~OHCI1394_RQPkt;
2473         }
2474         if (event & OHCI1394_RSPkt) {
2475                 struct dma_rcv_ctx *d = &ohci->ar_resp_context;
2476                 DBGMSG("Got RSPkt interrupt status=0x%08X",
2477                        reg_read(ohci, d->ctrlSet));
2478                 if (reg_read(ohci, d->ctrlSet) & 0x800)
2479                         ohci1394_stop_context(ohci, d->ctrlClear, "RSPkt");
2480                 else
2481                         tasklet_schedule(&d->task);
2482                 event &= ~OHCI1394_RSPkt;
2483         }
2484         if (event & OHCI1394_isochRx) {
2485                 quadlet_t rx_event;
2486
2487                 rx_event = reg_read(ohci, OHCI1394_IsoRecvIntEventSet);
2488                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, rx_event);
2489                 ohci_schedule_iso_tasklets(ohci, rx_event, 0);
2490                 event &= ~OHCI1394_isochRx;
2491         }
2492         if (event & OHCI1394_isochTx) {
2493                 quadlet_t tx_event;
2494
2495                 tx_event = reg_read(ohci, OHCI1394_IsoXmitIntEventSet);
2496                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, tx_event);
2497                 ohci_schedule_iso_tasklets(ohci, 0, tx_event);
2498                 event &= ~OHCI1394_isochTx;
2499         }
2500         if (event & OHCI1394_selfIDComplete) {
2501                 if (host->in_bus_reset) {
2502                         node_id = reg_read(ohci, OHCI1394_NodeID);
2503
2504                         if (!(node_id & 0x80000000)) {
2505                                 PRINT(KERN_ERR,
2506                                       "SelfID received, but NodeID invalid "
2507                                       "(probably new bus reset occurred): %08X",
2508                                       node_id);
2509                                 goto selfid_not_valid;
2510                         }
2511
2512                         phyid =  node_id & 0x0000003f;
2513                         isroot = (node_id & 0x40000000) != 0;
2514
2515                         DBGMSG("SelfID interrupt received "
2516                               "(phyid %d, %s)", phyid,
2517                               (isroot ? "root" : "not root"));
2518
2519                         handle_selfid(ohci, host, phyid, isroot);
2520
2521                         /* Clear the bus reset event and re-enable the
2522                          * busReset interrupt.  */
2523                         spin_lock_irqsave(&ohci->event_lock, flags);
2524                         reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
2525                         reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset);
2526                         spin_unlock_irqrestore(&ohci->event_lock, flags);
2527
2528                         /* Turn on phys dma reception.
2529                          *
2530                          * TODO: Enable some sort of filtering management.
2531                          */
2532                         if (phys_dma) {
2533                                 reg_write(ohci, OHCI1394_PhyReqFilterHiSet,
2534                                           0xffffffff);
2535                                 reg_write(ohci, OHCI1394_PhyReqFilterLoSet,
2536                                           0xffffffff);
2537                         }
2538
2539                         DBGMSG("PhyReqFilter=%08x%08x",
2540                                reg_read(ohci, OHCI1394_PhyReqFilterHiSet),
2541                                reg_read(ohci, OHCI1394_PhyReqFilterLoSet));
2542
2543                         hpsb_selfid_complete(host, phyid, isroot);
2544                 } else
2545                         PRINT(KERN_ERR,
2546                               "SelfID received outside of bus reset sequence");
2547
2548 selfid_not_valid:
2549                 event &= ~OHCI1394_selfIDComplete;
2550         }
2551
2552         /* Make sure we handle everything, just in case we accidentally
2553          * enabled an interrupt that we didn't write a handler for.  */
2554         if (event)
2555                 PRINT(KERN_ERR, "Unhandled interrupt(s) 0x%08x",
2556                       event);
2557
2558         return IRQ_HANDLED;
2559 }
2560
2561 /* Put the buffer back into the dma context */
2562 static void insert_dma_buffer(struct dma_rcv_ctx *d, int idx)
2563 {
2564         struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
2565         DBGMSG("Inserting dma buf ctx=%d idx=%d", d->ctx, idx);
2566
2567         d->prg_cpu[idx]->status = cpu_to_le32(d->buf_size);
2568         d->prg_cpu[idx]->branchAddress &= le32_to_cpu(0xfffffff0);
2569         idx = (idx + d->num_desc - 1 ) % d->num_desc;
2570         d->prg_cpu[idx]->branchAddress |= le32_to_cpu(0x00000001);
2571
2572         /* To avoid a race, ensure 1394 interface hardware sees the inserted
2573          * context program descriptors before it sees the wakeup bit set. */
2574         wmb();
2575
2576         /* wake up the dma context if necessary */
2577         if (!(reg_read(ohci, d->ctrlSet) & 0x400)) {
2578                 PRINT(KERN_INFO,
2579                       "Waking dma ctx=%d ... processing is probably too slow",
2580                       d->ctx);
2581         }
2582
2583         /* do this always, to avoid race condition */
2584         reg_write(ohci, d->ctrlSet, 0x1000);
2585 }
2586
2587 #define cond_le32_to_cpu(data, noswap) \
2588         (noswap ? data : le32_to_cpu(data))
2589
2590 static const int TCODE_SIZE[16] = {20, 0, 16, -1, 16, 20, 20, 0,
2591                             -1, 0, -1, 0, -1, -1, 16, -1};
2592
2593 /*
2594  * Determine the length of a packet in the buffer
2595  * Optimization suggested by Pascal Drolet <pascal.drolet@informission.ca>
2596  */
2597 static inline int packet_length(struct dma_rcv_ctx *d, int idx,
2598                                 quadlet_t *buf_ptr, int offset,
2599                                 unsigned char tcode, int noswap)
2600 {
2601         int length = -1;
2602
2603         if (d->type == DMA_CTX_ASYNC_REQ || d->type == DMA_CTX_ASYNC_RESP) {
2604                 length = TCODE_SIZE[tcode];
2605                 if (length == 0) {
2606                         if (offset + 12 >= d->buf_size) {
2607                                 length = (cond_le32_to_cpu(d->buf_cpu[(idx + 1) % d->num_desc]
2608                                                 [3 - ((d->buf_size - offset) >> 2)], noswap) >> 16);
2609                         } else {
2610                                 length = (cond_le32_to_cpu(buf_ptr[3], noswap) >> 16);
2611                         }
2612                         length += 20;
2613                 }
2614         } else if (d->type == DMA_CTX_ISO) {
2615                 /* Assumption: buffer fill mode with header/trailer */
2616                 length = (cond_le32_to_cpu(buf_ptr[0], noswap) >> 16) + 8;
2617         }
2618
2619         if (length > 0 && length % 4)
2620                 length += 4 - (length % 4);
2621
2622         return length;
2623 }
2624
2625 /* Tasklet that processes dma receive buffers */
2626 static void dma_rcv_tasklet (unsigned long data)
2627 {
2628         struct dma_rcv_ctx *d = (struct dma_rcv_ctx*)data;
2629         struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
2630         unsigned int split_left, idx, offset, rescount;
2631         unsigned char tcode;
2632         int length, bytes_left, ack;
2633         unsigned long flags;
2634         quadlet_t *buf_ptr;
2635         char *split_ptr;
2636         char msg[256];
2637
2638         spin_lock_irqsave(&d->lock, flags);
2639
2640         idx = d->buf_ind;
2641         offset = d->buf_offset;
2642         buf_ptr = d->buf_cpu[idx] + offset/4;
2643
2644         rescount = le32_to_cpu(d->prg_cpu[idx]->status) & 0xffff;
2645         bytes_left = d->buf_size - rescount - offset;
2646
2647         while (bytes_left > 0) {
2648                 tcode = (cond_le32_to_cpu(buf_ptr[0], ohci->no_swap_incoming) >> 4) & 0xf;
2649
2650                 /* packet_length() will return < 4 for an error */
2651                 length = packet_length(d, idx, buf_ptr, offset, tcode, ohci->no_swap_incoming);
2652
2653                 if (length < 4) { /* something is wrong */
2654                         sprintf(msg,"Unexpected tcode 0x%x(0x%08x) in AR ctx=%d, length=%d",
2655                                 tcode, cond_le32_to_cpu(buf_ptr[0], ohci->no_swap_incoming),
2656                                 d->ctx, length);
2657                         ohci1394_stop_context(ohci, d->ctrlClear, msg);
2658                         spin_unlock_irqrestore(&d->lock, flags);
2659                         return;
2660                 }
2661
2662                 /* The first case is where we have a packet that crosses
2663                  * over more than one descriptor. The next case is where
2664                  * it's all in the first descriptor.  */
2665                 if ((offset + length) > d->buf_size) {
2666                         DBGMSG("Split packet rcv'd");
2667                         if (length > d->split_buf_size) {
2668                                 ohci1394_stop_context(ohci, d->ctrlClear,
2669                                              "Split packet size exceeded");
2670                                 d->buf_ind = idx;
2671                                 d->buf_offset = offset;
2672                                 spin_unlock_irqrestore(&d->lock, flags);
2673                                 return;
2674                         }
2675
2676                         if (le32_to_cpu(d->prg_cpu[(idx+1)%d->num_desc]->status)
2677                             == d->buf_size) {
2678                                 /* Other part of packet not written yet.
2679                                  * this should never happen I think
2680                                  * anyway we'll get it on the next call.  */
2681                                 PRINT(KERN_INFO,
2682                                       "Got only half a packet!");
2683                                 d->buf_ind = idx;
2684                                 d->buf_offset = offset;
2685                                 spin_unlock_irqrestore(&d->lock, flags);
2686                                 return;
2687                         }
2688
2689                         split_left = length;
2690                         split_ptr = (char *)d->spb;
2691                         memcpy(split_ptr,buf_ptr,d->buf_size-offset);
2692                         split_left -= d->buf_size-offset;
2693                         split_ptr += d->buf_size-offset;
2694                         insert_dma_buffer(d, idx);
2695                         idx = (idx+1) % d->num_desc;
2696                         buf_ptr = d->buf_cpu[idx];
2697                         offset=0;
2698
2699                         while (split_left >= d->buf_size) {
2700                                 memcpy(split_ptr,buf_ptr,d->buf_size);
2701                                 split_ptr += d->buf_size;
2702                                 split_left -= d->buf_size;
2703                                 insert_dma_buffer(d, idx);
2704                                 idx = (idx+1) % d->num_desc;
2705                                 buf_ptr = d->buf_cpu[idx];
2706                         }
2707
2708                         if (split_left > 0) {
2709                                 memcpy(split_ptr, buf_ptr, split_left);
2710                                 offset = split_left;
2711                                 buf_ptr += offset/4;
2712                         }
2713                 } else {
2714                         DBGMSG("Single packet rcv'd");
2715                         memcpy(d->spb, buf_ptr, length);
2716                         offset += length;
2717                         buf_ptr += length/4;
2718                         if (offset==d->buf_size) {
2719                                 insert_dma_buffer(d, idx);
2720                                 idx = (idx+1) % d->num_desc;
2721                                 buf_ptr = d->buf_cpu[idx];
2722                                 offset=0;
2723                         }
2724                 }
2725
2726                 /* We get one phy packet to the async descriptor for each
2727                  * bus reset. We always ignore it.  */
2728                 if (tcode != OHCI1394_TCODE_PHY) {
2729                         if (!ohci->no_swap_incoming)
2730                                 header_le32_to_cpu(d->spb, tcode);
2731                         DBGMSG("Packet received from node"
2732                                 " %d ack=0x%02X spd=%d tcode=0x%X"
2733                                 " length=%d ctx=%d tlabel=%d",
2734                                 (d->spb[1]>>16)&0x3f,
2735                                 (cond_le32_to_cpu(d->spb[length/4-1], ohci->no_swap_incoming)>>16)&0x1f,
2736                                 (cond_le32_to_cpu(d->spb[length/4-1], ohci->no_swap_incoming)>>21)&0x3,
2737                                 tcode, length, d->ctx,
2738                                 (d->spb[0]>>10)&0x3f);
2739
2740                         ack = (((cond_le32_to_cpu(d->spb[length/4-1], ohci->no_swap_incoming)>>16)&0x1f)
2741                                 == 0x11) ? 1 : 0;
2742
2743                         hpsb_packet_received(ohci->host, d->spb,
2744                                              length-4, ack);
2745                 }
2746 #ifdef OHCI1394_DEBUG
2747                 else
2748                         PRINT (KERN_DEBUG, "Got phy packet ctx=%d ... discarded",
2749                                d->ctx);
2750 #endif
2751
2752                 rescount = le32_to_cpu(d->prg_cpu[idx]->status) & 0xffff;
2753
2754                 bytes_left = d->buf_size - rescount - offset;
2755
2756         }
2757
2758         d->buf_ind = idx;
2759         d->buf_offset = offset;
2760
2761         spin_unlock_irqrestore(&d->lock, flags);
2762 }
2763
2764 /* Bottom half that processes sent packets */
2765 static void dma_trm_tasklet (unsigned long data)
2766 {
2767         struct dma_trm_ctx *d = (struct dma_trm_ctx*)data;
2768         struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
2769         struct hpsb_packet *packet, *ptmp;
2770         unsigned long flags;
2771         u32 status, ack;
2772         size_t datasize;
2773
2774         spin_lock_irqsave(&d->lock, flags);
2775
2776         list_for_each_entry_safe(packet, ptmp, &d->fifo_list, driver_list) {
2777                 datasize = packet->data_size;
2778                 if (datasize && packet->type != hpsb_raw)
2779                         status = le32_to_cpu(
2780                                 d->prg_cpu[d->sent_ind]->end.status) >> 16;
2781                 else
2782                         status = le32_to_cpu(
2783                                 d->prg_cpu[d->sent_ind]->begin.status) >> 16;
2784
2785                 if (status == 0)
2786                         /* this packet hasn't been sent yet*/
2787                         break;
2788
2789 #ifdef OHCI1394_DEBUG
2790                 if (datasize)
2791                         if (((le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])>>4)&0xf) == 0xa)
2792                                 DBGMSG("Stream packet sent to channel %d tcode=0x%X "
2793                                        "ack=0x%X spd=%d dataLength=%d ctx=%d",
2794                                        (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])>>8)&0x3f,
2795                                        (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])>>4)&0xf,
2796                                        status&0x1f, (status>>5)&0x3,
2797                                        le32_to_cpu(d->prg_cpu[d->sent_ind]->data[1])>>16,
2798                                        d->ctx);
2799                         else
2800                                 DBGMSG("Packet sent to node %d tcode=0x%X tLabel="
2801                                        "%d ack=0x%X spd=%d dataLength=%d ctx=%d",
2802                                        (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[1])>>16)&0x3f,
2803                                        (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])>>4)&0xf,
2804                                        (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])>>10)&0x3f,
2805                                        status&0x1f, (status>>5)&0x3,
2806                                        le32_to_cpu(d->prg_cpu[d->sent_ind]->data[3])>>16,
2807                                        d->ctx);
2808                 else
2809                         DBGMSG("Packet sent to node %d tcode=0x%X tLabel="
2810                                "%d ack=0x%X spd=%d data=0x%08X ctx=%d",
2811                                 (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[1])
2812                                         >>16)&0x3f,
2813                                 (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])
2814                                         >>4)&0xf,
2815                                 (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])
2816                                         >>10)&0x3f,
2817                                 status&0x1f, (status>>5)&0x3,
2818                                 le32_to_cpu(d->prg_cpu[d->sent_ind]->data[3]),
2819                                 d->ctx);
2820 #endif
2821
2822                 if (status & 0x10) {
2823                         ack = status & 0xf;
2824                 } else {
2825                         switch (status & 0x1f) {
2826                         case EVT_NO_STATUS: /* that should never happen */
2827                         case EVT_RESERVED_A: /* that should never happen */
2828                         case EVT_LONG_PACKET: /* that should never happen */
2829                                 PRINT(KERN_WARNING, "Received OHCI evt_* error 0x%x", status & 0x1f);
2830                                 ack = ACKX_SEND_ERROR;
2831                                 break;
2832                         case EVT_MISSING_ACK:
2833                                 ack = ACKX_TIMEOUT;
2834                                 break;
2835                         case EVT_UNDERRUN:
2836                                 ack = ACKX_SEND_ERROR;
2837                                 break;
2838                         case EVT_OVERRUN: /* that should never happen */
2839                                 PRINT(KERN_WARNING, "Received OHCI evt_* error 0x%x", status & 0x1f);
2840                                 ack = ACKX_SEND_ERROR;
2841                                 break;
2842                         case EVT_DESCRIPTOR_READ:
2843                         case EVT_DATA_READ:
2844                         case EVT_DATA_WRITE:
2845                                 ack = ACKX_SEND_ERROR;
2846                                 break;
2847                         case EVT_BUS_RESET: /* that should never happen */
2848                                 PRINT(KERN_WARNING, "Received OHCI evt_* error 0x%x", status & 0x1f);
2849                                 ack = ACKX_SEND_ERROR;
2850                                 break;
2851                         case EVT_TIMEOUT:
2852                                 ack = ACKX_TIMEOUT;
2853                                 break;
2854                         case EVT_TCODE_ERR:
2855                                 ack = ACKX_SEND_ERROR;
2856                                 break;
2857                         case EVT_RESERVED_B: /* that should never happen */
2858                         case EVT_RESERVED_C: /* that should never happen */
2859                                 PRINT(KERN_WARNING, "Received OHCI evt_* error 0x%x", status & 0x1f);
2860                                 ack = ACKX_SEND_ERROR;
2861                                 break;
2862                         case EVT_UNKNOWN:
2863                         case EVT_FLUSHED:
2864                                 ack = ACKX_SEND_ERROR;
2865                                 break;
2866                         default:
2867                                 PRINT(KERN_ERR, "Unhandled OHCI evt_* error 0x%x", status & 0x1f);
2868                                 ack = ACKX_SEND_ERROR;
2869                                 BUG();
2870                         }
2871                 }
2872
2873                 list_del_init(&packet->driver_list);
2874                 hpsb_packet_sent(ohci->host, packet, ack);
2875
2876                 if (datasize) {
2877                         pci_unmap_single(ohci->dev,
2878                                          cpu_to_le32(d->prg_cpu[d->sent_ind]->end.address),
2879                                          datasize, PCI_DMA_TODEVICE);
2880                         OHCI_DMA_FREE("single Xmit data packet");
2881                 }
2882
2883                 d->sent_ind = (d->sent_ind+1)%d->num_desc;
2884                 d->free_prgs++;
2885         }
2886
2887         dma_trm_flush(ohci, d);
2888
2889         spin_unlock_irqrestore(&d->lock, flags);
2890 }
2891
2892 static void stop_dma_rcv_ctx(struct dma_rcv_ctx *d)
2893 {
2894         if (d->ctrlClear) {
2895                 ohci1394_stop_context(d->ohci, d->ctrlClear, NULL);
2896
2897                 if (d->type == DMA_CTX_ISO) {
2898                         /* disable interrupts */
2899                         reg_write(d->ohci, OHCI1394_IsoRecvIntMaskClear, 1 << d->ctx);
2900                         ohci1394_unregister_iso_tasklet(d->ohci, &d->ohci->ir_legacy_tasklet);
2901                 } else {
2902                         tasklet_kill(&d->task);
2903                 }
2904         }
2905 }
2906
2907
2908 static void free_dma_rcv_ctx(struct dma_rcv_ctx *d)
2909 {
2910         int i;
2911         struct ti_ohci *ohci = d->ohci;
2912
2913         if (ohci == NULL)
2914                 return;
2915
2916         DBGMSG("Freeing dma_rcv_ctx %d", d->ctx);
2917
2918         if (d->buf_cpu) {
2919                 for (i=0; i<d->num_desc; i++)
2920                         if (d->buf_cpu[i] && d->buf_bus[i]) {
2921                                 pci_free_consistent(
2922                                         ohci->dev, d->buf_size,
2923                                         d->buf_cpu[i], d->buf_bus[i]);
2924                                 OHCI_DMA_FREE("consistent dma_rcv buf[%d]", i);
2925                         }
2926                 kfree(d->buf_cpu);
2927                 kfree(d->buf_bus);
2928         }
2929         if (d->prg_cpu) {
2930                 for (i=0; i<d->num_desc; i++)
2931                         if (d->prg_cpu[i] && d->prg_bus[i]) {
2932                                 pci_pool_free(d->prg_pool, d->prg_cpu[i], d->prg_bus[i]);
2933                                 OHCI_DMA_FREE("consistent dma_rcv prg[%d]", i);
2934                         }
2935                 pci_pool_destroy(d->prg_pool);
2936                 OHCI_DMA_FREE("dma_rcv prg pool");
2937                 kfree(d->prg_cpu);
2938                 kfree(d->prg_bus);
2939         }
2940         kfree(d->spb);
2941
2942         /* Mark this context as freed. */
2943         d->ohci = NULL;
2944 }
2945
2946 static int
2947 alloc_dma_rcv_ctx(struct ti_ohci *ohci, struct dma_rcv_ctx *d,
2948                   enum context_type type, int ctx, int num_desc,
2949                   int buf_size, int split_buf_size, int context_base)
2950 {
2951         int i, len;
2952         static int num_allocs;
2953         static char pool_name[20];
2954
2955         d->ohci = ohci;
2956         d->type = type;
2957         d->ctx = ctx;
2958
2959         d->num_desc = num_desc;
2960         d->buf_size = buf_size;
2961         d->split_buf_size = split_buf_size;
2962
2963         d->ctrlSet = 0;
2964         d->ctrlClear = 0;
2965         d->cmdPtr = 0;
2966
2967         d->buf_cpu = kzalloc(d->num_desc * sizeof(*d->buf_cpu), GFP_ATOMIC);
2968         d->buf_bus = kzalloc(d->num_desc * sizeof(*d->buf_bus), GFP_ATOMIC);
2969
2970         if (d->buf_cpu == NULL || d->buf_bus == NULL) {
2971                 PRINT(KERN_ERR, "Failed to allocate dma buffer");
2972                 free_dma_rcv_ctx(d);
2973                 return -ENOMEM;
2974         }
2975
2976         d->prg_cpu = kzalloc(d->num_desc * sizeof(*d->prg_cpu), GFP_ATOMIC);
2977         d->prg_bus = kzalloc(d->num_desc * sizeof(*d->prg_bus), GFP_ATOMIC);
2978
2979         if (d->prg_cpu == NULL || d->prg_bus == NULL) {
2980                 PRINT(KERN_ERR, "Failed to allocate dma prg");
2981                 free_dma_rcv_ctx(d);
2982                 return -ENOMEM;
2983         }
2984
2985         d->spb = kmalloc(d->split_buf_size, GFP_ATOMIC);
2986
2987         if (d->spb == NULL) {
2988                 PRINT(KERN_ERR, "Failed to allocate split buffer");
2989                 free_dma_rcv_ctx(d);
2990                 return -ENOMEM;
2991         }
2992
2993         len = sprintf(pool_name, "ohci1394_rcv_prg");
2994         sprintf(pool_name+len, "%d", num_allocs);
2995         d->prg_pool = pci_pool_create(pool_name, ohci->dev,
2996                                 sizeof(struct dma_cmd), 4, 0);
2997         if(d->prg_pool == NULL)
2998         {
2999                 PRINT(KERN_ERR, "pci_pool_create failed for %s", pool_name);
3000                 free_dma_rcv_ctx(d);
3001                 return -ENOMEM;
3002         }
3003         num_allocs++;
3004
3005         OHCI_DMA_ALLOC("dma_rcv prg pool");
3006
3007         for (i=0; i<d->num_desc; i++) {
3008                 d->buf_cpu[i] = pci_alloc_consistent(ohci->dev,
3009                                                      d->buf_size,
3010                                                      d->buf_bus+i);
3011                 OHCI_DMA_ALLOC("consistent dma_rcv buf[%d]", i);
3012
3013                 if (d->buf_cpu[i] != NULL) {
3014                         memset(d->buf_cpu[i], 0, d->buf_size);
3015                 } else {
3016                         PRINT(KERN_ERR,
3017                               "Failed to allocate dma buffer");
3018                         free_dma_rcv_ctx(d);
3019                         return -ENOMEM;
3020                 }
3021
3022                 d->prg_cpu[i] = pci_pool_alloc(d->prg_pool, GFP_KERNEL, d->prg_bus+i);
3023                 OHCI_DMA_ALLOC("pool dma_rcv prg[%d]", i);
3024
3025                 if (d->prg_cpu[i] != NULL) {
3026                         memset(d->prg_cpu[i], 0, sizeof(struct dma_cmd));
3027                 } else {
3028                         PRINT(KERN_ERR,
3029                               "Failed to allocate dma prg");
3030                         free_dma_rcv_ctx(d);
3031                         return -ENOMEM;
3032                 }
3033         }
3034
3035         spin_lock_init(&d->lock);
3036
3037         if (type == DMA_CTX_ISO) {
3038                 ohci1394_init_iso_tasklet(&ohci->ir_legacy_tasklet,
3039                                           OHCI_ISO_MULTICHANNEL_RECEIVE,
3040                                           dma_rcv_tasklet, (unsigned long) d);
3041         } else {
3042                 d->ctrlSet = context_base + OHCI1394_ContextControlSet;
3043                 d->ctrlClear = context_base + OHCI1394_ContextControlClear;
3044                 d->cmdPtr = context_base + OHCI1394_ContextCommandPtr;
3045
3046                 tasklet_init (&d->task, dma_rcv_tasklet, (unsigned long) d);
3047         }
3048
3049         return 0;
3050 }
3051
3052 static void free_dma_trm_ctx(struct dma_trm_ctx *d)
3053 {
3054         int i;
3055         struct ti_ohci *ohci = d->ohci;
3056
3057         if (ohci == NULL)
3058                 return;
3059
3060         DBGMSG("Freeing dma_trm_ctx %d", d->ctx);
3061
3062         if (d->prg_cpu) {
3063                 for (i=0; i<d->num_desc; i++)
3064                         if (d->prg_cpu[i] && d->prg_bus[i]) {
3065                                 pci_pool_free(d->prg_pool, d->prg_cpu[i], d->prg_bus[i]);
3066                                 OHCI_DMA_FREE("pool dma_trm prg[%d]", i);
3067                         }
3068                 pci_pool_destroy(d->prg_pool);
3069                 OHCI_DMA_FREE("dma_trm prg pool");
3070                 kfree(d->prg_cpu);
3071                 kfree(d->prg_bus);
3072         }
3073
3074         /* Mark this context as freed. */
3075         d->ohci = NULL;
3076 }
3077
3078 static int
3079 alloc_dma_trm_ctx(struct ti_ohci *ohci, struct dma_trm_ctx *d,
3080                   enum context_type type, int ctx, int num_desc,
3081                   int context_base)
3082 {
3083         int i, len;
3084         static char pool_name[20];
3085         static int num_allocs=0;
3086
3087         d->ohci = ohci;
3088         d->type = type;
3089         d->ctx = ctx;
3090         d->num_desc = num_desc;
3091         d->ctrlSet = 0;
3092         d->ctrlClear = 0;
3093         d->cmdPtr = 0;
3094
3095         d->prg_cpu = kzalloc(d->num_desc * sizeof(*d->prg_cpu), GFP_KERNEL);
3096         d->prg_bus = kzalloc(d->num_desc * sizeof(*d->prg_bus), GFP_KERNEL);
3097
3098         if (d->prg_cpu == NULL || d->prg_bus == NULL) {
3099                 PRINT(KERN_ERR, "Failed to allocate at dma prg");
3100                 free_dma_trm_ctx(d);
3101                 return -ENOMEM;
3102         }
3103
3104         len = sprintf(pool_name, "ohci1394_trm_prg");
3105         sprintf(pool_name+len, "%d", num_allocs);
3106         d->prg_pool = pci_pool_create(pool_name, ohci->dev,
3107                                 sizeof(struct at_dma_prg), 4, 0);
3108         if (d->prg_pool == NULL) {
3109                 PRINT(KERN_ERR, "pci_pool_create failed for %s", pool_name);
3110                 free_dma_trm_ctx(d);
3111                 return -ENOMEM;
3112         }
3113         num_allocs++;
3114
3115         OHCI_DMA_ALLOC("dma_rcv prg pool");
3116
3117         for (i = 0; i < d->num_desc; i++) {
3118                 d->prg_cpu[i] = pci_pool_alloc(d->prg_pool, GFP_KERNEL, d->prg_bus+i);
3119                 OHCI_DMA_ALLOC("pool dma_trm prg[%d]", i);
3120
3121                 if (d->prg_cpu[i] != NULL) {
3122                         memset(d->prg_cpu[i], 0, sizeof(struct at_dma_prg));
3123                 } else {
3124                         PRINT(KERN_ERR,
3125                               "Failed to allocate at dma prg");
3126                         free_dma_trm_ctx(d);
3127                         return -ENOMEM;
3128                 }
3129         }
3130
3131         spin_lock_init(&d->lock);
3132
3133         /* initialize tasklet */
3134         if (type == DMA_CTX_ISO) {
3135                 ohci1394_init_iso_tasklet(&ohci->it_legacy_tasklet, OHCI_ISO_TRANSMIT,
3136                                           dma_trm_tasklet, (unsigned long) d);
3137                 if (ohci1394_register_iso_tasklet(ohci,
3138                                                   &ohci->it_legacy_tasklet) < 0) {
3139                         PRINT(KERN_ERR, "No IT DMA context available");
3140                         free_dma_trm_ctx(d);
3141                         return -EBUSY;
3142                 }
3143
3144                 /* IT can be assigned to any context by register_iso_tasklet */
3145                 d->ctx = ohci->it_legacy_tasklet.context;
3146                 d->ctrlSet = OHCI1394_IsoXmitContextControlSet + 16 * d->ctx;
3147                 d->ctrlClear = OHCI1394_IsoXmitContextControlClear + 16 * d->ctx;
3148                 d->cmdPtr = OHCI1394_IsoXmitCommandPtr + 16 * d->ctx;
3149         } else {
3150                 d->ctrlSet = context_base + OHCI1394_ContextControlSet;
3151                 d->ctrlClear = context_base + OHCI1394_ContextControlClear;
3152                 d->cmdPtr = context_base + OHCI1394_ContextCommandPtr;
3153                 tasklet_init (&d->task, dma_trm_tasklet, (unsigned long)d);
3154         }
3155
3156         return 0;
3157 }
3158
3159 static void ohci_set_hw_config_rom(struct hpsb_host *host, quadlet_t *config_rom)
3160 {
3161         struct ti_ohci *ohci = host->hostdata;
3162
3163         reg_write(ohci, OHCI1394_ConfigROMhdr, be32_to_cpu(config_rom[0]));
3164         reg_write(ohci, OHCI1394_BusOptions, be32_to_cpu(config_rom[2]));
3165
3166         memcpy(ohci->csr_config_rom_cpu, config_rom, OHCI_CONFIG_ROM_LEN);
3167 }
3168
3169
3170 static quadlet_t ohci_hw_csr_reg(struct hpsb_host *host, int reg,
3171                                  quadlet_t data, quadlet_t compare)
3172 {
3173         struct ti_ohci *ohci = host->hostdata;
3174         int i;
3175
3176         reg_write(ohci, OHCI1394_CSRData, data);
3177         reg_write(ohci, OHCI1394_CSRCompareData, compare);
3178         reg_write(ohci, OHCI1394_CSRControl, reg & 0x3);
3179
3180         for (i = 0; i < OHCI_LOOP_COUNT; i++) {
3181                 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
3182                         break;
3183
3184                 mdelay(1);
3185         }
3186
3187         return reg_read(ohci, OHCI1394_CSRData);
3188 }
3189
3190 static struct hpsb_host_driver ohci1394_driver = {
3191         .owner =                THIS_MODULE,
3192         .name =                 OHCI1394_DRIVER_NAME,
3193         .set_hw_config_rom =    ohci_set_hw_config_rom,
3194         .transmit_packet =      ohci_transmit,
3195         .devctl =               ohci_devctl,
3196         .isoctl =               ohci_isoctl,
3197         .hw_csr_reg =           ohci_hw_csr_reg,
3198 };
3199
3200 /***********************************
3201  * PCI Driver Interface functions  *
3202  ***********************************/
3203
3204 #define FAIL(err, fmt, args...)                 \
3205 do {                                            \
3206         PRINT_G(KERN_ERR, fmt , ## args);       \
3207         ohci1394_pci_remove(dev);               \
3208         return err;                             \
3209 } while (0)
3210
3211 static int __devinit ohci1394_pci_probe(struct pci_dev *dev,
3212                                         const struct pci_device_id *ent)
3213 {
3214         struct hpsb_host *host;
3215         struct ti_ohci *ohci;   /* shortcut to currently handled device */
3216         resource_size_t ohci_base;
3217
3218 #ifdef CONFIG_PPC_PMAC
3219         /* Necessary on some machines if ohci1394 was loaded/ unloaded before */
3220         if (machine_is(powermac)) {
3221                 struct device_node *ofn = pci_device_to_OF_node(dev);
3222
3223                 if (ofn) {
3224                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
3225                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
3226                 }
3227         }
3228 #endif /* CONFIG_PPC_PMAC */
3229
3230         if (pci_enable_device(dev))
3231                 FAIL(-ENXIO, "Failed to enable OHCI hardware");
3232         pci_set_master(dev);
3233
3234         host = hpsb_alloc_host(&ohci1394_driver, sizeof(struct ti_ohci), &dev->dev);
3235         if (!host) FAIL(-ENOMEM, "Failed to allocate host structure");
3236
3237         ohci = host->hostdata;
3238         ohci->dev = dev;
3239         ohci->host = host;
3240         ohci->init_state = OHCI_INIT_ALLOC_HOST;
3241         host->pdev = dev;
3242         pci_set_drvdata(dev, ohci);
3243
3244         /* We don't want hardware swapping */
3245         pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
3246
3247         /* Some oddball Apple controllers do not order the selfid
3248          * properly, so we make up for it here.  */
3249 #ifndef __LITTLE_ENDIAN
3250         /* XXX: Need a better way to check this. I'm wondering if we can
3251          * read the values of the OHCI1394_PCI_HCI_Control and the
3252          * noByteSwapData registers to see if they were not cleared to
3253          * zero. Should this work? Obviously it's not defined what these
3254          * registers will read when they aren't supported. Bleh! */
3255         if (dev->vendor == PCI_VENDOR_ID_APPLE &&
3256             dev->device == PCI_DEVICE_ID_APPLE_UNI_N_FW) {
3257                 ohci->no_swap_incoming = 1;
3258                 ohci->selfid_swap = 0;
3259         } else
3260                 ohci->selfid_swap = 1;
3261 #endif
3262
3263
3264 #ifndef PCI_DEVICE_ID_NVIDIA_NFORCE2_FW
3265 #define PCI_DEVICE_ID_NVIDIA_NFORCE2_FW 0x006e
3266 #endif
3267
3268         /* These chipsets require a bit of extra care when checking after
3269          * a busreset.  */
3270         if ((dev->vendor == PCI_VENDOR_ID_APPLE &&
3271              dev->device == PCI_DEVICE_ID_APPLE_UNI_N_FW) ||
3272             (dev->vendor ==  PCI_VENDOR_ID_NVIDIA &&
3273              dev->device == PCI_DEVICE_ID_NVIDIA_NFORCE2_FW))
3274                 ohci->check_busreset = 1;
3275
3276         /* We hardwire the MMIO length, since some CardBus adaptors
3277          * fail to report the right length.  Anyway, the ohci spec
3278          * clearly says it's 2kb, so this shouldn't be a problem. */
3279         ohci_base = pci_resource_start(dev, 0);
3280         if (pci_resource_len(dev, 0) < OHCI1394_REGISTER_SIZE)
3281                 PRINT(KERN_WARNING, "PCI resource length of 0x%llx too small!",
3282                       (unsigned long long)pci_resource_len(dev, 0));
3283
3284         /* Seems PCMCIA handles this internally. Not sure why. Seems
3285          * pretty bogus to force a driver to special case this.  */
3286 #ifndef PCMCIA
3287         if (!request_mem_region (ohci_base, OHCI1394_REGISTER_SIZE, OHCI1394_DRIVER_NAME))
3288                 FAIL(-ENOMEM, "MMIO resource (0x%llx - 0x%llx) unavailable",
3289                         (unsigned long long)ohci_base,
3290                         (unsigned long long)ohci_base + OHCI1394_REGISTER_SIZE);
3291 #endif
3292         ohci->init_state = OHCI_INIT_HAVE_MEM_REGION;
3293
3294         ohci->registers = ioremap(ohci_base, OHCI1394_REGISTER_SIZE);
3295         if (ohci->registers == NULL)
3296                 FAIL(-ENXIO, "Failed to remap registers - card not accessible");
3297         ohci->init_state = OHCI_INIT_HAVE_IOMAPPING;
3298         DBGMSG("Remapped memory spaces reg 0x%p", ohci->registers);
3299
3300         /* csr_config rom allocation */
3301         ohci->csr_config_rom_cpu =
3302                 pci_alloc_consistent(ohci->dev, OHCI_CONFIG_ROM_LEN,
3303                                      &ohci->csr_config_rom_bus);
3304         OHCI_DMA_ALLOC("consistent csr_config_rom");
3305         if (ohci->csr_config_rom_cpu == NULL)
3306                 FAIL(-ENOMEM, "Failed to allocate buffer config rom");
3307         ohci->init_state = OHCI_INIT_HAVE_CONFIG_ROM_BUFFER;
3308
3309         /* self-id dma buffer allocation */
3310         ohci->selfid_buf_cpu =
3311                 pci_alloc_consistent(ohci->dev, OHCI1394_SI_DMA_BUF_SIZE,
3312                       &ohci->selfid_buf_bus);
3313         OHCI_DMA_ALLOC("consistent selfid_buf");
3314
3315         if (ohci->selfid_buf_cpu == NULL)
3316                 FAIL(-ENOMEM, "Failed to allocate DMA buffer for self-id packets");
3317         ohci->init_state = OHCI_INIT_HAVE_SELFID_BUFFER;
3318
3319         if ((unsigned long)ohci->selfid_buf_cpu & 0x1fff)
3320                 PRINT(KERN_INFO, "SelfID buffer %p is not aligned on "
3321                       "8Kb boundary... may cause problems on some CXD3222 chip",
3322                       ohci->selfid_buf_cpu);
3323
3324         /* No self-id errors at startup */
3325         ohci->self_id_errors = 0;
3326
3327         ohci->init_state = OHCI_INIT_HAVE_TXRX_BUFFERS__MAYBE;
3328         /* AR DMA request context allocation */
3329         if (alloc_dma_rcv_ctx(ohci, &ohci->ar_req_context,
3330                               DMA_CTX_ASYNC_REQ, 0, AR_REQ_NUM_DESC,
3331                               AR_REQ_BUF_SIZE, AR_REQ_SPLIT_BUF_SIZE,
3332                               OHCI1394_AsReqRcvContextBase) < 0)
3333                 FAIL(-ENOMEM, "Failed to allocate AR Req context");
3334
3335         /* AR DMA response context allocation */
3336         if (alloc_dma_rcv_ctx(ohci, &ohci->ar_resp_context,
3337                               DMA_CTX_ASYNC_RESP, 0, AR_RESP_NUM_DESC,
3338                               AR_RESP_BUF_SIZE, AR_RESP_SPLIT_BUF_SIZE,
3339                               OHCI1394_AsRspRcvContextBase) < 0)
3340                 FAIL(-ENOMEM, "Failed to allocate AR Resp context");
3341
3342         /* AT DMA request context */
3343         if (alloc_dma_trm_ctx(ohci, &ohci->at_req_context,
3344                               DMA_CTX_ASYNC_REQ, 0, AT_REQ_NUM_DESC,
3345                               OHCI1394_AsReqTrContextBase) < 0)
3346                 FAIL(-ENOMEM, "Failed to allocate AT Req context");
3347
3348         /* AT DMA response context */
3349         if (alloc_dma_trm_ctx(ohci, &ohci->at_resp_context,
3350                               DMA_CTX_ASYNC_RESP, 1, AT_RESP_NUM_DESC,
3351                               OHCI1394_AsRspTrContextBase) < 0)
3352                 FAIL(-ENOMEM, "Failed to allocate AT Resp context");
3353
3354         /* Start off with a soft reset, to clear everything to a sane
3355          * state. */
3356         ohci_soft_reset(ohci);
3357
3358         /* Now enable LPS, which we need in order to start accessing
3359          * most of the registers.  In fact, on some cards (ALI M5251),
3360          * accessing registers in the SClk domain without LPS enabled
3361          * will lock up the machine.  Wait 50msec to make sure we have
3362          * full link enabled.  */
3363         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_LPS);
3364
3365         /* Disable and clear interrupts */
3366         reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff);
3367         reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff);
3368
3369         mdelay(50);
3370
3371         /* Determine the number of available IR and IT contexts. */
3372         ohci->nb_iso_rcv_ctx =
3373                 get_nb_iso_ctx(ohci, OHCI1394_IsoRecvIntMaskSet);
3374         ohci->nb_iso_xmit_ctx =
3375                 get_nb_iso_ctx(ohci, OHCI1394_IsoXmitIntMaskSet);
3376
3377         /* Set the usage bits for non-existent contexts so they can't
3378          * be allocated */
3379         ohci->ir_ctx_usage = ~0 << ohci->nb_iso_rcv_ctx;
3380         ohci->it_ctx_usage = ~0 << ohci->nb_iso_xmit_ctx;
3381
3382         INIT_LIST_HEAD(&ohci->iso_tasklet_list);
3383         spin_lock_init(&ohci->iso_tasklet_list_lock);
3384         ohci->ISO_channel_usage = 0;
3385         spin_lock_init(&ohci->IR_channel_lock);
3386
3387         /* Allocate the IR DMA context right here so we don't have
3388          * to do it in interrupt path - note that this doesn't
3389          * waste much memory and avoids the jugglery required to
3390          * allocate it in IRQ path. */
3391         if (alloc_dma_rcv_ctx(ohci, &ohci->ir_legacy_context,
3392                               DMA_CTX_ISO, 0, IR_NUM_DESC,
3393                               IR_BUF_SIZE, IR_SPLIT_BUF_SIZE,
3394                               OHCI1394_IsoRcvContextBase) < 0) {
3395                 FAIL(-ENOMEM, "Cannot allocate IR Legacy DMA context");
3396         }
3397
3398         /* We hopefully don't have to pre-allocate IT DMA like we did
3399          * for IR DMA above. Allocate it on-demand and mark inactive. */
3400         ohci->it_legacy_context.ohci = NULL;
3401         spin_lock_init(&ohci->event_lock);
3402
3403         /*
3404          * interrupts are disabled, all right, but... due to IRQF_SHARED we
3405          * might get called anyway.  We'll see no event, of course, but
3406          * we need to get to that "no event", so enough should be initialized
3407          * by that point.
3408          */
3409         if (request_irq(dev->irq, ohci_irq_handler, IRQF_SHARED,
3410                          OHCI1394_DRIVER_NAME, ohci))
3411                 FAIL(-ENOMEM, "Failed to allocate shared interrupt %d", dev->irq);
3412
3413         ohci->init_state = OHCI_INIT_HAVE_IRQ;
3414         ohci_initialize(ohci);
3415
3416         /* Set certain csr values */
3417         host->csr.guid_hi = reg_read(ohci, OHCI1394_GUIDHi);
3418         host->csr.guid_lo = reg_read(ohci, OHCI1394_GUIDLo);
3419         host->csr.cyc_clk_acc = 100;  /* how do we determine clk accuracy? */
3420         host->csr.max_rec = (reg_read(ohci, OHCI1394_BusOptions) >> 12) & 0xf;
3421         host->csr.lnk_spd = reg_read(ohci, OHCI1394_BusOptions) & 0x7;
3422
3423         if (phys_dma) {
3424                 host->low_addr_space =
3425                         (u64) reg_read(ohci, OHCI1394_PhyUpperBound) << 16;
3426                 if (!host->low_addr_space)
3427                         host->low_addr_space = OHCI1394_PHYS_UPPER_BOUND_FIXED;
3428         }
3429         host->middle_addr_space = OHCI1394_MIDDLE_ADDRESS_SPACE;
3430
3431         /* Tell the highlevel this host is ready */
3432         if (hpsb_add_host(host))
3433                 FAIL(-ENOMEM, "Failed to register host with highlevel");
3434
3435         ohci->init_state = OHCI_INIT_DONE;
3436
3437         return 0;
3438 #undef FAIL
3439 }
3440
3441 static void ohci1394_pci_remove(struct pci_dev *pdev)
3442 {
3443         struct ti_ohci *ohci;
3444         struct device *dev;
3445
3446         ohci = pci_get_drvdata(pdev);
3447         if (!ohci)
3448                 return;
3449
3450         dev = get_device(&ohci->host->device);
3451
3452         switch (ohci->init_state) {
3453         case OHCI_INIT_DONE:
3454                 hpsb_remove_host(ohci->host);
3455
3456                 /* Clear out BUS Options */
3457                 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
3458                 reg_write(ohci, OHCI1394_BusOptions,
3459                           (reg_read(ohci, OHCI1394_BusOptions) & 0x0000f007) |
3460                           0x00ff0000);
3461                 memset(ohci->csr_config_rom_cpu, 0, OHCI_CONFIG_ROM_LEN);
3462
3463         case OHCI_INIT_HAVE_IRQ:
3464                 /* Clear interrupt registers */
3465                 reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff);
3466                 reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff);
3467                 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 0xffffffff);
3468                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 0xffffffff);
3469                 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 0xffffffff);
3470                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 0xffffffff);
3471
3472                 /* Disable IRM Contender */
3473                 set_phy_reg(ohci, 4, ~0xc0 & get_phy_reg(ohci, 4));
3474
3475                 /* Clear link control register */
3476                 reg_write(ohci, OHCI1394_LinkControlClear, 0xffffffff);
3477
3478                 /* Let all other nodes know to ignore us */
3479                 ohci_devctl(ohci->host, RESET_BUS, LONG_RESET_NO_FORCE_ROOT);
3480
3481                 /* Soft reset before we start - this disables
3482                  * interrupts and clears linkEnable and LPS. */
3483                 ohci_soft_reset(ohci);
3484                 free_irq(ohci->dev->irq, ohci);
3485
3486         case OHCI_INIT_HAVE_TXRX_BUFFERS__MAYBE:
3487                 /* The ohci_soft_reset() stops all DMA contexts, so we
3488                  * dont need to do this.  */
3489                 free_dma_rcv_ctx(&ohci->ar_req_context);
3490                 free_dma_rcv_ctx(&ohci->ar_resp_context);
3491                 free_dma_trm_ctx(&ohci->at_req_context);
3492                 free_dma_trm_ctx(&ohci->at_resp_context);
3493                 free_dma_rcv_ctx(&ohci->ir_legacy_context);
3494                 free_dma_trm_ctx(&ohci->it_legacy_context);
3495
3496         case OHCI_INIT_HAVE_SELFID_BUFFER:
3497                 pci_free_consistent(ohci->dev, OHCI1394_SI_DMA_BUF_SIZE,
3498                                     ohci->selfid_buf_cpu,
3499                                     ohci->selfid_buf_bus);
3500                 OHCI_DMA_FREE("consistent selfid_buf");
3501
3502         case OHCI_INIT_HAVE_CONFIG_ROM_BUFFER:
3503                 pci_free_consistent(ohci->dev, OHCI_CONFIG_ROM_LEN,
3504                                     ohci->csr_config_rom_cpu,
3505                                     ohci->csr_config_rom_bus);
3506                 OHCI_DMA_FREE("consistent csr_config_rom");
3507
3508         case OHCI_INIT_HAVE_IOMAPPING:
3509                 iounmap(ohci->registers);
3510
3511         case OHCI_INIT_HAVE_MEM_REGION:
3512 #ifndef PCMCIA
3513                 release_mem_region(pci_resource_start(ohci->dev, 0),
3514                                    OHCI1394_REGISTER_SIZE);
3515 #endif
3516
3517 #ifdef CONFIG_PPC_PMAC
3518         /* On UniNorth, power down the cable and turn off the chip clock
3519          * to save power on laptops */
3520         if (machine_is(powermac)) {
3521                 struct device_node* ofn = pci_device_to_OF_node(ohci->dev);
3522
3523                 if (ofn) {
3524                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
3525                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
3526                 }
3527         }
3528 #endif /* CONFIG_PPC_PMAC */
3529
3530         case OHCI_INIT_ALLOC_HOST:
3531                 pci_set_drvdata(ohci->dev, NULL);
3532         }
3533
3534         if (dev)
3535                 put_device(dev);
3536 }
3537
3538 #ifdef CONFIG_PM
3539 static int ohci1394_pci_suspend(struct pci_dev *pdev, pm_message_t state)
3540 {
3541         int err;
3542         struct ti_ohci *ohci = pci_get_drvdata(pdev);
3543
3544         printk(KERN_INFO "%s does not fully support suspend and resume yet\n",
3545                OHCI1394_DRIVER_NAME);
3546
3547         if (!ohci) {
3548                 printk(KERN_ERR "%s: tried to suspend nonexisting host\n",
3549                        OHCI1394_DRIVER_NAME);
3550                 return -ENXIO;
3551         }
3552         DBGMSG("suspend called");
3553
3554         /* Clear the async DMA contexts and stop using the controller */
3555         hpsb_bus_reset(ohci->host);
3556
3557         /* See ohci1394_pci_remove() for comments on this sequence */
3558         reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
3559         reg_write(ohci, OHCI1394_BusOptions,
3560                   (reg_read(ohci, OHCI1394_BusOptions) & 0x0000f007) |
3561                   0x00ff0000);
3562         reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff);
3563         reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff);
3564         reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 0xffffffff);
3565         reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 0xffffffff);
3566         reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 0xffffffff);
3567         reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 0xffffffff);
3568         set_phy_reg(ohci, 4, ~0xc0 & get_phy_reg(ohci, 4));
3569         reg_write(ohci, OHCI1394_LinkControlClear, 0xffffffff);
3570         ohci_devctl(ohci->host, RESET_BUS, LONG_RESET_NO_FORCE_ROOT);
3571         ohci_soft_reset(ohci);
3572
3573         err = pci_save_state(pdev);
3574         if (err) {
3575                 PRINT(KERN_ERR, "pci_save_state failed with %d", err);
3576                 return err;
3577         }
3578         err = pci_set_power_state(pdev, pci_choose_state(pdev, state));
3579         if (err)
3580                 DBGMSG("pci_set_power_state failed with %d", err);
3581
3582 /* PowerMac suspend code comes last */
3583 #ifdef CONFIG_PPC_PMAC
3584         if (machine_is(powermac)) {
3585                 struct device_node *ofn = pci_device_to_OF_node(pdev);
3586
3587                 if (ofn)
3588                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
3589         }
3590 #endif /* CONFIG_PPC_PMAC */
3591
3592         return 0;
3593 }
3594
3595 static int ohci1394_pci_resume(struct pci_dev *pdev)
3596 {
3597         int err;
3598         struct ti_ohci *ohci = pci_get_drvdata(pdev);
3599
3600         if (!ohci) {
3601                 printk(KERN_ERR "%s: tried to resume nonexisting host\n",
3602                        OHCI1394_DRIVER_NAME);
3603                 return -ENXIO;
3604         }
3605         DBGMSG("resume called");
3606
3607 /* PowerMac resume code comes first */
3608 #ifdef CONFIG_PPC_PMAC
3609         if (machine_is(powermac)) {
3610                 struct device_node *ofn = pci_device_to_OF_node(pdev);
3611
3612                 if (ofn)
3613                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
3614         }
3615 #endif /* CONFIG_PPC_PMAC */
3616
3617         pci_set_power_state(pdev, PCI_D0);
3618         pci_restore_state(pdev);
3619         err = pci_enable_device(pdev);
3620         if (err) {
3621                 PRINT(KERN_ERR, "pci_enable_device failed with %d", err);
3622                 return err;
3623         }
3624
3625         /* See ohci1394_pci_probe() for comments on this sequence */
3626         ohci_soft_reset(ohci);
3627         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_LPS);
3628         reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff);
3629         reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff);
3630         mdelay(50);
3631         ohci_initialize(ohci);
3632
3633         return 0;
3634 }
3635 #endif /* CONFIG_PM */
3636
3637 #define PCI_CLASS_FIREWIRE_OHCI     ((PCI_CLASS_SERIAL_FIREWIRE << 8) | 0x10)
3638
3639 static struct pci_device_id ohci1394_pci_tbl[] = {
3640         {
3641                 .class =        PCI_CLASS_FIREWIRE_OHCI,
3642                 .class_mask =   PCI_ANY_ID,
3643                 .vendor =       PCI_ANY_ID,
3644                 .device =       PCI_ANY_ID,
3645                 .subvendor =    PCI_ANY_ID,
3646                 .subdevice =    PCI_ANY_ID,
3647         },
3648         { 0, },
3649 };
3650
3651 MODULE_DEVICE_TABLE(pci, ohci1394_pci_tbl);
3652
3653 static struct pci_driver ohci1394_pci_driver = {
3654         .name =         OHCI1394_DRIVER_NAME,
3655         .id_table =     ohci1394_pci_tbl,
3656         .probe =        ohci1394_pci_probe,
3657         .remove =       ohci1394_pci_remove,
3658 #ifdef CONFIG_PM
3659         .resume =       ohci1394_pci_resume,
3660         .suspend =      ohci1394_pci_suspend,
3661 #endif
3662 };
3663
3664 /***********************************
3665  * OHCI1394 Video Interface        *
3666  ***********************************/
3667
3668 /* essentially the only purpose of this code is to allow another
3669    module to hook into ohci's interrupt handler */
3670
3671 int ohci1394_stop_context(struct ti_ohci *ohci, int reg, char *msg)
3672 {
3673         int i=0;
3674
3675         /* stop the channel program if it's still running */
3676         reg_write(ohci, reg, 0x8000);
3677
3678         /* Wait until it effectively stops */
3679         while (reg_read(ohci, reg) & 0x400) {
3680                 i++;
3681                 if (i>5000) {
3682                         PRINT(KERN_ERR,
3683                               "Runaway loop while stopping context: %s...", msg ? msg : "");
3684                         return 1;
3685                 }
3686
3687                 mb();
3688                 udelay(10);
3689         }
3690         if (msg) PRINT(KERN_ERR, "%s: dma prg stopped", msg);
3691         return 0;
3692 }
3693
3694 void ohci1394_init_iso_tasklet(struct ohci1394_iso_tasklet *tasklet, int type,
3695                                void (*func)(unsigned long), unsigned long data)
3696 {
3697         tasklet_init(&tasklet->tasklet, func, data);
3698         tasklet->type = type;
3699         /* We init the tasklet->link field, so we can list_del() it
3700          * without worrying whether it was added to the list or not. */
3701         INIT_LIST_HEAD(&tasklet->link);
3702 }
3703
3704 int ohci1394_register_iso_tasklet(struct ti_ohci *ohci,
3705                                   struct ohci1394_iso_tasklet *tasklet)
3706 {
3707         unsigned long flags, *usage;
3708         int n, i, r = -EBUSY;
3709
3710         if (tasklet->type == OHCI_ISO_TRANSMIT) {
3711                 n = ohci->nb_iso_xmit_ctx;
3712                 usage = &ohci->it_ctx_usage;
3713         }
3714         else {
3715                 n = ohci->nb_iso_rcv_ctx;
3716                 usage = &ohci->ir_ctx_usage;
3717
3718                 /* only one receive context can be multichannel (OHCI sec 10.4.1) */
3719                 if (tasklet->type == OHCI_ISO_MULTICHANNEL_RECEIVE) {
3720                         if (test_and_set_bit(0, &ohci->ir_multichannel_used)) {
3721                                 return r;
3722                         }
3723                 }
3724         }
3725
3726         spin_lock_irqsave(&ohci->iso_tasklet_list_lock, flags);
3727
3728         for (i = 0; i < n; i++)
3729                 if (!test_and_set_bit(i, usage)) {
3730                         tasklet->context = i;
3731                         list_add_tail(&tasklet->link, &ohci->iso_tasklet_list);
3732                         r = 0;
3733                         break;
3734                 }
3735
3736         spin_unlock_irqrestore(&ohci->iso_tasklet_list_lock, flags);
3737
3738         return r;
3739 }
3740
3741 void ohci1394_unregister_iso_tasklet(struct ti_ohci *ohci,
3742                                      struct ohci1394_iso_tasklet *tasklet)
3743 {
3744         unsigned long flags;
3745
3746         tasklet_kill(&tasklet->tasklet);
3747
3748         spin_lock_irqsave(&ohci->iso_tasklet_list_lock, flags);
3749
3750         if (tasklet->type == OHCI_ISO_TRANSMIT)
3751                 clear_bit(tasklet->context, &ohci->it_ctx_usage);
3752         else {
3753                 clear_bit(tasklet->context, &ohci->ir_ctx_usage);
3754
3755                 if (tasklet->type == OHCI_ISO_MULTICHANNEL_RECEIVE) {
3756                         clear_bit(0, &ohci->ir_multichannel_used);
3757                 }
3758         }
3759
3760         list_del(&tasklet->link);
3761
3762         spin_unlock_irqrestore(&ohci->iso_tasklet_list_lock, flags);
3763 }
3764
3765 EXPORT_SYMBOL(ohci1394_stop_context);
3766 EXPORT_SYMBOL(ohci1394_init_iso_tasklet);
3767 EXPORT_SYMBOL(ohci1394_register_iso_tasklet);
3768 EXPORT_SYMBOL(ohci1394_unregister_iso_tasklet);
3769
3770 /***********************************
3771  * General module initialization   *
3772  ***********************************/
3773
3774 MODULE_AUTHOR("Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>");
3775 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE-1394 controllers");
3776 MODULE_LICENSE("GPL");
3777
3778 static void __exit ohci1394_cleanup (void)
3779 {
3780         pci_unregister_driver(&ohci1394_pci_driver);
3781 }
3782
3783 static int __init ohci1394_init(void)
3784 {
3785         return pci_register_driver(&ohci1394_pci_driver);
3786 }
3787
3788 /* Register before most other device drivers.
3789  * Useful for remote debugging via physical DMA, e.g. using firescope. */
3790 fs_initcall(ohci1394_init);
3791 module_exit(ohci1394_cleanup);