2 * intel_idle.c - native hardware idle loop for modern Intel processors
4 * Copyright (c) 2010, Intel Corporation.
5 * Len Brown <len.brown@intel.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
22 * intel_idle is a cpuidle driver that loads on specific Intel processors
23 * in lieu of the legacy ACPI processor_idle driver. The intent is to
24 * make Linux more efficient on these processors, as intel_idle knows
25 * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
31 * All CPUs have same idle states as boot CPU
33 * Chipset BM_STS (bus master status) bit is a NOP
34 * for preventing entry into deep C-stats
40 * The driver currently initializes for_each_online_cpu() upon modprobe.
41 * It it unaware of subsequent processors hot-added to the system.
42 * This means that if you boot with maxcpus=n and later online
43 * processors above n, those processors will use C1 only.
45 * ACPI has a .suspend hack to turn off deep c-statees during suspend
46 * to avoid complications with the lapic timer workaround.
47 * Have not seen issues with suspend, but may need same workaround here.
49 * There is currently no kernel-based automatic probing/loading mechanism
50 * if the driver is built as a module.
53 /* un-comment DEBUG to enable pr_debug() statements */
56 #include <linux/kernel.h>
57 #include <linux/cpuidle.h>
58 #include <linux/clockchips.h>
59 #include <linux/hrtimer.h> /* ktime_get_real() */
60 #include <trace/events/power.h>
61 #include <linux/sched.h>
62 #include <linux/notifier.h>
63 #include <linux/cpu.h>
64 #include <linux/module.h>
65 #include <asm/mwait.h>
68 #define INTEL_IDLE_VERSION "0.4"
69 #define PREFIX "intel_idle: "
71 static struct cpuidle_driver intel_idle_driver = {
75 /* intel_idle.max_cstate=0 disables driver */
76 static int max_cstate = MWAIT_MAX_NUM_CSTATES - 1;
78 static unsigned int mwait_substates;
80 #define LAPIC_TIMER_ALWAYS_RELIABLE 0xFFFFFFFF
81 /* Reliable LAPIC Timer States, bit 1 for C1 etc. */
82 static unsigned int lapic_timer_reliable_states = (1 << 1); /* Default to only C1 */
84 static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
85 static int intel_idle(struct cpuidle_device *dev,
86 struct cpuidle_driver *drv, int index);
88 static struct cpuidle_state *cpuidle_state_table;
91 * Hardware C-state auto-demotion may not always be optimal.
92 * Indicate which enable bits to clear here.
94 static unsigned long long auto_demotion_disable_flags;
97 * Set this flag for states where the HW flushes the TLB for us
98 * and so we don't need cross-calls to keep it consistent.
99 * If this flag is set, SW flushes the TLB, so even if the
100 * HW doesn't do the flushing, this flag is safe to use.
102 #define CPUIDLE_FLAG_TLB_FLUSHED 0x10000
105 * States are indexed by the cstate number,
106 * which is also the index into the MWAIT hint array.
107 * Thus C0 is a dummy.
109 static struct cpuidle_state nehalem_cstates[MWAIT_MAX_NUM_CSTATES] = {
113 .desc = "MWAIT 0x00",
114 .flags = CPUIDLE_FLAG_TIME_VALID,
116 .target_residency = 6,
117 .enter = &intel_idle },
120 .desc = "MWAIT 0x10",
121 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
123 .target_residency = 80,
124 .enter = &intel_idle },
127 .desc = "MWAIT 0x20",
128 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
130 .target_residency = 800,
131 .enter = &intel_idle },
134 static struct cpuidle_state snb_cstates[MWAIT_MAX_NUM_CSTATES] = {
138 .desc = "MWAIT 0x00",
139 .flags = CPUIDLE_FLAG_TIME_VALID,
141 .target_residency = 1,
142 .enter = &intel_idle },
145 .desc = "MWAIT 0x10",
146 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
148 .target_residency = 211,
149 .enter = &intel_idle },
152 .desc = "MWAIT 0x20",
153 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
155 .target_residency = 345,
156 .enter = &intel_idle },
159 .desc = "MWAIT 0x30",
160 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
162 .target_residency = 345,
163 .enter = &intel_idle },
166 static struct cpuidle_state ivb_cstates[MWAIT_MAX_NUM_CSTATES] = {
170 .desc = "MWAIT 0x00",
171 .flags = CPUIDLE_FLAG_TIME_VALID,
173 .target_residency = 1,
174 .enter = &intel_idle },
177 .desc = "MWAIT 0x10",
178 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
180 .target_residency = 156,
181 .enter = &intel_idle },
184 .desc = "MWAIT 0x20",
185 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
187 .target_residency = 300,
188 .enter = &intel_idle },
191 .desc = "MWAIT 0x30",
192 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
194 .target_residency = 300,
195 .enter = &intel_idle },
198 static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = {
202 .desc = "MWAIT 0x00",
203 .flags = CPUIDLE_FLAG_TIME_VALID,
205 .target_residency = 4,
206 .enter = &intel_idle },
209 .desc = "MWAIT 0x10",
210 .flags = CPUIDLE_FLAG_TIME_VALID,
212 .target_residency = 80,
213 .enter = &intel_idle },
217 .desc = "MWAIT 0x30",
218 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
220 .target_residency = 400,
221 .enter = &intel_idle },
225 .desc = "MWAIT 0x52",
226 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
228 .target_residency = 560,
229 .enter = &intel_idle },
232 static int get_driver_data(int cstate)
237 case 1: /* MWAIT C1 */
240 case 2: /* MWAIT C2 */
243 case 3: /* MWAIT C3 */
246 case 4: /* MWAIT C4 */
249 case 5: /* MWAIT C5 */
252 case 6: /* MWAIT C6 */
263 * @dev: cpuidle_device
264 * @drv: cpuidle driver
265 * @index: index of cpuidle state
268 static int intel_idle(struct cpuidle_device *dev,
269 struct cpuidle_driver *drv, int index)
271 unsigned long ecx = 1; /* break on interrupt flag */
272 struct cpuidle_state *state = &drv->states[index];
273 struct cpuidle_state_usage *state_usage = &dev->states_usage[index];
274 unsigned long eax = (unsigned long)cpuidle_get_statedata(state_usage);
276 ktime_t kt_before, kt_after;
278 int cpu = smp_processor_id();
280 cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1;
285 * leave_mm() to avoid costly and often unnecessary wakeups
286 * for flushing the user TLB's associated with the active mm.
288 if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED)
291 if (!(lapic_timer_reliable_states & (1 << (cstate))))
292 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
294 kt_before = ktime_get_real();
296 stop_critical_timings();
297 if (!need_resched()) {
299 __monitor((void *)¤t_thread_info()->flags, 0, 0);
305 start_critical_timings();
307 kt_after = ktime_get_real();
308 usec_delta = ktime_to_us(ktime_sub(kt_after, kt_before));
312 if (!(lapic_timer_reliable_states & (1 << (cstate))))
313 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
315 /* Update cpuidle counters */
316 dev->last_residency = (int)usec_delta;
321 static void __setup_broadcast_timer(void *arg)
323 unsigned long reason = (unsigned long)arg;
324 int cpu = smp_processor_id();
327 CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF;
329 clockevents_notify(reason, &cpu);
332 static int setup_broadcast_cpuhp_notify(struct notifier_block *n,
333 unsigned long action, void *hcpu)
335 int hotcpu = (unsigned long)hcpu;
337 switch (action & 0xf) {
339 smp_call_function_single(hotcpu, __setup_broadcast_timer,
346 static struct notifier_block setup_broadcast_notifier = {
347 .notifier_call = setup_broadcast_cpuhp_notify,
350 static void auto_demotion_disable(void *dummy)
352 unsigned long long msr_bits;
354 rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
355 msr_bits &= ~auto_demotion_disable_flags;
356 wrmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
362 static int intel_idle_probe(void)
364 unsigned int eax, ebx, ecx;
366 if (max_cstate == 0) {
367 pr_debug(PREFIX "disabled\n");
371 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
374 if (!boot_cpu_has(X86_FEATURE_MWAIT))
377 if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
380 cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
382 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
383 !(ecx & CPUID5_ECX_INTERRUPT_BREAK) ||
387 pr_debug(PREFIX "MWAIT substates: 0x%x\n", mwait_substates);
390 if (boot_cpu_data.x86 != 6) /* family 6 */
393 switch (boot_cpu_data.x86_model) {
395 case 0x1A: /* Core i7, Xeon 5500 series */
396 case 0x1E: /* Core i7 and i5 Processor - Lynnfield Jasper Forest */
397 case 0x1F: /* Core i7 and i5 Processor - Nehalem */
398 case 0x2E: /* Nehalem-EX Xeon */
399 case 0x2F: /* Westmere-EX Xeon */
400 case 0x25: /* Westmere */
401 case 0x2C: /* Westmere */
402 cpuidle_state_table = nehalem_cstates;
403 auto_demotion_disable_flags =
404 (NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE);
407 case 0x1C: /* 28 - Atom Processor */
408 cpuidle_state_table = atom_cstates;
411 case 0x26: /* 38 - Lincroft Atom Processor */
412 cpuidle_state_table = atom_cstates;
413 auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE;
417 case 0x2D: /* SNB Xeon */
418 cpuidle_state_table = snb_cstates;
422 case 0x3E: /* IVB Xeon */
423 cpuidle_state_table = ivb_cstates;
427 pr_debug(PREFIX "does not run on family %d model %d\n",
428 boot_cpu_data.x86, boot_cpu_data.x86_model);
432 if (boot_cpu_has(X86_FEATURE_ARAT)) /* Always Reliable APIC Timer */
433 lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE;
435 on_each_cpu(__setup_broadcast_timer, (void *)true, 1);
437 pr_debug(PREFIX "v" INTEL_IDLE_VERSION
438 " model 0x%X\n", boot_cpu_data.x86_model);
440 pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n",
441 lapic_timer_reliable_states);
446 * intel_idle_cpuidle_devices_uninit()
447 * unregister, free cpuidle_devices
449 static void intel_idle_cpuidle_devices_uninit(void)
452 struct cpuidle_device *dev;
454 for_each_online_cpu(i) {
455 dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
456 cpuidle_unregister_device(dev);
459 free_percpu(intel_idle_cpuidle_devices);
463 * intel_idle_cpuidle_driver_init()
464 * allocate, initialize cpuidle_states
466 static int intel_idle_cpuidle_driver_init(void)
469 struct cpuidle_driver *drv = &intel_idle_driver;
471 drv->state_count = 1;
473 for (cstate = 1; cstate < MWAIT_MAX_NUM_CSTATES; ++cstate) {
476 if (cstate > max_cstate) {
477 printk(PREFIX "max_cstate %d reached\n",
482 /* does the state exist in CPUID.MWAIT? */
483 num_substates = (mwait_substates >> ((cstate) * 4))
484 & MWAIT_SUBSTATE_MASK;
485 if (num_substates == 0)
487 /* is the state not enabled? */
488 if (cpuidle_state_table[cstate].enter == NULL) {
489 /* does the driver not know about the state? */
490 if (*cpuidle_state_table[cstate].name == '\0')
491 pr_debug(PREFIX "unaware of model 0x%x"
493 " contact lenb@kernel.org",
494 boot_cpu_data.x86_model, cstate);
499 !boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
500 mark_tsc_unstable("TSC halts in idle"
501 " states deeper than C2");
503 drv->states[drv->state_count] = /* structure copy */
504 cpuidle_state_table[cstate];
506 drv->state_count += 1;
509 if (auto_demotion_disable_flags)
510 on_each_cpu(auto_demotion_disable, NULL, 1);
517 * intel_idle_cpuidle_devices_init()
518 * allocate, initialize, register cpuidle_devices
520 static int intel_idle_cpuidle_devices_init(void)
523 struct cpuidle_device *dev;
525 intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
526 if (intel_idle_cpuidle_devices == NULL)
529 for_each_online_cpu(i) {
530 dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
532 dev->state_count = 1;
534 for (cstate = 1; cstate < MWAIT_MAX_NUM_CSTATES; ++cstate) {
537 if (cstate > max_cstate) {
538 printk(PREFIX "max_cstate %d reached\n",
543 /* does the state exist in CPUID.MWAIT? */
544 num_substates = (mwait_substates >> ((cstate) * 4))
545 & MWAIT_SUBSTATE_MASK;
546 if (num_substates == 0)
548 /* is the state not enabled? */
549 if (cpuidle_state_table[cstate].enter == NULL) {
553 dev->states_usage[dev->state_count].driver_data =
554 (void *)get_driver_data(cstate);
556 dev->state_count += 1;
560 if (cpuidle_register_device(dev)) {
561 pr_debug(PREFIX "cpuidle_register_device %d failed!\n",
563 intel_idle_cpuidle_devices_uninit();
572 static int __init intel_idle_init(void)
576 /* Do not load intel_idle at all for now if idle= is passed */
577 if (boot_option_idle_override != IDLE_NO_OVERRIDE)
580 retval = intel_idle_probe();
584 intel_idle_cpuidle_driver_init();
585 retval = cpuidle_register_driver(&intel_idle_driver);
587 struct cpuidle_driver *drv = cpuidle_get_driver();
588 printk(KERN_DEBUG PREFIX "intel_idle yielding to %s",
589 drv ? drv->name : "none");
593 retval = intel_idle_cpuidle_devices_init();
595 cpuidle_unregister_driver(&intel_idle_driver);
599 if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
600 register_cpu_notifier(&setup_broadcast_notifier);
605 static void __exit intel_idle_exit(void)
607 intel_idle_cpuidle_devices_uninit();
608 cpuidle_unregister_driver(&intel_idle_driver);
610 if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE) {
611 on_each_cpu(__setup_broadcast_timer, (void *)false, 1);
612 unregister_cpu_notifier(&setup_broadcast_notifier);
618 module_init(intel_idle_init);
619 module_exit(intel_idle_exit);
621 module_param(max_cstate, int, 0444);
623 MODULE_AUTHOR("Len Brown <len.brown@intel.com>");
624 MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION);
625 MODULE_LICENSE("GPL");