2 * intel_idle.c - native hardware idle loop for modern Intel processors
4 * Copyright (c) 2010, Intel Corporation.
5 * Len Brown <len.brown@intel.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
22 * intel_idle is a cpuidle driver that loads on specific Intel processors
23 * in lieu of the legacy ACPI processor_idle driver. The intent is to
24 * make Linux more efficient on these processors, as intel_idle knows
25 * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
31 * All CPUs have same idle states as boot CPU
33 * Chipset BM_STS (bus master status) bit is a NOP
34 * for preventing entry into deep C-stats
40 * The driver currently initializes for_each_online_cpu() upon modprobe.
41 * It it unaware of subsequent processors hot-added to the system.
42 * This means that if you boot with maxcpus=n and later online
43 * processors above n, those processors will use C1 only.
45 * ACPI has a .suspend hack to turn off deep c-statees during suspend
46 * to avoid complications with the lapic timer workaround.
47 * Have not seen issues with suspend, but may need same workaround here.
49 * There is currently no kernel-based automatic probing/loading mechanism
50 * if the driver is built as a module.
53 /* un-comment DEBUG to enable pr_debug() statements */
56 #include <linux/kernel.h>
57 #include <linux/cpuidle.h>
58 #include <linux/clockchips.h>
59 #include <linux/hrtimer.h> /* ktime_get_real() */
60 #include <trace/events/power.h>
61 #include <linux/sched.h>
63 #define INTEL_IDLE_VERSION "0.4"
64 #define PREFIX "intel_idle: "
66 #define MWAIT_SUBSTATE_MASK (0xf)
67 #define MWAIT_CSTATE_MASK (0xf)
68 #define MWAIT_SUBSTATE_SIZE (4)
69 #define MWAIT_MAX_NUM_CSTATES 8
70 #define CPUID_MWAIT_LEAF (5)
71 #define CPUID5_ECX_EXTENSIONS_SUPPORTED (0x1)
72 #define CPUID5_ECX_INTERRUPT_BREAK (0x2)
74 static struct cpuidle_driver intel_idle_driver = {
78 /* intel_idle.max_cstate=0 disables driver */
79 static int max_cstate = MWAIT_MAX_NUM_CSTATES - 1;
80 static int power_policy = 7; /* 0 = max perf; 15 = max powersave */
82 static unsigned int substates;
83 static int (*choose_substate)(int);
85 /* Reliable LAPIC Timer States, bit 1 for C1 etc. */
86 static unsigned int lapic_timer_reliable_states = (1 << 1); /* Default to only C1 */
88 static struct cpuidle_device *intel_idle_cpuidle_devices;
89 static int intel_idle(struct cpuidle_device *dev, struct cpuidle_state *state);
91 static struct cpuidle_state *cpuidle_state_table;
94 * States are indexed by the cstate number,
95 * which is also the index into the MWAIT hint array.
98 static struct cpuidle_state nehalem_cstates[MWAIT_MAX_NUM_CSTATES] = {
102 .desc = "MWAIT 0x00",
103 .driver_data = (void *) 0x00,
104 .flags = CPUIDLE_FLAG_TIME_VALID,
107 .target_residency = 6,
108 .enter = &intel_idle },
111 .desc = "MWAIT 0x10",
112 .driver_data = (void *) 0x10,
113 .flags = CPUIDLE_FLAG_TIME_VALID,
116 .target_residency = 80,
117 .enter = &intel_idle },
120 .desc = "MWAIT 0x20",
121 .driver_data = (void *) 0x20,
122 .flags = CPUIDLE_FLAG_TIME_VALID,
125 .target_residency = 800,
126 .enter = &intel_idle },
129 static struct cpuidle_state snb_cstates[MWAIT_MAX_NUM_CSTATES] = {
133 .desc = "MWAIT 0x00",
134 .driver_data = (void *) 0x00,
135 .flags = CPUIDLE_FLAG_TIME_VALID,
137 .target_residency = 4,
138 .enter = &intel_idle },
141 .desc = "MWAIT 0x10",
142 .driver_data = (void *) 0x10,
143 .flags = CPUIDLE_FLAG_TIME_VALID,
145 .target_residency = 160,
146 .enter = &intel_idle },
149 .desc = "MWAIT 0x20",
150 .driver_data = (void *) 0x20,
151 .flags = CPUIDLE_FLAG_TIME_VALID,
153 .target_residency = 208,
154 .enter = &intel_idle },
157 .desc = "MWAIT 0x30",
158 .driver_data = (void *) 0x30,
159 .flags = CPUIDLE_FLAG_TIME_VALID,
161 .target_residency = 300,
162 .enter = &intel_idle },
165 static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = {
169 .desc = "MWAIT 0x00",
170 .driver_data = (void *) 0x00,
171 .flags = CPUIDLE_FLAG_TIME_VALID,
174 .target_residency = 4,
175 .enter = &intel_idle },
178 .desc = "MWAIT 0x10",
179 .driver_data = (void *) 0x10,
180 .flags = CPUIDLE_FLAG_TIME_VALID,
183 .target_residency = 80,
184 .enter = &intel_idle },
188 .desc = "MWAIT 0x30",
189 .driver_data = (void *) 0x30,
190 .flags = CPUIDLE_FLAG_TIME_VALID,
193 .target_residency = 400,
194 .enter = &intel_idle },
198 .desc = "MWAIT 0x40",
199 .driver_data = (void *) 0x40,
200 .flags = CPUIDLE_FLAG_TIME_VALID,
203 .target_residency = 800,
204 .enter = NULL }, /* disabled */
208 * choose_tunable_substate()
210 * Run-time decision on which C-state substate to invoke
211 * If power_policy = 0, choose shallowest substate (0)
212 * If power_policy = 15, choose deepest substate
213 * If power_policy = middle, choose middle substate etc.
215 static int choose_tunable_substate(int cstate)
217 unsigned int num_substates;
218 unsigned int substate_choice;
220 power_policy &= 0xF; /* valid range: 0-15 */
221 cstate &= 7; /* valid range: 0-7 */
223 num_substates = (substates >> ((cstate) * 4)) & MWAIT_SUBSTATE_MASK;
225 if (num_substates <= 1)
228 substate_choice = ((power_policy + (power_policy + 1) *
229 (num_substates - 1)) / 16);
231 return substate_choice;
235 * choose_zero_substate()
237 static int choose_zero_substate(int cstate)
244 * @dev: cpuidle_device
245 * @state: cpuidle state
248 static int intel_idle(struct cpuidle_device *dev, struct cpuidle_state *state)
250 unsigned long ecx = 1; /* break on interrupt flag */
251 unsigned long eax = (unsigned long)cpuidle_get_statedata(state);
253 ktime_t kt_before, kt_after;
255 int cpu = smp_processor_id();
257 cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1;
259 eax = eax + (choose_substate)(cstate);
263 if (!(lapic_timer_reliable_states & (1 << (cstate))))
264 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
266 kt_before = ktime_get_real();
268 stop_critical_timings();
270 trace_power_start(POWER_CSTATE, (eax >> 4) + 1);
272 if (!need_resched()) {
274 __monitor((void *)¤t_thread_info()->flags, 0, 0);
280 start_critical_timings();
282 kt_after = ktime_get_real();
283 usec_delta = ktime_to_us(ktime_sub(kt_after, kt_before));
287 if (!(lapic_timer_reliable_states & (1 << (cstate))))
288 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
296 static int intel_idle_probe(void)
298 unsigned int eax, ebx, ecx, edx;
300 if (max_cstate == 0) {
301 pr_debug(PREFIX "disabled\n");
305 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
308 if (!boot_cpu_has(X86_FEATURE_MWAIT))
311 if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
314 cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &edx);
316 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
317 !(ecx & CPUID5_ECX_INTERRUPT_BREAK))
320 if (substates == 0) /* can over-ride via modparam */
324 pr_debug(PREFIX "MWAIT substates: 0x%x\n", substates);
326 if (boot_cpu_has(X86_FEATURE_ARAT)) /* Always Reliable APIC Timer */
327 lapic_timer_reliable_states = 0xFFFFFFFF;
329 if (boot_cpu_data.x86 != 6) /* family 6 */
332 switch (boot_cpu_data.x86_model) {
334 case 0x1A: /* Core i7, Xeon 5500 series */
335 case 0x1E: /* Core i7 and i5 Processor - Lynnfield Jasper Forest */
336 case 0x1F: /* Core i7 and i5 Processor - Nehalem */
337 case 0x2E: /* Nehalem-EX Xeon */
338 lapic_timer_reliable_states = (1 << 1); /* C1 */
340 case 0x25: /* Westmere */
341 case 0x2C: /* Westmere */
342 cpuidle_state_table = nehalem_cstates;
343 choose_substate = choose_tunable_substate;
346 case 0x1C: /* 28 - Atom Processor */
347 lapic_timer_reliable_states = (1 << 2) | (1 << 1); /* C2, C1 */
348 cpuidle_state_table = atom_cstates;
349 choose_substate = choose_zero_substate;
353 case 0x2D: /* SNB Xeon */
354 cpuidle_state_table = snb_cstates;
355 choose_substate = choose_zero_substate;
358 case 0x17: /* 23 - Core 2 Duo */
359 lapic_timer_reliable_states = (1 << 2) | (1 << 1); /* C2, C1 */
363 pr_debug(PREFIX "does not run on family %d model %d\n",
364 boot_cpu_data.x86, boot_cpu_data.x86_model);
368 pr_debug(PREFIX "v" INTEL_IDLE_VERSION
369 " model 0x%X\n", boot_cpu_data.x86_model);
371 pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n",
372 lapic_timer_reliable_states);
377 * intel_idle_cpuidle_devices_uninit()
378 * unregister, free cpuidle_devices
380 static void intel_idle_cpuidle_devices_uninit(void)
383 struct cpuidle_device *dev;
385 for_each_online_cpu(i) {
386 dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
387 cpuidle_unregister_device(dev);
390 free_percpu(intel_idle_cpuidle_devices);
394 * intel_idle_cpuidle_devices_init()
395 * allocate, initialize, register cpuidle_devices
397 static int intel_idle_cpuidle_devices_init(void)
400 struct cpuidle_device *dev;
402 intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
403 if (intel_idle_cpuidle_devices == NULL)
406 for_each_online_cpu(i) {
407 dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
409 dev->state_count = 1;
411 for (cstate = 1; cstate < MWAIT_MAX_NUM_CSTATES; ++cstate) {
414 if (cstate > max_cstate) {
415 printk(PREFIX "max_cstate %d reached\n",
420 /* does the state exist in CPUID.MWAIT? */
421 num_substates = (substates >> ((cstate) * 4))
422 & MWAIT_SUBSTATE_MASK;
423 if (num_substates == 0)
425 /* is the state not enabled? */
426 if (cpuidle_state_table[cstate].enter == NULL) {
427 /* does the driver not know about the state? */
428 if (*cpuidle_state_table[cstate].name == '\0')
429 pr_debug(PREFIX "unaware of model 0x%x"
431 " contact lenb@kernel.org",
432 boot_cpu_data.x86_model, cstate);
437 !boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
438 mark_tsc_unstable("TSC halts in idle"
439 " states deeper than C2");
441 dev->states[dev->state_count] = /* structure copy */
442 cpuidle_state_table[cstate];
444 dev->state_count += 1;
448 if (cpuidle_register_device(dev)) {
449 pr_debug(PREFIX "cpuidle_register_device %d failed!\n",
451 intel_idle_cpuidle_devices_uninit();
460 static int __init intel_idle_init(void)
464 retval = intel_idle_probe();
468 retval = cpuidle_register_driver(&intel_idle_driver);
470 printk(KERN_DEBUG PREFIX "intel_idle yielding to %s",
471 cpuidle_get_driver()->name);
475 retval = intel_idle_cpuidle_devices_init();
477 cpuidle_unregister_driver(&intel_idle_driver);
484 static void __exit intel_idle_exit(void)
486 intel_idle_cpuidle_devices_uninit();
487 cpuidle_unregister_driver(&intel_idle_driver);
492 module_init(intel_idle_init);
493 module_exit(intel_idle_exit);
495 module_param(power_policy, int, 0644);
496 module_param(max_cstate, int, 0444);
498 module_param(substates, int, 0444);
501 MODULE_AUTHOR("Len Brown <len.brown@intel.com>");
502 MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION);
503 MODULE_LICENSE("GPL");