drivers/idle/intel_idle.c

   1 /*
   2  * intel_idle.c - native hardware idle loop for modern Intel processors
   3  *
   4  * Copyright (c) 2010, Intel Corporation.
   5  * Len Brown <len.brown@intel.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program; if not, write to the Free Software Foundation, Inc.,
  18  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19  */
  20
  21 /*
  22  * intel_idle is a cpuidle driver that loads on specific Intel processors
  23  * in lieu of the legacy ACPI processor_idle driver.  The intent is to
  24  * make Linux more efficient on these processors, as intel_idle knows
  25  * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
  26  */
  27
  28 /*
  29  * Design Assumptions
  30  *
  31  * All CPUs have same idle states as boot CPU
  32  *
  33  * Chipset BM_STS (bus master status) bit is a NOP
  34  *      for preventing entry into deep C-stats
  35  */
  36
  37 /*
  38  * Known limitations
  39  *
  40  * The driver currently initializes for_each_online_cpu() upon modprobe.
  41  * It it unaware of subsequent processors hot-added to the system.
  42  * This means that if you boot with maxcpus=n and later online
  43  * processors above n, those processors will use C1 only.
  44  *
  45  * ACPI has a .suspend hack to turn off deep c-statees during suspend
  46  * to avoid complications with the lapic timer workaround.
  47  * Have not seen issues with suspend, but may need same workaround here.
  48  *
  49  * There is currently no kernel-based automatic probing/loading mechanism
  50  * if the driver is built as a module.
  51  */
  52
  53 /* un-comment DEBUG to enable pr_debug() statements */
  54 #define DEBUG
  55
  56 #include <linux/kernel.h>
  57 #include <linux/cpuidle.h>
  58 #include <linux/clockchips.h>
  59 #include <linux/hrtimer.h>      /* ktime_get_real() */
  60 #include <trace/events/power.h>
  61 #include <linux/sched.h>
  62
  63 #define INTEL_IDLE_VERSION "0.4"
  64 #define PREFIX "intel_idle: "
  65
  66 #define MWAIT_SUBSTATE_MASK     (0xf)
  67 #define MWAIT_CSTATE_MASK       (0xf)
  68 #define MWAIT_SUBSTATE_SIZE     (4)
  69 #define MWAIT_MAX_NUM_CSTATES   8
  70 #define CPUID_MWAIT_LEAF (5)
  71 #define CPUID5_ECX_EXTENSIONS_SUPPORTED (0x1)
  72 #define CPUID5_ECX_INTERRUPT_BREAK      (0x2)
  73
  74 static struct cpuidle_driver intel_idle_driver = {
  75         .name = "intel_idle",
  76         .owner = THIS_MODULE,
  77 };
  78 /* intel_idle.max_cstate=0 disables driver */
  79 static int max_cstate = MWAIT_MAX_NUM_CSTATES - 1;
  80
  81 static unsigned int mwait_substates;
  82
  83 /* Reliable LAPIC Timer States, bit 1 for C1 etc.  */
  84 static unsigned int lapic_timer_reliable_states;
  85
  86 static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
  87 static int intel_idle(struct cpuidle_device *dev, struct cpuidle_state *state);
  88
  89 static struct cpuidle_state *cpuidle_state_table;
  90
  91 /*
  92  * States are indexed by the cstate number,
  93  * which is also the index into the MWAIT hint array.
  94  * Thus C0 is a dummy.
  95  */
  96 static struct cpuidle_state nehalem_cstates[MWAIT_MAX_NUM_CSTATES] = {
  97         { /* MWAIT C0 */ },
  98         { /* MWAIT C1 */
  99                 .name = "NHM-C1",
 100                 .desc = "MWAIT 0x00",
 101                 .driver_data = (void *) 0x00,
 102                 .flags = CPUIDLE_FLAG_TIME_VALID,
 103                 .exit_latency = 3,
 104                 .power_usage = 1000,
 105                 .target_residency = 6,
 106                 .enter = &intel_idle },
 107         { /* MWAIT C2 */
 108                 .name = "NHM-C3",
 109                 .desc = "MWAIT 0x10",
 110                 .driver_data = (void *) 0x10,
 111                 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 112                 .exit_latency = 20,
 113                 .power_usage = 500,
 114                 .target_residency = 80,
 115                 .enter = &intel_idle },
 116         { /* MWAIT C3 */
 117                 .name = "NHM-C6",
 118                 .desc = "MWAIT 0x20",
 119                 .driver_data = (void *) 0x20,
 120                 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 121                 .exit_latency = 200,
 122                 .power_usage = 350,
 123                 .target_residency = 800,
 124                 .enter = &intel_idle },
 125 };
 126
 127 static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = {
 128         { /* MWAIT C0 */ },
 129         { /* MWAIT C1 */
 130                 .name = "ATM-C1",
 131                 .desc = "MWAIT 0x00",
 132                 .driver_data = (void *) 0x00,
 133                 .flags = CPUIDLE_FLAG_TIME_VALID,
 134                 .exit_latency = 1,
 135                 .power_usage = 1000,
 136                 .target_residency = 4,
 137                 .enter = &intel_idle },
 138         { /* MWAIT C2 */
 139                 .name = "ATM-C2",
 140                 .desc = "MWAIT 0x10",
 141                 .driver_data = (void *) 0x10,
 142                 .flags = CPUIDLE_FLAG_TIME_VALID,
 143                 .exit_latency = 20,
 144                 .power_usage = 500,
 145                 .target_residency = 80,
 146                 .enter = &intel_idle },
 147         { /* MWAIT C3 */ },
 148         { /* MWAIT C4 */
 149                 .name = "ATM-C4",
 150                 .desc = "MWAIT 0x30",
 151                 .driver_data = (void *) 0x30,
 152                 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 153                 .exit_latency = 100,
 154                 .power_usage = 250,
 155                 .target_residency = 400,
 156                 .enter = &intel_idle },
 157         { /* MWAIT C5 */ },
 158         { /* MWAIT C6 */
 159                 .name = "ATM-C6",
 160                 .desc = "MWAIT 0x52",
 161                 .driver_data = (void *) 0x52,
 162                 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 163                 .exit_latency = 140,
 164                 .power_usage = 150,
 165                 .target_residency = 560,
 166                 .enter = &intel_idle },
 167 };
 168
 169 /**
 170  * intel_idle
 171  * @dev: cpuidle_device
 172  * @state: cpuidle state
 173  *
 174  */
 175 static int intel_idle(struct cpuidle_device *dev, struct cpuidle_state *state)
 176 {
 177         unsigned long ecx = 1; /* break on interrupt flag */
 178         unsigned long eax = (unsigned long)cpuidle_get_statedata(state);
 179         unsigned int cstate;
 180         ktime_t kt_before, kt_after;
 181         s64 usec_delta;
 182         int cpu = smp_processor_id();
 183
 184         cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1;
 185
 186         local_irq_disable();
 187
 188         /*
 189          * If the state flag indicates that the TLB will be flushed or if this
 190          * is the deepest c-state supported, do a voluntary leave mm to avoid
 191          * costly and mostly unnecessary wakeups for flushing the user TLB's
 192          * associated with the active mm.
 193          */
 194         if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED ||
 195             (&dev->states[dev->state_count - 1] == state))
 196                 leave_mm(cpu);
 197
 198         if (!(lapic_timer_reliable_states & (1 << (cstate))))
 199                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
 200
 201         kt_before = ktime_get_real();
 202
 203         stop_critical_timings();
 204 #ifndef MODULE
 205         trace_power_start(POWER_CSTATE, (eax >> 4) + 1, cpu);
 206 #endif
 207         if (!need_resched()) {
 208
 209                 __monitor((void *)&current_thread_info()->flags, 0, 0);
 210                 smp_mb();
 211                 if (!need_resched())
 212                         __mwait(eax, ecx);
 213         }
 214
 215         start_critical_timings();
 216
 217         kt_after = ktime_get_real();
 218         usec_delta = ktime_to_us(ktime_sub(kt_after, kt_before));
 219
 220         local_irq_enable();
 221
 222         if (!(lapic_timer_reliable_states & (1 << (cstate))))
 223                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
 224
 225         return usec_delta;
 226 }
 227
 228 /*
 229  * intel_idle_probe()
 230  */
 231 static int intel_idle_probe(void)
 232 {
 233         unsigned int eax, ebx, ecx;
 234
 235         if (max_cstate == 0) {
 236                 pr_debug(PREFIX "disabled\n");
 237                 return -EPERM;
 238         }
 239
 240         if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
 241                 return -ENODEV;
 242
 243         if (!boot_cpu_has(X86_FEATURE_MWAIT))
 244                 return -ENODEV;
 245
 246         if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
 247                 return -ENODEV;
 248
 249         cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
 250
 251         if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
 252                 !(ecx & CPUID5_ECX_INTERRUPT_BREAK))
 253                         return -ENODEV;
 254
 255         pr_debug(PREFIX "MWAIT substates: 0x%x\n", mwait_substates);
 256
 257         if (boot_cpu_has(X86_FEATURE_ARAT))     /* Always Reliable APIC Timer */
 258                 lapic_timer_reliable_states = 0xFFFFFFFF;
 259
 260         if (boot_cpu_data.x86 != 6)     /* family 6 */
 261                 return -ENODEV;
 262
 263         switch (boot_cpu_data.x86_model) {
 264
 265         case 0x1A:      /* Core i7, Xeon 5500 series */
 266         case 0x1E:      /* Core i7 and i5 Processor - Lynnfield Jasper Forest */
 267         case 0x1F:      /* Core i7 and i5 Processor - Nehalem */
 268         case 0x2E:      /* Nehalem-EX Xeon */
 269         case 0x2F:      /* Westmere-EX Xeon */
 270                 lapic_timer_reliable_states = (1 << 1);  /* C1 */
 271
 272         case 0x25:      /* Westmere */
 273         case 0x2C:      /* Westmere */
 274                 cpuidle_state_table = nehalem_cstates;
 275                 break;
 276
 277         case 0x1C:      /* 28 - Atom Processor */
 278         case 0x26:      /* 38 - Lincroft Atom Processor */
 279                 lapic_timer_reliable_states = (1 << 2) | (1 << 1); /* C2, C1 */
 280                 cpuidle_state_table = atom_cstates;
 281                 break;
 282 #ifdef FUTURE_USE
 283         case 0x17:      /* 23 - Core 2 Duo */
 284                 lapic_timer_reliable_states = (1 << 2) | (1 << 1); /* C2, C1 */
 285 #endif
 286
 287         default:
 288                 pr_debug(PREFIX "does not run on family %d model %d\n",
 289                         boot_cpu_data.x86, boot_cpu_data.x86_model);
 290                 return -ENODEV;
 291         }
 292
 293         pr_debug(PREFIX "v" INTEL_IDLE_VERSION
 294                 " model 0x%X\n", boot_cpu_data.x86_model);
 295
 296         pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n",
 297                 lapic_timer_reliable_states);
 298         return 0;
 299 }
 300
 301 /*
 302  * intel_idle_cpuidle_devices_uninit()
 303  * unregister, free cpuidle_devices
 304  */
 305 static void intel_idle_cpuidle_devices_uninit(void)
 306 {
 307         int i;
 308         struct cpuidle_device *dev;
 309
 310         for_each_online_cpu(i) {
 311                 dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
 312                 cpuidle_unregister_device(dev);
 313         }
 314
 315         free_percpu(intel_idle_cpuidle_devices);
 316         return;
 317 }
 318 /*
 319  * intel_idle_cpuidle_devices_init()
 320  * allocate, initialize, register cpuidle_devices
 321  */
 322 static int intel_idle_cpuidle_devices_init(void)
 323 {
 324         int i, cstate;
 325         struct cpuidle_device *dev;
 326
 327         intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
 328         if (intel_idle_cpuidle_devices == NULL)
 329                 return -ENOMEM;
 330
 331         for_each_online_cpu(i) {
 332                 dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
 333
 334                 dev->state_count = 1;
 335
 336                 for (cstate = 1; cstate < MWAIT_MAX_NUM_CSTATES; ++cstate) {
 337                         int num_substates;
 338
 339                         if (cstate > max_cstate) {
 340                                 printk(PREFIX "max_cstate %d reached\n",
 341                                         max_cstate);
 342                                 break;
 343                         }
 344
 345                         /* does the state exist in CPUID.MWAIT? */
 346                         num_substates = (mwait_substates >> ((cstate) * 4))
 347                                                 & MWAIT_SUBSTATE_MASK;
 348                         if (num_substates == 0)
 349                                 continue;
 350                         /* is the state not enabled? */
 351                         if (cpuidle_state_table[cstate].enter == NULL) {
 352                                 /* does the driver not know about the state? */
 353                                 if (*cpuidle_state_table[cstate].name == '\0')
 354                                         pr_debug(PREFIX "unaware of model 0x%x"
 355                                                 " MWAIT %d please"
 356                                                 " contact lenb@kernel.org",
 357                                         boot_cpu_data.x86_model, cstate);
 358                                 continue;
 359                         }
 360
 361                         if ((cstate > 2) &&
 362                                 !boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
 363                                 mark_tsc_unstable("TSC halts in idle"
 364                                         " states deeper than C2");
 365
 366                         dev->states[dev->state_count] = /* structure copy */
 367                                 cpuidle_state_table[cstate];
 368
 369                         dev->state_count += 1;
 370                 }
 371
 372                 dev->cpu = i;
 373                 if (cpuidle_register_device(dev)) {
 374                         pr_debug(PREFIX "cpuidle_register_device %d failed!\n",
 375                                  i);
 376                         intel_idle_cpuidle_devices_uninit();
 377                         return -EIO;
 378                 }
 379         }
 380
 381         return 0;
 382 }
 383
 384
 385 static int __init intel_idle_init(void)
 386 {
 387         int retval;
 388
 389         retval = intel_idle_probe();
 390         if (retval)
 391                 return retval;
 392
 393         retval = cpuidle_register_driver(&intel_idle_driver);
 394         if (retval) {
 395                 printk(KERN_DEBUG PREFIX "intel_idle yielding to %s",
 396                         cpuidle_get_driver()->name);
 397                 return retval;
 398         }
 399
 400         retval = intel_idle_cpuidle_devices_init();
 401         if (retval) {
 402                 cpuidle_unregister_driver(&intel_idle_driver);
 403                 return retval;
 404         }
 405
 406         return 0;
 407 }
 408
 409 static void __exit intel_idle_exit(void)
 410 {
 411         intel_idle_cpuidle_devices_uninit();
 412         cpuidle_unregister_driver(&intel_idle_driver);
 413
 414         return;
 415 }
 416
 417 module_init(intel_idle_init);
 418 module_exit(intel_idle_exit);
 419
 420 module_param(max_cstate, int, 0444);
 421
 422 MODULE_AUTHOR("Len Brown <len.brown@intel.com>");
 423 MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION);
 424 MODULE_LICENSE("GPL");