drivers/ide/mips/au1xxx-ide.c

   1 /*
   2  * linux/drivers/ide/mips/au1xxx-ide.c  version 01.30.00        Aug. 02 2005
   3  *
   4  * BRIEF MODULE DESCRIPTION
   5  * AMD Alchemy Au1xxx IDE interface routines over the Static Bus
   6  *
   7  * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
   8  *
   9  * This program is free software; you can redistribute it and/or modify it under
  10  * the terms of the GNU General Public License as published by the Free Software
  11  * Foundation; either version 2 of the License, or (at your option) any later
  12  * version.
  13  *
  14  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
  15  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
  16  * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
  17  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  18  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  19  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  20  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  21  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  22  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  23  * POSSIBILITY OF SUCH DAMAGE.
  24  *
  25  * You should have received a copy of the GNU General Public License along with
  26  * this program; if not, write to the Free Software Foundation, Inc.,
  27  * 675 Mass Ave, Cambridge, MA 02139, USA.
  28  *
  29  * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
  30  *       Interface and Linux Device Driver" Application Note.
  31  */
  32 #include <linux/types.h>
  33 #include <linux/module.h>
  34 #include <linux/kernel.h>
  35 #include <linux/delay.h>
  36 #include <linux/platform_device.h>
  37
  38 #include <linux/init.h>
  39 #include <linux/ide.h>
  40 #include <linux/sysdev.h>
  41
  42 #include <linux/dma-mapping.h>
  43
  44 #include "ide-timing.h"
  45
  46 #include <asm/io.h>
  47 #include <asm/mach-au1x00/au1xxx.h>
  48 #include <asm/mach-au1x00/au1xxx_dbdma.h>
  49
  50 #include <asm/mach-au1x00/au1xxx_ide.h>
  51
  52 #define DRV_NAME        "au1200-ide"
  53 #define DRV_VERSION     "1.0"
  54 #define DRV_AUTHOR      "Enrico Walther <enrico.walther@amd.com> / Pete Popov <ppopov@embeddedalley.com>"
  55
  56 /* enable the burstmode in the dbdma */
  57 #define IDE_AU1XXX_BURSTMODE    1
  58
  59 static _auide_hwif auide_hwif;
  60 static int dbdma_init_done;
  61
  62 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
  63
  64 void auide_insw(unsigned long port, void *addr, u32 count)
  65 {
  66         _auide_hwif *ahwif = &auide_hwif;
  67         chan_tab_t *ctp;
  68         au1x_ddma_desc_t *dp;
  69
  70         if(!put_dest_flags(ahwif->rx_chan, (void*)addr, count << 1,
  71                            DDMA_FLAGS_NOIE)) {
  72                 printk(KERN_ERR "%s failed %d\n", __FUNCTION__, __LINE__);
  73                 return;
  74         }
  75         ctp = *((chan_tab_t **)ahwif->rx_chan);
  76         dp = ctp->cur_ptr;
  77         while (dp->dscr_cmd0 & DSCR_CMD0_V)
  78                 ;
  79         ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
  80 }
  81
  82 void auide_outsw(unsigned long port, void *addr, u32 count)
  83 {
  84         _auide_hwif *ahwif = &auide_hwif;
  85         chan_tab_t *ctp;
  86         au1x_ddma_desc_t *dp;
  87
  88         if(!put_source_flags(ahwif->tx_chan, (void*)addr,
  89                              count << 1, DDMA_FLAGS_NOIE)) {
  90                 printk(KERN_ERR "%s failed %d\n", __FUNCTION__, __LINE__);
  91                 return;
  92         }
  93         ctp = *((chan_tab_t **)ahwif->tx_chan);
  94         dp = ctp->cur_ptr;
  95         while (dp->dscr_cmd0 & DSCR_CMD0_V)
  96                 ;
  97         ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
  98 }
  99
 100 #endif
 101
 102 static void auide_tune_drive(ide_drive_t *drive, byte pio)
 103 {
 104         int mem_sttime;
 105         int mem_stcfg;
 106         u8 speed;
 107
 108         /* get the best pio mode for the drive */
 109         pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
 110
 111         printk(KERN_INFO "%s: setting Au1XXX IDE to PIO mode%d\n",
 112                drive->name, pio);
 113
 114         mem_sttime = 0;
 115         mem_stcfg  = au_readl(MEM_STCFG2);
 116
 117         /* set pio mode! */
 118         switch(pio) {
 119         case 0:
 120                 mem_sttime = SBC_IDE_TIMING(PIO0);
 121
 122                 /* set configuration for RCS2# */
 123                 mem_stcfg |= TS_MASK;
 124                 mem_stcfg &= ~TCSOE_MASK;
 125                 mem_stcfg &= ~TOECS_MASK;
 126                 mem_stcfg |= SBC_IDE_PIO0_TCSOE | SBC_IDE_PIO0_TOECS;
 127                 break;
 128
 129         case 1:
 130                 mem_sttime = SBC_IDE_TIMING(PIO1);
 131
 132                 /* set configuration for RCS2# */
 133                 mem_stcfg |= TS_MASK;
 134                 mem_stcfg &= ~TCSOE_MASK;
 135                 mem_stcfg &= ~TOECS_MASK;
 136                 mem_stcfg |= SBC_IDE_PIO1_TCSOE | SBC_IDE_PIO1_TOECS;
 137                 break;
 138
 139         case 2:
 140                 mem_sttime = SBC_IDE_TIMING(PIO2);
 141
 142                 /* set configuration for RCS2# */
 143                 mem_stcfg &= ~TS_MASK;
 144                 mem_stcfg &= ~TCSOE_MASK;
 145                 mem_stcfg &= ~TOECS_MASK;
 146                 mem_stcfg |= SBC_IDE_PIO2_TCSOE | SBC_IDE_PIO2_TOECS;
 147                 break;
 148
 149         case 3:
 150                 mem_sttime = SBC_IDE_TIMING(PIO3);
 151
 152                 /* set configuration for RCS2# */
 153                 mem_stcfg &= ~TS_MASK;
 154                 mem_stcfg &= ~TCSOE_MASK;
 155                 mem_stcfg &= ~TOECS_MASK;
 156                 mem_stcfg |= SBC_IDE_PIO3_TCSOE | SBC_IDE_PIO3_TOECS;
 157
 158                 break;
 159
 160         case 4:
 161                 mem_sttime = SBC_IDE_TIMING(PIO4);
 162
 163                 /* set configuration for RCS2# */
 164                 mem_stcfg &= ~TS_MASK;
 165                 mem_stcfg &= ~TCSOE_MASK;
 166                 mem_stcfg &= ~TOECS_MASK;
 167                 mem_stcfg |= SBC_IDE_PIO4_TCSOE | SBC_IDE_PIO4_TOECS;
 168                 break;
 169         }
 170
 171         au_writel(mem_sttime,MEM_STTIME2);
 172         au_writel(mem_stcfg,MEM_STCFG2);
 173
 174         speed = pio + XFER_PIO_0;
 175         ide_config_drive_speed(drive, speed);
 176 }
 177
 178 static int auide_tune_chipset (ide_drive_t *drive, u8 speed)
 179 {
 180         int mem_sttime;
 181         int mem_stcfg;
 182
 183         mem_sttime = 0;
 184         mem_stcfg  = au_readl(MEM_STCFG2);
 185
 186         if (speed >= XFER_PIO_0 && speed <= XFER_PIO_4) {
 187                 auide_tune_drive(drive, speed - XFER_PIO_0);
 188                 return 0;
 189         }
 190
 191         switch(speed) {
 192 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 193         case XFER_MW_DMA_2:
 194                 mem_sttime = SBC_IDE_TIMING(MDMA2);
 195
 196                 /* set configuration for RCS2# */
 197                 mem_stcfg &= ~TS_MASK;
 198                 mem_stcfg &= ~TCSOE_MASK;
 199                 mem_stcfg &= ~TOECS_MASK;
 200                 mem_stcfg |= SBC_IDE_MDMA2_TCSOE | SBC_IDE_MDMA2_TOECS;
 201
 202                 break;
 203         case XFER_MW_DMA_1:
 204                 mem_sttime = SBC_IDE_TIMING(MDMA1);
 205
 206                 /* set configuration for RCS2# */
 207                 mem_stcfg &= ~TS_MASK;
 208                 mem_stcfg &= ~TCSOE_MASK;
 209                 mem_stcfg &= ~TOECS_MASK;
 210                 mem_stcfg |= SBC_IDE_MDMA1_TCSOE | SBC_IDE_MDMA1_TOECS;
 211
 212                 break;
 213         case XFER_MW_DMA_0:
 214                 mem_sttime = SBC_IDE_TIMING(MDMA0);
 215
 216                 /* set configuration for RCS2# */
 217                 mem_stcfg |= TS_MASK;
 218                 mem_stcfg &= ~TCSOE_MASK;
 219                 mem_stcfg &= ~TOECS_MASK;
 220                 mem_stcfg |= SBC_IDE_MDMA0_TCSOE | SBC_IDE_MDMA0_TOECS;
 221
 222                 break;
 223 #endif
 224         default:
 225                 return 1;
 226         }
 227
 228         if (ide_config_drive_speed(drive, speed))
 229                 return 1;
 230
 231         au_writel(mem_sttime,MEM_STTIME2);
 232         au_writel(mem_stcfg,MEM_STCFG2);
 233
 234         return 0;
 235 }
 236
 237 /*
 238  * Multi-Word DMA + DbDMA functions
 239  */
 240
 241 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 242
 243 static int auide_build_sglist(ide_drive_t *drive,  struct request *rq)
 244 {
 245         ide_hwif_t *hwif = drive->hwif;
 246         _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data;
 247         struct scatterlist *sg = hwif->sg_table;
 248
 249         ide_map_sg(drive, rq);
 250
 251         if (rq_data_dir(rq) == READ)
 252                 hwif->sg_dma_direction = DMA_FROM_DEVICE;
 253         else
 254                 hwif->sg_dma_direction = DMA_TO_DEVICE;
 255
 256         return dma_map_sg(ahwif->dev, sg, hwif->sg_nents,
 257                           hwif->sg_dma_direction);
 258 }
 259
 260 static int auide_build_dmatable(ide_drive_t *drive)
 261 {
 262         int i, iswrite, count = 0;
 263         ide_hwif_t *hwif = HWIF(drive);
 264
 265         struct request *rq = HWGROUP(drive)->rq;
 266
 267         _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data;
 268         struct scatterlist *sg;
 269
 270         iswrite = (rq_data_dir(rq) == WRITE);
 271         /* Save for interrupt context */
 272         ahwif->drive = drive;
 273
 274         /* Build sglist */
 275         hwif->sg_nents = i = auide_build_sglist(drive, rq);
 276
 277         if (!i)
 278                 return 0;
 279
 280         /* fill the descriptors */
 281         sg = hwif->sg_table;
 282         while (i && sg_dma_len(sg)) {
 283                 u32 cur_addr;
 284                 u32 cur_len;
 285
 286                 cur_addr = sg_dma_address(sg);
 287                 cur_len = sg_dma_len(sg);
 288
 289                 while (cur_len) {
 290                         u32 flags = DDMA_FLAGS_NOIE;
 291                         unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
 292
 293                         if (++count >= PRD_ENTRIES) {
 294                                 printk(KERN_WARNING "%s: DMA table too small\n",
 295                                        drive->name);
 296                                 goto use_pio_instead;
 297                         }
 298
 299                         /* Lets enable intr for the last descriptor only */
 300                         if (1==i)
 301                                 flags = DDMA_FLAGS_IE;
 302                         else
 303                                 flags = DDMA_FLAGS_NOIE;
 304
 305                         if (iswrite) {
 306                                 if(!put_source_flags(ahwif->tx_chan,
 307                                                      (void*)(page_address(sg->page)
 308                                                              + sg->offset),
 309                                                      tc, flags)) {
 310                                         printk(KERN_ERR "%s failed %d\n",
 311                                                __FUNCTION__, __LINE__);
 312                                 }
 313                         } else
 314                         {
 315                                 if(!put_dest_flags(ahwif->rx_chan,
 316                                                    (void*)(page_address(sg->page)
 317                                                            + sg->offset),
 318                                                    tc, flags)) {
 319                                         printk(KERN_ERR "%s failed %d\n",
 320                                                __FUNCTION__, __LINE__);
 321                                 }
 322                         }
 323
 324                         cur_addr += tc;
 325                         cur_len -= tc;
 326                 }
 327                 sg++;
 328                 i--;
 329         }
 330
 331         if (count)
 332                 return 1;
 333
 334  use_pio_instead:
 335         dma_unmap_sg(ahwif->dev,
 336                      hwif->sg_table,
 337                      hwif->sg_nents,
 338                      hwif->sg_dma_direction);
 339
 340         return 0; /* revert to PIO for this request */
 341 }
 342
 343 static int auide_dma_end(ide_drive_t *drive)
 344 {
 345         ide_hwif_t *hwif = HWIF(drive);
 346         _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data;
 347
 348         if (hwif->sg_nents) {
 349                 dma_unmap_sg(ahwif->dev, hwif->sg_table, hwif->sg_nents,
 350                              hwif->sg_dma_direction);
 351                 hwif->sg_nents = 0;
 352         }
 353
 354         return 0;
 355 }
 356
 357 static void auide_dma_start(ide_drive_t *drive )
 358 {
 359 }
 360
 361
 362 static void auide_dma_exec_cmd(ide_drive_t *drive, u8 command)
 363 {
 364         /* issue cmd to drive */
 365         ide_execute_command(drive, command, &ide_dma_intr,
 366                             (2*WAIT_CMD), NULL);
 367 }
 368
 369 static int auide_dma_setup(ide_drive_t *drive)
 370 {
 371         struct request *rq = HWGROUP(drive)->rq;
 372
 373         if (!auide_build_dmatable(drive)) {
 374                 ide_map_sg(drive, rq);
 375                 return 1;
 376         }
 377
 378         drive->waiting_for_dma = 1;
 379         return 0;
 380 }
 381
 382 static int auide_dma_check(ide_drive_t *drive)
 383 {
 384         u8 speed;
 385
 386 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 387
 388         if( dbdma_init_done == 0 ){
 389                 auide_hwif.white_list = ide_in_drive_list(drive->id,
 390                                                           dma_white_list);
 391                 auide_hwif.black_list = ide_in_drive_list(drive->id,
 392                                                           dma_black_list);
 393                 auide_hwif.drive = drive;
 394                 auide_ddma_init(&auide_hwif);
 395                 dbdma_init_done = 1;
 396         }
 397 #endif
 398
 399         /* Is the drive in our DMA black list? */
 400
 401         if ( auide_hwif.black_list ) {
 402                 drive->using_dma = 0;
 403
 404                 /* Borrowed the warning message from ide-dma.c */
 405
 406                 printk(KERN_WARNING "%s: Disabling DMA for %s (blacklisted)\n",
 407                        drive->name, drive->id->model);
 408         }
 409         else
 410                 drive->using_dma = 1;
 411
 412         speed = ide_find_best_mode(drive, XFER_PIO | XFER_MWDMA);
 413
 414         if (drive->autodma && (speed & XFER_MODE) != XFER_PIO)
 415                 return 0;
 416
 417         return -1;
 418 }
 419
 420 static int auide_dma_test_irq(ide_drive_t *drive)
 421 {
 422         if (drive->waiting_for_dma == 0)
 423                 printk(KERN_WARNING "%s: ide_dma_test_irq \
 424                                      called while not waiting\n", drive->name);
 425
 426         /* If dbdma didn't execute the STOP command yet, the
 427          * active bit is still set
 428          */
 429         drive->waiting_for_dma++;
 430         if (drive->waiting_for_dma >= DMA_WAIT_TIMEOUT) {
 431                 printk(KERN_WARNING "%s: timeout waiting for ddma to \
 432                                      complete\n", drive->name);
 433                 return 1;
 434         }
 435         udelay(10);
 436         return 0;
 437 }
 438
 439 static void auide_dma_host_on(ide_drive_t *drive)
 440 {
 441 }
 442
 443 static int auide_dma_on(ide_drive_t *drive)
 444 {
 445         drive->using_dma = 1;
 446
 447         return 0;
 448 }
 449
 450 static void auide_dma_host_off(ide_drive_t *drive)
 451 {
 452 }
 453
 454 static void auide_dma_off_quietly(ide_drive_t *drive)
 455 {
 456         drive->using_dma = 0;
 457 }
 458
 459 static int auide_dma_lostirq(ide_drive_t *drive)
 460 {
 461         printk(KERN_ERR "%s: IRQ lost\n", drive->name);
 462         return 0;
 463 }
 464
 465 static void auide_ddma_tx_callback(int irq, void *param)
 466 {
 467         _auide_hwif *ahwif = (_auide_hwif*)param;
 468         ahwif->drive->waiting_for_dma = 0;
 469 }
 470
 471 static void auide_ddma_rx_callback(int irq, void *param)
 472 {
 473         _auide_hwif *ahwif = (_auide_hwif*)param;
 474         ahwif->drive->waiting_for_dma = 0;
 475 }
 476
 477 #endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
 478
 479 static void auide_init_dbdma_dev(dbdev_tab_t *dev, u32 dev_id, u32 tsize, u32 devwidth, u32 flags)
 480 {
 481         dev->dev_id          = dev_id;
 482         dev->dev_physaddr    = (u32)AU1XXX_ATA_PHYS_ADDR;
 483         dev->dev_intlevel    = 0;
 484         dev->dev_intpolarity = 0;
 485         dev->dev_tsize       = tsize;
 486         dev->dev_devwidth    = devwidth;
 487         dev->dev_flags       = flags;
 488 }
 489
 490 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
 491
 492 static int auide_dma_timeout(ide_drive_t *drive)
 493 {
 494 //      printk("%s\n", __FUNCTION__);
 495
 496         printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name);
 497
 498         if (HWIF(drive)->ide_dma_test_irq(drive))
 499                 return 0;
 500
 501         return HWIF(drive)->ide_dma_end(drive);
 502 }
 503
 504
 505 static int auide_ddma_init(_auide_hwif *auide) {
 506
 507         dbdev_tab_t source_dev_tab, target_dev_tab;
 508         u32 dev_id, tsize, devwidth, flags;
 509         ide_hwif_t *hwif = auide->hwif;
 510
 511         dev_id   = AU1XXX_ATA_DDMA_REQ;
 512
 513         if (auide->white_list || auide->black_list) {
 514                 tsize    = 8;
 515                 devwidth = 32;
 516         }
 517         else {
 518                 tsize    = 1;
 519                 devwidth = 16;
 520
 521                 printk(KERN_ERR "au1xxx-ide: %s is not on ide driver whitelist.\n",auide_hwif.drive->id->model);
 522                 printk(KERN_ERR "            please read 'Documentation/mips/AU1xxx_IDE.README'");
 523         }
 524
 525 #ifdef IDE_AU1XXX_BURSTMODE
 526         flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
 527 #else
 528         flags = DEV_FLAGS_SYNC;
 529 #endif
 530
 531         /* setup dev_tab for tx channel */
 532         auide_init_dbdma_dev( &source_dev_tab,
 533                               dev_id,
 534                               tsize, devwidth, DEV_FLAGS_OUT | flags);
 535         auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
 536
 537         auide_init_dbdma_dev( &source_dev_tab,
 538                               dev_id,
 539                               tsize, devwidth, DEV_FLAGS_IN | flags);
 540         auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
 541
 542         /* We also need to add a target device for the DMA */
 543         auide_init_dbdma_dev( &target_dev_tab,
 544                               (u32)DSCR_CMD0_ALWAYS,
 545                               tsize, devwidth, DEV_FLAGS_ANYUSE);
 546         auide->target_dev_id = au1xxx_ddma_add_device(&target_dev_tab);
 547
 548         /* Get a channel for TX */
 549         auide->tx_chan = au1xxx_dbdma_chan_alloc(auide->target_dev_id,
 550                                                  auide->tx_dev_id,
 551                                                  auide_ddma_tx_callback,
 552                                                  (void*)auide);
 553
 554         /* Get a channel for RX */
 555         auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
 556                                                  auide->target_dev_id,
 557                                                  auide_ddma_rx_callback,
 558                                                  (void*)auide);
 559
 560         auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
 561                                                              NUM_DESCRIPTORS);
 562         auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
 563                                                              NUM_DESCRIPTORS);
 564
 565         hwif->dmatable_cpu = dma_alloc_coherent(auide->dev,
 566                                                 PRD_ENTRIES * PRD_BYTES,        /* 1 Page */
 567                                                 &hwif->dmatable_dma, GFP_KERNEL);
 568
 569         au1xxx_dbdma_start( auide->tx_chan );
 570         au1xxx_dbdma_start( auide->rx_chan );
 571
 572         return 0;
 573 }
 574 #else
 575
 576 static int auide_ddma_init( _auide_hwif *auide )
 577 {
 578         dbdev_tab_t source_dev_tab;
 579         int flags;
 580
 581 #ifdef IDE_AU1XXX_BURSTMODE
 582         flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
 583 #else
 584         flags = DEV_FLAGS_SYNC;
 585 #endif
 586
 587         /* setup dev_tab for tx channel */
 588         auide_init_dbdma_dev( &source_dev_tab,
 589                               (u32)DSCR_CMD0_ALWAYS,
 590                               8, 32, DEV_FLAGS_OUT | flags);
 591         auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
 592
 593         auide_init_dbdma_dev( &source_dev_tab,
 594                               (u32)DSCR_CMD0_ALWAYS,
 595                               8, 32, DEV_FLAGS_IN | flags);
 596         auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
 597
 598         /* Get a channel for TX */
 599         auide->tx_chan = au1xxx_dbdma_chan_alloc(DSCR_CMD0_ALWAYS,
 600                                                  auide->tx_dev_id,
 601                                                  NULL,
 602                                                  (void*)auide);
 603
 604         /* Get a channel for RX */
 605         auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
 606                                                  DSCR_CMD0_ALWAYS,
 607                                                  NULL,
 608                                                  (void*)auide);
 609
 610         auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
 611                                                              NUM_DESCRIPTORS);
 612         auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
 613                                                              NUM_DESCRIPTORS);
 614
 615         au1xxx_dbdma_start( auide->tx_chan );
 616         au1xxx_dbdma_start( auide->rx_chan );
 617
 618         return 0;
 619 }
 620 #endif
 621
 622 static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif)
 623 {
 624         int i;
 625         unsigned long *ata_regs = hw->io_ports;
 626
 627         /* FIXME? */
 628         for (i = 0; i < IDE_CONTROL_OFFSET; i++) {
 629                 *ata_regs++ = ahwif->regbase + (i << AU1XXX_ATA_REG_OFFSET);
 630         }
 631
 632         /* set the Alternative Status register */
 633         *ata_regs = ahwif->regbase + (14 << AU1XXX_ATA_REG_OFFSET);
 634 }
 635
 636 static int au_ide_probe(struct device *dev)
 637 {
 638         struct platform_device *pdev = to_platform_device(dev);
 639         _auide_hwif *ahwif = &auide_hwif;
 640         ide_hwif_t *hwif;
 641         struct resource *res;
 642         hw_regs_t *hw;
 643         int ret = 0;
 644
 645 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
 646         char *mode = "MWDMA2";
 647 #elif defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
 648         char *mode = "PIO+DDMA(offload)";
 649 #endif
 650
 651         memset(&auide_hwif, 0, sizeof(_auide_hwif));
 652         auide_hwif.dev                  = 0;
 653
 654         ahwif->dev = dev;
 655         ahwif->irq = platform_get_irq(pdev, 0);
 656
 657         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 658
 659         if (res == NULL) {
 660                 pr_debug("%s %d: no base address\n", DRV_NAME, pdev->id);
 661                 ret = -ENODEV;
 662                 goto out;
 663         }
 664         if (ahwif->irq < 0) {
 665                 pr_debug("%s %d: no IRQ\n", DRV_NAME, pdev->id);
 666                 ret = -ENODEV;
 667                 goto out;
 668         }
 669
 670         if (!request_mem_region (res->start, res->end-res->start, pdev->name)) {
 671                 pr_debug("%s: request_mem_region failed\n", DRV_NAME);
 672                 ret =  -EBUSY;
 673                 goto out;
 674         }
 675
 676         ahwif->regbase = (u32)ioremap(res->start, res->end-res->start);
 677         if (ahwif->regbase == 0) {
 678                 ret = -ENOMEM;
 679                 goto out;
 680         }
 681
 682         /* FIXME:  This might possibly break PCMCIA IDE devices */
 683
 684         hwif                            = &ide_hwifs[pdev->id];
 685         hw                              = &hwif->hw;
 686         hwif->irq = hw->irq             = ahwif->irq;
 687         hwif->chipset                   = ide_au1xxx;
 688
 689         auide_setup_ports(hw, ahwif);
 690         memcpy(hwif->io_ports, hw->io_ports, sizeof(hwif->io_ports));
 691
 692         hwif->ultra_mask                = 0x0;  /* Disable Ultra DMA */
 693 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 694         hwif->mwdma_mask                = 0x07; /* Multimode-2 DMA  */
 695         hwif->swdma_mask                = 0x00;
 696 #else
 697         hwif->mwdma_mask                = 0x0;
 698         hwif->swdma_mask                = 0x0;
 699 #endif
 700
 701         hwif->noprobe = 0;
 702         hwif->drives[0].unmask          = 1;
 703         hwif->drives[1].unmask          = 1;
 704
 705         /* hold should be on in all cases */
 706         hwif->hold                      = 1;
 707
 708         hwif->mmio  = 1;
 709
 710         /* If the user has selected DDMA assisted copies,
 711            then set up a few local I/O function entry points
 712         */
 713
 714 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
 715         hwif->INSW                      = auide_insw;
 716         hwif->OUTSW                     = auide_outsw;
 717 #endif
 718
 719         hwif->tuneproc                  = &auide_tune_drive;
 720         hwif->speedproc                 = &auide_tune_chipset;
 721
 722 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 723         hwif->dma_off_quietly           = &auide_dma_off_quietly;
 724         hwif->ide_dma_timeout           = &auide_dma_timeout;
 725
 726         hwif->ide_dma_check             = &auide_dma_check;
 727         hwif->dma_exec_cmd              = &auide_dma_exec_cmd;
 728         hwif->dma_start                 = &auide_dma_start;
 729         hwif->ide_dma_end               = &auide_dma_end;
 730         hwif->dma_setup                 = &auide_dma_setup;
 731         hwif->ide_dma_test_irq          = &auide_dma_test_irq;
 732         hwif->dma_host_off              = &auide_dma_host_off;
 733         hwif->dma_host_on               = &auide_dma_host_on;
 734         hwif->ide_dma_lostirq           = &auide_dma_lostirq;
 735         hwif->ide_dma_on                = &auide_dma_on;
 736
 737         hwif->autodma                   = 1;
 738         hwif->drives[0].autodma         = hwif->autodma;
 739         hwif->drives[1].autodma         = hwif->autodma;
 740         hwif->atapi_dma                 = 1;
 741
 742 #else /* !CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
 743         hwif->autodma                   = 0;
 744         hwif->channel                   = 0;
 745         hwif->hold                      = 1;
 746         hwif->select_data               = 0;    /* no chipset-specific code */
 747         hwif->config_data               = 0;    /* no chipset-specific code */
 748
 749         hwif->drives[0].autodma         = 0;
 750         hwif->drives[0].autotune        = 1;    /* 1=autotune, 2=noautotune, 0=default */
 751 #endif
 752         hwif->drives[0].no_io_32bit     = 1;
 753
 754         auide_hwif.hwif                 = hwif;
 755         hwif->hwif_data                 = &auide_hwif;
 756
 757 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
 758         auide_ddma_init(&auide_hwif);
 759         dbdma_init_done = 1;
 760 #endif
 761
 762         probe_hwif_init(hwif);
 763         dev_set_drvdata(dev, hwif);
 764
 765         printk(KERN_INFO "Au1xxx IDE(builtin) configured for %s\n", mode );
 766
 767  out:
 768         return ret;
 769 }
 770
 771 static int au_ide_remove(struct device *dev)
 772 {
 773         struct platform_device *pdev = to_platform_device(dev);
 774         struct resource *res;
 775         ide_hwif_t *hwif = dev_get_drvdata(dev);
 776         _auide_hwif *ahwif = &auide_hwif;
 777
 778         ide_unregister(hwif - ide_hwifs);
 779
 780         iounmap((void *)ahwif->regbase);
 781
 782         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 783         release_mem_region(res->start, res->end - res->start);
 784
 785         return 0;
 786 }
 787
 788 static struct device_driver au1200_ide_driver = {
 789         .name           = "au1200-ide",
 790         .bus            = &platform_bus_type,
 791         .probe          = au_ide_probe,
 792         .remove         = au_ide_remove,
 793 };
 794
 795 static int __init au_ide_init(void)
 796 {
 797         return driver_register(&au1200_ide_driver);
 798 }
 799
 800 static void __exit au_ide_exit(void)
 801 {
 802         driver_unregister(&au1200_ide_driver);
 803 }
 804
 805 MODULE_LICENSE("GPL");
 806 MODULE_DESCRIPTION("AU1200 IDE driver");
 807
 808 module_init(au_ide_init);
 809 module_exit(au_ide_exit);