drivers/i2c/busses/i2c-tegra.c

   1 /*
   2  * drivers/i2c/busses/i2c-tegra.c
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  * Author: Colin Cross <ccross@android.com>
   6  *
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/clk.h>
  22 #include <linux/err.h>
  23 #include <linux/i2c.h>
  24 #include <linux/io.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/delay.h>
  27 #include <linux/slab.h>
  28 #include <linux/i2c-tegra.h>
  29
  30 #include <asm/unaligned.h>
  31
  32 #include <mach/clk.h>
  33
  34 #define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
  35 #define BYTES_PER_FIFO_WORD 4
  36
  37 #define I2C_CNFG                                0x000
  38 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT             12
  39 #define I2C_CNFG_PACKET_MODE_EN                 (1<<10)
  40 #define I2C_CNFG_NEW_MASTER_FSM                 (1<<11)
  41 #define I2C_STATUS                              0x01C
  42 #define I2C_SL_CNFG                             0x020
  43 #define I2C_SL_CNFG_NACK                        (1<<1)
  44 #define I2C_SL_CNFG_NEWSL                       (1<<2)
  45 #define I2C_SL_ADDR1                            0x02c
  46 #define I2C_SL_ADDR2                            0x030
  47 #define I2C_TX_FIFO                             0x050
  48 #define I2C_RX_FIFO                             0x054
  49 #define I2C_PACKET_TRANSFER_STATUS              0x058
  50 #define I2C_FIFO_CONTROL                        0x05c
  51 #define I2C_FIFO_CONTROL_TX_FLUSH               (1<<1)
  52 #define I2C_FIFO_CONTROL_RX_FLUSH               (1<<0)
  53 #define I2C_FIFO_CONTROL_TX_TRIG_SHIFT          5
  54 #define I2C_FIFO_CONTROL_RX_TRIG_SHIFT          2
  55 #define I2C_FIFO_STATUS                         0x060
  56 #define I2C_FIFO_STATUS_TX_MASK                 0xF0
  57 #define I2C_FIFO_STATUS_TX_SHIFT                4
  58 #define I2C_FIFO_STATUS_RX_MASK                 0x0F
  59 #define I2C_FIFO_STATUS_RX_SHIFT                0
  60 #define I2C_INT_MASK                            0x064
  61 #define I2C_INT_STATUS                          0x068
  62 #define I2C_INT_PACKET_XFER_COMPLETE            (1<<7)
  63 #define I2C_INT_ALL_PACKETS_XFER_COMPLETE       (1<<6)
  64 #define I2C_INT_TX_FIFO_OVERFLOW                (1<<5)
  65 #define I2C_INT_RX_FIFO_UNDERFLOW               (1<<4)
  66 #define I2C_INT_NO_ACK                          (1<<3)
  67 #define I2C_INT_ARBITRATION_LOST                (1<<2)
  68 #define I2C_INT_TX_FIFO_DATA_REQ                (1<<1)
  69 #define I2C_INT_RX_FIFO_DATA_REQ                (1<<0)
  70 #define I2C_CLK_DIVISOR                         0x06c
  71
  72 #define DVC_CTRL_REG1                           0x000
  73 #define DVC_CTRL_REG1_INTR_EN                   (1<<10)
  74 #define DVC_CTRL_REG2                           0x004
  75 #define DVC_CTRL_REG3                           0x008
  76 #define DVC_CTRL_REG3_SW_PROG                   (1<<26)
  77 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN          (1<<30)
  78 #define DVC_STATUS                              0x00c
  79 #define DVC_STATUS_I2C_DONE_INTR                (1<<30)
  80
  81 #define I2C_ERR_NONE                            0x00
  82 #define I2C_ERR_NO_ACK                          0x01
  83 #define I2C_ERR_ARBITRATION_LOST                0x02
  84 #define I2C_ERR_UNKNOWN_INTERRUPT               0x04
  85
  86 #define PACKET_HEADER0_HEADER_SIZE_SHIFT        28
  87 #define PACKET_HEADER0_PACKET_ID_SHIFT          16
  88 #define PACKET_HEADER0_CONT_ID_SHIFT            12
  89 #define PACKET_HEADER0_PROTOCOL_I2C             (1<<4)
  90
  91 #define I2C_HEADER_HIGHSPEED_MODE               (1<<22)
  92 #define I2C_HEADER_CONT_ON_NAK                  (1<<21)
  93 #define I2C_HEADER_SEND_START_BYTE              (1<<20)
  94 #define I2C_HEADER_READ                         (1<<19)
  95 #define I2C_HEADER_10BIT_ADDR                   (1<<18)
  96 #define I2C_HEADER_IE_ENABLE                    (1<<17)
  97 #define I2C_HEADER_REPEAT_START                 (1<<16)
  98 #define I2C_HEADER_MASTER_ADDR_SHIFT            12
  99 #define I2C_HEADER_SLAVE_ADDR_SHIFT             1
 100
 101 /**
 102  * struct tegra_i2c_dev - per device i2c context
 103  * @dev: device reference for power management
 104  * @adapter: core i2c layer adapter information
 105  * @clk: clock reference for i2c controller
 106  * @i2c_clk: clock reference for i2c bus
 107  * @iomem: memory resource for registers
 108  * @base: ioremapped registers cookie
 109  * @cont_id: i2c controller id, used for for packet header
 110  * @irq: irq number of transfer complete interrupt
 111  * @is_dvc: identifies the DVC i2c controller, has a different register layout
 112  * @msg_complete: transfer completion notifier
 113  * @msg_err: error code for completed message
 114  * @msg_buf: pointer to current message data
 115  * @msg_buf_remaining: size of unsent data in the message buffer
 116  * @msg_read: identifies read transfers
 117  * @bus_clk_rate: current i2c bus clock rate
 118  * @is_suspended: prevents i2c controller accesses after suspend is called
 119  */
 120 struct tegra_i2c_dev {
 121         struct device *dev;
 122         struct i2c_adapter adapter;
 123         struct clk *clk;
 124         struct clk *i2c_clk;
 125         struct resource *iomem;
 126         void __iomem *base;
 127         int cont_id;
 128         int irq;
 129         bool irq_disabled;
 130         int is_dvc;
 131         struct completion msg_complete;
 132         int msg_err;
 133         u8 *msg_buf;
 134         size_t msg_buf_remaining;
 135         int msg_read;
 136         unsigned long bus_clk_rate;
 137         bool is_suspended;
 138 };
 139
 140 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg)
 141 {
 142         writel(val, i2c_dev->base + reg);
 143 }
 144
 145 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
 146 {
 147         return readl(i2c_dev->base + reg);
 148 }
 149
 150 /*
 151  * i2c_writel and i2c_readl will offset the register if necessary to talk
 152  * to the I2C block inside the DVC block
 153  */
 154 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
 155         unsigned long reg)
 156 {
 157         if (i2c_dev->is_dvc)
 158                 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
 159         return reg;
 160 }
 161
 162 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
 163         unsigned long reg)
 164 {
 165         writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 166 }
 167
 168 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
 169 {
 170         return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 171 }
 172
 173 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
 174         unsigned long reg, int len)
 175 {
 176         writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
 177 }
 178
 179 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
 180         unsigned long reg, int len)
 181 {
 182         readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
 183 }
 184
 185 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 186 {
 187         u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
 188         int_mask &= ~mask;
 189         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 190 }
 191
 192 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 193 {
 194         u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
 195         int_mask |= mask;
 196         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 197 }
 198
 199 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
 200 {
 201         unsigned long timeout = jiffies + HZ;
 202         u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL);
 203         val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH;
 204         i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
 205
 206         while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) &
 207                 (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) {
 208                 if (time_after(jiffies, timeout)) {
 209                         dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
 210                         return -ETIMEDOUT;
 211                 }
 212                 msleep(1);
 213         }
 214         return 0;
 215 }
 216
 217 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
 218 {
 219         u32 val;
 220         int rx_fifo_avail;
 221         u8 *buf = i2c_dev->msg_buf;
 222         size_t buf_remaining = i2c_dev->msg_buf_remaining;
 223         int words_to_transfer;
 224
 225         val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 226         rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
 227                 I2C_FIFO_STATUS_RX_SHIFT;
 228
 229         /* Rounds down to not include partial word at the end of buf */
 230         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 231         if (words_to_transfer > rx_fifo_avail)
 232                 words_to_transfer = rx_fifo_avail;
 233
 234         i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
 235
 236         buf += words_to_transfer * BYTES_PER_FIFO_WORD;
 237         buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 238         rx_fifo_avail -= words_to_transfer;
 239
 240         /*
 241          * If there is a partial word at the end of buf, handle it manually to
 242          * prevent overwriting past the end of buf
 243          */
 244         if (rx_fifo_avail > 0 && buf_remaining > 0) {
 245                 BUG_ON(buf_remaining > 3);
 246                 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
 247                 memcpy(buf, &val, buf_remaining);
 248                 buf_remaining = 0;
 249                 rx_fifo_avail--;
 250         }
 251
 252         BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0);
 253         i2c_dev->msg_buf_remaining = buf_remaining;
 254         i2c_dev->msg_buf = buf;
 255         return 0;
 256 }
 257
 258 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
 259 {
 260         u32 val;
 261         int tx_fifo_avail;
 262         u8 *buf = i2c_dev->msg_buf;
 263         size_t buf_remaining = i2c_dev->msg_buf_remaining;
 264         int words_to_transfer;
 265
 266         val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 267         tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
 268                 I2C_FIFO_STATUS_TX_SHIFT;
 269
 270         /* Rounds down to not include partial word at the end of buf */
 271         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 272         if (words_to_transfer > tx_fifo_avail)
 273                 words_to_transfer = tx_fifo_avail;
 274
 275         i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
 276
 277         buf += words_to_transfer * BYTES_PER_FIFO_WORD;
 278         buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 279         tx_fifo_avail -= words_to_transfer;
 280
 281         /*
 282          * If there is a partial word at the end of buf, handle it manually to
 283          * prevent reading past the end of buf, which could cross a page
 284          * boundary and fault.
 285          */
 286         if (tx_fifo_avail > 0 && buf_remaining > 0) {
 287                 BUG_ON(buf_remaining > 3);
 288                 memcpy(&val, buf, buf_remaining);
 289                 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
 290                 buf_remaining = 0;
 291                 tx_fifo_avail--;
 292         }
 293
 294         BUG_ON(tx_fifo_avail > 0 && buf_remaining > 0);
 295         i2c_dev->msg_buf_remaining = buf_remaining;
 296         i2c_dev->msg_buf = buf;
 297         return 0;
 298 }
 299
 300 /*
 301  * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
 302  * block.  This block is identical to the rest of the I2C blocks, except that
 303  * it only supports master mode, it has registers moved around, and it needs
 304  * some extra init to get it into I2C mode.  The register moves are handled
 305  * by i2c_readl and i2c_writel
 306  */
 307 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
 308 {
 309         u32 val = 0;
 310         val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
 311         val |= DVC_CTRL_REG3_SW_PROG;
 312         val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
 313         dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
 314
 315         val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
 316         val |= DVC_CTRL_REG1_INTR_EN;
 317         dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
 318 }
 319
 320 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
 321 {
 322         u32 val;
 323         int err = 0;
 324
 325         clk_enable(i2c_dev->clk);
 326
 327         tegra_periph_reset_assert(i2c_dev->clk);
 328         udelay(2);
 329         tegra_periph_reset_deassert(i2c_dev->clk);
 330
 331         if (i2c_dev->is_dvc)
 332                 tegra_dvc_init(i2c_dev);
 333
 334         val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
 335                 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
 336         i2c_writel(i2c_dev, val, I2C_CNFG);
 337         i2c_writel(i2c_dev, 0, I2C_INT_MASK);
 338         clk_set_rate(i2c_dev->clk, i2c_dev->bus_clk_rate * 8);
 339
 340         if (!i2c_dev->is_dvc) {
 341                 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
 342                 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
 343                 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
 344                 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
 345                 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
 346
 347         }
 348
 349         val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
 350                 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
 351         i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
 352
 353         if (tegra_i2c_flush_fifos(i2c_dev))
 354                 err = -ETIMEDOUT;
 355
 356         clk_disable(i2c_dev->clk);
 357
 358         if (i2c_dev->irq_disabled) {
 359                 i2c_dev->irq_disabled = 0;
 360                 enable_irq(i2c_dev->irq);
 361         }
 362
 363         return err;
 364 }
 365
 366 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
 367 {
 368         u32 status;
 369         const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
 370         struct tegra_i2c_dev *i2c_dev = dev_id;
 371
 372         status = i2c_readl(i2c_dev, I2C_INT_STATUS);
 373
 374         if (status == 0) {
 375                 dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n",
 376                          i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
 377                          i2c_readl(i2c_dev, I2C_STATUS),
 378                          i2c_readl(i2c_dev, I2C_CNFG));
 379                 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
 380
 381                 if (!i2c_dev->irq_disabled) {
 382                         disable_irq_nosync(i2c_dev->irq);
 383                         i2c_dev->irq_disabled = 1;
 384                 }
 385
 386                 complete(&i2c_dev->msg_complete);
 387                 goto err;
 388         }
 389
 390         if (unlikely(status & status_err)) {
 391                 if (status & I2C_INT_NO_ACK)
 392                         i2c_dev->msg_err |= I2C_ERR_NO_ACK;
 393                 if (status & I2C_INT_ARBITRATION_LOST)
 394                         i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
 395                 complete(&i2c_dev->msg_complete);
 396                 goto err;
 397         }
 398
 399         if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
 400                 if (i2c_dev->msg_buf_remaining)
 401                         tegra_i2c_empty_rx_fifo(i2c_dev);
 402                 else
 403                         BUG();
 404         }
 405
 406         if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
 407                 if (i2c_dev->msg_buf_remaining)
 408                         tegra_i2c_fill_tx_fifo(i2c_dev);
 409                 else
 410                         tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ);
 411         }
 412
 413         if ((status & I2C_INT_PACKET_XFER_COMPLETE) &&
 414                         !i2c_dev->msg_buf_remaining)
 415                 complete(&i2c_dev->msg_complete);
 416
 417         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 418         if (i2c_dev->is_dvc)
 419                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
 420         return IRQ_HANDLED;
 421 err:
 422         /* An error occurred, mask all interrupts */
 423         tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
 424                 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
 425                 I2C_INT_RX_FIFO_DATA_REQ);
 426         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 427         if (i2c_dev->is_dvc)
 428                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
 429         return IRQ_HANDLED;
 430 }
 431
 432 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
 433         struct i2c_msg *msg, int stop)
 434 {
 435         u32 packet_header;
 436         u32 int_mask;
 437         int ret;
 438
 439         tegra_i2c_flush_fifos(i2c_dev);
 440         i2c_writel(i2c_dev, 0xFF, I2C_INT_STATUS);
 441
 442         if (msg->len == 0)
 443                 return -EINVAL;
 444
 445         i2c_dev->msg_buf = msg->buf;
 446         i2c_dev->msg_buf_remaining = msg->len;
 447         i2c_dev->msg_err = I2C_ERR_NONE;
 448         i2c_dev->msg_read = (msg->flags & I2C_M_RD);
 449         INIT_COMPLETION(i2c_dev->msg_complete);
 450
 451         packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
 452                         PACKET_HEADER0_PROTOCOL_I2C |
 453                         (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
 454                         (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
 455         i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
 456
 457         packet_header = msg->len - 1;
 458         i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
 459
 460         packet_header = msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
 461         packet_header |= I2C_HEADER_IE_ENABLE;
 462         if (!stop)
 463                 packet_header |= I2C_HEADER_REPEAT_START;
 464         if (msg->flags & I2C_M_TEN)
 465                 packet_header |= I2C_HEADER_10BIT_ADDR;
 466         if (msg->flags & I2C_M_IGNORE_NAK)
 467                 packet_header |= I2C_HEADER_CONT_ON_NAK;
 468         if (msg->flags & I2C_M_RD)
 469                 packet_header |= I2C_HEADER_READ;
 470         i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
 471
 472         if (!(msg->flags & I2C_M_RD))
 473                 tegra_i2c_fill_tx_fifo(i2c_dev);
 474
 475         int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
 476         if (msg->flags & I2C_M_RD)
 477                 int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
 478         else if (i2c_dev->msg_buf_remaining)
 479                 int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
 480         tegra_i2c_unmask_irq(i2c_dev, int_mask);
 481         dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
 482                 i2c_readl(i2c_dev, I2C_INT_MASK));
 483
 484         ret = wait_for_completion_timeout(&i2c_dev->msg_complete, TEGRA_I2C_TIMEOUT);
 485         tegra_i2c_mask_irq(i2c_dev, int_mask);
 486
 487         if (WARN_ON(ret == 0)) {
 488                 dev_err(i2c_dev->dev, "i2c transfer timed out\n");
 489
 490                 tegra_i2c_init(i2c_dev);
 491                 return -ETIMEDOUT;
 492         }
 493
 494         dev_dbg(i2c_dev->dev, "transfer complete: %d %d %d\n",
 495                 ret, completion_done(&i2c_dev->msg_complete), i2c_dev->msg_err);
 496
 497         if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
 498                 return 0;
 499
 500         tegra_i2c_init(i2c_dev);
 501         if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
 502                 if (msg->flags & I2C_M_IGNORE_NAK)
 503                         return 0;
 504                 return -EREMOTEIO;
 505         }
 506
 507         return -EIO;
 508 }
 509
 510 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
 511         int num)
 512 {
 513         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
 514         int i;
 515         int ret = 0;
 516
 517         if (i2c_dev->is_suspended)
 518                 return -EBUSY;
 519
 520         clk_enable(i2c_dev->clk);
 521         for (i = 0; i < num; i++) {
 522                 int stop = (i == (num - 1)) ? 1  : 0;
 523                 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], stop);
 524                 if (ret)
 525                         break;
 526         }
 527         clk_disable(i2c_dev->clk);
 528         return ret ?: i;
 529 }
 530
 531 static u32 tegra_i2c_func(struct i2c_adapter *adap)
 532 {
 533         return I2C_FUNC_I2C;
 534 }
 535
 536 static const struct i2c_algorithm tegra_i2c_algo = {
 537         .master_xfer    = tegra_i2c_xfer,
 538         .functionality  = tegra_i2c_func,
 539 };
 540
 541 static int tegra_i2c_probe(struct platform_device *pdev)
 542 {
 543         struct tegra_i2c_dev *i2c_dev;
 544         struct tegra_i2c_platform_data *pdata = pdev->dev.platform_data;
 545         struct resource *res;
 546         struct resource *iomem;
 547         struct clk *clk;
 548         struct clk *i2c_clk;
 549         void *base;
 550         int irq;
 551         int ret = 0;
 552
 553         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 554         if (!res) {
 555                 dev_err(&pdev->dev, "no mem resource\n");
 556                 return -EINVAL;
 557         }
 558         iomem = request_mem_region(res->start, resource_size(res), pdev->name);
 559         if (!iomem) {
 560                 dev_err(&pdev->dev, "I2C region already claimed\n");
 561                 return -EBUSY;
 562         }
 563
 564         base = ioremap(iomem->start, resource_size(iomem));
 565         if (!base) {
 566                 dev_err(&pdev->dev, "Cannot ioremap I2C region\n");
 567                 return -ENOMEM;
 568         }
 569
 570         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 571         if (!res) {
 572                 dev_err(&pdev->dev, "no irq resource\n");
 573                 ret = -EINVAL;
 574                 goto err_iounmap;
 575         }
 576         irq = res->start;
 577
 578         clk = clk_get(&pdev->dev, NULL);
 579         if (IS_ERR(clk)) {
 580                 dev_err(&pdev->dev, "missing controller clock");
 581                 ret = PTR_ERR(clk);
 582                 goto err_release_region;
 583         }
 584
 585         i2c_clk = clk_get(&pdev->dev, "i2c");
 586         if (IS_ERR(i2c_clk)) {
 587                 dev_err(&pdev->dev, "missing bus clock");
 588                 ret = PTR_ERR(i2c_clk);
 589                 goto err_clk_put;
 590         }
 591
 592         i2c_dev = kzalloc(sizeof(struct tegra_i2c_dev), GFP_KERNEL);
 593         if (!i2c_dev) {
 594                 ret = -ENOMEM;
 595                 goto err_i2c_clk_put;
 596         }
 597
 598         i2c_dev->base = base;
 599         i2c_dev->clk = clk;
 600         i2c_dev->i2c_clk = i2c_clk;
 601         i2c_dev->iomem = iomem;
 602         i2c_dev->adapter.algo = &tegra_i2c_algo;
 603         i2c_dev->irq = irq;
 604         i2c_dev->cont_id = pdev->id;
 605         i2c_dev->dev = &pdev->dev;
 606         i2c_dev->bus_clk_rate = pdata ? pdata->bus_clk_rate : 100000;
 607
 608         if (pdev->id == 3)
 609                 i2c_dev->is_dvc = 1;
 610         init_completion(&i2c_dev->msg_complete);
 611
 612         platform_set_drvdata(pdev, i2c_dev);
 613
 614         ret = tegra_i2c_init(i2c_dev);
 615         if (ret) {
 616                 dev_err(&pdev->dev, "Failed to initialize i2c controller");
 617                 goto err_free;
 618         }
 619
 620         ret = request_irq(i2c_dev->irq, tegra_i2c_isr, 0, pdev->name, i2c_dev);
 621         if (ret) {
 622                 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
 623                 goto err_free;
 624         }
 625
 626         clk_enable(i2c_dev->i2c_clk);
 627
 628         i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
 629         i2c_dev->adapter.owner = THIS_MODULE;
 630         i2c_dev->adapter.class = I2C_CLASS_HWMON;
 631         strlcpy(i2c_dev->adapter.name, "Tegra I2C adapter",
 632                 sizeof(i2c_dev->adapter.name));
 633         i2c_dev->adapter.algo = &tegra_i2c_algo;
 634         i2c_dev->adapter.dev.parent = &pdev->dev;
 635         i2c_dev->adapter.nr = pdev->id;
 636
 637         ret = i2c_add_numbered_adapter(&i2c_dev->adapter);
 638         if (ret) {
 639                 dev_err(&pdev->dev, "Failed to add I2C adapter\n");
 640                 goto err_free_irq;
 641         }
 642
 643         return 0;
 644 err_free_irq:
 645         free_irq(i2c_dev->irq, i2c_dev);
 646 err_free:
 647         kfree(i2c_dev);
 648 err_i2c_clk_put:
 649         clk_put(i2c_clk);
 650 err_clk_put:
 651         clk_put(clk);
 652 err_release_region:
 653         release_mem_region(iomem->start, resource_size(iomem));
 654 err_iounmap:
 655         iounmap(base);
 656         return ret;
 657 }
 658
 659 static int tegra_i2c_remove(struct platform_device *pdev)
 660 {
 661         struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
 662         i2c_del_adapter(&i2c_dev->adapter);
 663         free_irq(i2c_dev->irq, i2c_dev);
 664         clk_put(i2c_dev->i2c_clk);
 665         clk_put(i2c_dev->clk);
 666         release_mem_region(i2c_dev->iomem->start,
 667                 resource_size(i2c_dev->iomem));
 668         iounmap(i2c_dev->base);
 669         kfree(i2c_dev);
 670         return 0;
 671 }
 672
 673 #ifdef CONFIG_PM
 674 static int tegra_i2c_suspend(struct platform_device *pdev, pm_message_t state)
 675 {
 676         struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
 677
 678         i2c_lock_adapter(&i2c_dev->adapter);
 679         i2c_dev->is_suspended = true;
 680         i2c_unlock_adapter(&i2c_dev->adapter);
 681
 682         return 0;
 683 }
 684
 685 static int tegra_i2c_resume(struct platform_device *pdev)
 686 {
 687         struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
 688         int ret;
 689
 690         i2c_lock_adapter(&i2c_dev->adapter);
 691
 692         ret = tegra_i2c_init(i2c_dev);
 693
 694         if (ret) {
 695                 i2c_unlock_adapter(&i2c_dev->adapter);
 696                 return ret;
 697         }
 698
 699         i2c_dev->is_suspended = false;
 700
 701         i2c_unlock_adapter(&i2c_dev->adapter);
 702
 703         return 0;
 704 }
 705 #endif
 706
 707 static struct platform_driver tegra_i2c_driver = {
 708         .probe   = tegra_i2c_probe,
 709         .remove  = tegra_i2c_remove,
 710 #ifdef CONFIG_PM
 711         .suspend = tegra_i2c_suspend,
 712         .resume  = tegra_i2c_resume,
 713 #endif
 714         .driver  = {
 715                 .name  = "tegra-i2c",
 716                 .owner = THIS_MODULE,
 717         },
 718 };
 719
 720 static int __init tegra_i2c_init_driver(void)
 721 {
 722         return platform_driver_register(&tegra_i2c_driver);
 723 }
 724
 725 static void __exit tegra_i2c_exit_driver(void)
 726 {
 727         platform_driver_unregister(&tegra_i2c_driver);
 728 }
 729
 730 subsys_initcall(tegra_i2c_init_driver);
 731 module_exit(tegra_i2c_exit_driver);
 732
 733 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
 734 MODULE_AUTHOR("Colin Cross");
 735 MODULE_LICENSE("GPL v2");