drivers/i2c/busses/i2c-tegra.c

   1 /*
   2  * drivers/i2c/busses/i2c-tegra.c
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  * Author: Colin Cross <ccross@android.com>
   6  *
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/clk.h>
  22 #include <linux/err.h>
  23 #include <linux/i2c.h>
  24 #include <linux/io.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/delay.h>
  27 #include <linux/slab.h>
  28 #include <linux/i2c-tegra.h>
  29
  30 #include <asm/unaligned.h>
  31
  32 #include <mach/clk.h>
  33
  34 #define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
  35 #define BYTES_PER_FIFO_WORD 4
  36
  37 #define I2C_CNFG                                0x000
  38 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT             12
  39 #define I2C_CNFG_PACKET_MODE_EN                 (1<<10)
  40 #define I2C_CNFG_NEW_MASTER_FSM                 (1<<11)
  41 #define I2C_STATUS                              0x01C
  42 #define I2C_SL_CNFG                             0x020
  43 #define I2C_SL_CNFG_NEWSL                       (1<<2)
  44 #define I2C_SL_ADDR1                            0x02c
  45 #define I2C_TX_FIFO                             0x050
  46 #define I2C_RX_FIFO                             0x054
  47 #define I2C_PACKET_TRANSFER_STATUS              0x058
  48 #define I2C_FIFO_CONTROL                        0x05c
  49 #define I2C_FIFO_CONTROL_TX_FLUSH               (1<<1)
  50 #define I2C_FIFO_CONTROL_RX_FLUSH               (1<<0)
  51 #define I2C_FIFO_CONTROL_TX_TRIG_SHIFT          5
  52 #define I2C_FIFO_CONTROL_RX_TRIG_SHIFT          2
  53 #define I2C_FIFO_STATUS                         0x060
  54 #define I2C_FIFO_STATUS_TX_MASK                 0xF0
  55 #define I2C_FIFO_STATUS_TX_SHIFT                4
  56 #define I2C_FIFO_STATUS_RX_MASK                 0x0F
  57 #define I2C_FIFO_STATUS_RX_SHIFT                0
  58 #define I2C_INT_MASK                            0x064
  59 #define I2C_INT_STATUS                          0x068
  60 #define I2C_INT_PACKET_XFER_COMPLETE            (1<<7)
  61 #define I2C_INT_ALL_PACKETS_XFER_COMPLETE       (1<<6)
  62 #define I2C_INT_TX_FIFO_OVERFLOW                (1<<5)
  63 #define I2C_INT_RX_FIFO_UNDERFLOW               (1<<4)
  64 #define I2C_INT_NO_ACK                          (1<<3)
  65 #define I2C_INT_ARBITRATION_LOST                (1<<2)
  66 #define I2C_INT_TX_FIFO_DATA_REQ                (1<<1)
  67 #define I2C_INT_RX_FIFO_DATA_REQ                (1<<0)
  68 #define I2C_CLK_DIVISOR                         0x06c
  69
  70 #define DVC_CTRL_REG1                           0x000
  71 #define DVC_CTRL_REG1_INTR_EN                   (1<<10)
  72 #define DVC_CTRL_REG2                           0x004
  73 #define DVC_CTRL_REG3                           0x008
  74 #define DVC_CTRL_REG3_SW_PROG                   (1<<26)
  75 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN          (1<<30)
  76 #define DVC_STATUS                              0x00c
  77 #define DVC_STATUS_I2C_DONE_INTR                (1<<30)
  78
  79 #define I2C_ERR_NONE                            0x00
  80 #define I2C_ERR_NO_ACK                          0x01
  81 #define I2C_ERR_ARBITRATION_LOST                0x02
  82 #define I2C_ERR_UNKNOWN_INTERRUPT               0x04
  83
  84 #define PACKET_HEADER0_HEADER_SIZE_SHIFT        28
  85 #define PACKET_HEADER0_PACKET_ID_SHIFT          16
  86 #define PACKET_HEADER0_CONT_ID_SHIFT            12
  87 #define PACKET_HEADER0_PROTOCOL_I2C             (1<<4)
  88
  89 #define I2C_HEADER_HIGHSPEED_MODE               (1<<22)
  90 #define I2C_HEADER_CONT_ON_NAK                  (1<<21)
  91 #define I2C_HEADER_SEND_START_BYTE              (1<<20)
  92 #define I2C_HEADER_READ                         (1<<19)
  93 #define I2C_HEADER_10BIT_ADDR                   (1<<18)
  94 #define I2C_HEADER_IE_ENABLE                    (1<<17)
  95 #define I2C_HEADER_REPEAT_START                 (1<<16)
  96 #define I2C_HEADER_MASTER_ADDR_SHIFT            12
  97 #define I2C_HEADER_SLAVE_ADDR_SHIFT             1
  98
  99 /**
 100  * struct tegra_i2c_dev - per device i2c context
 101  * @dev: device reference for power management
 102  * @adapter: core i2c layer adapter information
 103  * @clk: clock reference for i2c controller
 104  * @i2c_clk: clock reference for i2c bus
 105  * @iomem: memory resource for registers
 106  * @base: ioremapped registers cookie
 107  * @cont_id: i2c controller id, used for for packet header
 108  * @irq: irq number of transfer complete interrupt
 109  * @is_dvc: identifies the DVC i2c controller, has a different register layout
 110  * @msg_complete: transfer completion notifier
 111  * @msg_err: error code for completed message
 112  * @msg_buf: pointer to current message data
 113  * @msg_buf_remaining: size of unsent data in the message buffer
 114  * @msg_read: identifies read transfers
 115  * @bus_clk_rate: current i2c bus clock rate
 116  * @is_suspended: prevents i2c controller accesses after suspend is called
 117  */
 118 struct tegra_i2c_dev {
 119         struct device *dev;
 120         struct i2c_adapter adapter;
 121         struct clk *clk;
 122         struct clk *i2c_clk;
 123         struct resource *iomem;
 124         void __iomem *base;
 125         int cont_id;
 126         int irq;
 127         bool irq_disabled;
 128         int is_dvc;
 129         struct completion msg_complete;
 130         int msg_err;
 131         u8 *msg_buf;
 132         size_t msg_buf_remaining;
 133         int msg_read;
 134         unsigned long bus_clk_rate;
 135         bool is_suspended;
 136 };
 137
 138 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg)
 139 {
 140         writel(val, i2c_dev->base + reg);
 141 }
 142
 143 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
 144 {
 145         return readl(i2c_dev->base + reg);
 146 }
 147
 148 /*
 149  * i2c_writel and i2c_readl will offset the register if necessary to talk
 150  * to the I2C block inside the DVC block
 151  */
 152 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
 153         unsigned long reg)
 154 {
 155         if (i2c_dev->is_dvc)
 156                 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
 157         return reg;
 158 }
 159
 160 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
 161         unsigned long reg)
 162 {
 163         writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 164 }
 165
 166 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
 167 {
 168         return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 169 }
 170
 171 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
 172         unsigned long reg, int len)
 173 {
 174         writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
 175 }
 176
 177 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
 178         unsigned long reg, int len)
 179 {
 180         readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
 181 }
 182
 183 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 184 {
 185         u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
 186         int_mask &= ~mask;
 187         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 188 }
 189
 190 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 191 {
 192         u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
 193         int_mask |= mask;
 194         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 195 }
 196
 197 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
 198 {
 199         unsigned long timeout = jiffies + HZ;
 200         u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL);
 201         val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH;
 202         i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
 203
 204         while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) &
 205                 (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) {
 206                 if (time_after(jiffies, timeout)) {
 207                         dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
 208                         return -ETIMEDOUT;
 209                 }
 210                 msleep(1);
 211         }
 212         return 0;
 213 }
 214
 215 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
 216 {
 217         u32 val;
 218         int rx_fifo_avail;
 219         u8 *buf = i2c_dev->msg_buf;
 220         size_t buf_remaining = i2c_dev->msg_buf_remaining;
 221         int words_to_transfer;
 222
 223         val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 224         rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
 225                 I2C_FIFO_STATUS_RX_SHIFT;
 226
 227         /* Rounds down to not include partial word at the end of buf */
 228         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 229         if (words_to_transfer > rx_fifo_avail)
 230                 words_to_transfer = rx_fifo_avail;
 231
 232         i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
 233
 234         buf += words_to_transfer * BYTES_PER_FIFO_WORD;
 235         buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 236         rx_fifo_avail -= words_to_transfer;
 237
 238         /*
 239          * If there is a partial word at the end of buf, handle it manually to
 240          * prevent overwriting past the end of buf
 241          */
 242         if (rx_fifo_avail > 0 && buf_remaining > 0) {
 243                 BUG_ON(buf_remaining > 3);
 244                 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
 245                 memcpy(buf, &val, buf_remaining);
 246                 buf_remaining = 0;
 247                 rx_fifo_avail--;
 248         }
 249
 250         BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0);
 251         i2c_dev->msg_buf_remaining = buf_remaining;
 252         i2c_dev->msg_buf = buf;
 253         return 0;
 254 }
 255
 256 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
 257 {
 258         u32 val;
 259         int tx_fifo_avail;
 260         u8 *buf = i2c_dev->msg_buf;
 261         size_t buf_remaining = i2c_dev->msg_buf_remaining;
 262         int words_to_transfer;
 263
 264         val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 265         tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
 266                 I2C_FIFO_STATUS_TX_SHIFT;
 267
 268         /* Rounds down to not include partial word at the end of buf */
 269         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 270         if (words_to_transfer > tx_fifo_avail)
 271                 words_to_transfer = tx_fifo_avail;
 272
 273         i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
 274
 275         buf += words_to_transfer * BYTES_PER_FIFO_WORD;
 276         buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 277         tx_fifo_avail -= words_to_transfer;
 278
 279         /*
 280          * If there is a partial word at the end of buf, handle it manually to
 281          * prevent reading past the end of buf, which could cross a page
 282          * boundary and fault.
 283          */
 284         if (tx_fifo_avail > 0 && buf_remaining > 0) {
 285                 BUG_ON(buf_remaining > 3);
 286                 memcpy(&val, buf, buf_remaining);
 287                 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
 288                 buf_remaining = 0;
 289                 tx_fifo_avail--;
 290         }
 291
 292         BUG_ON(tx_fifo_avail > 0 && buf_remaining > 0);
 293         i2c_dev->msg_buf_remaining = buf_remaining;
 294         i2c_dev->msg_buf = buf;
 295         return 0;
 296 }
 297
 298 /*
 299  * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
 300  * block.  This block is identical to the rest of the I2C blocks, except that
 301  * it only supports master mode, it has registers moved around, and it needs
 302  * some extra init to get it into I2C mode.  The register moves are handled
 303  * by i2c_readl and i2c_writel
 304  */
 305 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
 306 {
 307         u32 val = 0;
 308         val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
 309         val |= DVC_CTRL_REG3_SW_PROG;
 310         val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
 311         dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
 312
 313         val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
 314         val |= DVC_CTRL_REG1_INTR_EN;
 315         dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
 316 }
 317
 318 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
 319 {
 320         u32 val;
 321         int err = 0;
 322
 323         clk_enable(i2c_dev->clk);
 324
 325         tegra_periph_reset_assert(i2c_dev->clk);
 326         udelay(2);
 327         tegra_periph_reset_deassert(i2c_dev->clk);
 328
 329         if (i2c_dev->is_dvc)
 330                 tegra_dvc_init(i2c_dev);
 331
 332         val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
 333                 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
 334         i2c_writel(i2c_dev, val, I2C_CNFG);
 335         i2c_writel(i2c_dev, 0, I2C_INT_MASK);
 336         clk_set_rate(i2c_dev->clk, i2c_dev->bus_clk_rate * 8);
 337
 338         if (!i2c_dev->is_dvc) {
 339                 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
 340                 i2c_writel(i2c_dev, sl_cfg | I2C_SL_CNFG_NEWSL, I2C_SL_CNFG);
 341         }
 342
 343         val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
 344                 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
 345         i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
 346
 347         if (tegra_i2c_flush_fifos(i2c_dev))
 348                 err = -ETIMEDOUT;
 349
 350         clk_disable(i2c_dev->clk);
 351
 352         if (i2c_dev->irq_disabled) {
 353                 i2c_dev->irq_disabled = 0;
 354                 enable_irq(i2c_dev->irq);
 355         }
 356
 357         return err;
 358 }
 359
 360 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
 361 {
 362         u32 status;
 363         const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
 364         struct tegra_i2c_dev *i2c_dev = dev_id;
 365
 366         status = i2c_readl(i2c_dev, I2C_INT_STATUS);
 367
 368         if (status == 0) {
 369                 dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n",
 370                          i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
 371                          i2c_readl(i2c_dev, I2C_STATUS),
 372                          i2c_readl(i2c_dev, I2C_CNFG));
 373                 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
 374
 375                 if (!i2c_dev->irq_disabled) {
 376                         disable_irq_nosync(i2c_dev->irq);
 377                         i2c_dev->irq_disabled = 1;
 378                 }
 379
 380                 complete(&i2c_dev->msg_complete);
 381                 goto err;
 382         }
 383
 384         if (unlikely(status & status_err)) {
 385                 if (status & I2C_INT_NO_ACK)
 386                         i2c_dev->msg_err |= I2C_ERR_NO_ACK;
 387                 if (status & I2C_INT_ARBITRATION_LOST)
 388                         i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
 389                 complete(&i2c_dev->msg_complete);
 390                 goto err;
 391         }
 392
 393         if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
 394                 if (i2c_dev->msg_buf_remaining)
 395                         tegra_i2c_empty_rx_fifo(i2c_dev);
 396                 else
 397                         BUG();
 398         }
 399
 400         if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
 401                 if (i2c_dev->msg_buf_remaining)
 402                         tegra_i2c_fill_tx_fifo(i2c_dev);
 403                 else
 404                         tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ);
 405         }
 406
 407         if ((status & I2C_INT_PACKET_XFER_COMPLETE) &&
 408                         !i2c_dev->msg_buf_remaining)
 409                 complete(&i2c_dev->msg_complete);
 410
 411         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 412         if (i2c_dev->is_dvc)
 413                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
 414         return IRQ_HANDLED;
 415 err:
 416         /* An error occurred, mask all interrupts */
 417         tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
 418                 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
 419                 I2C_INT_RX_FIFO_DATA_REQ);
 420         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 421         if (i2c_dev->is_dvc)
 422                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
 423         return IRQ_HANDLED;
 424 }
 425
 426 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
 427         struct i2c_msg *msg, int stop)
 428 {
 429         u32 packet_header;
 430         u32 int_mask;
 431         int ret;
 432
 433         tegra_i2c_flush_fifos(i2c_dev);
 434         i2c_writel(i2c_dev, 0xFF, I2C_INT_STATUS);
 435
 436         if (msg->len == 0)
 437                 return -EINVAL;
 438
 439         i2c_dev->msg_buf = msg->buf;
 440         i2c_dev->msg_buf_remaining = msg->len;
 441         i2c_dev->msg_err = I2C_ERR_NONE;
 442         i2c_dev->msg_read = (msg->flags & I2C_M_RD);
 443         INIT_COMPLETION(i2c_dev->msg_complete);
 444
 445         packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
 446                         PACKET_HEADER0_PROTOCOL_I2C |
 447                         (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
 448                         (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
 449         i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
 450
 451         packet_header = msg->len - 1;
 452         i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
 453
 454         packet_header = msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
 455         packet_header |= I2C_HEADER_IE_ENABLE;
 456         if (!stop)
 457                 packet_header |= I2C_HEADER_REPEAT_START;
 458         if (msg->flags & I2C_M_TEN)
 459                 packet_header |= I2C_HEADER_10BIT_ADDR;
 460         if (msg->flags & I2C_M_IGNORE_NAK)
 461                 packet_header |= I2C_HEADER_CONT_ON_NAK;
 462         if (msg->flags & I2C_M_RD)
 463                 packet_header |= I2C_HEADER_READ;
 464         i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
 465
 466         if (!(msg->flags & I2C_M_RD))
 467                 tegra_i2c_fill_tx_fifo(i2c_dev);
 468
 469         int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
 470         if (msg->flags & I2C_M_RD)
 471                 int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
 472         else if (i2c_dev->msg_buf_remaining)
 473                 int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
 474         tegra_i2c_unmask_irq(i2c_dev, int_mask);
 475         dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
 476                 i2c_readl(i2c_dev, I2C_INT_MASK));
 477
 478         ret = wait_for_completion_timeout(&i2c_dev->msg_complete, TEGRA_I2C_TIMEOUT);
 479         tegra_i2c_mask_irq(i2c_dev, int_mask);
 480
 481         if (WARN_ON(ret == 0)) {
 482                 dev_err(i2c_dev->dev, "i2c transfer timed out\n");
 483
 484                 tegra_i2c_init(i2c_dev);
 485                 return -ETIMEDOUT;
 486         }
 487
 488         dev_dbg(i2c_dev->dev, "transfer complete: %d %d %d\n",
 489                 ret, completion_done(&i2c_dev->msg_complete), i2c_dev->msg_err);
 490
 491         if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
 492                 return 0;
 493
 494         tegra_i2c_init(i2c_dev);
 495         if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
 496                 if (msg->flags & I2C_M_IGNORE_NAK)
 497                         return 0;
 498                 return -EREMOTEIO;
 499         }
 500
 501         return -EIO;
 502 }
 503
 504 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
 505         int num)
 506 {
 507         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
 508         int i;
 509         int ret = 0;
 510
 511         if (i2c_dev->is_suspended)
 512                 return -EBUSY;
 513
 514         clk_enable(i2c_dev->clk);
 515         for (i = 0; i < num; i++) {
 516                 int stop = (i == (num - 1)) ? 1  : 0;
 517                 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], stop);
 518                 if (ret)
 519                         break;
 520         }
 521         clk_disable(i2c_dev->clk);
 522         return ret ?: i;
 523 }
 524
 525 static u32 tegra_i2c_func(struct i2c_adapter *adap)
 526 {
 527         return I2C_FUNC_I2C;
 528 }
 529
 530 static const struct i2c_algorithm tegra_i2c_algo = {
 531         .master_xfer    = tegra_i2c_xfer,
 532         .functionality  = tegra_i2c_func,
 533 };
 534
 535 static int tegra_i2c_probe(struct platform_device *pdev)
 536 {
 537         struct tegra_i2c_dev *i2c_dev;
 538         struct tegra_i2c_platform_data *pdata = pdev->dev.platform_data;
 539         struct resource *res;
 540         struct resource *iomem;
 541         struct clk *clk;
 542         struct clk *i2c_clk;
 543         void *base;
 544         int irq;
 545         int ret = 0;
 546
 547         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 548         if (!res) {
 549                 dev_err(&pdev->dev, "no mem resource\n");
 550                 return -EINVAL;
 551         }
 552         iomem = request_mem_region(res->start, resource_size(res), pdev->name);
 553         if (!iomem) {
 554                 dev_err(&pdev->dev, "I2C region already claimed\n");
 555                 return -EBUSY;
 556         }
 557
 558         base = ioremap(iomem->start, resource_size(iomem));
 559         if (!base) {
 560                 dev_err(&pdev->dev, "Cannot ioremap I2C region\n");
 561                 return -ENOMEM;
 562         }
 563
 564         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 565         if (!res) {
 566                 dev_err(&pdev->dev, "no irq resource\n");
 567                 ret = -EINVAL;
 568                 goto err_iounmap;
 569         }
 570         irq = res->start;
 571
 572         clk = clk_get(&pdev->dev, NULL);
 573         if (IS_ERR(clk)) {
 574                 dev_err(&pdev->dev, "missing controller clock");
 575                 ret = PTR_ERR(clk);
 576                 goto err_release_region;
 577         }
 578
 579         i2c_clk = clk_get(&pdev->dev, "i2c");
 580         if (IS_ERR(i2c_clk)) {
 581                 dev_err(&pdev->dev, "missing bus clock");
 582                 ret = PTR_ERR(i2c_clk);
 583                 goto err_clk_put;
 584         }
 585
 586         i2c_dev = kzalloc(sizeof(struct tegra_i2c_dev), GFP_KERNEL);
 587         if (!i2c_dev) {
 588                 ret = -ENOMEM;
 589                 goto err_i2c_clk_put;
 590         }
 591
 592         i2c_dev->base = base;
 593         i2c_dev->clk = clk;
 594         i2c_dev->i2c_clk = i2c_clk;
 595         i2c_dev->iomem = iomem;
 596         i2c_dev->adapter.algo = &tegra_i2c_algo;
 597         i2c_dev->irq = irq;
 598         i2c_dev->cont_id = pdev->id;
 599         i2c_dev->dev = &pdev->dev;
 600         i2c_dev->bus_clk_rate = pdata ? pdata->bus_clk_rate : 100000;
 601
 602         if (pdev->id == 3)
 603                 i2c_dev->is_dvc = 1;
 604         init_completion(&i2c_dev->msg_complete);
 605
 606         platform_set_drvdata(pdev, i2c_dev);
 607
 608         ret = tegra_i2c_init(i2c_dev);
 609         if (ret) {
 610                 dev_err(&pdev->dev, "Failed to initialize i2c controller");
 611                 goto err_free;
 612         }
 613
 614         ret = request_irq(i2c_dev->irq, tegra_i2c_isr, 0, pdev->name, i2c_dev);
 615         if (ret) {
 616                 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
 617                 goto err_free;
 618         }
 619
 620         clk_enable(i2c_dev->i2c_clk);
 621
 622         i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
 623         i2c_dev->adapter.owner = THIS_MODULE;
 624         i2c_dev->adapter.class = I2C_CLASS_HWMON;
 625         strlcpy(i2c_dev->adapter.name, "Tegra I2C adapter",
 626                 sizeof(i2c_dev->adapter.name));
 627         i2c_dev->adapter.algo = &tegra_i2c_algo;
 628         i2c_dev->adapter.dev.parent = &pdev->dev;
 629         i2c_dev->adapter.nr = pdev->id;
 630
 631         ret = i2c_add_numbered_adapter(&i2c_dev->adapter);
 632         if (ret) {
 633                 dev_err(&pdev->dev, "Failed to add I2C adapter\n");
 634                 goto err_free_irq;
 635         }
 636
 637         return 0;
 638 err_free_irq:
 639         free_irq(i2c_dev->irq, i2c_dev);
 640 err_free:
 641         kfree(i2c_dev);
 642 err_i2c_clk_put:
 643         clk_put(i2c_clk);
 644 err_clk_put:
 645         clk_put(clk);
 646 err_release_region:
 647         release_mem_region(iomem->start, resource_size(iomem));
 648 err_iounmap:
 649         iounmap(base);
 650         return ret;
 651 }
 652
 653 static int tegra_i2c_remove(struct platform_device *pdev)
 654 {
 655         struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
 656         i2c_del_adapter(&i2c_dev->adapter);
 657         free_irq(i2c_dev->irq, i2c_dev);
 658         clk_put(i2c_dev->i2c_clk);
 659         clk_put(i2c_dev->clk);
 660         release_mem_region(i2c_dev->iomem->start,
 661                 resource_size(i2c_dev->iomem));
 662         iounmap(i2c_dev->base);
 663         kfree(i2c_dev);
 664         return 0;
 665 }
 666
 667 #ifdef CONFIG_PM
 668 static int tegra_i2c_suspend(struct platform_device *pdev, pm_message_t state)
 669 {
 670         struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
 671
 672         i2c_lock_adapter(&i2c_dev->adapter);
 673         i2c_dev->is_suspended = true;
 674         i2c_unlock_adapter(&i2c_dev->adapter);
 675
 676         return 0;
 677 }
 678
 679 static int tegra_i2c_resume(struct platform_device *pdev)
 680 {
 681         struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
 682         int ret;
 683
 684         i2c_lock_adapter(&i2c_dev->adapter);
 685
 686         ret = tegra_i2c_init(i2c_dev);
 687
 688         if (ret) {
 689                 i2c_unlock_adapter(&i2c_dev->adapter);
 690                 return ret;
 691         }
 692
 693         i2c_dev->is_suspended = false;
 694
 695         i2c_unlock_adapter(&i2c_dev->adapter);
 696
 697         return 0;
 698 }
 699 #endif
 700
 701 static struct platform_driver tegra_i2c_driver = {
 702         .probe   = tegra_i2c_probe,
 703         .remove  = tegra_i2c_remove,
 704 #ifdef CONFIG_PM
 705         .suspend = tegra_i2c_suspend,
 706         .resume  = tegra_i2c_resume,
 707 #endif
 708         .driver  = {
 709                 .name  = "tegra-i2c",
 710                 .owner = THIS_MODULE,
 711         },
 712 };
 713
 714 static int __init tegra_i2c_init_driver(void)
 715 {
 716         return platform_driver_register(&tegra_i2c_driver);
 717 }
 718
 719 static void __exit tegra_i2c_exit_driver(void)
 720 {
 721         platform_driver_unregister(&tegra_i2c_driver);
 722 }
 723
 724 subsys_initcall(tegra_i2c_init_driver);
 725 module_exit(tegra_i2c_exit_driver);
 726
 727 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
 728 MODULE_AUTHOR("Colin Cross");
 729 MODULE_LICENSE("GPL v2");