drivers/i2c/busses/i2c-omap.c

   1 /*
   2  * TI OMAP I2C master mode driver
   3  *
   4  * Copyright (C) 2003 MontaVista Software, Inc.
   5  * Copyright (C) 2005 Nokia Corporation
   6  * Copyright (C) 2004 - 2007 Texas Instruments.
   7  *
   8  * Originally written by MontaVista Software, Inc.
   9  * Additional contributions by:
  10  *      Tony Lindgren <tony@atomide.com>
  11  *      Imre Deak <imre.deak@nokia.com>
  12  *      Juha Yrjölä <juha.yrjola@solidboot.com>
  13  *      Syed Khasim <x0khasim@ti.com>
  14  *      Nishant Menon <nm@ti.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License as published by
  18  * the Free Software Foundation; either version 2 of the License, or
  19  * (at your option) any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24  * GNU General Public License for more details.
  25  *
  26  * You should have received a copy of the GNU General Public License
  27  * along with this program; if not, write to the Free Software
  28  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  29  */
  30
  31 #include <linux/module.h>
  32 #include <linux/delay.h>
  33 #include <linux/i2c.h>
  34 #include <linux/err.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/completion.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/clk.h>
  39 #include <linux/io.h>
  40 #include <linux/slab.h>
  41 #include <linux/i2c-omap.h>
  42 #include <linux/pm_runtime.h>
  43
  44 /* I2C controller revisions */
  45 #define OMAP_I2C_REV_2                  0x20
  46
  47 /* I2C controller revisions present on specific hardware */
  48 #define OMAP_I2C_REV_ON_2430            0x36
  49 #define OMAP_I2C_REV_ON_3430            0x3C
  50 #define OMAP_I2C_REV_ON_4430            0x40
  51
  52 /* timeout waiting for the controller to respond */
  53 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
  54
  55 /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
  56 enum {
  57         OMAP_I2C_REV_REG = 0,
  58         OMAP_I2C_IE_REG,
  59         OMAP_I2C_STAT_REG,
  60         OMAP_I2C_IV_REG,
  61         OMAP_I2C_WE_REG,
  62         OMAP_I2C_SYSS_REG,
  63         OMAP_I2C_BUF_REG,
  64         OMAP_I2C_CNT_REG,
  65         OMAP_I2C_DATA_REG,
  66         OMAP_I2C_SYSC_REG,
  67         OMAP_I2C_CON_REG,
  68         OMAP_I2C_OA_REG,
  69         OMAP_I2C_SA_REG,
  70         OMAP_I2C_PSC_REG,
  71         OMAP_I2C_SCLL_REG,
  72         OMAP_I2C_SCLH_REG,
  73         OMAP_I2C_SYSTEST_REG,
  74         OMAP_I2C_BUFSTAT_REG,
  75         OMAP_I2C_REVNB_LO,
  76         OMAP_I2C_REVNB_HI,
  77         OMAP_I2C_IRQSTATUS_RAW,
  78         OMAP_I2C_IRQENABLE_SET,
  79         OMAP_I2C_IRQENABLE_CLR,
  80 };
  81
  82 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
  83 #define OMAP_I2C_IE_XDR         (1 << 14)       /* TX Buffer drain int enable */
  84 #define OMAP_I2C_IE_RDR         (1 << 13)       /* RX Buffer drain int enable */
  85 #define OMAP_I2C_IE_XRDY        (1 << 4)        /* TX data ready int enable */
  86 #define OMAP_I2C_IE_RRDY        (1 << 3)        /* RX data ready int enable */
  87 #define OMAP_I2C_IE_ARDY        (1 << 2)        /* Access ready int enable */
  88 #define OMAP_I2C_IE_NACK        (1 << 1)        /* No ack interrupt enable */
  89 #define OMAP_I2C_IE_AL          (1 << 0)        /* Arbitration lost int ena */
  90
  91 /* I2C Status Register (OMAP_I2C_STAT): */
  92 #define OMAP_I2C_STAT_XDR       (1 << 14)       /* TX Buffer draining */
  93 #define OMAP_I2C_STAT_RDR       (1 << 13)       /* RX Buffer draining */
  94 #define OMAP_I2C_STAT_BB        (1 << 12)       /* Bus busy */
  95 #define OMAP_I2C_STAT_ROVR      (1 << 11)       /* Receive overrun */
  96 #define OMAP_I2C_STAT_XUDF      (1 << 10)       /* Transmit underflow */
  97 #define OMAP_I2C_STAT_AAS       (1 << 9)        /* Address as slave */
  98 #define OMAP_I2C_STAT_AD0       (1 << 8)        /* Address zero */
  99 #define OMAP_I2C_STAT_XRDY      (1 << 4)        /* Transmit data ready */
 100 #define OMAP_I2C_STAT_RRDY      (1 << 3)        /* Receive data ready */
 101 #define OMAP_I2C_STAT_ARDY      (1 << 2)        /* Register access ready */
 102 #define OMAP_I2C_STAT_NACK      (1 << 1)        /* No ack interrupt enable */
 103 #define OMAP_I2C_STAT_AL        (1 << 0)        /* Arbitration lost int ena */
 104
 105 /* I2C WE wakeup enable register */
 106 #define OMAP_I2C_WE_XDR_WE      (1 << 14)       /* TX drain wakup */
 107 #define OMAP_I2C_WE_RDR_WE      (1 << 13)       /* RX drain wakeup */
 108 #define OMAP_I2C_WE_AAS_WE      (1 << 9)        /* Address as slave wakeup*/
 109 #define OMAP_I2C_WE_BF_WE       (1 << 8)        /* Bus free wakeup */
 110 #define OMAP_I2C_WE_STC_WE      (1 << 6)        /* Start condition wakeup */
 111 #define OMAP_I2C_WE_GC_WE       (1 << 5)        /* General call wakeup */
 112 #define OMAP_I2C_WE_DRDY_WE     (1 << 3)        /* TX/RX data ready wakeup */
 113 #define OMAP_I2C_WE_ARDY_WE     (1 << 2)        /* Reg access ready wakeup */
 114 #define OMAP_I2C_WE_NACK_WE     (1 << 1)        /* No acknowledgment wakeup */
 115 #define OMAP_I2C_WE_AL_WE       (1 << 0)        /* Arbitration lost wakeup */
 116
 117 #define OMAP_I2C_WE_ALL         (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
 118                                 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
 119                                 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
 120                                 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
 121                                 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
 122
 123 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
 124 #define OMAP_I2C_BUF_RDMA_EN    (1 << 15)       /* RX DMA channel enable */
 125 #define OMAP_I2C_BUF_RXFIF_CLR  (1 << 14)       /* RX FIFO Clear */
 126 #define OMAP_I2C_BUF_XDMA_EN    (1 << 7)        /* TX DMA channel enable */
 127 #define OMAP_I2C_BUF_TXFIF_CLR  (1 << 6)        /* TX FIFO Clear */
 128
 129 /* I2C Configuration Register (OMAP_I2C_CON): */
 130 #define OMAP_I2C_CON_EN         (1 << 15)       /* I2C module enable */
 131 #define OMAP_I2C_CON_BE         (1 << 14)       /* Big endian mode */
 132 #define OMAP_I2C_CON_OPMODE_HS  (1 << 12)       /* High Speed support */
 133 #define OMAP_I2C_CON_STB        (1 << 11)       /* Start byte mode (master) */
 134 #define OMAP_I2C_CON_MST        (1 << 10)       /* Master/slave mode */
 135 #define OMAP_I2C_CON_TRX        (1 << 9)        /* TX/RX mode (master only) */
 136 #define OMAP_I2C_CON_XA         (1 << 8)        /* Expand address */
 137 #define OMAP_I2C_CON_RM         (1 << 2)        /* Repeat mode (master only) */
 138 #define OMAP_I2C_CON_STP        (1 << 1)        /* Stop cond (master only) */
 139 #define OMAP_I2C_CON_STT        (1 << 0)        /* Start condition (master) */
 140
 141 /* I2C SCL time value when Master */
 142 #define OMAP_I2C_SCLL_HSSCLL    8
 143 #define OMAP_I2C_SCLH_HSSCLH    8
 144
 145 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
 146 #ifdef DEBUG
 147 #define OMAP_I2C_SYSTEST_ST_EN          (1 << 15)       /* System test enable */
 148 #define OMAP_I2C_SYSTEST_FREE           (1 << 14)       /* Free running mode */
 149 #define OMAP_I2C_SYSTEST_TMODE_MASK     (3 << 12)       /* Test mode select */
 150 #define OMAP_I2C_SYSTEST_TMODE_SHIFT    (12)            /* Test mode select */
 151 #define OMAP_I2C_SYSTEST_SCL_I          (1 << 3)        /* SCL line sense in */
 152 #define OMAP_I2C_SYSTEST_SCL_O          (1 << 2)        /* SCL line drive out */
 153 #define OMAP_I2C_SYSTEST_SDA_I          (1 << 1)        /* SDA line sense in */
 154 #define OMAP_I2C_SYSTEST_SDA_O          (1 << 0)        /* SDA line drive out */
 155 #endif
 156
 157 /* OCP_SYSSTATUS bit definitions */
 158 #define SYSS_RESETDONE_MASK             (1 << 0)
 159
 160 /* OCP_SYSCONFIG bit definitions */
 161 #define SYSC_CLOCKACTIVITY_MASK         (0x3 << 8)
 162 #define SYSC_SIDLEMODE_MASK             (0x3 << 3)
 163 #define SYSC_ENAWAKEUP_MASK             (1 << 2)
 164 #define SYSC_SOFTRESET_MASK             (1 << 1)
 165 #define SYSC_AUTOIDLE_MASK              (1 << 0)
 166
 167 #define SYSC_IDLEMODE_SMART             0x2
 168 #define SYSC_CLOCKACTIVITY_FCLK         0x2
 169
 170 /* Errata definitions */
 171 #define I2C_OMAP_ERRATA_I207            (1 << 0)
 172 #define I2C_OMAP3_1P153                 (1 << 1)
 173
 174 struct omap_i2c_dev {
 175         struct device           *dev;
 176         void __iomem            *base;          /* virtual */
 177         int                     irq;
 178         int                     reg_shift;      /* bit shift for I2C register addresses */
 179         struct completion       cmd_complete;
 180         struct resource         *ioarea;
 181         u32                     latency;        /* maximum mpu wkup latency */
 182         void                    (*set_mpu_wkup_lat)(struct device *dev,
 183                                                     long latency);
 184         u32                     speed;          /* Speed of bus in Khz */
 185         u16                     cmd_err;
 186         u8                      *buf;
 187         u8                      *regs;
 188         size_t                  buf_len;
 189         struct i2c_adapter      adapter;
 190         u8                      fifo_size;      /* use as flag and value
 191                                                  * fifo_size==0 implies no fifo
 192                                                  * if set, should be trsh+1
 193                                                  */
 194         u8                      rev;
 195         unsigned                b_hw:1;         /* bad h/w fixes */
 196         unsigned                idle:1;
 197         u16                     iestate;        /* Saved interrupt register */
 198         u16                     pscstate;
 199         u16                     scllstate;
 200         u16                     sclhstate;
 201         u16                     bufstate;
 202         u16                     syscstate;
 203         u16                     westate;
 204         u16                     errata;
 205 };
 206
 207 static const u8 reg_map[] = {
 208         [OMAP_I2C_REV_REG] = 0x00,
 209         [OMAP_I2C_IE_REG] = 0x01,
 210         [OMAP_I2C_STAT_REG] = 0x02,
 211         [OMAP_I2C_IV_REG] = 0x03,
 212         [OMAP_I2C_WE_REG] = 0x03,
 213         [OMAP_I2C_SYSS_REG] = 0x04,
 214         [OMAP_I2C_BUF_REG] = 0x05,
 215         [OMAP_I2C_CNT_REG] = 0x06,
 216         [OMAP_I2C_DATA_REG] = 0x07,
 217         [OMAP_I2C_SYSC_REG] = 0x08,
 218         [OMAP_I2C_CON_REG] = 0x09,
 219         [OMAP_I2C_OA_REG] = 0x0a,
 220         [OMAP_I2C_SA_REG] = 0x0b,
 221         [OMAP_I2C_PSC_REG] = 0x0c,
 222         [OMAP_I2C_SCLL_REG] = 0x0d,
 223         [OMAP_I2C_SCLH_REG] = 0x0e,
 224         [OMAP_I2C_SYSTEST_REG] = 0x0f,
 225         [OMAP_I2C_BUFSTAT_REG] = 0x10,
 226 };
 227
 228 static const u8 omap4_reg_map[] = {
 229         [OMAP_I2C_REV_REG] = 0x04,
 230         [OMAP_I2C_IE_REG] = 0x2c,
 231         [OMAP_I2C_STAT_REG] = 0x28,
 232         [OMAP_I2C_IV_REG] = 0x34,
 233         [OMAP_I2C_WE_REG] = 0x34,
 234         [OMAP_I2C_SYSS_REG] = 0x90,
 235         [OMAP_I2C_BUF_REG] = 0x94,
 236         [OMAP_I2C_CNT_REG] = 0x98,
 237         [OMAP_I2C_DATA_REG] = 0x9c,
 238         [OMAP_I2C_SYSC_REG] = 0x20,
 239         [OMAP_I2C_CON_REG] = 0xa4,
 240         [OMAP_I2C_OA_REG] = 0xa8,
 241         [OMAP_I2C_SA_REG] = 0xac,
 242         [OMAP_I2C_PSC_REG] = 0xb0,
 243         [OMAP_I2C_SCLL_REG] = 0xb4,
 244         [OMAP_I2C_SCLH_REG] = 0xb8,
 245         [OMAP_I2C_SYSTEST_REG] = 0xbC,
 246         [OMAP_I2C_BUFSTAT_REG] = 0xc0,
 247         [OMAP_I2C_REVNB_LO] = 0x00,
 248         [OMAP_I2C_REVNB_HI] = 0x04,
 249         [OMAP_I2C_IRQSTATUS_RAW] = 0x24,
 250         [OMAP_I2C_IRQENABLE_SET] = 0x2c,
 251         [OMAP_I2C_IRQENABLE_CLR] = 0x30,
 252 };
 253
 254 static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
 255                                       int reg, u16 val)
 256 {
 257         __raw_writew(val, i2c_dev->base +
 258                         (i2c_dev->regs[reg] << i2c_dev->reg_shift));
 259 }
 260
 261 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
 262 {
 263         return __raw_readw(i2c_dev->base +
 264                                 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
 265 }
 266
 267 static void omap_i2c_unidle(struct omap_i2c_dev *dev)
 268 {
 269         struct platform_device *pdev;
 270         struct omap_i2c_bus_platform_data *pdata;
 271
 272         WARN_ON(!dev->idle);
 273
 274         pdev = to_platform_device(dev->dev);
 275         pdata = pdev->dev.platform_data;
 276
 277         pm_runtime_get_sync(&pdev->dev);
 278
 279         if (cpu_is_omap34xx()) {
 280                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 281                 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);
 282                 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate);
 283                 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate);
 284                 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, dev->bufstate);
 285                 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, dev->syscstate);
 286                 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
 287                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 288         }
 289         dev->idle = 0;
 290
 291         /*
 292          * Don't write to this register if the IE state is 0 as it can
 293          * cause deadlock.
 294          */
 295         if (dev->iestate)
 296                 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
 297 }
 298
 299 static void omap_i2c_idle(struct omap_i2c_dev *dev)
 300 {
 301         struct platform_device *pdev;
 302         struct omap_i2c_bus_platform_data *pdata;
 303         u16 iv;
 304
 305         WARN_ON(dev->idle);
 306
 307         pdev = to_platform_device(dev->dev);
 308         pdata = pdev->dev.platform_data;
 309
 310         dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
 311         if (dev->rev >= OMAP_I2C_REV_ON_4430)
 312                 omap_i2c_write_reg(dev, OMAP_I2C_IRQENABLE_CLR, 1);
 313         else
 314                 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
 315
 316         if (dev->rev < OMAP_I2C_REV_2) {
 317                 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */
 318         } else {
 319                 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);
 320
 321                 /* Flush posted write before the dev->idle store occurs */
 322                 omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
 323         }
 324         dev->idle = 1;
 325
 326         pm_runtime_put_sync(&pdev->dev);
 327 }
 328
 329 static int omap_i2c_init(struct omap_i2c_dev *dev)
 330 {
 331         u16 psc = 0, scll = 0, sclh = 0, buf = 0;
 332         u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
 333         unsigned long fclk_rate = 12000000;
 334         unsigned long timeout;
 335         unsigned long internal_clk = 0;
 336         struct clk *fclk;
 337
 338         if (dev->rev >= OMAP_I2C_REV_2) {
 339                 /* Disable I2C controller before soft reset */
 340                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
 341                         omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) &
 342                                 ~(OMAP_I2C_CON_EN));
 343
 344                 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
 345                 /* For some reason we need to set the EN bit before the
 346                  * reset done bit gets set. */
 347                 timeout = jiffies + OMAP_I2C_TIMEOUT;
 348                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 349                 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
 350                          SYSS_RESETDONE_MASK)) {
 351                         if (time_after(jiffies, timeout)) {
 352                                 dev_warn(dev->dev, "timeout waiting "
 353                                                 "for controller reset\n");
 354                                 return -ETIMEDOUT;
 355                         }
 356                         msleep(1);
 357                 }
 358
 359                 /* SYSC register is cleared by the reset; rewrite it */
 360                 if (dev->rev == OMAP_I2C_REV_ON_2430) {
 361
 362                         omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
 363                                            SYSC_AUTOIDLE_MASK);
 364
 365                 } else if (dev->rev >= OMAP_I2C_REV_ON_3430) {
 366                         dev->syscstate = SYSC_AUTOIDLE_MASK;
 367                         dev->syscstate |= SYSC_ENAWAKEUP_MASK;
 368                         dev->syscstate |= (SYSC_IDLEMODE_SMART <<
 369                               __ffs(SYSC_SIDLEMODE_MASK));
 370                         dev->syscstate |= (SYSC_CLOCKACTIVITY_FCLK <<
 371                               __ffs(SYSC_CLOCKACTIVITY_MASK));
 372
 373                         omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
 374                                                         dev->syscstate);
 375                         /*
 376                          * Enabling all wakup sources to stop I2C freezing on
 377                          * WFI instruction.
 378                          * REVISIT: Some wkup sources might not be needed.
 379                          */
 380                         dev->westate = OMAP_I2C_WE_ALL;
 381                         omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
 382                 }
 383         }
 384         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 385
 386         if (cpu_class_is_omap1()) {
 387                 /*
 388                  * The I2C functional clock is the armxor_ck, so there's
 389                  * no need to get "armxor_ck" separately.  Now, if OMAP2420
 390                  * always returns 12MHz for the functional clock, we can
 391                  * do this bit unconditionally.
 392                  */
 393                 fclk = clk_get(dev->dev, "fck");
 394                 fclk_rate = clk_get_rate(fclk);
 395                 clk_put(fclk);
 396
 397                 /* TRM for 5912 says the I2C clock must be prescaled to be
 398                  * between 7 - 12 MHz. The XOR input clock is typically
 399                  * 12, 13 or 19.2 MHz. So we should have code that produces:
 400                  *
 401                  * XOR MHz      Divider         Prescaler
 402                  * 12           1               0
 403                  * 13           2               1
 404                  * 19.2         2               1
 405                  */
 406                 if (fclk_rate > 12000000)
 407                         psc = fclk_rate / 12000000;
 408         }
 409
 410         if (!(cpu_class_is_omap1() || cpu_is_omap2420())) {
 411
 412                 /*
 413                  * HSI2C controller internal clk rate should be 19.2 Mhz for
 414                  * HS and for all modes on 2430. On 34xx we can use lower rate
 415                  * to get longer filter period for better noise suppression.
 416                  * The filter is iclk (fclk for HS) period.
 417                  */
 418                 if (dev->speed > 400 || cpu_is_omap2430())
 419                         internal_clk = 19200;
 420                 else if (dev->speed > 100)
 421                         internal_clk = 9600;
 422                 else
 423                         internal_clk = 4000;
 424                 fclk = clk_get(dev->dev, "fck");
 425                 fclk_rate = clk_get_rate(fclk) / 1000;
 426                 clk_put(fclk);
 427
 428                 /* Compute prescaler divisor */
 429                 psc = fclk_rate / internal_clk;
 430                 psc = psc - 1;
 431
 432                 /* If configured for High Speed */
 433                 if (dev->speed > 400) {
 434                         unsigned long scl;
 435
 436                         /* For first phase of HS mode */
 437                         scl = internal_clk / 400;
 438                         fsscll = scl - (scl / 3) - 7;
 439                         fssclh = (scl / 3) - 5;
 440
 441                         /* For second phase of HS mode */
 442                         scl = fclk_rate / dev->speed;
 443                         hsscll = scl - (scl / 3) - 7;
 444                         hssclh = (scl / 3) - 5;
 445                 } else if (dev->speed > 100) {
 446                         unsigned long scl;
 447
 448                         /* Fast mode */
 449                         scl = internal_clk / dev->speed;
 450                         fsscll = scl - (scl / 3) - 7;
 451                         fssclh = (scl / 3) - 5;
 452                 } else {
 453                         /* Standard mode */
 454                         fsscll = internal_clk / (dev->speed * 2) - 7;
 455                         fssclh = internal_clk / (dev->speed * 2) - 5;
 456                 }
 457                 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
 458                 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
 459         } else {
 460                 /* Program desired operating rate */
 461                 fclk_rate /= (psc + 1) * 1000;
 462                 if (psc > 2)
 463                         psc = 2;
 464                 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
 465                 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
 466         }
 467
 468         /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
 469         omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
 470
 471         /* SCL low and high time values */
 472         omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
 473         omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
 474
 475         if (dev->fifo_size) {
 476                 /* Note: setup required fifo size - 1. RTRSH and XTRSH */
 477                 buf = (dev->fifo_size - 1) << 8 | OMAP_I2C_BUF_RXFIF_CLR |
 478                         (dev->fifo_size - 1) | OMAP_I2C_BUF_TXFIF_CLR;
 479                 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);
 480         }
 481
 482         /* Take the I2C module out of reset: */
 483         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 484
 485         dev->errata = 0;
 486
 487         if (cpu_is_omap2430() || cpu_is_omap34xx())
 488                 dev->errata |= I2C_OMAP_ERRATA_I207;
 489
 490         /* Enable interrupts */
 491         dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
 492                         OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
 493                         OMAP_I2C_IE_AL)  | ((dev->fifo_size) ?
 494                                 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
 495         omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
 496         if (cpu_is_omap34xx()) {
 497                 dev->pscstate = psc;
 498                 dev->scllstate = scll;
 499                 dev->sclhstate = sclh;
 500                 dev->bufstate = buf;
 501         }
 502         return 0;
 503 }
 504
 505 /*
 506  * Waiting on Bus Busy
 507  */
 508 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
 509 {
 510         unsigned long timeout;
 511
 512         timeout = jiffies + OMAP_I2C_TIMEOUT;
 513         while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
 514                 if (time_after(jiffies, timeout)) {
 515                         dev_warn(dev->dev, "timeout waiting for bus ready\n");
 516                         return -ETIMEDOUT;
 517                 }
 518                 msleep(1);
 519         }
 520
 521         return 0;
 522 }
 523
 524 /*
 525  * Low level master read/write transaction.
 526  */
 527 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
 528                              struct i2c_msg *msg, int stop)
 529 {
 530         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
 531         int r;
 532         u16 w;
 533
 534         dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
 535                 msg->addr, msg->len, msg->flags, stop);
 536
 537         if (msg->len == 0)
 538                 return -EINVAL;
 539
 540         omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
 541
 542         /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
 543         dev->buf = msg->buf;
 544         dev->buf_len = msg->len;
 545
 546         omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
 547
 548         /* Clear the FIFO Buffers */
 549         w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
 550         w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
 551         omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
 552
 553         init_completion(&dev->cmd_complete);
 554         dev->cmd_err = 0;
 555
 556         w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
 557
 558         /* High speed configuration */
 559         if (dev->speed > 400)
 560                 w |= OMAP_I2C_CON_OPMODE_HS;
 561
 562         if (msg->flags & I2C_M_TEN)
 563                 w |= OMAP_I2C_CON_XA;
 564         if (!(msg->flags & I2C_M_RD))
 565                 w |= OMAP_I2C_CON_TRX;
 566
 567         if (!dev->b_hw && stop)
 568                 w |= OMAP_I2C_CON_STP;
 569
 570         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 571
 572         /*
 573          * Don't write stt and stp together on some hardware.
 574          */
 575         if (dev->b_hw && stop) {
 576                 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
 577                 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
 578                 while (con & OMAP_I2C_CON_STT) {
 579                         con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
 580
 581                         /* Let the user know if i2c is in a bad state */
 582                         if (time_after(jiffies, delay)) {
 583                                 dev_err(dev->dev, "controller timed out "
 584                                 "waiting for start condition to finish\n");
 585                                 return -ETIMEDOUT;
 586                         }
 587                         cpu_relax();
 588                 }
 589
 590                 w |= OMAP_I2C_CON_STP;
 591                 w &= ~OMAP_I2C_CON_STT;
 592                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 593         }
 594
 595         /*
 596          * REVISIT: We should abort the transfer on signals, but the bus goes
 597          * into arbitration and we're currently unable to recover from it.
 598          */
 599         r = wait_for_completion_timeout(&dev->cmd_complete,
 600                                         OMAP_I2C_TIMEOUT);
 601         dev->buf_len = 0;
 602         if (r < 0)
 603                 return r;
 604         if (r == 0) {
 605                 dev_err(dev->dev, "controller timed out\n");
 606                 omap_i2c_init(dev);
 607                 return -ETIMEDOUT;
 608         }
 609
 610         if (likely(!dev->cmd_err))
 611                 return 0;
 612
 613         /* We have an error */
 614         if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
 615                             OMAP_I2C_STAT_XUDF)) {
 616                 omap_i2c_init(dev);
 617                 return -EIO;
 618         }
 619
 620         if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
 621                 if (msg->flags & I2C_M_IGNORE_NAK)
 622                         return 0;
 623                 if (stop) {
 624                         w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
 625                         w |= OMAP_I2C_CON_STP;
 626                         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 627                 }
 628                 return -EREMOTEIO;
 629         }
 630         return -EIO;
 631 }
 632
 633
 634 /*
 635  * Prepare controller for a transaction and call omap_i2c_xfer_msg
 636  * to do the work during IRQ processing.
 637  */
 638 static int
 639 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 640 {
 641         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
 642         int i;
 643         int r;
 644
 645         omap_i2c_unidle(dev);
 646
 647         r = omap_i2c_wait_for_bb(dev);
 648         if (r < 0)
 649                 goto out;
 650
 651         if (dev->set_mpu_wkup_lat != NULL)
 652                 dev->set_mpu_wkup_lat(dev->dev, dev->latency);
 653
 654         for (i = 0; i < num; i++) {
 655                 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
 656                 if (r != 0)
 657                         break;
 658         }
 659
 660         if (dev->set_mpu_wkup_lat != NULL)
 661                 dev->set_mpu_wkup_lat(dev->dev, -1);
 662
 663         if (r == 0)
 664                 r = num;
 665
 666         omap_i2c_wait_for_bb(dev);
 667 out:
 668         omap_i2c_idle(dev);
 669         return r;
 670 }
 671
 672 static u32
 673 omap_i2c_func(struct i2c_adapter *adap)
 674 {
 675         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
 676 }
 677
 678 static inline void
 679 omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
 680 {
 681         dev->cmd_err |= err;
 682         complete(&dev->cmd_complete);
 683 }
 684
 685 static inline void
 686 omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
 687 {
 688         omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
 689 }
 690
 691 static inline void i2c_omap_errata_i207(struct omap_i2c_dev *dev, u16 stat)
 692 {
 693         /*
 694          * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8)
 695          * Not applicable for OMAP4.
 696          * Under certain rare conditions, RDR could be set again
 697          * when the bus is busy, then ignore the interrupt and
 698          * clear the interrupt.
 699          */
 700         if (stat & OMAP_I2C_STAT_RDR) {
 701                 /* Step 1: If RDR is set, clear it */
 702                 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
 703
 704                 /* Step 2: */
 705                 if (!(omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
 706                                                 & OMAP_I2C_STAT_BB)) {
 707
 708                         /* Step 3: */
 709                         if (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
 710                                                 & OMAP_I2C_STAT_RDR) {
 711                                 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
 712                                 dev_dbg(dev->dev, "RDR when bus is busy.\n");
 713                         }
 714
 715                 }
 716         }
 717 }
 718
 719 /* rev1 devices are apparently only on some 15xx */
 720 #ifdef CONFIG_ARCH_OMAP15XX
 721
 722 static irqreturn_t
 723 omap_i2c_rev1_isr(int this_irq, void *dev_id)
 724 {
 725         struct omap_i2c_dev *dev = dev_id;
 726         u16 iv, w;
 727
 728         if (dev->idle)
 729                 return IRQ_NONE;
 730
 731         iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
 732         switch (iv) {
 733         case 0x00:      /* None */
 734                 break;
 735         case 0x01:      /* Arbitration lost */
 736                 dev_err(dev->dev, "Arbitration lost\n");
 737                 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
 738                 break;
 739         case 0x02:      /* No acknowledgement */
 740                 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
 741                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
 742                 break;
 743         case 0x03:      /* Register access ready */
 744                 omap_i2c_complete_cmd(dev, 0);
 745                 break;
 746         case 0x04:      /* Receive data ready */
 747                 if (dev->buf_len) {
 748                         w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
 749                         *dev->buf++ = w;
 750                         dev->buf_len--;
 751                         if (dev->buf_len) {
 752                                 *dev->buf++ = w >> 8;
 753                                 dev->buf_len--;
 754                         }
 755                 } else
 756                         dev_err(dev->dev, "RRDY IRQ while no data requested\n");
 757                 break;
 758         case 0x05:      /* Transmit data ready */
 759                 if (dev->buf_len) {
 760                         w = *dev->buf++;
 761                         dev->buf_len--;
 762                         if (dev->buf_len) {
 763                                 w |= *dev->buf++ << 8;
 764                                 dev->buf_len--;
 765                         }
 766                         omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
 767                 } else
 768                         dev_err(dev->dev, "XRDY IRQ while no data to send\n");
 769                 break;
 770         default:
 771                 return IRQ_NONE;
 772         }
 773
 774         return IRQ_HANDLED;
 775 }
 776 #else
 777 #define omap_i2c_rev1_isr               NULL
 778 #endif
 779
 780 /*
 781  * OMAP3430 Errata 1.153: When an XRDY/XDR is hit, wait for XUDF before writing
 782  * data to DATA_REG. Otherwise some data bytes can be lost while transferring
 783  * them from the memory to the I2C interface.
 784  */
 785 static int errata_omap3_1p153(struct omap_i2c_dev *dev, u16 *stat, int *err)
 786 {
 787         unsigned long timeout = 10000;
 788
 789         while (--timeout && !(*stat & OMAP_I2C_STAT_XUDF)) {
 790                 if (*stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
 791                         omap_i2c_ack_stat(dev, *stat & (OMAP_I2C_STAT_XRDY |
 792                                                         OMAP_I2C_STAT_XDR));
 793                         *err |= OMAP_I2C_STAT_XUDF;
 794                         return -ETIMEDOUT;
 795                 }
 796
 797                 cpu_relax();
 798                 *stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
 799         }
 800
 801         if (!timeout) {
 802                 dev_err(dev->dev, "timeout waiting on XUDF bit\n");
 803                 return 0;
 804         }
 805
 806         return 0;
 807 }
 808
 809 static irqreturn_t
 810 omap_i2c_isr(int this_irq, void *dev_id)
 811 {
 812         struct omap_i2c_dev *dev = dev_id;
 813         u16 bits;
 814         u16 stat, w;
 815         int err, count = 0;
 816
 817         if (dev->idle)
 818                 return IRQ_NONE;
 819
 820         bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
 821         while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
 822                 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
 823                 if (count++ == 100) {
 824                         dev_warn(dev->dev, "Too much work in one IRQ\n");
 825                         break;
 826                 }
 827
 828                 err = 0;
 829 complete:
 830                 /*
 831                  * Ack the stat in one go, but [R/X]DR and [R/X]RDY should be
 832                  * acked after the data operation is complete.
 833                  * Ref: TRM SWPU114Q Figure 18-31
 834                  */
 835                 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat &
 836                                 ~(OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
 837                                 OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
 838
 839                 if (stat & OMAP_I2C_STAT_NACK) {
 840                         err |= OMAP_I2C_STAT_NACK;
 841                         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
 842                                            OMAP_I2C_CON_STP);
 843                 }
 844                 if (stat & OMAP_I2C_STAT_AL) {
 845                         dev_err(dev->dev, "Arbitration lost\n");
 846                         err |= OMAP_I2C_STAT_AL;
 847                 }
 848                 /*
 849                  * ProDB0017052: Clear ARDY bit twice
 850                  */
 851                 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
 852                                         OMAP_I2C_STAT_AL)) {
 853                         omap_i2c_ack_stat(dev, stat &
 854                                 (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
 855                                 OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR |
 856                                 OMAP_I2C_STAT_ARDY));
 857                         omap_i2c_complete_cmd(dev, err);
 858                         return IRQ_HANDLED;
 859                 }
 860                 if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
 861                         u8 num_bytes = 1;
 862
 863                         if (dev->errata & I2C_OMAP_ERRATA_I207)
 864                                 i2c_omap_errata_i207(dev, stat);
 865
 866                         if (dev->fifo_size) {
 867                                 if (stat & OMAP_I2C_STAT_RRDY)
 868                                         num_bytes = dev->fifo_size;
 869                                 else    /* read RXSTAT on RDR interrupt */
 870                                         num_bytes = (omap_i2c_read_reg(dev,
 871                                                         OMAP_I2C_BUFSTAT_REG)
 872                                                         >> 8) & 0x3F;
 873                         }
 874                         while (num_bytes) {
 875                                 num_bytes--;
 876                                 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
 877                                 if (dev->buf_len) {
 878                                         *dev->buf++ = w;
 879                                         dev->buf_len--;
 880                                         /*
 881                                          * Data reg in 2430, omap3 and
 882                                          * omap4 is 8 bit wide
 883                                          */
 884                                         if (cpu_class_is_omap1() ||
 885                                                         cpu_is_omap2420()) {
 886                                                 if (dev->buf_len) {
 887                                                         *dev->buf++ = w >> 8;
 888                                                         dev->buf_len--;
 889                                                 }
 890                                         }
 891                                 } else {
 892                                         if (stat & OMAP_I2C_STAT_RRDY)
 893                                                 dev_err(dev->dev,
 894                                                         "RRDY IRQ while no data"
 895                                                                 " requested\n");
 896                                         if (stat & OMAP_I2C_STAT_RDR)
 897                                                 dev_err(dev->dev,
 898                                                         "RDR IRQ while no data"
 899                                                                 " requested\n");
 900                                         break;
 901                                 }
 902                         }
 903                         omap_i2c_ack_stat(dev,
 904                                 stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
 905                         continue;
 906                 }
 907                 if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
 908                         u8 num_bytes = 1;
 909                         if (dev->fifo_size) {
 910                                 if (stat & OMAP_I2C_STAT_XRDY)
 911                                         num_bytes = dev->fifo_size;
 912                                 else    /* read TXSTAT on XDR interrupt */
 913                                         num_bytes = omap_i2c_read_reg(dev,
 914                                                         OMAP_I2C_BUFSTAT_REG)
 915                                                         & 0x3F;
 916                         }
 917                         while (num_bytes) {
 918                                 num_bytes--;
 919                                 w = 0;
 920                                 if (dev->buf_len) {
 921                                         w = *dev->buf++;
 922                                         dev->buf_len--;
 923                                         /*
 924                                          * Data reg in 2430, omap3 and
 925                                          * omap4 is 8 bit wide
 926                                          */
 927                                         if (cpu_class_is_omap1() ||
 928                                                         cpu_is_omap2420()) {
 929                                                 if (dev->buf_len) {
 930                                                         w |= *dev->buf++ << 8;
 931                                                         dev->buf_len--;
 932                                                 }
 933                                         }
 934                                 } else {
 935                                         if (stat & OMAP_I2C_STAT_XRDY)
 936                                                 dev_err(dev->dev,
 937                                                         "XRDY IRQ while no "
 938                                                         "data to send\n");
 939                                         if (stat & OMAP_I2C_STAT_XDR)
 940                                                 dev_err(dev->dev,
 941                                                         "XDR IRQ while no "
 942                                                         "data to send\n");
 943                                         break;
 944                                 }
 945
 946                                 if ((dev->errata & I2C_OMAP3_1P153) &&
 947                                     errata_omap3_1p153(dev, &stat, &err))
 948                                         goto complete;
 949
 950                                 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
 951                         }
 952                         omap_i2c_ack_stat(dev,
 953                                 stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
 954                         continue;
 955                 }
 956                 if (stat & OMAP_I2C_STAT_ROVR) {
 957                         dev_err(dev->dev, "Receive overrun\n");
 958                         dev->cmd_err |= OMAP_I2C_STAT_ROVR;
 959                 }
 960                 if (stat & OMAP_I2C_STAT_XUDF) {
 961                         dev_err(dev->dev, "Transmit underflow\n");
 962                         dev->cmd_err |= OMAP_I2C_STAT_XUDF;
 963                 }
 964         }
 965
 966         return count ? IRQ_HANDLED : IRQ_NONE;
 967 }
 968
 969 static const struct i2c_algorithm omap_i2c_algo = {
 970         .master_xfer    = omap_i2c_xfer,
 971         .functionality  = omap_i2c_func,
 972 };
 973
 974 static int __devinit
 975 omap_i2c_probe(struct platform_device *pdev)
 976 {
 977         struct omap_i2c_dev     *dev;
 978         struct i2c_adapter      *adap;
 979         struct resource         *mem, *irq, *ioarea;
 980         struct omap_i2c_bus_platform_data *pdata = pdev->dev.platform_data;
 981         irq_handler_t isr;
 982         int r;
 983         u32 speed = 0;
 984
 985         /* NOTE: driver uses the static register mapping */
 986         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 987         if (!mem) {
 988                 dev_err(&pdev->dev, "no mem resource?\n");
 989                 return -ENODEV;
 990         }
 991         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 992         if (!irq) {
 993                 dev_err(&pdev->dev, "no irq resource?\n");
 994                 return -ENODEV;
 995         }
 996
 997         ioarea = request_mem_region(mem->start, resource_size(mem),
 998                         pdev->name);
 999         if (!ioarea) {
1000                 dev_err(&pdev->dev, "I2C region already claimed\n");
1001                 return -EBUSY;
1002         }
1003
1004         dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
1005         if (!dev) {
1006                 r = -ENOMEM;
1007                 goto err_release_region;
1008         }
1009
1010         if (pdata != NULL) {
1011                 speed = pdata->clkrate;
1012                 dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
1013         } else {
1014                 speed = 100;    /* Default speed */
1015                 dev->set_mpu_wkup_lat = NULL;
1016         }
1017
1018         dev->speed = speed;
1019         dev->idle = 1;
1020         dev->dev = &pdev->dev;
1021         dev->irq = irq->start;
1022         dev->base = ioremap(mem->start, resource_size(mem));
1023         if (!dev->base) {
1024                 r = -ENOMEM;
1025                 goto err_free_mem;
1026         }
1027
1028         platform_set_drvdata(pdev, dev);
1029
1030         if (cpu_is_omap7xx())
1031                 dev->reg_shift = 1;
1032         else if (cpu_is_omap44xx())
1033                 dev->reg_shift = 0;
1034         else
1035                 dev->reg_shift = 2;
1036
1037         if (cpu_is_omap44xx())
1038                 dev->regs = (u8 *) omap4_reg_map;
1039         else
1040                 dev->regs = (u8 *) reg_map;
1041
1042         pm_runtime_enable(&pdev->dev);
1043         omap_i2c_unidle(dev);
1044
1045         dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
1046
1047         if (dev->rev <= OMAP_I2C_REV_ON_3430)
1048                 dev->errata |= I2C_OMAP3_1P153;
1049
1050         if (!(cpu_class_is_omap1() || cpu_is_omap2420())) {
1051                 u16 s;
1052
1053                 /* Set up the fifo size - Get total size */
1054                 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
1055                 dev->fifo_size = 0x8 << s;
1056
1057                 /*
1058                  * Set up notification threshold as half the total available
1059                  * size. This is to ensure that we can handle the status on int
1060                  * call back latencies.
1061                  */
1062                 if (dev->rev >= OMAP_I2C_REV_ON_4430) {
1063                         dev->fifo_size = 0;
1064                         dev->b_hw = 0; /* Disable hardware fixes */
1065                 } else {
1066                         dev->fifo_size = (dev->fifo_size / 2);
1067                         dev->b_hw = 1; /* Enable hardware fixes */
1068                 }
1069                 /* calculate wakeup latency constraint for MPU */
1070                 if (dev->set_mpu_wkup_lat != NULL)
1071                         dev->latency = (1000000 * dev->fifo_size) /
1072                                        (1000 * speed / 8);
1073         }
1074
1075         /* reset ASAP, clearing any IRQs */
1076         omap_i2c_init(dev);
1077
1078         isr = (dev->rev < OMAP_I2C_REV_2) ? omap_i2c_rev1_isr : omap_i2c_isr;
1079         r = request_irq(dev->irq, isr, 0, pdev->name, dev);
1080
1081         if (r) {
1082                 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
1083                 goto err_unuse_clocks;
1084         }
1085
1086         dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
1087                  pdev->id, dev->rev >> 4, dev->rev & 0xf, dev->speed);
1088
1089         omap_i2c_idle(dev);
1090
1091         adap = &dev->adapter;
1092         i2c_set_adapdata(adap, dev);
1093         adap->owner = THIS_MODULE;
1094         adap->class = I2C_CLASS_HWMON;
1095         strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
1096         adap->algo = &omap_i2c_algo;
1097         adap->dev.parent = &pdev->dev;
1098
1099         /* i2c device drivers may be active on return from add_adapter() */
1100         adap->nr = pdev->id;
1101         r = i2c_add_numbered_adapter(adap);
1102         if (r) {
1103                 dev_err(dev->dev, "failure adding adapter\n");
1104                 goto err_free_irq;
1105         }
1106
1107         return 0;
1108
1109 err_free_irq:
1110         free_irq(dev->irq, dev);
1111 err_unuse_clocks:
1112         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
1113         omap_i2c_idle(dev);
1114         iounmap(dev->base);
1115 err_free_mem:
1116         platform_set_drvdata(pdev, NULL);
1117         kfree(dev);
1118 err_release_region:
1119         release_mem_region(mem->start, resource_size(mem));
1120
1121         return r;
1122 }
1123
1124 static int
1125 omap_i2c_remove(struct platform_device *pdev)
1126 {
1127         struct omap_i2c_dev     *dev = platform_get_drvdata(pdev);
1128         struct resource         *mem;
1129
1130         platform_set_drvdata(pdev, NULL);
1131
1132         free_irq(dev->irq, dev);
1133         i2c_del_adapter(&dev->adapter);
1134         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
1135         iounmap(dev->base);
1136         kfree(dev);
1137         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1138         release_mem_region(mem->start, resource_size(mem));
1139         return 0;
1140 }
1141
1142 static struct platform_driver omap_i2c_driver = {
1143         .probe          = omap_i2c_probe,
1144         .remove         = omap_i2c_remove,
1145         .driver         = {
1146                 .name   = "omap_i2c",
1147                 .owner  = THIS_MODULE,
1148         },
1149 };
1150
1151 /* I2C may be needed to bring up other drivers */
1152 static int __init
1153 omap_i2c_init_driver(void)
1154 {
1155         return platform_driver_register(&omap_i2c_driver);
1156 }
1157 subsys_initcall(omap_i2c_init_driver);
1158
1159 static void __exit omap_i2c_exit_driver(void)
1160 {
1161         platform_driver_unregister(&omap_i2c_driver);
1162 }
1163 module_exit(omap_i2c_exit_driver);
1164
1165 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
1166 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
1167 MODULE_LICENSE("GPL");
1168 MODULE_ALIAS("platform:omap_i2c");