drivers/i2c/busses/i2c-i801.c

   1 /*
   2     Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
   3     Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
   4     <mdsxyz123@yahoo.com>
   5     Copyright (C) 2007, 2008   Jean Delvare <khali@linux-fr.org>
   6
   7     This program is free software; you can redistribute it and/or modify
   8     it under the terms of the GNU General Public License as published by
   9     the Free Software Foundation; either version 2 of the License, or
  10     (at your option) any later version.
  11
  12     This program is distributed in the hope that it will be useful,
  13     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15     GNU General Public License for more details.
  16
  17     You should have received a copy of the GNU General Public License
  18     along with this program; if not, write to the Free Software
  19     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20 */
  21
  22 /*
  23   Supports the following Intel I/O Controller Hubs (ICH):
  24
  25                                   I/O                     Block   I2C
  26                                   region  SMBus   Block   proc.   block
  27   Chip name             PCI ID    size    PEC     buffer  call    read
  28   ----------------------------------------------------------------------
  29   82801AA  (ICH)        0x2413     16      no      no      no      no
  30   82801AB  (ICH0)       0x2423     16      no      no      no      no
  31   82801BA  (ICH2)       0x2443     16      no      no      no      no
  32   82801CA  (ICH3)       0x2483     32     soft     no      no      no
  33   82801DB  (ICH4)       0x24c3     32     hard     yes     no      no
  34   82801E   (ICH5)       0x24d3     32     hard     yes     yes     yes
  35   6300ESB               0x25a4     32     hard     yes     yes     yes
  36   82801F   (ICH6)       0x266a     32     hard     yes     yes     yes
  37   6310ESB/6320ESB       0x269b     32     hard     yes     yes     yes
  38   82801G   (ICH7)       0x27da     32     hard     yes     yes     yes
  39   82801H   (ICH8)       0x283e     32     hard     yes     yes     yes
  40   82801I   (ICH9)       0x2930     32     hard     yes     yes     yes
  41   EP80579 (Tolapai)     0x5032     32     hard     yes     yes     yes
  42   ICH10                 0x3a30     32     hard     yes     yes     yes
  43   ICH10                 0x3a60     32     hard     yes     yes     yes
  44   5/3400 Series (PCH)   0x3b30     32     hard     yes     yes     yes
  45   Cougar Point (PCH)    0x1c22     32     hard     yes     yes     yes
  46
  47   Features supported by this driver:
  48   Software PEC                     no
  49   Hardware PEC                     yes
  50   Block buffer                     yes
  51   Block process call transaction   no
  52   I2C block read transaction       yes  (doesn't use the block buffer)
  53
  54   See the file Documentation/i2c/busses/i2c-i801 for details.
  55 */
  56
  57 /* Note: we assume there can only be one I801, with one SMBus interface */
  58
  59 #include <linux/module.h>
  60 #include <linux/pci.h>
  61 #include <linux/kernel.h>
  62 #include <linux/stddef.h>
  63 #include <linux/delay.h>
  64 #include <linux/ioport.h>
  65 #include <linux/init.h>
  66 #include <linux/i2c.h>
  67 #include <linux/acpi.h>
  68 #include <linux/io.h>
  69 #include <linux/dmi.h>
  70
  71 /* I801 SMBus address offsets */
  72 #define SMBHSTSTS       (0 + i801_smba)
  73 #define SMBHSTCNT       (2 + i801_smba)
  74 #define SMBHSTCMD       (3 + i801_smba)
  75 #define SMBHSTADD       (4 + i801_smba)
  76 #define SMBHSTDAT0      (5 + i801_smba)
  77 #define SMBHSTDAT1      (6 + i801_smba)
  78 #define SMBBLKDAT       (7 + i801_smba)
  79 #define SMBPEC          (8 + i801_smba)         /* ICH3 and later */
  80 #define SMBAUXSTS       (12 + i801_smba)        /* ICH4 and later */
  81 #define SMBAUXCTL       (13 + i801_smba)        /* ICH4 and later */
  82
  83 /* PCI Address Constants */
  84 #define SMBBAR          4
  85 #define SMBHSTCFG       0x040
  86
  87 /* Host configuration bits for SMBHSTCFG */
  88 #define SMBHSTCFG_HST_EN        1
  89 #define SMBHSTCFG_SMB_SMI_EN    2
  90 #define SMBHSTCFG_I2C_EN        4
  91
  92 /* Auxillary control register bits, ICH4+ only */
  93 #define SMBAUXCTL_CRC           1
  94 #define SMBAUXCTL_E32B          2
  95
  96 /* kill bit for SMBHSTCNT */
  97 #define SMBHSTCNT_KILL          2
  98
  99 /* Other settings */
 100 #define MAX_TIMEOUT             100
 101 #define ENABLE_INT9             0       /* set to 0x01 to enable - untested */
 102
 103 /* I801 command constants */
 104 #define I801_QUICK              0x00
 105 #define I801_BYTE               0x04
 106 #define I801_BYTE_DATA          0x08
 107 #define I801_WORD_DATA          0x0C
 108 #define I801_PROC_CALL          0x10    /* unimplemented */
 109 #define I801_BLOCK_DATA         0x14
 110 #define I801_I2C_BLOCK_DATA     0x18    /* ICH5 and later */
 111 #define I801_BLOCK_LAST         0x34
 112 #define I801_I2C_BLOCK_LAST     0x38    /* ICH5 and later */
 113 #define I801_START              0x40
 114 #define I801_PEC_EN             0x80    /* ICH3 and later */
 115
 116 /* I801 Hosts Status register bits */
 117 #define SMBHSTSTS_BYTE_DONE     0x80
 118 #define SMBHSTSTS_INUSE_STS     0x40
 119 #define SMBHSTSTS_SMBALERT_STS  0x20
 120 #define SMBHSTSTS_FAILED        0x10
 121 #define SMBHSTSTS_BUS_ERR       0x08
 122 #define SMBHSTSTS_DEV_ERR       0x04
 123 #define SMBHSTSTS_INTR          0x02
 124 #define SMBHSTSTS_HOST_BUSY     0x01
 125
 126 #define STATUS_FLAGS            (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_FAILED | \
 127                                  SMBHSTSTS_BUS_ERR | SMBHSTSTS_DEV_ERR | \
 128                                  SMBHSTSTS_INTR)
 129
 130 static unsigned long i801_smba;
 131 static unsigned char i801_original_hstcfg;
 132 static struct pci_driver i801_driver;
 133 static struct pci_dev *I801_dev;
 134
 135 #define FEATURE_SMBUS_PEC       (1 << 0)
 136 #define FEATURE_BLOCK_BUFFER    (1 << 1)
 137 #define FEATURE_BLOCK_PROC      (1 << 2)
 138 #define FEATURE_I2C_BLOCK_READ  (1 << 3)
 139 static unsigned int i801_features;
 140
 141 static const char *i801_feature_names[] = {
 142         "SMBus PEC",
 143         "Block buffer",
 144         "Block process call",
 145         "I2C block read",
 146 };
 147
 148 static unsigned int disable_features;
 149 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
 150 MODULE_PARM_DESC(disable_features, "Disable selected driver features");
 151
 152 /* Make sure the SMBus host is ready to start transmitting.
 153    Return 0 if it is, -EBUSY if it is not. */
 154 static int i801_check_pre(void)
 155 {
 156         int status;
 157
 158         status = inb_p(SMBHSTSTS);
 159         if (status & SMBHSTSTS_HOST_BUSY) {
 160                 dev_err(&I801_dev->dev, "SMBus is busy, can't use it!\n");
 161                 return -EBUSY;
 162         }
 163
 164         status &= STATUS_FLAGS;
 165         if (status) {
 166                 dev_dbg(&I801_dev->dev, "Clearing status flags (%02x)\n",
 167                         status);
 168                 outb_p(status, SMBHSTSTS);
 169                 status = inb_p(SMBHSTSTS) & STATUS_FLAGS;
 170                 if (status) {
 171                         dev_err(&I801_dev->dev,
 172                                 "Failed clearing status flags (%02x)\n",
 173                                 status);
 174                         return -EBUSY;
 175                 }
 176         }
 177
 178         return 0;
 179 }
 180
 181 /* Convert the status register to an error code, and clear it. */
 182 static int i801_check_post(int status, int timeout)
 183 {
 184         int result = 0;
 185
 186         /* If the SMBus is still busy, we give up */
 187         if (timeout) {
 188                 dev_err(&I801_dev->dev, "Transaction timeout\n");
 189                 /* try to stop the current command */
 190                 dev_dbg(&I801_dev->dev, "Terminating the current operation\n");
 191                 outb_p(inb_p(SMBHSTCNT) | SMBHSTCNT_KILL, SMBHSTCNT);
 192                 msleep(1);
 193                 outb_p(inb_p(SMBHSTCNT) & (~SMBHSTCNT_KILL), SMBHSTCNT);
 194
 195                 /* Check if it worked */
 196                 status = inb_p(SMBHSTSTS);
 197                 if ((status & SMBHSTSTS_HOST_BUSY) ||
 198                     !(status & SMBHSTSTS_FAILED))
 199                         dev_err(&I801_dev->dev,
 200                                 "Failed terminating the transaction\n");
 201                 outb_p(STATUS_FLAGS, SMBHSTSTS);
 202                 return -ETIMEDOUT;
 203         }
 204
 205         if (status & SMBHSTSTS_FAILED) {
 206                 result = -EIO;
 207                 dev_err(&I801_dev->dev, "Transaction failed\n");
 208         }
 209         if (status & SMBHSTSTS_DEV_ERR) {
 210                 result = -ENXIO;
 211                 dev_dbg(&I801_dev->dev, "No response\n");
 212         }
 213         if (status & SMBHSTSTS_BUS_ERR) {
 214                 result = -EAGAIN;
 215                 dev_dbg(&I801_dev->dev, "Lost arbitration\n");
 216         }
 217
 218         if (result) {
 219                 /* Clear error flags */
 220                 outb_p(status & STATUS_FLAGS, SMBHSTSTS);
 221                 status = inb_p(SMBHSTSTS) & STATUS_FLAGS;
 222                 if (status) {
 223                         dev_warn(&I801_dev->dev, "Failed clearing status "
 224                                  "flags at end of transaction (%02x)\n",
 225                                  status);
 226                 }
 227         }
 228
 229         return result;
 230 }
 231
 232 static int i801_transaction(int xact)
 233 {
 234         int status;
 235         int result;
 236         int timeout = 0;
 237
 238         result = i801_check_pre();
 239         if (result < 0)
 240                 return result;
 241
 242         /* the current contents of SMBHSTCNT can be overwritten, since PEC,
 243          * INTREN, SMBSCMD are passed in xact */
 244         outb_p(xact | I801_START, SMBHSTCNT);
 245
 246         /* We will always wait for a fraction of a second! */
 247         do {
 248                 msleep(1);
 249                 status = inb_p(SMBHSTSTS);
 250         } while ((status & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_TIMEOUT));
 251
 252         result = i801_check_post(status, timeout > MAX_TIMEOUT);
 253         if (result < 0)
 254                 return result;
 255
 256         outb_p(SMBHSTSTS_INTR, SMBHSTSTS);
 257         return 0;
 258 }
 259
 260 /* wait for INTR bit as advised by Intel */
 261 static void i801_wait_hwpec(void)
 262 {
 263         int timeout = 0;
 264         int status;
 265
 266         do {
 267                 msleep(1);
 268                 status = inb_p(SMBHSTSTS);
 269         } while ((!(status & SMBHSTSTS_INTR))
 270                  && (timeout++ < MAX_TIMEOUT));
 271
 272         if (timeout > MAX_TIMEOUT)
 273                 dev_dbg(&I801_dev->dev, "PEC Timeout!\n");
 274
 275         outb_p(status, SMBHSTSTS);
 276 }
 277
 278 static int i801_block_transaction_by_block(union i2c_smbus_data *data,
 279                                            char read_write, int hwpec)
 280 {
 281         int i, len;
 282         int status;
 283
 284         inb_p(SMBHSTCNT); /* reset the data buffer index */
 285
 286         /* Use 32-byte buffer to process this transaction */
 287         if (read_write == I2C_SMBUS_WRITE) {
 288                 len = data->block[0];
 289                 outb_p(len, SMBHSTDAT0);
 290                 for (i = 0; i < len; i++)
 291                         outb_p(data->block[i+1], SMBBLKDAT);
 292         }
 293
 294         status = i801_transaction(I801_BLOCK_DATA | ENABLE_INT9 |
 295                                   I801_PEC_EN * hwpec);
 296         if (status)
 297                 return status;
 298
 299         if (read_write == I2C_SMBUS_READ) {
 300                 len = inb_p(SMBHSTDAT0);
 301                 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
 302                         return -EPROTO;
 303
 304                 data->block[0] = len;
 305                 for (i = 0; i < len; i++)
 306                         data->block[i + 1] = inb_p(SMBBLKDAT);
 307         }
 308         return 0;
 309 }
 310
 311 static int i801_block_transaction_byte_by_byte(union i2c_smbus_data *data,
 312                                                char read_write, int command,
 313                                                int hwpec)
 314 {
 315         int i, len;
 316         int smbcmd;
 317         int status;
 318         int result;
 319         int timeout;
 320
 321         result = i801_check_pre();
 322         if (result < 0)
 323                 return result;
 324
 325         len = data->block[0];
 326
 327         if (read_write == I2C_SMBUS_WRITE) {
 328                 outb_p(len, SMBHSTDAT0);
 329                 outb_p(data->block[1], SMBBLKDAT);
 330         }
 331
 332         for (i = 1; i <= len; i++) {
 333                 if (i == len && read_write == I2C_SMBUS_READ) {
 334                         if (command == I2C_SMBUS_I2C_BLOCK_DATA)
 335                                 smbcmd = I801_I2C_BLOCK_LAST;
 336                         else
 337                                 smbcmd = I801_BLOCK_LAST;
 338                 } else {
 339                         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 340                          && read_write == I2C_SMBUS_READ)
 341                                 smbcmd = I801_I2C_BLOCK_DATA;
 342                         else
 343                                 smbcmd = I801_BLOCK_DATA;
 344                 }
 345                 outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT);
 346
 347                 if (i == 1)
 348                         outb_p(inb(SMBHSTCNT) | I801_START, SMBHSTCNT);
 349
 350                 /* We will always wait for a fraction of a second! */
 351                 timeout = 0;
 352                 do {
 353                         msleep(1);
 354                         status = inb_p(SMBHSTSTS);
 355                 } while ((!(status & SMBHSTSTS_BYTE_DONE))
 356                          && (timeout++ < MAX_TIMEOUT));
 357
 358                 result = i801_check_post(status, timeout > MAX_TIMEOUT);
 359                 if (result < 0)
 360                         return result;
 361
 362                 if (i == 1 && read_write == I2C_SMBUS_READ
 363                  && command != I2C_SMBUS_I2C_BLOCK_DATA) {
 364                         len = inb_p(SMBHSTDAT0);
 365                         if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
 366                                 dev_err(&I801_dev->dev,
 367                                         "Illegal SMBus block read size %d\n",
 368                                         len);
 369                                 /* Recover */
 370                                 while (inb_p(SMBHSTSTS) & SMBHSTSTS_HOST_BUSY)
 371                                         outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS);
 372                                 outb_p(SMBHSTSTS_INTR, SMBHSTSTS);
 373                                 return -EPROTO;
 374                         }
 375                         data->block[0] = len;
 376                 }
 377
 378                 /* Retrieve/store value in SMBBLKDAT */
 379                 if (read_write == I2C_SMBUS_READ)
 380                         data->block[i] = inb_p(SMBBLKDAT);
 381                 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
 382                         outb_p(data->block[i+1], SMBBLKDAT);
 383
 384                 /* signals SMBBLKDAT ready */
 385                 outb_p(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR, SMBHSTSTS);
 386         }
 387
 388         return 0;
 389 }
 390
 391 static int i801_set_block_buffer_mode(void)
 392 {
 393         outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_E32B, SMBAUXCTL);
 394         if ((inb_p(SMBAUXCTL) & SMBAUXCTL_E32B) == 0)
 395                 return -EIO;
 396         return 0;
 397 }
 398
 399 /* Block transaction function */
 400 static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
 401                                   int command, int hwpec)
 402 {
 403         int result = 0;
 404         unsigned char hostc;
 405
 406         if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
 407                 if (read_write == I2C_SMBUS_WRITE) {
 408                         /* set I2C_EN bit in configuration register */
 409                         pci_read_config_byte(I801_dev, SMBHSTCFG, &hostc);
 410                         pci_write_config_byte(I801_dev, SMBHSTCFG,
 411                                               hostc | SMBHSTCFG_I2C_EN);
 412                 } else if (!(i801_features & FEATURE_I2C_BLOCK_READ)) {
 413                         dev_err(&I801_dev->dev,
 414                                 "I2C block read is unsupported!\n");
 415                         return -EOPNOTSUPP;
 416                 }
 417         }
 418
 419         if (read_write == I2C_SMBUS_WRITE
 420          || command == I2C_SMBUS_I2C_BLOCK_DATA) {
 421                 if (data->block[0] < 1)
 422                         data->block[0] = 1;
 423                 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
 424                         data->block[0] = I2C_SMBUS_BLOCK_MAX;
 425         } else {
 426                 data->block[0] = 32;    /* max for SMBus block reads */
 427         }
 428
 429         /* Experience has shown that the block buffer can only be used for
 430            SMBus (not I2C) block transactions, even though the datasheet
 431            doesn't mention this limitation. */
 432         if ((i801_features & FEATURE_BLOCK_BUFFER)
 433          && command != I2C_SMBUS_I2C_BLOCK_DATA
 434          && i801_set_block_buffer_mode() == 0)
 435                 result = i801_block_transaction_by_block(data, read_write,
 436                                                          hwpec);
 437         else
 438                 result = i801_block_transaction_byte_by_byte(data, read_write,
 439                                                              command, hwpec);
 440
 441         if (result == 0 && hwpec)
 442                 i801_wait_hwpec();
 443
 444         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 445          && read_write == I2C_SMBUS_WRITE) {
 446                 /* restore saved configuration register value */
 447                 pci_write_config_byte(I801_dev, SMBHSTCFG, hostc);
 448         }
 449         return result;
 450 }
 451
 452 /* Return negative errno on error. */
 453 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
 454                        unsigned short flags, char read_write, u8 command,
 455                        int size, union i2c_smbus_data *data)
 456 {
 457         int hwpec;
 458         int block = 0;
 459         int ret, xact = 0;
 460
 461         hwpec = (i801_features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
 462                 && size != I2C_SMBUS_QUICK
 463                 && size != I2C_SMBUS_I2C_BLOCK_DATA;
 464
 465         switch (size) {
 466         case I2C_SMBUS_QUICK:
 467                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 468                        SMBHSTADD);
 469                 xact = I801_QUICK;
 470                 break;
 471         case I2C_SMBUS_BYTE:
 472                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 473                        SMBHSTADD);
 474                 if (read_write == I2C_SMBUS_WRITE)
 475                         outb_p(command, SMBHSTCMD);
 476                 xact = I801_BYTE;
 477                 break;
 478         case I2C_SMBUS_BYTE_DATA:
 479                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 480                        SMBHSTADD);
 481                 outb_p(command, SMBHSTCMD);
 482                 if (read_write == I2C_SMBUS_WRITE)
 483                         outb_p(data->byte, SMBHSTDAT0);
 484                 xact = I801_BYTE_DATA;
 485                 break;
 486         case I2C_SMBUS_WORD_DATA:
 487                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 488                        SMBHSTADD);
 489                 outb_p(command, SMBHSTCMD);
 490                 if (read_write == I2C_SMBUS_WRITE) {
 491                         outb_p(data->word & 0xff, SMBHSTDAT0);
 492                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
 493                 }
 494                 xact = I801_WORD_DATA;
 495                 break;
 496         case I2C_SMBUS_BLOCK_DATA:
 497                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 498                        SMBHSTADD);
 499                 outb_p(command, SMBHSTCMD);
 500                 block = 1;
 501                 break;
 502         case I2C_SMBUS_I2C_BLOCK_DATA:
 503                 /* NB: page 240 of ICH5 datasheet shows that the R/#W
 504                  * bit should be cleared here, even when reading */
 505                 outb_p((addr & 0x7f) << 1, SMBHSTADD);
 506                 if (read_write == I2C_SMBUS_READ) {
 507                         /* NB: page 240 of ICH5 datasheet also shows
 508                          * that DATA1 is the cmd field when reading */
 509                         outb_p(command, SMBHSTDAT1);
 510                 } else
 511                         outb_p(command, SMBHSTCMD);
 512                 block = 1;
 513                 break;
 514         default:
 515                 dev_err(&I801_dev->dev, "Unsupported transaction %d\n", size);
 516                 return -EOPNOTSUPP;
 517         }
 518
 519         if (hwpec)      /* enable/disable hardware PEC */
 520                 outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_CRC, SMBAUXCTL);
 521         else
 522                 outb_p(inb_p(SMBAUXCTL) & (~SMBAUXCTL_CRC), SMBAUXCTL);
 523
 524         if (block)
 525                 ret = i801_block_transaction(data, read_write, size, hwpec);
 526         else
 527                 ret = i801_transaction(xact | ENABLE_INT9);
 528
 529         /* Some BIOSes don't like it when PEC is enabled at reboot or resume
 530            time, so we forcibly disable it after every transaction. Turn off
 531            E32B for the same reason. */
 532         if (hwpec || block)
 533                 outb_p(inb_p(SMBAUXCTL) & ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B),
 534                        SMBAUXCTL);
 535
 536         if (block)
 537                 return ret;
 538         if (ret)
 539                 return ret;
 540         if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
 541                 return 0;
 542
 543         switch (xact & 0x7f) {
 544         case I801_BYTE: /* Result put in SMBHSTDAT0 */
 545         case I801_BYTE_DATA:
 546                 data->byte = inb_p(SMBHSTDAT0);
 547                 break;
 548         case I801_WORD_DATA:
 549                 data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
 550                 break;
 551         }
 552         return 0;
 553 }
 554
 555
 556 static u32 i801_func(struct i2c_adapter *adapter)
 557 {
 558         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 559                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 560                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
 561                ((i801_features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
 562                ((i801_features & FEATURE_I2C_BLOCK_READ) ?
 563                 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
 564 }
 565
 566 static const struct i2c_algorithm smbus_algorithm = {
 567         .smbus_xfer     = i801_access,
 568         .functionality  = i801_func,
 569 };
 570
 571 static struct i2c_adapter i801_adapter = {
 572         .owner          = THIS_MODULE,
 573         .class          = I2C_CLASS_HWMON | I2C_CLASS_SPD,
 574         .algo           = &smbus_algorithm,
 575 };
 576
 577 static const struct pci_device_id i801_ids[] = {
 578         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
 579         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
 580         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
 581         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
 582         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
 583         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
 584         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
 585         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
 586         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
 587         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
 588         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
 589         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
 590         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
 591         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
 592         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
 593         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
 594         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
 595         { 0, }
 596 };
 597
 598 MODULE_DEVICE_TABLE(pci, i801_ids);
 599
 600 #if defined CONFIG_INPUT_APANEL || defined CONFIG_INPUT_APANEL_MODULE
 601 static unsigned char apanel_addr;
 602
 603 /* Scan the system ROM for the signature "FJKEYINF" */
 604 static __init const void __iomem *bios_signature(const void __iomem *bios)
 605 {
 606         ssize_t offset;
 607         const unsigned char signature[] = "FJKEYINF";
 608
 609         for (offset = 0; offset < 0x10000; offset += 0x10) {
 610                 if (check_signature(bios + offset, signature,
 611                                     sizeof(signature)-1))
 612                         return bios + offset;
 613         }
 614         return NULL;
 615 }
 616
 617 static void __init input_apanel_init(void)
 618 {
 619         void __iomem *bios;
 620         const void __iomem *p;
 621
 622         bios = ioremap(0xF0000, 0x10000); /* Can't fail */
 623         p = bios_signature(bios);
 624         if (p) {
 625                 /* just use the first address */
 626                 apanel_addr = readb(p + 8 + 3) >> 1;
 627         }
 628         iounmap(bios);
 629 }
 630 #else
 631 static void __init input_apanel_init(void) {}
 632 #endif
 633
 634 #if defined CONFIG_SENSORS_FSCHMD || defined CONFIG_SENSORS_FSCHMD_MODULE
 635 struct dmi_onboard_device_info {
 636         const char *name;
 637         u8 type;
 638         unsigned short i2c_addr;
 639         const char *i2c_type;
 640 };
 641
 642 static struct dmi_onboard_device_info __devinitdata dmi_devices[] = {
 643         { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
 644         { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
 645         { "Hades",  DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
 646 };
 647
 648 static void __devinit dmi_check_onboard_device(u8 type, const char *name,
 649                                                struct i2c_adapter *adap)
 650 {
 651         int i;
 652         struct i2c_board_info info;
 653
 654         for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
 655                 /* & ~0x80, ignore enabled/disabled bit */
 656                 if ((type & ~0x80) != dmi_devices[i].type)
 657                         continue;
 658                 if (strcasecmp(name, dmi_devices[i].name))
 659                         continue;
 660
 661                 memset(&info, 0, sizeof(struct i2c_board_info));
 662                 info.addr = dmi_devices[i].i2c_addr;
 663                 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
 664                 i2c_new_device(adap, &info);
 665                 break;
 666         }
 667 }
 668
 669 /* We use our own function to check for onboard devices instead of
 670    dmi_find_device() as some buggy BIOS's have the devices we are interested
 671    in marked as disabled */
 672 static void __devinit dmi_check_onboard_devices(const struct dmi_header *dm,
 673                                                 void *adap)
 674 {
 675         int i, count;
 676
 677         if (dm->type != 10)
 678                 return;
 679
 680         count = (dm->length - sizeof(struct dmi_header)) / 2;
 681         for (i = 0; i < count; i++) {
 682                 const u8 *d = (char *)(dm + 1) + (i * 2);
 683                 const char *name = ((char *) dm) + dm->length;
 684                 u8 type = d[0];
 685                 u8 s = d[1];
 686
 687                 if (!s)
 688                         continue;
 689                 s--;
 690                 while (s > 0 && name[0]) {
 691                         name += strlen(name) + 1;
 692                         s--;
 693                 }
 694                 if (name[0] == 0) /* Bogus string reference */
 695                         continue;
 696
 697                 dmi_check_onboard_device(type, name, adap);
 698         }
 699 }
 700 #endif
 701
 702 static int __devinit i801_probe(struct pci_dev *dev,
 703                                 const struct pci_device_id *id)
 704 {
 705         unsigned char temp;
 706         int err, i;
 707
 708         I801_dev = dev;
 709         i801_features = 0;
 710         switch (dev->device) {
 711         default:
 712                 i801_features |= FEATURE_I2C_BLOCK_READ;
 713                 /* fall through */
 714         case PCI_DEVICE_ID_INTEL_82801DB_3:
 715                 i801_features |= FEATURE_SMBUS_PEC;
 716                 i801_features |= FEATURE_BLOCK_BUFFER;
 717                 /* fall through */
 718         case PCI_DEVICE_ID_INTEL_82801CA_3:
 719         case PCI_DEVICE_ID_INTEL_82801BA_2:
 720         case PCI_DEVICE_ID_INTEL_82801AB_3:
 721         case PCI_DEVICE_ID_INTEL_82801AA_3:
 722                 break;
 723         }
 724
 725         /* Disable features on user request */
 726         for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
 727                 if (i801_features & disable_features & (1 << i))
 728                         dev_notice(&dev->dev, "%s disabled by user\n",
 729                                    i801_feature_names[i]);
 730         }
 731         i801_features &= ~disable_features;
 732
 733         err = pci_enable_device(dev);
 734         if (err) {
 735                 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
 736                         err);
 737                 goto exit;
 738         }
 739
 740         /* Determine the address of the SMBus area */
 741         i801_smba = pci_resource_start(dev, SMBBAR);
 742         if (!i801_smba) {
 743                 dev_err(&dev->dev, "SMBus base address uninitialized, "
 744                         "upgrade BIOS\n");
 745                 err = -ENODEV;
 746                 goto exit;
 747         }
 748
 749         err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
 750         if (err) {
 751                 err = -ENODEV;
 752                 goto exit;
 753         }
 754
 755         err = pci_request_region(dev, SMBBAR, i801_driver.name);
 756         if (err) {
 757                 dev_err(&dev->dev, "Failed to request SMBus region "
 758                         "0x%lx-0x%Lx\n", i801_smba,
 759                         (unsigned long long)pci_resource_end(dev, SMBBAR));
 760                 goto exit;
 761         }
 762
 763         pci_read_config_byte(I801_dev, SMBHSTCFG, &temp);
 764         i801_original_hstcfg = temp;
 765         temp &= ~SMBHSTCFG_I2C_EN;      /* SMBus timing */
 766         if (!(temp & SMBHSTCFG_HST_EN)) {
 767                 dev_info(&dev->dev, "Enabling SMBus device\n");
 768                 temp |= SMBHSTCFG_HST_EN;
 769         }
 770         pci_write_config_byte(I801_dev, SMBHSTCFG, temp);
 771
 772         if (temp & SMBHSTCFG_SMB_SMI_EN)
 773                 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
 774         else
 775                 dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n");
 776
 777         /* Clear special mode bits */
 778         if (i801_features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
 779                 outb_p(inb_p(SMBAUXCTL) & ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B),
 780                        SMBAUXCTL);
 781
 782         /* set up the sysfs linkage to our parent device */
 783         i801_adapter.dev.parent = &dev->dev;
 784
 785         /* Retry up to 3 times on lost arbitration */
 786         i801_adapter.retries = 3;
 787
 788         snprintf(i801_adapter.name, sizeof(i801_adapter.name),
 789                 "SMBus I801 adapter at %04lx", i801_smba);
 790         err = i2c_add_adapter(&i801_adapter);
 791         if (err) {
 792                 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
 793                 goto exit_release;
 794         }
 795
 796         /* Register optional slaves */
 797 #if defined CONFIG_INPUT_APANEL || defined CONFIG_INPUT_APANEL_MODULE
 798         if (apanel_addr) {
 799                 struct i2c_board_info info;
 800
 801                 memset(&info, 0, sizeof(struct i2c_board_info));
 802                 info.addr = apanel_addr;
 803                 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
 804                 i2c_new_device(&i801_adapter, &info);
 805         }
 806 #endif
 807 #if defined CONFIG_SENSORS_FSCHMD || defined CONFIG_SENSORS_FSCHMD_MODULE
 808         if (dmi_name_in_vendors("FUJITSU"))
 809                 dmi_walk(dmi_check_onboard_devices, &i801_adapter);
 810 #endif
 811
 812         return 0;
 813
 814 exit_release:
 815         pci_release_region(dev, SMBBAR);
 816 exit:
 817         return err;
 818 }
 819
 820 static void __devexit i801_remove(struct pci_dev *dev)
 821 {
 822         i2c_del_adapter(&i801_adapter);
 823         pci_write_config_byte(I801_dev, SMBHSTCFG, i801_original_hstcfg);
 824         pci_release_region(dev, SMBBAR);
 825         /*
 826          * do not call pci_disable_device(dev) since it can cause hard hangs on
 827          * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
 828          */
 829 }
 830
 831 #ifdef CONFIG_PM
 832 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
 833 {
 834         pci_save_state(dev);
 835         pci_write_config_byte(dev, SMBHSTCFG, i801_original_hstcfg);
 836         pci_set_power_state(dev, pci_choose_state(dev, mesg));
 837         return 0;
 838 }
 839
 840 static int i801_resume(struct pci_dev *dev)
 841 {
 842         pci_set_power_state(dev, PCI_D0);
 843         pci_restore_state(dev);
 844         return pci_enable_device(dev);
 845 }
 846 #else
 847 #define i801_suspend NULL
 848 #define i801_resume NULL
 849 #endif
 850
 851 static struct pci_driver i801_driver = {
 852         .name           = "i801_smbus",
 853         .id_table       = i801_ids,
 854         .probe          = i801_probe,
 855         .remove         = __devexit_p(i801_remove),
 856         .suspend        = i801_suspend,
 857         .resume         = i801_resume,
 858 };
 859
 860 static int __init i2c_i801_init(void)
 861 {
 862         input_apanel_init();
 863         return pci_register_driver(&i801_driver);
 864 }
 865
 866 static void __exit i2c_i801_exit(void)
 867 {
 868         pci_unregister_driver(&i801_driver);
 869 }
 870
 871 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, "
 872               "Jean Delvare <khali@linux-fr.org>");
 873 MODULE_DESCRIPTION("I801 SMBus driver");
 874 MODULE_LICENSE("GPL");
 875
 876 module_init(i2c_i801_init);
 877 module_exit(i2c_i801_exit);