drivers/i2c/busses/i2c-i801.c

   1 /*
   2     Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
   3     Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
   4     <mdsxyz123@yahoo.com>
   5     Copyright (C) 2007, 2008   Jean Delvare <khali@linux-fr.org>
   6     Copyright (C) 2010         Intel Corporation,
   7                                David Woodhouse <dwmw2@infradead.org>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18
  19     You should have received a copy of the GNU General Public License
  20     along with this program; if not, write to the Free Software
  21     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22 */
  23
  24 /*
  25  * Supports the following Intel I/O Controller Hubs (ICH):
  26  *
  27  *                                      I/O                     Block   I2C
  28  *                                      region  SMBus   Block   proc.   block
  29  * Chip name                    PCI ID  size    PEC     buffer  call    read
  30  * ---------------------------------------------------------------------------
  31  * 82801AA (ICH)                0x2413  16      no      no      no      no
  32  * 82801AB (ICH0)               0x2423  16      no      no      no      no
  33  * 82801BA (ICH2)               0x2443  16      no      no      no      no
  34  * 82801CA (ICH3)               0x2483  32      soft    no      no      no
  35  * 82801DB (ICH4)               0x24c3  32      hard    yes     no      no
  36  * 82801E (ICH5)                0x24d3  32      hard    yes     yes     yes
  37  * 6300ESB                      0x25a4  32      hard    yes     yes     yes
  38  * 82801F (ICH6)                0x266a  32      hard    yes     yes     yes
  39  * 6310ESB/6320ESB              0x269b  32      hard    yes     yes     yes
  40  * 82801G (ICH7)                0x27da  32      hard    yes     yes     yes
  41  * 82801H (ICH8)                0x283e  32      hard    yes     yes     yes
  42  * 82801I (ICH9)                0x2930  32      hard    yes     yes     yes
  43  * EP80579 (Tolapai)            0x5032  32      hard    yes     yes     yes
  44  * ICH10                        0x3a30  32      hard    yes     yes     yes
  45  * ICH10                        0x3a60  32      hard    yes     yes     yes
  46  * 5/3400 Series (PCH)          0x3b30  32      hard    yes     yes     yes
  47  * 6 Series (PCH)               0x1c22  32      hard    yes     yes     yes
  48  * Patsburg (PCH)               0x1d22  32      hard    yes     yes     yes
  49  * Patsburg (PCH) IDF           0x1d70  32      hard    yes     yes     yes
  50  * Patsburg (PCH) IDF           0x1d71  32      hard    yes     yes     yes
  51  * Patsburg (PCH) IDF           0x1d72  32      hard    yes     yes     yes
  52  * DH89xxCC (PCH)               0x2330  32      hard    yes     yes     yes
  53  * Panther Point (PCH)          0x1e22  32      hard    yes     yes     yes
  54  * Lynx Point (PCH)             0x8c22  32      hard    yes     yes     yes
  55  * Lynx Point-LP (PCH)          0x9c22  32      hard    yes     yes     yes
  56  * Avoton (SOC)                 0x1f3c  32      hard    yes     yes     yes
  57  * Wellsburg (PCH)              0x8d22  32      hard    yes     yes     yes
  58  * Wellsburg (PCH) MS           0x8d7d  32      hard    yes     yes     yes
  59  * Wellsburg (PCH) MS           0x8d7e  32      hard    yes     yes     yes
  60  * Wellsburg (PCH) MS           0x8d7f  32      hard    yes     yes     yes
  61  * Coleto Creek (PCH)           0x23b0  32      hard    yes     yes     yes
  62  * Wildcat Point (PCH)          0x8ca2  32      hard    yes     yes     yes
  63  * Wildcat Point-LP (PCH)       0x9ca2  32      hard    yes     yes     yes
  64  * BayTrail (SOC)               0x0f12  32      hard    yes     yes     yes
  65  * Sunrise Point-H (PCH)        0xa123  32      hard    yes     yes     yes
  66  *
  67  * Features supported by this driver:
  68  * Software PEC                         no
  69  * Hardware PEC                         yes
  70  * Block buffer                         yes
  71  * Block process call transaction       no
  72  * I2C block read transaction           yes (doesn't use the block buffer)
  73  * Slave mode                           no
  74  *
  75  * See the file Documentation/i2c/busses/i2c-i801 for details.
  76  */
  77
  78 #include <linux/module.h>
  79 #include <linux/pci.h>
  80 #include <linux/kernel.h>
  81 #include <linux/stddef.h>
  82 #include <linux/delay.h>
  83 #include <linux/ioport.h>
  84 #include <linux/init.h>
  85 #include <linux/i2c.h>
  86 #include <linux/acpi.h>
  87 #include <linux/io.h>
  88 #include <linux/dmi.h>
  89 #include <linux/slab.h>
  90
  91 /* I801 SMBus address offsets */
  92 #define SMBHSTSTS(p)    (0 + (p)->smba)
  93 #define SMBHSTCNT(p)    (2 + (p)->smba)
  94 #define SMBHSTCMD(p)    (3 + (p)->smba)
  95 #define SMBHSTADD(p)    (4 + (p)->smba)
  96 #define SMBHSTDAT0(p)   (5 + (p)->smba)
  97 #define SMBHSTDAT1(p)   (6 + (p)->smba)
  98 #define SMBBLKDAT(p)    (7 + (p)->smba)
  99 #define SMBPEC(p)       (8 + (p)->smba)         /* ICH3 and later */
 100 #define SMBAUXSTS(p)    (12 + (p)->smba)        /* ICH4 and later */
 101 #define SMBAUXCTL(p)    (13 + (p)->smba)        /* ICH4 and later */
 102
 103 /* PCI Address Constants */
 104 #define SMBBAR          4
 105 #define SMBHSTCFG       0x040
 106
 107 /* Host configuration bits for SMBHSTCFG */
 108 #define SMBHSTCFG_HST_EN        1
 109 #define SMBHSTCFG_SMB_SMI_EN    2
 110 #define SMBHSTCFG_I2C_EN        4
 111
 112 /* Auxiliary control register bits, ICH4+ only */
 113 #define SMBAUXCTL_CRC           1
 114 #define SMBAUXCTL_E32B          2
 115
 116 /* kill bit for SMBHSTCNT */
 117 #define SMBHSTCNT_KILL          2
 118
 119 /* Other settings */
 120 #define MAX_TIMEOUT             100
 121 #define ENABLE_INT9             0       /* set to 0x01 to enable - untested */
 122
 123 /* I801 command constants */
 124 #define I801_QUICK              0x00
 125 #define I801_BYTE               0x04
 126 #define I801_BYTE_DATA          0x08
 127 #define I801_WORD_DATA          0x0C
 128 #define I801_PROC_CALL          0x10    /* unimplemented */
 129 #define I801_BLOCK_DATA         0x14
 130 #define I801_I2C_BLOCK_DATA     0x18    /* ICH5 and later */
 131 #define I801_BLOCK_LAST         0x34
 132 #define I801_I2C_BLOCK_LAST     0x38    /* ICH5 and later */
 133 #define I801_START              0x40
 134 #define I801_PEC_EN             0x80    /* ICH3 and later */
 135
 136 /* I801 Hosts Status register bits */
 137 #define SMBHSTSTS_BYTE_DONE     0x80
 138 #define SMBHSTSTS_INUSE_STS     0x40
 139 #define SMBHSTSTS_SMBALERT_STS  0x20
 140 #define SMBHSTSTS_FAILED        0x10
 141 #define SMBHSTSTS_BUS_ERR       0x08
 142 #define SMBHSTSTS_DEV_ERR       0x04
 143 #define SMBHSTSTS_INTR          0x02
 144 #define SMBHSTSTS_HOST_BUSY     0x01
 145
 146 #define STATUS_FLAGS            (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_FAILED | \
 147                                  SMBHSTSTS_BUS_ERR | SMBHSTSTS_DEV_ERR | \
 148                                  SMBHSTSTS_INTR)
 149
 150 /* Older devices have their ID defined in <linux/pci_ids.h> */
 151 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS              0x0f12
 152 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS              0x2292
 153 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS           0x1c22
 154 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS              0x1d22
 155 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
 156 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0         0x1d70
 157 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1         0x1d71
 158 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2         0x1d72
 159 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS          0x1e22
 160 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS                0x1f3c
 161 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS              0x2330
 162 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS           0x23b0
 163 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS         0x3b30
 164 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS             0x8c22
 165 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS          0x8ca2
 166 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS             0x8d22
 167 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0         0x8d7d
 168 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1         0x8d7e
 169 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2         0x8d7f
 170 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS          0x9c22
 171 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS       0x9ca2
 172 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS        0xa123
 173
 174 struct i801_priv {
 175         struct i2c_adapter adapter;
 176         unsigned long smba;
 177         unsigned char original_hstcfg;
 178         struct pci_dev *pci_dev;
 179         unsigned int features;
 180 };
 181
 182 static struct pci_driver i801_driver;
 183
 184 #define FEATURE_SMBUS_PEC       (1 << 0)
 185 #define FEATURE_BLOCK_BUFFER    (1 << 1)
 186 #define FEATURE_BLOCK_PROC      (1 << 2)
 187 #define FEATURE_I2C_BLOCK_READ  (1 << 3)
 188 /* Not really a feature, but it's convenient to handle it as such */
 189 #define FEATURE_IDF             (1 << 15)
 190
 191 static const char *i801_feature_names[] = {
 192         "SMBus PEC",
 193         "Block buffer",
 194         "Block process call",
 195         "I2C block read",
 196 };
 197
 198 static unsigned int disable_features;
 199 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
 200 MODULE_PARM_DESC(disable_features, "Disable selected driver features");
 201
 202 /* Make sure the SMBus host is ready to start transmitting.
 203    Return 0 if it is, -EBUSY if it is not. */
 204 static int i801_check_pre(struct i801_priv *priv)
 205 {
 206         int status;
 207
 208         status = inb_p(SMBHSTSTS(priv));
 209         if (status & SMBHSTSTS_HOST_BUSY) {
 210                 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
 211                 return -EBUSY;
 212         }
 213
 214         status &= STATUS_FLAGS;
 215         if (status) {
 216                 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
 217                         status);
 218                 outb_p(status, SMBHSTSTS(priv));
 219                 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
 220                 if (status) {
 221                         dev_err(&priv->pci_dev->dev,
 222                                 "Failed clearing status flags (%02x)\n",
 223                                 status);
 224                         return -EBUSY;
 225                 }
 226         }
 227
 228         return 0;
 229 }
 230
 231 /* Convert the status register to an error code, and clear it. */
 232 static int i801_check_post(struct i801_priv *priv, int status, int timeout)
 233 {
 234         int result = 0;
 235
 236         /* If the SMBus is still busy, we give up */
 237         if (timeout) {
 238                 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
 239                 /* try to stop the current command */
 240                 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
 241                 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
 242                        SMBHSTCNT(priv));
 243                 msleep(1);
 244                 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
 245                        SMBHSTCNT(priv));
 246
 247                 /* Check if it worked */
 248                 status = inb_p(SMBHSTSTS(priv));
 249                 if ((status & SMBHSTSTS_HOST_BUSY) ||
 250                     !(status & SMBHSTSTS_FAILED))
 251                         dev_err(&priv->pci_dev->dev,
 252                                 "Failed terminating the transaction\n");
 253                 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
 254                 return -ETIMEDOUT;
 255         }
 256
 257         if (status & SMBHSTSTS_FAILED) {
 258                 result = -EIO;
 259                 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
 260         }
 261         if (status & SMBHSTSTS_DEV_ERR) {
 262                 result = -ENXIO;
 263                 dev_dbg(&priv->pci_dev->dev, "No response\n");
 264         }
 265         if (status & SMBHSTSTS_BUS_ERR) {
 266                 result = -EAGAIN;
 267                 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
 268         }
 269
 270         if (result) {
 271                 /* Clear error flags */
 272                 outb_p(status & STATUS_FLAGS, SMBHSTSTS(priv));
 273                 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
 274                 if (status) {
 275                         dev_warn(&priv->pci_dev->dev, "Failed clearing status "
 276                                  "flags at end of transaction (%02x)\n",
 277                                  status);
 278                 }
 279         }
 280
 281         return result;
 282 }
 283
 284 static int i801_transaction(struct i801_priv *priv, int xact)
 285 {
 286         int status;
 287         int result;
 288         int timeout = 0;
 289
 290         result = i801_check_pre(priv);
 291         if (result < 0)
 292                 return result;
 293
 294         /* the current contents of SMBHSTCNT can be overwritten, since PEC,
 295          * INTREN, SMBSCMD are passed in xact */
 296         outb_p(xact | I801_START, SMBHSTCNT(priv));
 297
 298         /* We will always wait for a fraction of a second! */
 299         do {
 300                 msleep(1);
 301                 status = inb_p(SMBHSTSTS(priv));
 302         } while ((status & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_TIMEOUT));
 303
 304         result = i801_check_post(priv, status, timeout > MAX_TIMEOUT);
 305         if (result < 0)
 306                 return result;
 307
 308         outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 309         return 0;
 310 }
 311
 312 /* wait for INTR bit as advised by Intel */
 313 static void i801_wait_hwpec(struct i801_priv *priv)
 314 {
 315         int timeout = 0;
 316         int status;
 317
 318         do {
 319                 msleep(1);
 320                 status = inb_p(SMBHSTSTS(priv));
 321         } while ((!(status & SMBHSTSTS_INTR))
 322                  && (timeout++ < MAX_TIMEOUT));
 323
 324         if (timeout > MAX_TIMEOUT)
 325                 dev_dbg(&priv->pci_dev->dev, "PEC Timeout!\n");
 326
 327         outb_p(status, SMBHSTSTS(priv));
 328 }
 329
 330 static int i801_block_transaction_by_block(struct i801_priv *priv,
 331                                            union i2c_smbus_data *data,
 332                                            char read_write, int hwpec)
 333 {
 334         int i, len;
 335         int status;
 336
 337         inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
 338
 339         /* Use 32-byte buffer to process this transaction */
 340         if (read_write == I2C_SMBUS_WRITE) {
 341                 len = data->block[0];
 342                 outb_p(len, SMBHSTDAT0(priv));
 343                 for (i = 0; i < len; i++)
 344                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 345         }
 346
 347         status = i801_transaction(priv, I801_BLOCK_DATA | ENABLE_INT9 |
 348                                   I801_PEC_EN * hwpec);
 349         if (status)
 350                 return status;
 351
 352         if (read_write == I2C_SMBUS_READ) {
 353                 len = inb_p(SMBHSTDAT0(priv));
 354                 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
 355                         return -EPROTO;
 356
 357                 data->block[0] = len;
 358                 for (i = 0; i < len; i++)
 359                         data->block[i + 1] = inb_p(SMBBLKDAT(priv));
 360         }
 361         return 0;
 362 }
 363
 364 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
 365                                                union i2c_smbus_data *data,
 366                                                char read_write, int command,
 367                                                int hwpec)
 368 {
 369         int i, len;
 370         int smbcmd;
 371         int status;
 372         int result;
 373         int timeout;
 374
 375         result = i801_check_pre(priv);
 376         if (result < 0)
 377                 return result;
 378
 379         len = data->block[0];
 380
 381         if (read_write == I2C_SMBUS_WRITE) {
 382                 outb_p(len, SMBHSTDAT0(priv));
 383                 outb_p(data->block[1], SMBBLKDAT(priv));
 384         }
 385
 386         for (i = 1; i <= len; i++) {
 387                 if (i == len && read_write == I2C_SMBUS_READ) {
 388                         if (command == I2C_SMBUS_I2C_BLOCK_DATA)
 389                                 smbcmd = I801_I2C_BLOCK_LAST;
 390                         else
 391                                 smbcmd = I801_BLOCK_LAST;
 392                 } else {
 393                         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 394                          && read_write == I2C_SMBUS_READ)
 395                                 smbcmd = I801_I2C_BLOCK_DATA;
 396                         else
 397                                 smbcmd = I801_BLOCK_DATA;
 398                 }
 399                 outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT(priv));
 400
 401                 if (i == 1)
 402                         outb_p(inb(SMBHSTCNT(priv)) | I801_START,
 403                                SMBHSTCNT(priv));
 404
 405                 /* We will always wait for a fraction of a second! */
 406                 timeout = 0;
 407                 do {
 408                         msleep(1);
 409                         status = inb_p(SMBHSTSTS(priv));
 410                 } while ((!(status & SMBHSTSTS_BYTE_DONE))
 411                          && (timeout++ < MAX_TIMEOUT));
 412
 413                 result = i801_check_post(priv, status, timeout > MAX_TIMEOUT);
 414                 if (result < 0)
 415                         return result;
 416
 417                 if (i == 1 && read_write == I2C_SMBUS_READ
 418                  && command != I2C_SMBUS_I2C_BLOCK_DATA) {
 419                         len = inb_p(SMBHSTDAT0(priv));
 420                         if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
 421                                 dev_err(&priv->pci_dev->dev,
 422                                         "Illegal SMBus block read size %d\n",
 423                                         len);
 424                                 /* Recover */
 425                                 while (inb_p(SMBHSTSTS(priv)) &
 426                                        SMBHSTSTS_HOST_BUSY)
 427                                         outb_p(SMBHSTSTS_BYTE_DONE,
 428                                                SMBHSTSTS(priv));
 429                                 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 430                                 return -EPROTO;
 431                         }
 432                         data->block[0] = len;
 433                 }
 434
 435                 /* Retrieve/store value in SMBBLKDAT */
 436                 if (read_write == I2C_SMBUS_READ)
 437                         data->block[i] = inb_p(SMBBLKDAT(priv));
 438                 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
 439                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 440
 441                 /* signals SMBBLKDAT ready */
 442                 outb_p(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR, SMBHSTSTS(priv));
 443         }
 444
 445         return 0;
 446 }
 447
 448 static int i801_set_block_buffer_mode(struct i801_priv *priv)
 449 {
 450         outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
 451         if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
 452                 return -EIO;
 453         return 0;
 454 }
 455
 456 /* Block transaction function */
 457 static int i801_block_transaction(struct i801_priv *priv,
 458                                   union i2c_smbus_data *data, char read_write,
 459                                   int command, int hwpec)
 460 {
 461         int result = 0;
 462         unsigned char hostc;
 463
 464         if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
 465                 if (read_write == I2C_SMBUS_WRITE) {
 466                         /* set I2C_EN bit in configuration register */
 467                         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
 468                         pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
 469                                               hostc | SMBHSTCFG_I2C_EN);
 470                 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
 471                         dev_err(&priv->pci_dev->dev,
 472                                 "I2C block read is unsupported!\n");
 473                         return -EOPNOTSUPP;
 474                 }
 475         }
 476
 477         if (read_write == I2C_SMBUS_WRITE
 478          || command == I2C_SMBUS_I2C_BLOCK_DATA) {
 479                 if (data->block[0] < 1)
 480                         data->block[0] = 1;
 481                 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
 482                         data->block[0] = I2C_SMBUS_BLOCK_MAX;
 483         } else {
 484                 data->block[0] = 32;    /* max for SMBus block reads */
 485         }
 486
 487         /* Experience has shown that the block buffer can only be used for
 488            SMBus (not I2C) block transactions, even though the datasheet
 489            doesn't mention this limitation. */
 490         if ((priv->features & FEATURE_BLOCK_BUFFER)
 491          && command != I2C_SMBUS_I2C_BLOCK_DATA
 492          && i801_set_block_buffer_mode(priv) == 0)
 493                 result = i801_block_transaction_by_block(priv, data,
 494                                                          read_write, hwpec);
 495         else
 496                 result = i801_block_transaction_byte_by_byte(priv, data,
 497                                                              read_write,
 498                                                              command, hwpec);
 499
 500         if (result == 0 && hwpec)
 501                 i801_wait_hwpec(priv);
 502
 503         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 504          && read_write == I2C_SMBUS_WRITE) {
 505                 /* restore saved configuration register value */
 506                 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
 507         }
 508         return result;
 509 }
 510
 511 /* Return negative errno on error. */
 512 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
 513                        unsigned short flags, char read_write, u8 command,
 514                        int size, union i2c_smbus_data *data)
 515 {
 516         int hwpec;
 517         int block = 0;
 518         int ret, xact = 0;
 519         struct i801_priv *priv = i2c_get_adapdata(adap);
 520
 521         hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
 522                 && size != I2C_SMBUS_QUICK
 523                 && size != I2C_SMBUS_I2C_BLOCK_DATA;
 524
 525         switch (size) {
 526         case I2C_SMBUS_QUICK:
 527                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 528                        SMBHSTADD(priv));
 529                 xact = I801_QUICK;
 530                 break;
 531         case I2C_SMBUS_BYTE:
 532                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 533                        SMBHSTADD(priv));
 534                 if (read_write == I2C_SMBUS_WRITE)
 535                         outb_p(command, SMBHSTCMD(priv));
 536                 xact = I801_BYTE;
 537                 break;
 538         case I2C_SMBUS_BYTE_DATA:
 539                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 540                        SMBHSTADD(priv));
 541                 outb_p(command, SMBHSTCMD(priv));
 542                 if (read_write == I2C_SMBUS_WRITE)
 543                         outb_p(data->byte, SMBHSTDAT0(priv));
 544                 xact = I801_BYTE_DATA;
 545                 break;
 546         case I2C_SMBUS_WORD_DATA:
 547                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 548                        SMBHSTADD(priv));
 549                 outb_p(command, SMBHSTCMD(priv));
 550                 if (read_write == I2C_SMBUS_WRITE) {
 551                         outb_p(data->word & 0xff, SMBHSTDAT0(priv));
 552                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
 553                 }
 554                 xact = I801_WORD_DATA;
 555                 break;
 556         case I2C_SMBUS_BLOCK_DATA:
 557                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 558                        SMBHSTADD(priv));
 559                 outb_p(command, SMBHSTCMD(priv));
 560                 block = 1;
 561                 break;
 562         case I2C_SMBUS_I2C_BLOCK_DATA:
 563                 /* NB: page 240 of ICH5 datasheet shows that the R/#W
 564                  * bit should be cleared here, even when reading */
 565                 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
 566                 if (read_write == I2C_SMBUS_READ) {
 567                         /* NB: page 240 of ICH5 datasheet also shows
 568                          * that DATA1 is the cmd field when reading */
 569                         outb_p(command, SMBHSTDAT1(priv));
 570                 } else
 571                         outb_p(command, SMBHSTCMD(priv));
 572                 block = 1;
 573                 break;
 574         default:
 575                 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
 576                         size);
 577                 return -EOPNOTSUPP;
 578         }
 579
 580         if (hwpec)      /* enable/disable hardware PEC */
 581                 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
 582         else
 583                 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
 584                        SMBAUXCTL(priv));
 585
 586         if (block)
 587                 ret = i801_block_transaction(priv, data, read_write, size,
 588                                              hwpec);
 589         else
 590                 ret = i801_transaction(priv, xact | ENABLE_INT9);
 591
 592         /* Some BIOSes don't like it when PEC is enabled at reboot or resume
 593            time, so we forcibly disable it after every transaction. Turn off
 594            E32B for the same reason. */
 595         if (hwpec || block)
 596                 outb_p(inb_p(SMBAUXCTL(priv)) &
 597                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
 598
 599         if (block)
 600                 return ret;
 601         if (ret)
 602                 return ret;
 603         if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
 604                 return 0;
 605
 606         switch (xact & 0x7f) {
 607         case I801_BYTE: /* Result put in SMBHSTDAT0 */
 608         case I801_BYTE_DATA:
 609                 data->byte = inb_p(SMBHSTDAT0(priv));
 610                 break;
 611         case I801_WORD_DATA:
 612                 data->word = inb_p(SMBHSTDAT0(priv)) +
 613                              (inb_p(SMBHSTDAT1(priv)) << 8);
 614                 break;
 615         }
 616         return 0;
 617 }
 618
 619
 620 static u32 i801_func(struct i2c_adapter *adapter)
 621 {
 622         struct i801_priv *priv = i2c_get_adapdata(adapter);
 623
 624         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 625                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 626                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
 627                ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
 628                ((priv->features & FEATURE_I2C_BLOCK_READ) ?
 629                 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
 630 }
 631
 632 static const struct i2c_algorithm smbus_algorithm = {
 633         .smbus_xfer     = i801_access,
 634         .functionality  = i801_func,
 635 };
 636
 637 static const struct pci_device_id i801_ids[] = {
 638         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
 639         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
 640         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
 641         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
 642         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
 643         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
 644         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
 645         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
 646         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
 647         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
 648         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
 649         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
 650         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
 651         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
 652         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
 653         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
 654         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
 655         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
 656         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
 657         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
 658         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
 659         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
 660         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
 661         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
 662         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
 663         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
 664         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
 665         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
 666         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
 667         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
 668         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
 669         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
 670         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
 671         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
 672         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
 673         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
 674         { 0, }
 675 };
 676
 677 MODULE_DEVICE_TABLE(pci, i801_ids);
 678
 679 #if defined CONFIG_X86 && defined CONFIG_DMI
 680 static unsigned char apanel_addr;
 681
 682 /* Scan the system ROM for the signature "FJKEYINF" */
 683 static __init const void __iomem *bios_signature(const void __iomem *bios)
 684 {
 685         ssize_t offset;
 686         const unsigned char signature[] = "FJKEYINF";
 687
 688         for (offset = 0; offset < 0x10000; offset += 0x10) {
 689                 if (check_signature(bios + offset, signature,
 690                                     sizeof(signature)-1))
 691                         return bios + offset;
 692         }
 693         return NULL;
 694 }
 695
 696 static void __init input_apanel_init(void)
 697 {
 698         void __iomem *bios;
 699         const void __iomem *p;
 700
 701         bios = ioremap(0xF0000, 0x10000); /* Can't fail */
 702         p = bios_signature(bios);
 703         if (p) {
 704                 /* just use the first address */
 705                 apanel_addr = readb(p + 8 + 3) >> 1;
 706         }
 707         iounmap(bios);
 708 }
 709
 710 struct dmi_onboard_device_info {
 711         const char *name;
 712         u8 type;
 713         unsigned short i2c_addr;
 714         const char *i2c_type;
 715 };
 716
 717 static struct dmi_onboard_device_info __devinitdata dmi_devices[] = {
 718         { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
 719         { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
 720         { "Hades",  DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
 721 };
 722
 723 static void __devinit dmi_check_onboard_device(u8 type, const char *name,
 724                                                struct i2c_adapter *adap)
 725 {
 726         int i;
 727         struct i2c_board_info info;
 728
 729         for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
 730                 /* & ~0x80, ignore enabled/disabled bit */
 731                 if ((type & ~0x80) != dmi_devices[i].type)
 732                         continue;
 733                 if (strcasecmp(name, dmi_devices[i].name))
 734                         continue;
 735
 736                 memset(&info, 0, sizeof(struct i2c_board_info));
 737                 info.addr = dmi_devices[i].i2c_addr;
 738                 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
 739                 i2c_new_device(adap, &info);
 740                 break;
 741         }
 742 }
 743
 744 /* We use our own function to check for onboard devices instead of
 745    dmi_find_device() as some buggy BIOS's have the devices we are interested
 746    in marked as disabled */
 747 static void __devinit dmi_check_onboard_devices(const struct dmi_header *dm,
 748                                                 void *adap)
 749 {
 750         int i, count;
 751
 752         if (dm->type != 10)
 753                 return;
 754
 755         count = (dm->length - sizeof(struct dmi_header)) / 2;
 756         for (i = 0; i < count; i++) {
 757                 const u8 *d = (char *)(dm + 1) + (i * 2);
 758                 const char *name = ((char *) dm) + dm->length;
 759                 u8 type = d[0];
 760                 u8 s = d[1];
 761
 762                 if (!s)
 763                         continue;
 764                 s--;
 765                 while (s > 0 && name[0]) {
 766                         name += strlen(name) + 1;
 767                         s--;
 768                 }
 769                 if (name[0] == 0) /* Bogus string reference */
 770                         continue;
 771
 772                 dmi_check_onboard_device(type, name, adap);
 773         }
 774 }
 775
 776 /* Register optional slaves */
 777 static void __devinit i801_probe_optional_slaves(struct i801_priv *priv)
 778 {
 779         /* Only register slaves on main SMBus channel */
 780         if (priv->features & FEATURE_IDF)
 781                 return;
 782
 783         if (apanel_addr) {
 784                 struct i2c_board_info info;
 785
 786                 memset(&info, 0, sizeof(struct i2c_board_info));
 787                 info.addr = apanel_addr;
 788                 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
 789                 i2c_new_device(&priv->adapter, &info);
 790         }
 791
 792         if (dmi_name_in_vendors("FUJITSU"))
 793                 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
 794 }
 795 #else
 796 static void __init input_apanel_init(void) {}
 797 static void __devinit i801_probe_optional_slaves(struct i801_priv *priv) {}
 798 #endif  /* CONFIG_X86 && CONFIG_DMI */
 799
 800 static int __devinit i801_probe(struct pci_dev *dev,
 801                                 const struct pci_device_id *id)
 802 {
 803         unsigned char temp;
 804         int err, i;
 805         struct i801_priv *priv;
 806
 807         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 808         if (!priv)
 809                 return -ENOMEM;
 810
 811         i2c_set_adapdata(&priv->adapter, priv);
 812         priv->adapter.owner = THIS_MODULE;
 813         priv->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
 814         priv->adapter.algo = &smbus_algorithm;
 815
 816         priv->pci_dev = dev;
 817         switch (dev->device) {
 818         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
 819         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
 820         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
 821         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
 822         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
 823         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
 824                 priv->features |= FEATURE_IDF;
 825                 /* fall through */
 826         default:
 827                 priv->features |= FEATURE_I2C_BLOCK_READ;
 828                 /* fall through */
 829         case PCI_DEVICE_ID_INTEL_82801DB_3:
 830                 priv->features |= FEATURE_SMBUS_PEC;
 831                 priv->features |= FEATURE_BLOCK_BUFFER;
 832                 /* fall through */
 833         case PCI_DEVICE_ID_INTEL_82801CA_3:
 834         case PCI_DEVICE_ID_INTEL_82801BA_2:
 835         case PCI_DEVICE_ID_INTEL_82801AB_3:
 836         case PCI_DEVICE_ID_INTEL_82801AA_3:
 837                 break;
 838         }
 839
 840         /* Disable features on user request */
 841         for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
 842                 if (priv->features & disable_features & (1 << i))
 843                         dev_notice(&dev->dev, "%s disabled by user\n",
 844                                    i801_feature_names[i]);
 845         }
 846         priv->features &= ~disable_features;
 847
 848         err = pci_enable_device(dev);
 849         if (err) {
 850                 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
 851                         err);
 852                 goto exit;
 853         }
 854
 855         /* Determine the address of the SMBus area */
 856         priv->smba = pci_resource_start(dev, SMBBAR);
 857         if (!priv->smba) {
 858                 dev_err(&dev->dev, "SMBus base address uninitialized, "
 859                         "upgrade BIOS\n");
 860                 err = -ENODEV;
 861                 goto exit;
 862         }
 863
 864         err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
 865         if (err) {
 866                 err = -ENODEV;
 867                 goto exit;
 868         }
 869
 870         err = pci_request_region(dev, SMBBAR, i801_driver.name);
 871         if (err) {
 872                 dev_err(&dev->dev, "Failed to request SMBus region "
 873                         "0x%lx-0x%Lx\n", priv->smba,
 874                         (unsigned long long)pci_resource_end(dev, SMBBAR));
 875                 goto exit;
 876         }
 877
 878         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
 879         priv->original_hstcfg = temp;
 880         temp &= ~SMBHSTCFG_I2C_EN;      /* SMBus timing */
 881         if (!(temp & SMBHSTCFG_HST_EN)) {
 882                 dev_info(&dev->dev, "Enabling SMBus device\n");
 883                 temp |= SMBHSTCFG_HST_EN;
 884         }
 885         pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
 886
 887         if (temp & SMBHSTCFG_SMB_SMI_EN)
 888                 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
 889         else
 890                 dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n");
 891
 892         /* Clear special mode bits */
 893         if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
 894                 outb_p(inb_p(SMBAUXCTL(priv)) &
 895                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
 896
 897         /* set up the sysfs linkage to our parent device */
 898         priv->adapter.dev.parent = &dev->dev;
 899
 900         /* Retry up to 3 times on lost arbitration */
 901         priv->adapter.retries = 3;
 902
 903         snprintf(priv->adapter.name, sizeof(priv->adapter.name),
 904                 "SMBus I801 adapter at %04lx", priv->smba);
 905         err = i2c_add_adapter(&priv->adapter);
 906         if (err) {
 907                 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
 908                 goto exit_release;
 909         }
 910
 911         i801_probe_optional_slaves(priv);
 912
 913         pci_set_drvdata(dev, priv);
 914         return 0;
 915
 916 exit_release:
 917         pci_release_region(dev, SMBBAR);
 918 exit:
 919         kfree(priv);
 920         return err;
 921 }
 922
 923 static void __devexit i801_remove(struct pci_dev *dev)
 924 {
 925         struct i801_priv *priv = pci_get_drvdata(dev);
 926
 927         i2c_del_adapter(&priv->adapter);
 928         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
 929         pci_release_region(dev, SMBBAR);
 930         pci_set_drvdata(dev, NULL);
 931         kfree(priv);
 932         /*
 933          * do not call pci_disable_device(dev) since it can cause hard hangs on
 934          * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
 935          */
 936 }
 937
 938 #ifdef CONFIG_PM
 939 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
 940 {
 941         struct i801_priv *priv = pci_get_drvdata(dev);
 942
 943         pci_save_state(dev);
 944         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
 945         pci_set_power_state(dev, pci_choose_state(dev, mesg));
 946         return 0;
 947 }
 948
 949 static int i801_resume(struct pci_dev *dev)
 950 {
 951         pci_set_power_state(dev, PCI_D0);
 952         pci_restore_state(dev);
 953         return pci_enable_device(dev);
 954 }
 955 #else
 956 #define i801_suspend NULL
 957 #define i801_resume NULL
 958 #endif
 959
 960 static struct pci_driver i801_driver = {
 961         .name           = "i801_smbus",
 962         .id_table       = i801_ids,
 963         .probe          = i801_probe,
 964         .remove         = __devexit_p(i801_remove),
 965         .suspend        = i801_suspend,
 966         .resume         = i801_resume,
 967 };
 968
 969 static int __init i2c_i801_init(void)
 970 {
 971         if (dmi_name_in_vendors("FUJITSU"))
 972                 input_apanel_init();
 973         return pci_register_driver(&i801_driver);
 974 }
 975
 976 static void __exit i2c_i801_exit(void)
 977 {
 978         pci_unregister_driver(&i801_driver);
 979 }
 980
 981 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, "
 982               "Jean Delvare <khali@linux-fr.org>");
 983 MODULE_DESCRIPTION("I801 SMBus driver");
 984 MODULE_LICENSE("GPL");
 985
 986 module_init(i2c_i801_init);
 987 module_exit(i2c_i801_exit);