drivers/i2c/busses/i2c-i801.c

   1 /*
   2     Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
   3     Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
   4     <mdsxyz123@yahoo.com>
   5     Copyright (C) 2007, 2008   Jean Delvare <khali@linux-fr.org>
   6     Copyright (C) 2010         Intel Corporation,
   7                                David Woodhouse <dwmw2@infradead.org>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18
  19     You should have received a copy of the GNU General Public License
  20     along with this program; if not, write to the Free Software
  21     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22 */
  23
  24 /*
  25  * Supports the following Intel I/O Controller Hubs (ICH):
  26  *
  27  *                                      I/O                     Block   I2C
  28  *                                      region  SMBus   Block   proc.   block
  29  * Chip name                    PCI ID  size    PEC     buffer  call    read
  30  * ---------------------------------------------------------------------------
  31  * 82801AA (ICH)                0x2413  16      no      no      no      no
  32  * 82801AB (ICH0)               0x2423  16      no      no      no      no
  33  * 82801BA (ICH2)               0x2443  16      no      no      no      no
  34  * 82801CA (ICH3)               0x2483  32      soft    no      no      no
  35  * 82801DB (ICH4)               0x24c3  32      hard    yes     no      no
  36  * 82801E (ICH5)                0x24d3  32      hard    yes     yes     yes
  37  * 6300ESB                      0x25a4  32      hard    yes     yes     yes
  38  * 82801F (ICH6)                0x266a  32      hard    yes     yes     yes
  39  * 6310ESB/6320ESB              0x269b  32      hard    yes     yes     yes
  40  * 82801G (ICH7)                0x27da  32      hard    yes     yes     yes
  41  * 82801H (ICH8)                0x283e  32      hard    yes     yes     yes
  42  * 82801I (ICH9)                0x2930  32      hard    yes     yes     yes
  43  * EP80579 (Tolapai)            0x5032  32      hard    yes     yes     yes
  44  * ICH10                        0x3a30  32      hard    yes     yes     yes
  45  * ICH10                        0x3a60  32      hard    yes     yes     yes
  46  * 5/3400 Series (PCH)          0x3b30  32      hard    yes     yes     yes
  47  * 6 Series (PCH)               0x1c22  32      hard    yes     yes     yes
  48  * Patsburg (PCH)               0x1d22  32      hard    yes     yes     yes
  49  * Patsburg (PCH) IDF           0x1d70  32      hard    yes     yes     yes
  50  * Patsburg (PCH) IDF           0x1d71  32      hard    yes     yes     yes
  51  * Patsburg (PCH) IDF           0x1d72  32      hard    yes     yes     yes
  52  * DH89xxCC (PCH)               0x2330  32      hard    yes     yes     yes
  53  * Panther Point (PCH)          0x1e22  32      hard    yes     yes     yes
  54  * Lynx Point (PCH)             0x8c22  32      hard    yes     yes     yes
  55  * Lynx Point-LP (PCH)          0x9c22  32      hard    yes     yes     yes
  56  * Avoton (SOC)                 0x1f3c  32      hard    yes     yes     yes
  57  * Wellsburg (PCH)              0x8d22  32      hard    yes     yes     yes
  58  * Wellsburg (PCH) MS           0x8d7d  32      hard    yes     yes     yes
  59  * Wellsburg (PCH) MS           0x8d7e  32      hard    yes     yes     yes
  60  * Wellsburg (PCH) MS           0x8d7f  32      hard    yes     yes     yes
  61  * Coleto Creek (PCH)           0x23b0  32      hard    yes     yes     yes
  62  * Wildcat Point (PCH)          0x8ca2  32      hard    yes     yes     yes
  63  * Wildcat Point-LP (PCH)       0x9ca2  32      hard    yes     yes     yes
  64  * BayTrail (SOC)               0x0f12  32      hard    yes     yes     yes
  65  *
  66  * Features supported by this driver:
  67  * Software PEC                         no
  68  * Hardware PEC                         yes
  69  * Block buffer                         yes
  70  * Block process call transaction       no
  71  * I2C block read transaction           yes (doesn't use the block buffer)
  72  * Slave mode                           no
  73  *
  74  * See the file Documentation/i2c/busses/i2c-i801 for details.
  75  */
  76
  77 #include <linux/module.h>
  78 #include <linux/pci.h>
  79 #include <linux/kernel.h>
  80 #include <linux/stddef.h>
  81 #include <linux/delay.h>
  82 #include <linux/ioport.h>
  83 #include <linux/init.h>
  84 #include <linux/i2c.h>
  85 #include <linux/acpi.h>
  86 #include <linux/io.h>
  87 #include <linux/dmi.h>
  88 #include <linux/slab.h>
  89
  90 /* I801 SMBus address offsets */
  91 #define SMBHSTSTS(p)    (0 + (p)->smba)
  92 #define SMBHSTCNT(p)    (2 + (p)->smba)
  93 #define SMBHSTCMD(p)    (3 + (p)->smba)
  94 #define SMBHSTADD(p)    (4 + (p)->smba)
  95 #define SMBHSTDAT0(p)   (5 + (p)->smba)
  96 #define SMBHSTDAT1(p)   (6 + (p)->smba)
  97 #define SMBBLKDAT(p)    (7 + (p)->smba)
  98 #define SMBPEC(p)       (8 + (p)->smba)         /* ICH3 and later */
  99 #define SMBAUXSTS(p)    (12 + (p)->smba)        /* ICH4 and later */
 100 #define SMBAUXCTL(p)    (13 + (p)->smba)        /* ICH4 and later */
 101
 102 /* PCI Address Constants */
 103 #define SMBBAR          4
 104 #define SMBHSTCFG       0x040
 105
 106 /* Host configuration bits for SMBHSTCFG */
 107 #define SMBHSTCFG_HST_EN        1
 108 #define SMBHSTCFG_SMB_SMI_EN    2
 109 #define SMBHSTCFG_I2C_EN        4
 110
 111 /* Auxiliary control register bits, ICH4+ only */
 112 #define SMBAUXCTL_CRC           1
 113 #define SMBAUXCTL_E32B          2
 114
 115 /* kill bit for SMBHSTCNT */
 116 #define SMBHSTCNT_KILL          2
 117
 118 /* Other settings */
 119 #define MAX_TIMEOUT             100
 120 #define ENABLE_INT9             0       /* set to 0x01 to enable - untested */
 121
 122 /* I801 command constants */
 123 #define I801_QUICK              0x00
 124 #define I801_BYTE               0x04
 125 #define I801_BYTE_DATA          0x08
 126 #define I801_WORD_DATA          0x0C
 127 #define I801_PROC_CALL          0x10    /* unimplemented */
 128 #define I801_BLOCK_DATA         0x14
 129 #define I801_I2C_BLOCK_DATA     0x18    /* ICH5 and later */
 130 #define I801_BLOCK_LAST         0x34
 131 #define I801_I2C_BLOCK_LAST     0x38    /* ICH5 and later */
 132 #define I801_START              0x40
 133 #define I801_PEC_EN             0x80    /* ICH3 and later */
 134
 135 /* I801 Hosts Status register bits */
 136 #define SMBHSTSTS_BYTE_DONE     0x80
 137 #define SMBHSTSTS_INUSE_STS     0x40
 138 #define SMBHSTSTS_SMBALERT_STS  0x20
 139 #define SMBHSTSTS_FAILED        0x10
 140 #define SMBHSTSTS_BUS_ERR       0x08
 141 #define SMBHSTSTS_DEV_ERR       0x04
 142 #define SMBHSTSTS_INTR          0x02
 143 #define SMBHSTSTS_HOST_BUSY     0x01
 144
 145 #define STATUS_FLAGS            (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_FAILED | \
 146                                  SMBHSTSTS_BUS_ERR | SMBHSTSTS_DEV_ERR | \
 147                                  SMBHSTSTS_INTR)
 148
 149 /* Older devices have their ID defined in <linux/pci_ids.h> */
 150 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS              0x0f12
 151 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS              0x2292
 152 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS           0x1c22
 153 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS              0x1d22
 154 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
 155 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0         0x1d70
 156 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1         0x1d71
 157 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2         0x1d72
 158 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS          0x1e22
 159 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS                0x1f3c
 160 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS              0x2330
 161 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS           0x23b0
 162 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS         0x3b30
 163 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS             0x8c22
 164 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS          0x8ca2
 165 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS             0x8d22
 166 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0         0x8d7d
 167 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1         0x8d7e
 168 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2         0x8d7f
 169 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS          0x9c22
 170 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS       0x9ca2
 171
 172 struct i801_priv {
 173         struct i2c_adapter adapter;
 174         unsigned long smba;
 175         unsigned char original_hstcfg;
 176         struct pci_dev *pci_dev;
 177         unsigned int features;
 178 };
 179
 180 static struct pci_driver i801_driver;
 181
 182 #define FEATURE_SMBUS_PEC       (1 << 0)
 183 #define FEATURE_BLOCK_BUFFER    (1 << 1)
 184 #define FEATURE_BLOCK_PROC      (1 << 2)
 185 #define FEATURE_I2C_BLOCK_READ  (1 << 3)
 186 /* Not really a feature, but it's convenient to handle it as such */
 187 #define FEATURE_IDF             (1 << 15)
 188
 189 static const char *i801_feature_names[] = {
 190         "SMBus PEC",
 191         "Block buffer",
 192         "Block process call",
 193         "I2C block read",
 194 };
 195
 196 static unsigned int disable_features;
 197 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
 198 MODULE_PARM_DESC(disable_features, "Disable selected driver features");
 199
 200 /* Make sure the SMBus host is ready to start transmitting.
 201    Return 0 if it is, -EBUSY if it is not. */
 202 static int i801_check_pre(struct i801_priv *priv)
 203 {
 204         int status;
 205
 206         status = inb_p(SMBHSTSTS(priv));
 207         if (status & SMBHSTSTS_HOST_BUSY) {
 208                 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
 209                 return -EBUSY;
 210         }
 211
 212         status &= STATUS_FLAGS;
 213         if (status) {
 214                 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
 215                         status);
 216                 outb_p(status, SMBHSTSTS(priv));
 217                 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
 218                 if (status) {
 219                         dev_err(&priv->pci_dev->dev,
 220                                 "Failed clearing status flags (%02x)\n",
 221                                 status);
 222                         return -EBUSY;
 223                 }
 224         }
 225
 226         return 0;
 227 }
 228
 229 /* Convert the status register to an error code, and clear it. */
 230 static int i801_check_post(struct i801_priv *priv, int status, int timeout)
 231 {
 232         int result = 0;
 233
 234         /* If the SMBus is still busy, we give up */
 235         if (timeout) {
 236                 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
 237                 /* try to stop the current command */
 238                 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
 239                 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
 240                        SMBHSTCNT(priv));
 241                 msleep(1);
 242                 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
 243                        SMBHSTCNT(priv));
 244
 245                 /* Check if it worked */
 246                 status = inb_p(SMBHSTSTS(priv));
 247                 if ((status & SMBHSTSTS_HOST_BUSY) ||
 248                     !(status & SMBHSTSTS_FAILED))
 249                         dev_err(&priv->pci_dev->dev,
 250                                 "Failed terminating the transaction\n");
 251                 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
 252                 return -ETIMEDOUT;
 253         }
 254
 255         if (status & SMBHSTSTS_FAILED) {
 256                 result = -EIO;
 257                 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
 258         }
 259         if (status & SMBHSTSTS_DEV_ERR) {
 260                 result = -ENXIO;
 261                 dev_dbg(&priv->pci_dev->dev, "No response\n");
 262         }
 263         if (status & SMBHSTSTS_BUS_ERR) {
 264                 result = -EAGAIN;
 265                 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
 266         }
 267
 268         if (result) {
 269                 /* Clear error flags */
 270                 outb_p(status & STATUS_FLAGS, SMBHSTSTS(priv));
 271                 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
 272                 if (status) {
 273                         dev_warn(&priv->pci_dev->dev, "Failed clearing status "
 274                                  "flags at end of transaction (%02x)\n",
 275                                  status);
 276                 }
 277         }
 278
 279         return result;
 280 }
 281
 282 static int i801_transaction(struct i801_priv *priv, int xact)
 283 {
 284         int status;
 285         int result;
 286         int timeout = 0;
 287
 288         result = i801_check_pre(priv);
 289         if (result < 0)
 290                 return result;
 291
 292         /* the current contents of SMBHSTCNT can be overwritten, since PEC,
 293          * INTREN, SMBSCMD are passed in xact */
 294         outb_p(xact | I801_START, SMBHSTCNT(priv));
 295
 296         /* We will always wait for a fraction of a second! */
 297         do {
 298                 msleep(1);
 299                 status = inb_p(SMBHSTSTS(priv));
 300         } while ((status & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_TIMEOUT));
 301
 302         result = i801_check_post(priv, status, timeout > MAX_TIMEOUT);
 303         if (result < 0)
 304                 return result;
 305
 306         outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 307         return 0;
 308 }
 309
 310 /* wait for INTR bit as advised by Intel */
 311 static void i801_wait_hwpec(struct i801_priv *priv)
 312 {
 313         int timeout = 0;
 314         int status;
 315
 316         do {
 317                 msleep(1);
 318                 status = inb_p(SMBHSTSTS(priv));
 319         } while ((!(status & SMBHSTSTS_INTR))
 320                  && (timeout++ < MAX_TIMEOUT));
 321
 322         if (timeout > MAX_TIMEOUT)
 323                 dev_dbg(&priv->pci_dev->dev, "PEC Timeout!\n");
 324
 325         outb_p(status, SMBHSTSTS(priv));
 326 }
 327
 328 static int i801_block_transaction_by_block(struct i801_priv *priv,
 329                                            union i2c_smbus_data *data,
 330                                            char read_write, int hwpec)
 331 {
 332         int i, len;
 333         int status;
 334
 335         inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
 336
 337         /* Use 32-byte buffer to process this transaction */
 338         if (read_write == I2C_SMBUS_WRITE) {
 339                 len = data->block[0];
 340                 outb_p(len, SMBHSTDAT0(priv));
 341                 for (i = 0; i < len; i++)
 342                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 343         }
 344
 345         status = i801_transaction(priv, I801_BLOCK_DATA | ENABLE_INT9 |
 346                                   I801_PEC_EN * hwpec);
 347         if (status)
 348                 return status;
 349
 350         if (read_write == I2C_SMBUS_READ) {
 351                 len = inb_p(SMBHSTDAT0(priv));
 352                 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
 353                         return -EPROTO;
 354
 355                 data->block[0] = len;
 356                 for (i = 0; i < len; i++)
 357                         data->block[i + 1] = inb_p(SMBBLKDAT(priv));
 358         }
 359         return 0;
 360 }
 361
 362 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
 363                                                union i2c_smbus_data *data,
 364                                                char read_write, int command,
 365                                                int hwpec)
 366 {
 367         int i, len;
 368         int smbcmd;
 369         int status;
 370         int result;
 371         int timeout;
 372
 373         result = i801_check_pre(priv);
 374         if (result < 0)
 375                 return result;
 376
 377         len = data->block[0];
 378
 379         if (read_write == I2C_SMBUS_WRITE) {
 380                 outb_p(len, SMBHSTDAT0(priv));
 381                 outb_p(data->block[1], SMBBLKDAT(priv));
 382         }
 383
 384         for (i = 1; i <= len; i++) {
 385                 if (i == len && read_write == I2C_SMBUS_READ) {
 386                         if (command == I2C_SMBUS_I2C_BLOCK_DATA)
 387                                 smbcmd = I801_I2C_BLOCK_LAST;
 388                         else
 389                                 smbcmd = I801_BLOCK_LAST;
 390                 } else {
 391                         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 392                          && read_write == I2C_SMBUS_READ)
 393                                 smbcmd = I801_I2C_BLOCK_DATA;
 394                         else
 395                                 smbcmd = I801_BLOCK_DATA;
 396                 }
 397                 outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT(priv));
 398
 399                 if (i == 1)
 400                         outb_p(inb(SMBHSTCNT(priv)) | I801_START,
 401                                SMBHSTCNT(priv));
 402
 403                 /* We will always wait for a fraction of a second! */
 404                 timeout = 0;
 405                 do {
 406                         msleep(1);
 407                         status = inb_p(SMBHSTSTS(priv));
 408                 } while ((!(status & SMBHSTSTS_BYTE_DONE))
 409                          && (timeout++ < MAX_TIMEOUT));
 410
 411                 result = i801_check_post(priv, status, timeout > MAX_TIMEOUT);
 412                 if (result < 0)
 413                         return result;
 414
 415                 if (i == 1 && read_write == I2C_SMBUS_READ
 416                  && command != I2C_SMBUS_I2C_BLOCK_DATA) {
 417                         len = inb_p(SMBHSTDAT0(priv));
 418                         if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
 419                                 dev_err(&priv->pci_dev->dev,
 420                                         "Illegal SMBus block read size %d\n",
 421                                         len);
 422                                 /* Recover */
 423                                 while (inb_p(SMBHSTSTS(priv)) &
 424                                        SMBHSTSTS_HOST_BUSY)
 425                                         outb_p(SMBHSTSTS_BYTE_DONE,
 426                                                SMBHSTSTS(priv));
 427                                 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 428                                 return -EPROTO;
 429                         }
 430                         data->block[0] = len;
 431                 }
 432
 433                 /* Retrieve/store value in SMBBLKDAT */
 434                 if (read_write == I2C_SMBUS_READ)
 435                         data->block[i] = inb_p(SMBBLKDAT(priv));
 436                 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
 437                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 438
 439                 /* signals SMBBLKDAT ready */
 440                 outb_p(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR, SMBHSTSTS(priv));
 441         }
 442
 443         return 0;
 444 }
 445
 446 static int i801_set_block_buffer_mode(struct i801_priv *priv)
 447 {
 448         outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
 449         if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
 450                 return -EIO;
 451         return 0;
 452 }
 453
 454 /* Block transaction function */
 455 static int i801_block_transaction(struct i801_priv *priv,
 456                                   union i2c_smbus_data *data, char read_write,
 457                                   int command, int hwpec)
 458 {
 459         int result = 0;
 460         unsigned char hostc;
 461
 462         if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
 463                 if (read_write == I2C_SMBUS_WRITE) {
 464                         /* set I2C_EN bit in configuration register */
 465                         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
 466                         pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
 467                                               hostc | SMBHSTCFG_I2C_EN);
 468                 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
 469                         dev_err(&priv->pci_dev->dev,
 470                                 "I2C block read is unsupported!\n");
 471                         return -EOPNOTSUPP;
 472                 }
 473         }
 474
 475         if (read_write == I2C_SMBUS_WRITE
 476          || command == I2C_SMBUS_I2C_BLOCK_DATA) {
 477                 if (data->block[0] < 1)
 478                         data->block[0] = 1;
 479                 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
 480                         data->block[0] = I2C_SMBUS_BLOCK_MAX;
 481         } else {
 482                 data->block[0] = 32;    /* max for SMBus block reads */
 483         }
 484
 485         /* Experience has shown that the block buffer can only be used for
 486            SMBus (not I2C) block transactions, even though the datasheet
 487            doesn't mention this limitation. */
 488         if ((priv->features & FEATURE_BLOCK_BUFFER)
 489          && command != I2C_SMBUS_I2C_BLOCK_DATA
 490          && i801_set_block_buffer_mode(priv) == 0)
 491                 result = i801_block_transaction_by_block(priv, data,
 492                                                          read_write, hwpec);
 493         else
 494                 result = i801_block_transaction_byte_by_byte(priv, data,
 495                                                              read_write,
 496                                                              command, hwpec);
 497
 498         if (result == 0 && hwpec)
 499                 i801_wait_hwpec(priv);
 500
 501         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 502          && read_write == I2C_SMBUS_WRITE) {
 503                 /* restore saved configuration register value */
 504                 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
 505         }
 506         return result;
 507 }
 508
 509 /* Return negative errno on error. */
 510 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
 511                        unsigned short flags, char read_write, u8 command,
 512                        int size, union i2c_smbus_data *data)
 513 {
 514         int hwpec;
 515         int block = 0;
 516         int ret, xact = 0;
 517         struct i801_priv *priv = i2c_get_adapdata(adap);
 518
 519         hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
 520                 && size != I2C_SMBUS_QUICK
 521                 && size != I2C_SMBUS_I2C_BLOCK_DATA;
 522
 523         switch (size) {
 524         case I2C_SMBUS_QUICK:
 525                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 526                        SMBHSTADD(priv));
 527                 xact = I801_QUICK;
 528                 break;
 529         case I2C_SMBUS_BYTE:
 530                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 531                        SMBHSTADD(priv));
 532                 if (read_write == I2C_SMBUS_WRITE)
 533                         outb_p(command, SMBHSTCMD(priv));
 534                 xact = I801_BYTE;
 535                 break;
 536         case I2C_SMBUS_BYTE_DATA:
 537                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 538                        SMBHSTADD(priv));
 539                 outb_p(command, SMBHSTCMD(priv));
 540                 if (read_write == I2C_SMBUS_WRITE)
 541                         outb_p(data->byte, SMBHSTDAT0(priv));
 542                 xact = I801_BYTE_DATA;
 543                 break;
 544         case I2C_SMBUS_WORD_DATA:
 545                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 546                        SMBHSTADD(priv));
 547                 outb_p(command, SMBHSTCMD(priv));
 548                 if (read_write == I2C_SMBUS_WRITE) {
 549                         outb_p(data->word & 0xff, SMBHSTDAT0(priv));
 550                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
 551                 }
 552                 xact = I801_WORD_DATA;
 553                 break;
 554         case I2C_SMBUS_BLOCK_DATA:
 555                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 556                        SMBHSTADD(priv));
 557                 outb_p(command, SMBHSTCMD(priv));
 558                 block = 1;
 559                 break;
 560         case I2C_SMBUS_I2C_BLOCK_DATA:
 561                 /* NB: page 240 of ICH5 datasheet shows that the R/#W
 562                  * bit should be cleared here, even when reading */
 563                 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
 564                 if (read_write == I2C_SMBUS_READ) {
 565                         /* NB: page 240 of ICH5 datasheet also shows
 566                          * that DATA1 is the cmd field when reading */
 567                         outb_p(command, SMBHSTDAT1(priv));
 568                 } else
 569                         outb_p(command, SMBHSTCMD(priv));
 570                 block = 1;
 571                 break;
 572         default:
 573                 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
 574                         size);
 575                 return -EOPNOTSUPP;
 576         }
 577
 578         if (hwpec)      /* enable/disable hardware PEC */
 579                 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
 580         else
 581                 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
 582                        SMBAUXCTL(priv));
 583
 584         if (block)
 585                 ret = i801_block_transaction(priv, data, read_write, size,
 586                                              hwpec);
 587         else
 588                 ret = i801_transaction(priv, xact | ENABLE_INT9);
 589
 590         /* Some BIOSes don't like it when PEC is enabled at reboot or resume
 591            time, so we forcibly disable it after every transaction. Turn off
 592            E32B for the same reason. */
 593         if (hwpec || block)
 594                 outb_p(inb_p(SMBAUXCTL(priv)) &
 595                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
 596
 597         if (block)
 598                 return ret;
 599         if (ret)
 600                 return ret;
 601         if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
 602                 return 0;
 603
 604         switch (xact & 0x7f) {
 605         case I801_BYTE: /* Result put in SMBHSTDAT0 */
 606         case I801_BYTE_DATA:
 607                 data->byte = inb_p(SMBHSTDAT0(priv));
 608                 break;
 609         case I801_WORD_DATA:
 610                 data->word = inb_p(SMBHSTDAT0(priv)) +
 611                              (inb_p(SMBHSTDAT1(priv)) << 8);
 612                 break;
 613         }
 614         return 0;
 615 }
 616
 617
 618 static u32 i801_func(struct i2c_adapter *adapter)
 619 {
 620         struct i801_priv *priv = i2c_get_adapdata(adapter);
 621
 622         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 623                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 624                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
 625                ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
 626                ((priv->features & FEATURE_I2C_BLOCK_READ) ?
 627                 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
 628 }
 629
 630 static const struct i2c_algorithm smbus_algorithm = {
 631         .smbus_xfer     = i801_access,
 632         .functionality  = i801_func,
 633 };
 634
 635 static const struct pci_device_id i801_ids[] = {
 636         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
 637         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
 638         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
 639         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
 640         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
 641         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
 642         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
 643         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
 644         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
 645         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
 646         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
 647         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
 648         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
 649         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
 650         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
 651         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
 652         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
 653         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
 654         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
 655         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
 656         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
 657         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
 658         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
 659         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
 660         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
 661         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
 662         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
 663         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
 664         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
 665         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
 666         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
 667         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
 668         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
 669         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
 670         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
 671         { 0, }
 672 };
 673
 674 MODULE_DEVICE_TABLE(pci, i801_ids);
 675
 676 #if defined CONFIG_X86 && defined CONFIG_DMI
 677 static unsigned char apanel_addr;
 678
 679 /* Scan the system ROM for the signature "FJKEYINF" */
 680 static __init const void __iomem *bios_signature(const void __iomem *bios)
 681 {
 682         ssize_t offset;
 683         const unsigned char signature[] = "FJKEYINF";
 684
 685         for (offset = 0; offset < 0x10000; offset += 0x10) {
 686                 if (check_signature(bios + offset, signature,
 687                                     sizeof(signature)-1))
 688                         return bios + offset;
 689         }
 690         return NULL;
 691 }
 692
 693 static void __init input_apanel_init(void)
 694 {
 695         void __iomem *bios;
 696         const void __iomem *p;
 697
 698         bios = ioremap(0xF0000, 0x10000); /* Can't fail */
 699         p = bios_signature(bios);
 700         if (p) {
 701                 /* just use the first address */
 702                 apanel_addr = readb(p + 8 + 3) >> 1;
 703         }
 704         iounmap(bios);
 705 }
 706
 707 struct dmi_onboard_device_info {
 708         const char *name;
 709         u8 type;
 710         unsigned short i2c_addr;
 711         const char *i2c_type;
 712 };
 713
 714 static struct dmi_onboard_device_info __devinitdata dmi_devices[] = {
 715         { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
 716         { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
 717         { "Hades",  DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
 718 };
 719
 720 static void __devinit dmi_check_onboard_device(u8 type, const char *name,
 721                                                struct i2c_adapter *adap)
 722 {
 723         int i;
 724         struct i2c_board_info info;
 725
 726         for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
 727                 /* & ~0x80, ignore enabled/disabled bit */
 728                 if ((type & ~0x80) != dmi_devices[i].type)
 729                         continue;
 730                 if (strcasecmp(name, dmi_devices[i].name))
 731                         continue;
 732
 733                 memset(&info, 0, sizeof(struct i2c_board_info));
 734                 info.addr = dmi_devices[i].i2c_addr;
 735                 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
 736                 i2c_new_device(adap, &info);
 737                 break;
 738         }
 739 }
 740
 741 /* We use our own function to check for onboard devices instead of
 742    dmi_find_device() as some buggy BIOS's have the devices we are interested
 743    in marked as disabled */
 744 static void __devinit dmi_check_onboard_devices(const struct dmi_header *dm,
 745                                                 void *adap)
 746 {
 747         int i, count;
 748
 749         if (dm->type != 10)
 750                 return;
 751
 752         count = (dm->length - sizeof(struct dmi_header)) / 2;
 753         for (i = 0; i < count; i++) {
 754                 const u8 *d = (char *)(dm + 1) + (i * 2);
 755                 const char *name = ((char *) dm) + dm->length;
 756                 u8 type = d[0];
 757                 u8 s = d[1];
 758
 759                 if (!s)
 760                         continue;
 761                 s--;
 762                 while (s > 0 && name[0]) {
 763                         name += strlen(name) + 1;
 764                         s--;
 765                 }
 766                 if (name[0] == 0) /* Bogus string reference */
 767                         continue;
 768
 769                 dmi_check_onboard_device(type, name, adap);
 770         }
 771 }
 772
 773 /* Register optional slaves */
 774 static void __devinit i801_probe_optional_slaves(struct i801_priv *priv)
 775 {
 776         /* Only register slaves on main SMBus channel */
 777         if (priv->features & FEATURE_IDF)
 778                 return;
 779
 780         if (apanel_addr) {
 781                 struct i2c_board_info info;
 782
 783                 memset(&info, 0, sizeof(struct i2c_board_info));
 784                 info.addr = apanel_addr;
 785                 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
 786                 i2c_new_device(&priv->adapter, &info);
 787         }
 788
 789         if (dmi_name_in_vendors("FUJITSU"))
 790                 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
 791 }
 792 #else
 793 static void __init input_apanel_init(void) {}
 794 static void __devinit i801_probe_optional_slaves(struct i801_priv *priv) {}
 795 #endif  /* CONFIG_X86 && CONFIG_DMI */
 796
 797 static int __devinit i801_probe(struct pci_dev *dev,
 798                                 const struct pci_device_id *id)
 799 {
 800         unsigned char temp;
 801         int err, i;
 802         struct i801_priv *priv;
 803
 804         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 805         if (!priv)
 806                 return -ENOMEM;
 807
 808         i2c_set_adapdata(&priv->adapter, priv);
 809         priv->adapter.owner = THIS_MODULE;
 810         priv->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
 811         priv->adapter.algo = &smbus_algorithm;
 812
 813         priv->pci_dev = dev;
 814         switch (dev->device) {
 815         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
 816         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
 817         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
 818         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
 819         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
 820         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
 821                 priv->features |= FEATURE_IDF;
 822                 /* fall through */
 823         default:
 824                 priv->features |= FEATURE_I2C_BLOCK_READ;
 825                 /* fall through */
 826         case PCI_DEVICE_ID_INTEL_82801DB_3:
 827                 priv->features |= FEATURE_SMBUS_PEC;
 828                 priv->features |= FEATURE_BLOCK_BUFFER;
 829                 /* fall through */
 830         case PCI_DEVICE_ID_INTEL_82801CA_3:
 831         case PCI_DEVICE_ID_INTEL_82801BA_2:
 832         case PCI_DEVICE_ID_INTEL_82801AB_3:
 833         case PCI_DEVICE_ID_INTEL_82801AA_3:
 834                 break;
 835         }
 836
 837         /* Disable features on user request */
 838         for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
 839                 if (priv->features & disable_features & (1 << i))
 840                         dev_notice(&dev->dev, "%s disabled by user\n",
 841                                    i801_feature_names[i]);
 842         }
 843         priv->features &= ~disable_features;
 844
 845         err = pci_enable_device(dev);
 846         if (err) {
 847                 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
 848                         err);
 849                 goto exit;
 850         }
 851
 852         /* Determine the address of the SMBus area */
 853         priv->smba = pci_resource_start(dev, SMBBAR);
 854         if (!priv->smba) {
 855                 dev_err(&dev->dev, "SMBus base address uninitialized, "
 856                         "upgrade BIOS\n");
 857                 err = -ENODEV;
 858                 goto exit;
 859         }
 860
 861         err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
 862         if (err) {
 863                 err = -ENODEV;
 864                 goto exit;
 865         }
 866
 867         err = pci_request_region(dev, SMBBAR, i801_driver.name);
 868         if (err) {
 869                 dev_err(&dev->dev, "Failed to request SMBus region "
 870                         "0x%lx-0x%Lx\n", priv->smba,
 871                         (unsigned long long)pci_resource_end(dev, SMBBAR));
 872                 goto exit;
 873         }
 874
 875         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
 876         priv->original_hstcfg = temp;
 877         temp &= ~SMBHSTCFG_I2C_EN;      /* SMBus timing */
 878         if (!(temp & SMBHSTCFG_HST_EN)) {
 879                 dev_info(&dev->dev, "Enabling SMBus device\n");
 880                 temp |= SMBHSTCFG_HST_EN;
 881         }
 882         pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
 883
 884         if (temp & SMBHSTCFG_SMB_SMI_EN)
 885                 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
 886         else
 887                 dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n");
 888
 889         /* Clear special mode bits */
 890         if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
 891                 outb_p(inb_p(SMBAUXCTL(priv)) &
 892                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
 893
 894         /* set up the sysfs linkage to our parent device */
 895         priv->adapter.dev.parent = &dev->dev;
 896
 897         /* Retry up to 3 times on lost arbitration */
 898         priv->adapter.retries = 3;
 899
 900         snprintf(priv->adapter.name, sizeof(priv->adapter.name),
 901                 "SMBus I801 adapter at %04lx", priv->smba);
 902         err = i2c_add_adapter(&priv->adapter);
 903         if (err) {
 904                 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
 905                 goto exit_release;
 906         }
 907
 908         i801_probe_optional_slaves(priv);
 909
 910         pci_set_drvdata(dev, priv);
 911         return 0;
 912
 913 exit_release:
 914         pci_release_region(dev, SMBBAR);
 915 exit:
 916         kfree(priv);
 917         return err;
 918 }
 919
 920 static void __devexit i801_remove(struct pci_dev *dev)
 921 {
 922         struct i801_priv *priv = pci_get_drvdata(dev);
 923
 924         i2c_del_adapter(&priv->adapter);
 925         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
 926         pci_release_region(dev, SMBBAR);
 927         pci_set_drvdata(dev, NULL);
 928         kfree(priv);
 929         /*
 930          * do not call pci_disable_device(dev) since it can cause hard hangs on
 931          * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
 932          */
 933 }
 934
 935 #ifdef CONFIG_PM
 936 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
 937 {
 938         struct i801_priv *priv = pci_get_drvdata(dev);
 939
 940         pci_save_state(dev);
 941         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
 942         pci_set_power_state(dev, pci_choose_state(dev, mesg));
 943         return 0;
 944 }
 945
 946 static int i801_resume(struct pci_dev *dev)
 947 {
 948         pci_set_power_state(dev, PCI_D0);
 949         pci_restore_state(dev);
 950         return pci_enable_device(dev);
 951 }
 952 #else
 953 #define i801_suspend NULL
 954 #define i801_resume NULL
 955 #endif
 956
 957 static struct pci_driver i801_driver = {
 958         .name           = "i801_smbus",
 959         .id_table       = i801_ids,
 960         .probe          = i801_probe,
 961         .remove         = __devexit_p(i801_remove),
 962         .suspend        = i801_suspend,
 963         .resume         = i801_resume,
 964 };
 965
 966 static int __init i2c_i801_init(void)
 967 {
 968         if (dmi_name_in_vendors("FUJITSU"))
 969                 input_apanel_init();
 970         return pci_register_driver(&i801_driver);
 971 }
 972
 973 static void __exit i2c_i801_exit(void)
 974 {
 975         pci_unregister_driver(&i801_driver);
 976 }
 977
 978 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, "
 979               "Jean Delvare <khali@linux-fr.org>");
 980 MODULE_DESCRIPTION("I801 SMBus driver");
 981 MODULE_LICENSE("GPL");
 982
 983 module_init(i2c_i801_init);
 984 module_exit(i2c_i801_exit);