drivers/i2c/busses/i2c-i801.c

   1 /*
   2     Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
   3     Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
   4     <mdsxyz123@yahoo.com>
   5     Copyright (C) 2007, 2008   Jean Delvare <khali@linux-fr.org>
   6     Copyright (C) 2010         Intel Corporation,
   7                                David Woodhouse <dwmw2@infradead.org>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18
  19     You should have received a copy of the GNU General Public License
  20     along with this program; if not, write to the Free Software
  21     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22 */
  23
  24 /*
  25   Supports the following Intel I/O Controller Hubs (ICH):
  26
  27                                   I/O                     Block   I2C
  28                                   region  SMBus   Block   proc.   block
  29   Chip name             PCI ID    size    PEC     buffer  call    read
  30   ----------------------------------------------------------------------
  31   82801AA  (ICH)        0x2413     16      no      no      no      no
  32   82801AB  (ICH0)       0x2423     16      no      no      no      no
  33   82801BA  (ICH2)       0x2443     16      no      no      no      no
  34   82801CA  (ICH3)       0x2483     32     soft     no      no      no
  35   82801DB  (ICH4)       0x24c3     32     hard     yes     no      no
  36   82801E   (ICH5)       0x24d3     32     hard     yes     yes     yes
  37   6300ESB               0x25a4     32     hard     yes     yes     yes
  38   82801F   (ICH6)       0x266a     32     hard     yes     yes     yes
  39   6310ESB/6320ESB       0x269b     32     hard     yes     yes     yes
  40   82801G   (ICH7)       0x27da     32     hard     yes     yes     yes
  41   82801H   (ICH8)       0x283e     32     hard     yes     yes     yes
  42   82801I   (ICH9)       0x2930     32     hard     yes     yes     yes
  43   EP80579 (Tolapai)     0x5032     32     hard     yes     yes     yes
  44   ICH10                 0x3a30     32     hard     yes     yes     yes
  45   ICH10                 0x3a60     32     hard     yes     yes     yes
  46   5/3400 Series (PCH)   0x3b30     32     hard     yes     yes     yes
  47   6 Series (PCH)        0x1c22     32     hard     yes     yes     yes
  48   Patsburg (PCH)        0x1d22     32     hard     yes     yes     yes
  49   Patsburg (PCH) IDF    0x1d70     32     hard     yes     yes     yes
  50   Patsburg (PCH) IDF    0x1d71     32     hard     yes     yes     yes
  51   Patsburg (PCH) IDF    0x1d72     32     hard     yes     yes     yes
  52   DH89xxCC (PCH)        0x2330     32     hard     yes     yes     yes
  53   Panther Point (PCH)   0x1e22     32     hard     yes     yes     yes
  54   Lynx Point (PCH)      0x8c22     32     hard     yes     yes     yes
  55   Lynx Point-LP (PCH)   0x9c22     32     hard     yes     yes     yes
  56   Avoton (SOC)          0x1f3c     32     hard     yes     yes     yes
  57   Wellsburg (PCH)       0x8d22     32     hard     yes     yes     yes
  58   Wellsburg (PCH) MS    0x8d7d     32     hard     yes     yes     yes
  59   Wellsburg (PCH) MS    0x8d7e     32     hard     yes     yes     yes
  60   Wellsburg (PCH) MS    0x8d7f     32     hard     yes     yes     yes
  61   Coleto Creek (PCH)    0x23b0     32     hard     yes     yes     yes
  62   Wildcat Point-LP (PCH)   0x9ca2     32     hard     yes     yes     yes
  63   BayTrail (SOC)        0x0f12     32     hard     yes     yes     yes
  64
  65   Features supported by this driver:
  66   Software PEC                     no
  67   Hardware PEC                     yes
  68   Block buffer                     yes
  69   Block process call transaction   no
  70   I2C block read transaction       yes  (doesn't use the block buffer)
  71   Slave mode                       no
  72
  73   See the file Documentation/i2c/busses/i2c-i801 for details.
  74 */
  75
  76 #include <linux/module.h>
  77 #include <linux/pci.h>
  78 #include <linux/kernel.h>
  79 #include <linux/stddef.h>
  80 #include <linux/delay.h>
  81 #include <linux/ioport.h>
  82 #include <linux/init.h>
  83 #include <linux/i2c.h>
  84 #include <linux/acpi.h>
  85 #include <linux/io.h>
  86 #include <linux/dmi.h>
  87 #include <linux/slab.h>
  88
  89 /* I801 SMBus address offsets */
  90 #define SMBHSTSTS(p)    (0 + (p)->smba)
  91 #define SMBHSTCNT(p)    (2 + (p)->smba)
  92 #define SMBHSTCMD(p)    (3 + (p)->smba)
  93 #define SMBHSTADD(p)    (4 + (p)->smba)
  94 #define SMBHSTDAT0(p)   (5 + (p)->smba)
  95 #define SMBHSTDAT1(p)   (6 + (p)->smba)
  96 #define SMBBLKDAT(p)    (7 + (p)->smba)
  97 #define SMBPEC(p)       (8 + (p)->smba)         /* ICH3 and later */
  98 #define SMBAUXSTS(p)    (12 + (p)->smba)        /* ICH4 and later */
  99 #define SMBAUXCTL(p)    (13 + (p)->smba)        /* ICH4 and later */
 100
 101 /* PCI Address Constants */
 102 #define SMBBAR          4
 103 #define SMBHSTCFG       0x040
 104
 105 /* Host configuration bits for SMBHSTCFG */
 106 #define SMBHSTCFG_HST_EN        1
 107 #define SMBHSTCFG_SMB_SMI_EN    2
 108 #define SMBHSTCFG_I2C_EN        4
 109
 110 /* Auxiliary control register bits, ICH4+ only */
 111 #define SMBAUXCTL_CRC           1
 112 #define SMBAUXCTL_E32B          2
 113
 114 /* kill bit for SMBHSTCNT */
 115 #define SMBHSTCNT_KILL          2
 116
 117 /* Other settings */
 118 #define MAX_TIMEOUT             100
 119 #define ENABLE_INT9             0       /* set to 0x01 to enable - untested */
 120
 121 /* I801 command constants */
 122 #define I801_QUICK              0x00
 123 #define I801_BYTE               0x04
 124 #define I801_BYTE_DATA          0x08
 125 #define I801_WORD_DATA          0x0C
 126 #define I801_PROC_CALL          0x10    /* unimplemented */
 127 #define I801_BLOCK_DATA         0x14
 128 #define I801_I2C_BLOCK_DATA     0x18    /* ICH5 and later */
 129 #define I801_BLOCK_LAST         0x34
 130 #define I801_I2C_BLOCK_LAST     0x38    /* ICH5 and later */
 131 #define I801_START              0x40
 132 #define I801_PEC_EN             0x80    /* ICH3 and later */
 133
 134 /* I801 Hosts Status register bits */
 135 #define SMBHSTSTS_BYTE_DONE     0x80
 136 #define SMBHSTSTS_INUSE_STS     0x40
 137 #define SMBHSTSTS_SMBALERT_STS  0x20
 138 #define SMBHSTSTS_FAILED        0x10
 139 #define SMBHSTSTS_BUS_ERR       0x08
 140 #define SMBHSTSTS_DEV_ERR       0x04
 141 #define SMBHSTSTS_INTR          0x02
 142 #define SMBHSTSTS_HOST_BUSY     0x01
 143
 144 #define STATUS_FLAGS            (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_FAILED | \
 145                                  SMBHSTSTS_BUS_ERR | SMBHSTSTS_DEV_ERR | \
 146                                  SMBHSTSTS_INTR)
 147
 148 /* Older devices have their ID defined in <linux/pci_ids.h> */
 149 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS      0x0f12
 150 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS   0x1c22
 151 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS      0x1d22
 152 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
 153 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
 154 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
 155 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
 156 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS  0x1e22
 157 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS        0x1f3c
 158 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS      0x2330
 159 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS   0x23b0
 160 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
 161 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS     0x8c22
 162 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS     0x8d22
 163 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d
 164 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e
 165 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f
 166 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS  0x9c22
 167 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS       0x9ca2
 168
 169 struct i801_priv {
 170         struct i2c_adapter adapter;
 171         unsigned long smba;
 172         unsigned char original_hstcfg;
 173         struct pci_dev *pci_dev;
 174         unsigned int features;
 175 };
 176
 177 static struct pci_driver i801_driver;
 178
 179 #define FEATURE_SMBUS_PEC       (1 << 0)
 180 #define FEATURE_BLOCK_BUFFER    (1 << 1)
 181 #define FEATURE_BLOCK_PROC      (1 << 2)
 182 #define FEATURE_I2C_BLOCK_READ  (1 << 3)
 183 /* Not really a feature, but it's convenient to handle it as such */
 184 #define FEATURE_IDF             (1 << 15)
 185
 186 static const char *i801_feature_names[] = {
 187         "SMBus PEC",
 188         "Block buffer",
 189         "Block process call",
 190         "I2C block read",
 191 };
 192
 193 static unsigned int disable_features;
 194 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
 195 MODULE_PARM_DESC(disable_features, "Disable selected driver features");
 196
 197 /* Make sure the SMBus host is ready to start transmitting.
 198    Return 0 if it is, -EBUSY if it is not. */
 199 static int i801_check_pre(struct i801_priv *priv)
 200 {
 201         int status;
 202
 203         status = inb_p(SMBHSTSTS(priv));
 204         if (status & SMBHSTSTS_HOST_BUSY) {
 205                 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
 206                 return -EBUSY;
 207         }
 208
 209         status &= STATUS_FLAGS;
 210         if (status) {
 211                 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
 212                         status);
 213                 outb_p(status, SMBHSTSTS(priv));
 214                 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
 215                 if (status) {
 216                         dev_err(&priv->pci_dev->dev,
 217                                 "Failed clearing status flags (%02x)\n",
 218                                 status);
 219                         return -EBUSY;
 220                 }
 221         }
 222
 223         return 0;
 224 }
 225
 226 /* Convert the status register to an error code, and clear it. */
 227 static int i801_check_post(struct i801_priv *priv, int status, int timeout)
 228 {
 229         int result = 0;
 230
 231         /* If the SMBus is still busy, we give up */
 232         if (timeout) {
 233                 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
 234                 /* try to stop the current command */
 235                 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
 236                 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
 237                        SMBHSTCNT(priv));
 238                 msleep(1);
 239                 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
 240                        SMBHSTCNT(priv));
 241
 242                 /* Check if it worked */
 243                 status = inb_p(SMBHSTSTS(priv));
 244                 if ((status & SMBHSTSTS_HOST_BUSY) ||
 245                     !(status & SMBHSTSTS_FAILED))
 246                         dev_err(&priv->pci_dev->dev,
 247                                 "Failed terminating the transaction\n");
 248                 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
 249                 return -ETIMEDOUT;
 250         }
 251
 252         if (status & SMBHSTSTS_FAILED) {
 253                 result = -EIO;
 254                 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
 255         }
 256         if (status & SMBHSTSTS_DEV_ERR) {
 257                 result = -ENXIO;
 258                 dev_dbg(&priv->pci_dev->dev, "No response\n");
 259         }
 260         if (status & SMBHSTSTS_BUS_ERR) {
 261                 result = -EAGAIN;
 262                 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
 263         }
 264
 265         if (result) {
 266                 /* Clear error flags */
 267                 outb_p(status & STATUS_FLAGS, SMBHSTSTS(priv));
 268                 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
 269                 if (status) {
 270                         dev_warn(&priv->pci_dev->dev, "Failed clearing status "
 271                                  "flags at end of transaction (%02x)\n",
 272                                  status);
 273                 }
 274         }
 275
 276         return result;
 277 }
 278
 279 static int i801_transaction(struct i801_priv *priv, int xact)
 280 {
 281         int status;
 282         int result;
 283         int timeout = 0;
 284
 285         result = i801_check_pre(priv);
 286         if (result < 0)
 287                 return result;
 288
 289         /* the current contents of SMBHSTCNT can be overwritten, since PEC,
 290          * INTREN, SMBSCMD are passed in xact */
 291         outb_p(xact | I801_START, SMBHSTCNT(priv));
 292
 293         /* We will always wait for a fraction of a second! */
 294         do {
 295                 msleep(1);
 296                 status = inb_p(SMBHSTSTS(priv));
 297         } while ((status & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_TIMEOUT));
 298
 299         result = i801_check_post(priv, status, timeout > MAX_TIMEOUT);
 300         if (result < 0)
 301                 return result;
 302
 303         outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 304         return 0;
 305 }
 306
 307 /* wait for INTR bit as advised by Intel */
 308 static void i801_wait_hwpec(struct i801_priv *priv)
 309 {
 310         int timeout = 0;
 311         int status;
 312
 313         do {
 314                 msleep(1);
 315                 status = inb_p(SMBHSTSTS(priv));
 316         } while ((!(status & SMBHSTSTS_INTR))
 317                  && (timeout++ < MAX_TIMEOUT));
 318
 319         if (timeout > MAX_TIMEOUT)
 320                 dev_dbg(&priv->pci_dev->dev, "PEC Timeout!\n");
 321
 322         outb_p(status, SMBHSTSTS(priv));
 323 }
 324
 325 static int i801_block_transaction_by_block(struct i801_priv *priv,
 326                                            union i2c_smbus_data *data,
 327                                            char read_write, int hwpec)
 328 {
 329         int i, len;
 330         int status;
 331
 332         inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
 333
 334         /* Use 32-byte buffer to process this transaction */
 335         if (read_write == I2C_SMBUS_WRITE) {
 336                 len = data->block[0];
 337                 outb_p(len, SMBHSTDAT0(priv));
 338                 for (i = 0; i < len; i++)
 339                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 340         }
 341
 342         status = i801_transaction(priv, I801_BLOCK_DATA | ENABLE_INT9 |
 343                                   I801_PEC_EN * hwpec);
 344         if (status)
 345                 return status;
 346
 347         if (read_write == I2C_SMBUS_READ) {
 348                 len = inb_p(SMBHSTDAT0(priv));
 349                 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
 350                         return -EPROTO;
 351
 352                 data->block[0] = len;
 353                 for (i = 0; i < len; i++)
 354                         data->block[i + 1] = inb_p(SMBBLKDAT(priv));
 355         }
 356         return 0;
 357 }
 358
 359 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
 360                                                union i2c_smbus_data *data,
 361                                                char read_write, int command,
 362                                                int hwpec)
 363 {
 364         int i, len;
 365         int smbcmd;
 366         int status;
 367         int result;
 368         int timeout;
 369
 370         result = i801_check_pre(priv);
 371         if (result < 0)
 372                 return result;
 373
 374         len = data->block[0];
 375
 376         if (read_write == I2C_SMBUS_WRITE) {
 377                 outb_p(len, SMBHSTDAT0(priv));
 378                 outb_p(data->block[1], SMBBLKDAT(priv));
 379         }
 380
 381         for (i = 1; i <= len; i++) {
 382                 if (i == len && read_write == I2C_SMBUS_READ) {
 383                         if (command == I2C_SMBUS_I2C_BLOCK_DATA)
 384                                 smbcmd = I801_I2C_BLOCK_LAST;
 385                         else
 386                                 smbcmd = I801_BLOCK_LAST;
 387                 } else {
 388                         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 389                          && read_write == I2C_SMBUS_READ)
 390                                 smbcmd = I801_I2C_BLOCK_DATA;
 391                         else
 392                                 smbcmd = I801_BLOCK_DATA;
 393                 }
 394                 outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT(priv));
 395
 396                 if (i == 1)
 397                         outb_p(inb(SMBHSTCNT(priv)) | I801_START,
 398                                SMBHSTCNT(priv));
 399
 400                 /* We will always wait for a fraction of a second! */
 401                 timeout = 0;
 402                 do {
 403                         msleep(1);
 404                         status = inb_p(SMBHSTSTS(priv));
 405                 } while ((!(status & SMBHSTSTS_BYTE_DONE))
 406                          && (timeout++ < MAX_TIMEOUT));
 407
 408                 result = i801_check_post(priv, status, timeout > MAX_TIMEOUT);
 409                 if (result < 0)
 410                         return result;
 411
 412                 if (i == 1 && read_write == I2C_SMBUS_READ
 413                  && command != I2C_SMBUS_I2C_BLOCK_DATA) {
 414                         len = inb_p(SMBHSTDAT0(priv));
 415                         if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
 416                                 dev_err(&priv->pci_dev->dev,
 417                                         "Illegal SMBus block read size %d\n",
 418                                         len);
 419                                 /* Recover */
 420                                 while (inb_p(SMBHSTSTS(priv)) &
 421                                        SMBHSTSTS_HOST_BUSY)
 422                                         outb_p(SMBHSTSTS_BYTE_DONE,
 423                                                SMBHSTSTS(priv));
 424                                 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 425                                 return -EPROTO;
 426                         }
 427                         data->block[0] = len;
 428                 }
 429
 430                 /* Retrieve/store value in SMBBLKDAT */
 431                 if (read_write == I2C_SMBUS_READ)
 432                         data->block[i] = inb_p(SMBBLKDAT(priv));
 433                 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
 434                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 435
 436                 /* signals SMBBLKDAT ready */
 437                 outb_p(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR, SMBHSTSTS(priv));
 438         }
 439
 440         return 0;
 441 }
 442
 443 static int i801_set_block_buffer_mode(struct i801_priv *priv)
 444 {
 445         outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
 446         if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
 447                 return -EIO;
 448         return 0;
 449 }
 450
 451 /* Block transaction function */
 452 static int i801_block_transaction(struct i801_priv *priv,
 453                                   union i2c_smbus_data *data, char read_write,
 454                                   int command, int hwpec)
 455 {
 456         int result = 0;
 457         unsigned char hostc;
 458
 459         if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
 460                 if (read_write == I2C_SMBUS_WRITE) {
 461                         /* set I2C_EN bit in configuration register */
 462                         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
 463                         pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
 464                                               hostc | SMBHSTCFG_I2C_EN);
 465                 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
 466                         dev_err(&priv->pci_dev->dev,
 467                                 "I2C block read is unsupported!\n");
 468                         return -EOPNOTSUPP;
 469                 }
 470         }
 471
 472         if (read_write == I2C_SMBUS_WRITE
 473          || command == I2C_SMBUS_I2C_BLOCK_DATA) {
 474                 if (data->block[0] < 1)
 475                         data->block[0] = 1;
 476                 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
 477                         data->block[0] = I2C_SMBUS_BLOCK_MAX;
 478         } else {
 479                 data->block[0] = 32;    /* max for SMBus block reads */
 480         }
 481
 482         /* Experience has shown that the block buffer can only be used for
 483            SMBus (not I2C) block transactions, even though the datasheet
 484            doesn't mention this limitation. */
 485         if ((priv->features & FEATURE_BLOCK_BUFFER)
 486          && command != I2C_SMBUS_I2C_BLOCK_DATA
 487          && i801_set_block_buffer_mode(priv) == 0)
 488                 result = i801_block_transaction_by_block(priv, data,
 489                                                          read_write, hwpec);
 490         else
 491                 result = i801_block_transaction_byte_by_byte(priv, data,
 492                                                              read_write,
 493                                                              command, hwpec);
 494
 495         if (result == 0 && hwpec)
 496                 i801_wait_hwpec(priv);
 497
 498         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 499          && read_write == I2C_SMBUS_WRITE) {
 500                 /* restore saved configuration register value */
 501                 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
 502         }
 503         return result;
 504 }
 505
 506 /* Return negative errno on error. */
 507 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
 508                        unsigned short flags, char read_write, u8 command,
 509                        int size, union i2c_smbus_data *data)
 510 {
 511         int hwpec;
 512         int block = 0;
 513         int ret, xact = 0;
 514         struct i801_priv *priv = i2c_get_adapdata(adap);
 515
 516         hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
 517                 && size != I2C_SMBUS_QUICK
 518                 && size != I2C_SMBUS_I2C_BLOCK_DATA;
 519
 520         switch (size) {
 521         case I2C_SMBUS_QUICK:
 522                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 523                        SMBHSTADD(priv));
 524                 xact = I801_QUICK;
 525                 break;
 526         case I2C_SMBUS_BYTE:
 527                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 528                        SMBHSTADD(priv));
 529                 if (read_write == I2C_SMBUS_WRITE)
 530                         outb_p(command, SMBHSTCMD(priv));
 531                 xact = I801_BYTE;
 532                 break;
 533         case I2C_SMBUS_BYTE_DATA:
 534                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 535                        SMBHSTADD(priv));
 536                 outb_p(command, SMBHSTCMD(priv));
 537                 if (read_write == I2C_SMBUS_WRITE)
 538                         outb_p(data->byte, SMBHSTDAT0(priv));
 539                 xact = I801_BYTE_DATA;
 540                 break;
 541         case I2C_SMBUS_WORD_DATA:
 542                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 543                        SMBHSTADD(priv));
 544                 outb_p(command, SMBHSTCMD(priv));
 545                 if (read_write == I2C_SMBUS_WRITE) {
 546                         outb_p(data->word & 0xff, SMBHSTDAT0(priv));
 547                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
 548                 }
 549                 xact = I801_WORD_DATA;
 550                 break;
 551         case I2C_SMBUS_BLOCK_DATA:
 552                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 553                        SMBHSTADD(priv));
 554                 outb_p(command, SMBHSTCMD(priv));
 555                 block = 1;
 556                 break;
 557         case I2C_SMBUS_I2C_BLOCK_DATA:
 558                 /* NB: page 240 of ICH5 datasheet shows that the R/#W
 559                  * bit should be cleared here, even when reading */
 560                 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
 561                 if (read_write == I2C_SMBUS_READ) {
 562                         /* NB: page 240 of ICH5 datasheet also shows
 563                          * that DATA1 is the cmd field when reading */
 564                         outb_p(command, SMBHSTDAT1(priv));
 565                 } else
 566                         outb_p(command, SMBHSTCMD(priv));
 567                 block = 1;
 568                 break;
 569         default:
 570                 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
 571                         size);
 572                 return -EOPNOTSUPP;
 573         }
 574
 575         if (hwpec)      /* enable/disable hardware PEC */
 576                 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
 577         else
 578                 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
 579                        SMBAUXCTL(priv));
 580
 581         if (block)
 582                 ret = i801_block_transaction(priv, data, read_write, size,
 583                                              hwpec);
 584         else
 585                 ret = i801_transaction(priv, xact | ENABLE_INT9);
 586
 587         /* Some BIOSes don't like it when PEC is enabled at reboot or resume
 588            time, so we forcibly disable it after every transaction. Turn off
 589            E32B for the same reason. */
 590         if (hwpec || block)
 591                 outb_p(inb_p(SMBAUXCTL(priv)) &
 592                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
 593
 594         if (block)
 595                 return ret;
 596         if (ret)
 597                 return ret;
 598         if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
 599                 return 0;
 600
 601         switch (xact & 0x7f) {
 602         case I801_BYTE: /* Result put in SMBHSTDAT0 */
 603         case I801_BYTE_DATA:
 604                 data->byte = inb_p(SMBHSTDAT0(priv));
 605                 break;
 606         case I801_WORD_DATA:
 607                 data->word = inb_p(SMBHSTDAT0(priv)) +
 608                              (inb_p(SMBHSTDAT1(priv)) << 8);
 609                 break;
 610         }
 611         return 0;
 612 }
 613
 614
 615 static u32 i801_func(struct i2c_adapter *adapter)
 616 {
 617         struct i801_priv *priv = i2c_get_adapdata(adapter);
 618
 619         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 620                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 621                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
 622                ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
 623                ((priv->features & FEATURE_I2C_BLOCK_READ) ?
 624                 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
 625 }
 626
 627 static const struct i2c_algorithm smbus_algorithm = {
 628         .smbus_xfer     = i801_access,
 629         .functionality  = i801_func,
 630 };
 631
 632 static const struct pci_device_id i801_ids[] = {
 633         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
 634         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
 635         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
 636         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
 637         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
 638         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
 639         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
 640         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
 641         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
 642         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
 643         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
 644         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
 645         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
 646         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
 647         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
 648         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
 649         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
 650         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
 651         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
 652         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
 653         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
 654         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
 655         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
 656         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
 657         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
 658         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
 659         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
 660         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
 661         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
 662         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
 663         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
 664         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
 665         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
 666         { 0, }
 667 };
 668
 669 MODULE_DEVICE_TABLE(pci, i801_ids);
 670
 671 #if defined CONFIG_X86 && defined CONFIG_DMI
 672 static unsigned char apanel_addr;
 673
 674 /* Scan the system ROM for the signature "FJKEYINF" */
 675 static __init const void __iomem *bios_signature(const void __iomem *bios)
 676 {
 677         ssize_t offset;
 678         const unsigned char signature[] = "FJKEYINF";
 679
 680         for (offset = 0; offset < 0x10000; offset += 0x10) {
 681                 if (check_signature(bios + offset, signature,
 682                                     sizeof(signature)-1))
 683                         return bios + offset;
 684         }
 685         return NULL;
 686 }
 687
 688 static void __init input_apanel_init(void)
 689 {
 690         void __iomem *bios;
 691         const void __iomem *p;
 692
 693         bios = ioremap(0xF0000, 0x10000); /* Can't fail */
 694         p = bios_signature(bios);
 695         if (p) {
 696                 /* just use the first address */
 697                 apanel_addr = readb(p + 8 + 3) >> 1;
 698         }
 699         iounmap(bios);
 700 }
 701
 702 struct dmi_onboard_device_info {
 703         const char *name;
 704         u8 type;
 705         unsigned short i2c_addr;
 706         const char *i2c_type;
 707 };
 708
 709 static struct dmi_onboard_device_info __devinitdata dmi_devices[] = {
 710         { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
 711         { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
 712         { "Hades",  DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
 713 };
 714
 715 static void __devinit dmi_check_onboard_device(u8 type, const char *name,
 716                                                struct i2c_adapter *adap)
 717 {
 718         int i;
 719         struct i2c_board_info info;
 720
 721         for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
 722                 /* & ~0x80, ignore enabled/disabled bit */
 723                 if ((type & ~0x80) != dmi_devices[i].type)
 724                         continue;
 725                 if (strcasecmp(name, dmi_devices[i].name))
 726                         continue;
 727
 728                 memset(&info, 0, sizeof(struct i2c_board_info));
 729                 info.addr = dmi_devices[i].i2c_addr;
 730                 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
 731                 i2c_new_device(adap, &info);
 732                 break;
 733         }
 734 }
 735
 736 /* We use our own function to check for onboard devices instead of
 737    dmi_find_device() as some buggy BIOS's have the devices we are interested
 738    in marked as disabled */
 739 static void __devinit dmi_check_onboard_devices(const struct dmi_header *dm,
 740                                                 void *adap)
 741 {
 742         int i, count;
 743
 744         if (dm->type != 10)
 745                 return;
 746
 747         count = (dm->length - sizeof(struct dmi_header)) / 2;
 748         for (i = 0; i < count; i++) {
 749                 const u8 *d = (char *)(dm + 1) + (i * 2);
 750                 const char *name = ((char *) dm) + dm->length;
 751                 u8 type = d[0];
 752                 u8 s = d[1];
 753
 754                 if (!s)
 755                         continue;
 756                 s--;
 757                 while (s > 0 && name[0]) {
 758                         name += strlen(name) + 1;
 759                         s--;
 760                 }
 761                 if (name[0] == 0) /* Bogus string reference */
 762                         continue;
 763
 764                 dmi_check_onboard_device(type, name, adap);
 765         }
 766 }
 767
 768 /* Register optional slaves */
 769 static void __devinit i801_probe_optional_slaves(struct i801_priv *priv)
 770 {
 771         /* Only register slaves on main SMBus channel */
 772         if (priv->features & FEATURE_IDF)
 773                 return;
 774
 775         if (apanel_addr) {
 776                 struct i2c_board_info info;
 777
 778                 memset(&info, 0, sizeof(struct i2c_board_info));
 779                 info.addr = apanel_addr;
 780                 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
 781                 i2c_new_device(&priv->adapter, &info);
 782         }
 783
 784         if (dmi_name_in_vendors("FUJITSU"))
 785                 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
 786 }
 787 #else
 788 static void __init input_apanel_init(void) {}
 789 static void __devinit i801_probe_optional_slaves(struct i801_priv *priv) {}
 790 #endif  /* CONFIG_X86 && CONFIG_DMI */
 791
 792 static int __devinit i801_probe(struct pci_dev *dev,
 793                                 const struct pci_device_id *id)
 794 {
 795         unsigned char temp;
 796         int err, i;
 797         struct i801_priv *priv;
 798
 799         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 800         if (!priv)
 801                 return -ENOMEM;
 802
 803         i2c_set_adapdata(&priv->adapter, priv);
 804         priv->adapter.owner = THIS_MODULE;
 805         priv->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
 806         priv->adapter.algo = &smbus_algorithm;
 807
 808         priv->pci_dev = dev;
 809         switch (dev->device) {
 810         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
 811         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
 812         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
 813         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
 814         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
 815         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
 816                 priv->features |= FEATURE_IDF;
 817                 /* fall through */
 818         default:
 819                 priv->features |= FEATURE_I2C_BLOCK_READ;
 820                 /* fall through */
 821         case PCI_DEVICE_ID_INTEL_82801DB_3:
 822                 priv->features |= FEATURE_SMBUS_PEC;
 823                 priv->features |= FEATURE_BLOCK_BUFFER;
 824                 /* fall through */
 825         case PCI_DEVICE_ID_INTEL_82801CA_3:
 826         case PCI_DEVICE_ID_INTEL_82801BA_2:
 827         case PCI_DEVICE_ID_INTEL_82801AB_3:
 828         case PCI_DEVICE_ID_INTEL_82801AA_3:
 829                 break;
 830         }
 831
 832         /* Disable features on user request */
 833         for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
 834                 if (priv->features & disable_features & (1 << i))
 835                         dev_notice(&dev->dev, "%s disabled by user\n",
 836                                    i801_feature_names[i]);
 837         }
 838         priv->features &= ~disable_features;
 839
 840         err = pci_enable_device(dev);
 841         if (err) {
 842                 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
 843                         err);
 844                 goto exit;
 845         }
 846
 847         /* Determine the address of the SMBus area */
 848         priv->smba = pci_resource_start(dev, SMBBAR);
 849         if (!priv->smba) {
 850                 dev_err(&dev->dev, "SMBus base address uninitialized, "
 851                         "upgrade BIOS\n");
 852                 err = -ENODEV;
 853                 goto exit;
 854         }
 855
 856         err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
 857         if (err) {
 858                 err = -ENODEV;
 859                 goto exit;
 860         }
 861
 862         err = pci_request_region(dev, SMBBAR, i801_driver.name);
 863         if (err) {
 864                 dev_err(&dev->dev, "Failed to request SMBus region "
 865                         "0x%lx-0x%Lx\n", priv->smba,
 866                         (unsigned long long)pci_resource_end(dev, SMBBAR));
 867                 goto exit;
 868         }
 869
 870         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
 871         priv->original_hstcfg = temp;
 872         temp &= ~SMBHSTCFG_I2C_EN;      /* SMBus timing */
 873         if (!(temp & SMBHSTCFG_HST_EN)) {
 874                 dev_info(&dev->dev, "Enabling SMBus device\n");
 875                 temp |= SMBHSTCFG_HST_EN;
 876         }
 877         pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
 878
 879         if (temp & SMBHSTCFG_SMB_SMI_EN)
 880                 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
 881         else
 882                 dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n");
 883
 884         /* Clear special mode bits */
 885         if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
 886                 outb_p(inb_p(SMBAUXCTL(priv)) &
 887                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
 888
 889         /* set up the sysfs linkage to our parent device */
 890         priv->adapter.dev.parent = &dev->dev;
 891
 892         /* Retry up to 3 times on lost arbitration */
 893         priv->adapter.retries = 3;
 894
 895         snprintf(priv->adapter.name, sizeof(priv->adapter.name),
 896                 "SMBus I801 adapter at %04lx", priv->smba);
 897         err = i2c_add_adapter(&priv->adapter);
 898         if (err) {
 899                 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
 900                 goto exit_release;
 901         }
 902
 903         i801_probe_optional_slaves(priv);
 904
 905         pci_set_drvdata(dev, priv);
 906         return 0;
 907
 908 exit_release:
 909         pci_release_region(dev, SMBBAR);
 910 exit:
 911         kfree(priv);
 912         return err;
 913 }
 914
 915 static void __devexit i801_remove(struct pci_dev *dev)
 916 {
 917         struct i801_priv *priv = pci_get_drvdata(dev);
 918
 919         i2c_del_adapter(&priv->adapter);
 920         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
 921         pci_release_region(dev, SMBBAR);
 922         pci_set_drvdata(dev, NULL);
 923         kfree(priv);
 924         /*
 925          * do not call pci_disable_device(dev) since it can cause hard hangs on
 926          * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
 927          */
 928 }
 929
 930 #ifdef CONFIG_PM
 931 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
 932 {
 933         struct i801_priv *priv = pci_get_drvdata(dev);
 934
 935         pci_save_state(dev);
 936         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
 937         pci_set_power_state(dev, pci_choose_state(dev, mesg));
 938         return 0;
 939 }
 940
 941 static int i801_resume(struct pci_dev *dev)
 942 {
 943         pci_set_power_state(dev, PCI_D0);
 944         pci_restore_state(dev);
 945         return pci_enable_device(dev);
 946 }
 947 #else
 948 #define i801_suspend NULL
 949 #define i801_resume NULL
 950 #endif
 951
 952 static struct pci_driver i801_driver = {
 953         .name           = "i801_smbus",
 954         .id_table       = i801_ids,
 955         .probe          = i801_probe,
 956         .remove         = __devexit_p(i801_remove),
 957         .suspend        = i801_suspend,
 958         .resume         = i801_resume,
 959 };
 960
 961 static int __init i2c_i801_init(void)
 962 {
 963         if (dmi_name_in_vendors("FUJITSU"))
 964                 input_apanel_init();
 965         return pci_register_driver(&i801_driver);
 966 }
 967
 968 static void __exit i2c_i801_exit(void)
 969 {
 970         pci_unregister_driver(&i801_driver);
 971 }
 972
 973 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, "
 974               "Jean Delvare <khali@linux-fr.org>");
 975 MODULE_DESCRIPTION("I801 SMBus driver");
 976 MODULE_LICENSE("GPL");
 977
 978 module_init(i2c_i801_init);
 979 module_exit(i2c_i801_exit);