drivers/i2c/busses/i2c-i801.c

   1 /*
   2     Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
   3     Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
   4     <mdsxyz123@yahoo.com>
   5     Copyright (C) 2007, 2008   Jean Delvare <khali@linux-fr.org>
   6     Copyright (C) 2010         Intel Corporation,
   7                                David Woodhouse <dwmw2@infradead.org>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18
  19     You should have received a copy of the GNU General Public License
  20     along with this program; if not, write to the Free Software
  21     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22 */
  23
  24 /*
  25   Supports the following Intel I/O Controller Hubs (ICH):
  26
  27                                   I/O                     Block   I2C
  28                                   region  SMBus   Block   proc.   block
  29   Chip name             PCI ID    size    PEC     buffer  call    read
  30   ----------------------------------------------------------------------
  31   82801AA  (ICH)        0x2413     16      no      no      no      no
  32   82801AB  (ICH0)       0x2423     16      no      no      no      no
  33   82801BA  (ICH2)       0x2443     16      no      no      no      no
  34   82801CA  (ICH3)       0x2483     32     soft     no      no      no
  35   82801DB  (ICH4)       0x24c3     32     hard     yes     no      no
  36   82801E   (ICH5)       0x24d3     32     hard     yes     yes     yes
  37   6300ESB               0x25a4     32     hard     yes     yes     yes
  38   82801F   (ICH6)       0x266a     32     hard     yes     yes     yes
  39   6310ESB/6320ESB       0x269b     32     hard     yes     yes     yes
  40   82801G   (ICH7)       0x27da     32     hard     yes     yes     yes
  41   82801H   (ICH8)       0x283e     32     hard     yes     yes     yes
  42   82801I   (ICH9)       0x2930     32     hard     yes     yes     yes
  43   EP80579 (Tolapai)     0x5032     32     hard     yes     yes     yes
  44   ICH10                 0x3a30     32     hard     yes     yes     yes
  45   ICH10                 0x3a60     32     hard     yes     yes     yes
  46   5/3400 Series (PCH)   0x3b30     32     hard     yes     yes     yes
  47   6 Series (PCH)        0x1c22     32     hard     yes     yes     yes
  48   Patsburg (PCH)        0x1d22     32     hard     yes     yes     yes
  49   Patsburg (PCH) IDF    0x1d70     32     hard     yes     yes     yes
  50   Patsburg (PCH) IDF    0x1d71     32     hard     yes     yes     yes
  51   Patsburg (PCH) IDF    0x1d72     32     hard     yes     yes     yes
  52   DH89xxCC (PCH)        0x2330     32     hard     yes     yes     yes
  53   Panther Point (PCH)   0x1e22     32     hard     yes     yes     yes
  54   Lynx Point (PCH)      0x8c22     32     hard     yes     yes     yes
  55   Lynx Point-LP (PCH)   0x9c22     32     hard     yes     yes     yes
  56   Avoton (SOC)          0x1f3c     32     hard     yes     yes     yes
  57   Wellsburg (PCH)       0x8d22     32     hard     yes     yes     yes
  58   Wellsburg (PCH) MS    0x8d7d     32     hard     yes     yes     yes
  59   Wellsburg (PCH) MS    0x8d7e     32     hard     yes     yes     yes
  60   Wellsburg (PCH) MS    0x8d7f     32     hard     yes     yes     yes
  61
  62   Features supported by this driver:
  63   Software PEC                     no
  64   Hardware PEC                     yes
  65   Block buffer                     yes
  66   Block process call transaction   no
  67   I2C block read transaction       yes  (doesn't use the block buffer)
  68   Slave mode                       no
  69
  70   See the file Documentation/i2c/busses/i2c-i801 for details.
  71 */
  72
  73 #include <linux/module.h>
  74 #include <linux/pci.h>
  75 #include <linux/kernel.h>
  76 #include <linux/stddef.h>
  77 #include <linux/delay.h>
  78 #include <linux/ioport.h>
  79 #include <linux/init.h>
  80 #include <linux/i2c.h>
  81 #include <linux/acpi.h>
  82 #include <linux/io.h>
  83 #include <linux/dmi.h>
  84 #include <linux/slab.h>
  85
  86 /* I801 SMBus address offsets */
  87 #define SMBHSTSTS(p)    (0 + (p)->smba)
  88 #define SMBHSTCNT(p)    (2 + (p)->smba)
  89 #define SMBHSTCMD(p)    (3 + (p)->smba)
  90 #define SMBHSTADD(p)    (4 + (p)->smba)
  91 #define SMBHSTDAT0(p)   (5 + (p)->smba)
  92 #define SMBHSTDAT1(p)   (6 + (p)->smba)
  93 #define SMBBLKDAT(p)    (7 + (p)->smba)
  94 #define SMBPEC(p)       (8 + (p)->smba)         /* ICH3 and later */
  95 #define SMBAUXSTS(p)    (12 + (p)->smba)        /* ICH4 and later */
  96 #define SMBAUXCTL(p)    (13 + (p)->smba)        /* ICH4 and later */
  97
  98 /* PCI Address Constants */
  99 #define SMBBAR          4
 100 #define SMBHSTCFG       0x040
 101
 102 /* Host configuration bits for SMBHSTCFG */
 103 #define SMBHSTCFG_HST_EN        1
 104 #define SMBHSTCFG_SMB_SMI_EN    2
 105 #define SMBHSTCFG_I2C_EN        4
 106
 107 /* Auxiliary control register bits, ICH4+ only */
 108 #define SMBAUXCTL_CRC           1
 109 #define SMBAUXCTL_E32B          2
 110
 111 /* kill bit for SMBHSTCNT */
 112 #define SMBHSTCNT_KILL          2
 113
 114 /* Other settings */
 115 #define MAX_TIMEOUT             100
 116 #define ENABLE_INT9             0       /* set to 0x01 to enable - untested */
 117
 118 /* I801 command constants */
 119 #define I801_QUICK              0x00
 120 #define I801_BYTE               0x04
 121 #define I801_BYTE_DATA          0x08
 122 #define I801_WORD_DATA          0x0C
 123 #define I801_PROC_CALL          0x10    /* unimplemented */
 124 #define I801_BLOCK_DATA         0x14
 125 #define I801_I2C_BLOCK_DATA     0x18    /* ICH5 and later */
 126 #define I801_BLOCK_LAST         0x34
 127 #define I801_I2C_BLOCK_LAST     0x38    /* ICH5 and later */
 128 #define I801_START              0x40
 129 #define I801_PEC_EN             0x80    /* ICH3 and later */
 130
 131 /* I801 Hosts Status register bits */
 132 #define SMBHSTSTS_BYTE_DONE     0x80
 133 #define SMBHSTSTS_INUSE_STS     0x40
 134 #define SMBHSTSTS_SMBALERT_STS  0x20
 135 #define SMBHSTSTS_FAILED        0x10
 136 #define SMBHSTSTS_BUS_ERR       0x08
 137 #define SMBHSTSTS_DEV_ERR       0x04
 138 #define SMBHSTSTS_INTR          0x02
 139 #define SMBHSTSTS_HOST_BUSY     0x01
 140
 141 #define STATUS_FLAGS            (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_FAILED | \
 142                                  SMBHSTSTS_BUS_ERR | SMBHSTSTS_DEV_ERR | \
 143                                  SMBHSTSTS_INTR)
 144
 145 /* Older devices have their ID defined in <linux/pci_ids.h> */
 146 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS   0x1c22
 147 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS      0x1d22
 148 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
 149 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
 150 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
 151 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
 152 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS  0x1e22
 153 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS        0x1f3c
 154 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS      0x2330
 155 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
 156 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS     0x8c22
 157 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS     0x8d22
 158 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d
 159 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e
 160 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f
 161 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS  0x9c22
 162
 163 struct i801_priv {
 164         struct i2c_adapter adapter;
 165         unsigned long smba;
 166         unsigned char original_hstcfg;
 167         struct pci_dev *pci_dev;
 168         unsigned int features;
 169 };
 170
 171 static struct pci_driver i801_driver;
 172
 173 #define FEATURE_SMBUS_PEC       (1 << 0)
 174 #define FEATURE_BLOCK_BUFFER    (1 << 1)
 175 #define FEATURE_BLOCK_PROC      (1 << 2)
 176 #define FEATURE_I2C_BLOCK_READ  (1 << 3)
 177 /* Not really a feature, but it's convenient to handle it as such */
 178 #define FEATURE_IDF             (1 << 15)
 179
 180 static const char *i801_feature_names[] = {
 181         "SMBus PEC",
 182         "Block buffer",
 183         "Block process call",
 184         "I2C block read",
 185 };
 186
 187 static unsigned int disable_features;
 188 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
 189 MODULE_PARM_DESC(disable_features, "Disable selected driver features");
 190
 191 /* Make sure the SMBus host is ready to start transmitting.
 192    Return 0 if it is, -EBUSY if it is not. */
 193 static int i801_check_pre(struct i801_priv *priv)
 194 {
 195         int status;
 196
 197         status = inb_p(SMBHSTSTS(priv));
 198         if (status & SMBHSTSTS_HOST_BUSY) {
 199                 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
 200                 return -EBUSY;
 201         }
 202
 203         status &= STATUS_FLAGS;
 204         if (status) {
 205                 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
 206                         status);
 207                 outb_p(status, SMBHSTSTS(priv));
 208                 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
 209                 if (status) {
 210                         dev_err(&priv->pci_dev->dev,
 211                                 "Failed clearing status flags (%02x)\n",
 212                                 status);
 213                         return -EBUSY;
 214                 }
 215         }
 216
 217         return 0;
 218 }
 219
 220 /* Convert the status register to an error code, and clear it. */
 221 static int i801_check_post(struct i801_priv *priv, int status, int timeout)
 222 {
 223         int result = 0;
 224
 225         /* If the SMBus is still busy, we give up */
 226         if (timeout) {
 227                 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
 228                 /* try to stop the current command */
 229                 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
 230                 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
 231                        SMBHSTCNT(priv));
 232                 msleep(1);
 233                 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
 234                        SMBHSTCNT(priv));
 235
 236                 /* Check if it worked */
 237                 status = inb_p(SMBHSTSTS(priv));
 238                 if ((status & SMBHSTSTS_HOST_BUSY) ||
 239                     !(status & SMBHSTSTS_FAILED))
 240                         dev_err(&priv->pci_dev->dev,
 241                                 "Failed terminating the transaction\n");
 242                 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
 243                 return -ETIMEDOUT;
 244         }
 245
 246         if (status & SMBHSTSTS_FAILED) {
 247                 result = -EIO;
 248                 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
 249         }
 250         if (status & SMBHSTSTS_DEV_ERR) {
 251                 result = -ENXIO;
 252                 dev_dbg(&priv->pci_dev->dev, "No response\n");
 253         }
 254         if (status & SMBHSTSTS_BUS_ERR) {
 255                 result = -EAGAIN;
 256                 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
 257         }
 258
 259         if (result) {
 260                 /* Clear error flags */
 261                 outb_p(status & STATUS_FLAGS, SMBHSTSTS(priv));
 262                 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
 263                 if (status) {
 264                         dev_warn(&priv->pci_dev->dev, "Failed clearing status "
 265                                  "flags at end of transaction (%02x)\n",
 266                                  status);
 267                 }
 268         }
 269
 270         return result;
 271 }
 272
 273 static int i801_transaction(struct i801_priv *priv, int xact)
 274 {
 275         int status;
 276         int result;
 277         int timeout = 0;
 278
 279         result = i801_check_pre(priv);
 280         if (result < 0)
 281                 return result;
 282
 283         /* the current contents of SMBHSTCNT can be overwritten, since PEC,
 284          * INTREN, SMBSCMD are passed in xact */
 285         outb_p(xact | I801_START, SMBHSTCNT(priv));
 286
 287         /* We will always wait for a fraction of a second! */
 288         do {
 289                 msleep(1);
 290                 status = inb_p(SMBHSTSTS(priv));
 291         } while ((status & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_TIMEOUT));
 292
 293         result = i801_check_post(priv, status, timeout > MAX_TIMEOUT);
 294         if (result < 0)
 295                 return result;
 296
 297         outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 298         return 0;
 299 }
 300
 301 /* wait for INTR bit as advised by Intel */
 302 static void i801_wait_hwpec(struct i801_priv *priv)
 303 {
 304         int timeout = 0;
 305         int status;
 306
 307         do {
 308                 msleep(1);
 309                 status = inb_p(SMBHSTSTS(priv));
 310         } while ((!(status & SMBHSTSTS_INTR))
 311                  && (timeout++ < MAX_TIMEOUT));
 312
 313         if (timeout > MAX_TIMEOUT)
 314                 dev_dbg(&priv->pci_dev->dev, "PEC Timeout!\n");
 315
 316         outb_p(status, SMBHSTSTS(priv));
 317 }
 318
 319 static int i801_block_transaction_by_block(struct i801_priv *priv,
 320                                            union i2c_smbus_data *data,
 321                                            char read_write, int hwpec)
 322 {
 323         int i, len;
 324         int status;
 325
 326         inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
 327
 328         /* Use 32-byte buffer to process this transaction */
 329         if (read_write == I2C_SMBUS_WRITE) {
 330                 len = data->block[0];
 331                 outb_p(len, SMBHSTDAT0(priv));
 332                 for (i = 0; i < len; i++)
 333                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 334         }
 335
 336         status = i801_transaction(priv, I801_BLOCK_DATA | ENABLE_INT9 |
 337                                   I801_PEC_EN * hwpec);
 338         if (status)
 339                 return status;
 340
 341         if (read_write == I2C_SMBUS_READ) {
 342                 len = inb_p(SMBHSTDAT0(priv));
 343                 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
 344                         return -EPROTO;
 345
 346                 data->block[0] = len;
 347                 for (i = 0; i < len; i++)
 348                         data->block[i + 1] = inb_p(SMBBLKDAT(priv));
 349         }
 350         return 0;
 351 }
 352
 353 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
 354                                                union i2c_smbus_data *data,
 355                                                char read_write, int command,
 356                                                int hwpec)
 357 {
 358         int i, len;
 359         int smbcmd;
 360         int status;
 361         int result;
 362         int timeout;
 363
 364         result = i801_check_pre(priv);
 365         if (result < 0)
 366                 return result;
 367
 368         len = data->block[0];
 369
 370         if (read_write == I2C_SMBUS_WRITE) {
 371                 outb_p(len, SMBHSTDAT0(priv));
 372                 outb_p(data->block[1], SMBBLKDAT(priv));
 373         }
 374
 375         for (i = 1; i <= len; i++) {
 376                 if (i == len && read_write == I2C_SMBUS_READ) {
 377                         if (command == I2C_SMBUS_I2C_BLOCK_DATA)
 378                                 smbcmd = I801_I2C_BLOCK_LAST;
 379                         else
 380                                 smbcmd = I801_BLOCK_LAST;
 381                 } else {
 382                         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 383                          && read_write == I2C_SMBUS_READ)
 384                                 smbcmd = I801_I2C_BLOCK_DATA;
 385                         else
 386                                 smbcmd = I801_BLOCK_DATA;
 387                 }
 388                 outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT(priv));
 389
 390                 if (i == 1)
 391                         outb_p(inb(SMBHSTCNT(priv)) | I801_START,
 392                                SMBHSTCNT(priv));
 393
 394                 /* We will always wait for a fraction of a second! */
 395                 timeout = 0;
 396                 do {
 397                         msleep(1);
 398                         status = inb_p(SMBHSTSTS(priv));
 399                 } while ((!(status & SMBHSTSTS_BYTE_DONE))
 400                          && (timeout++ < MAX_TIMEOUT));
 401
 402                 result = i801_check_post(priv, status, timeout > MAX_TIMEOUT);
 403                 if (result < 0)
 404                         return result;
 405
 406                 if (i == 1 && read_write == I2C_SMBUS_READ
 407                  && command != I2C_SMBUS_I2C_BLOCK_DATA) {
 408                         len = inb_p(SMBHSTDAT0(priv));
 409                         if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
 410                                 dev_err(&priv->pci_dev->dev,
 411                                         "Illegal SMBus block read size %d\n",
 412                                         len);
 413                                 /* Recover */
 414                                 while (inb_p(SMBHSTSTS(priv)) &
 415                                        SMBHSTSTS_HOST_BUSY)
 416                                         outb_p(SMBHSTSTS_BYTE_DONE,
 417                                                SMBHSTSTS(priv));
 418                                 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 419                                 return -EPROTO;
 420                         }
 421                         data->block[0] = len;
 422                 }
 423
 424                 /* Retrieve/store value in SMBBLKDAT */
 425                 if (read_write == I2C_SMBUS_READ)
 426                         data->block[i] = inb_p(SMBBLKDAT(priv));
 427                 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
 428                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 429
 430                 /* signals SMBBLKDAT ready */
 431                 outb_p(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR, SMBHSTSTS(priv));
 432         }
 433
 434         return 0;
 435 }
 436
 437 static int i801_set_block_buffer_mode(struct i801_priv *priv)
 438 {
 439         outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
 440         if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
 441                 return -EIO;
 442         return 0;
 443 }
 444
 445 /* Block transaction function */
 446 static int i801_block_transaction(struct i801_priv *priv,
 447                                   union i2c_smbus_data *data, char read_write,
 448                                   int command, int hwpec)
 449 {
 450         int result = 0;
 451         unsigned char hostc;
 452
 453         if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
 454                 if (read_write == I2C_SMBUS_WRITE) {
 455                         /* set I2C_EN bit in configuration register */
 456                         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
 457                         pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
 458                                               hostc | SMBHSTCFG_I2C_EN);
 459                 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
 460                         dev_err(&priv->pci_dev->dev,
 461                                 "I2C block read is unsupported!\n");
 462                         return -EOPNOTSUPP;
 463                 }
 464         }
 465
 466         if (read_write == I2C_SMBUS_WRITE
 467          || command == I2C_SMBUS_I2C_BLOCK_DATA) {
 468                 if (data->block[0] < 1)
 469                         data->block[0] = 1;
 470                 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
 471                         data->block[0] = I2C_SMBUS_BLOCK_MAX;
 472         } else {
 473                 data->block[0] = 32;    /* max for SMBus block reads */
 474         }
 475
 476         /* Experience has shown that the block buffer can only be used for
 477            SMBus (not I2C) block transactions, even though the datasheet
 478            doesn't mention this limitation. */
 479         if ((priv->features & FEATURE_BLOCK_BUFFER)
 480          && command != I2C_SMBUS_I2C_BLOCK_DATA
 481          && i801_set_block_buffer_mode(priv) == 0)
 482                 result = i801_block_transaction_by_block(priv, data,
 483                                                          read_write, hwpec);
 484         else
 485                 result = i801_block_transaction_byte_by_byte(priv, data,
 486                                                              read_write,
 487                                                              command, hwpec);
 488
 489         if (result == 0 && hwpec)
 490                 i801_wait_hwpec(priv);
 491
 492         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 493          && read_write == I2C_SMBUS_WRITE) {
 494                 /* restore saved configuration register value */
 495                 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
 496         }
 497         return result;
 498 }
 499
 500 /* Return negative errno on error. */
 501 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
 502                        unsigned short flags, char read_write, u8 command,
 503                        int size, union i2c_smbus_data *data)
 504 {
 505         int hwpec;
 506         int block = 0;
 507         int ret, xact = 0;
 508         struct i801_priv *priv = i2c_get_adapdata(adap);
 509
 510         hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
 511                 && size != I2C_SMBUS_QUICK
 512                 && size != I2C_SMBUS_I2C_BLOCK_DATA;
 513
 514         switch (size) {
 515         case I2C_SMBUS_QUICK:
 516                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 517                        SMBHSTADD(priv));
 518                 xact = I801_QUICK;
 519                 break;
 520         case I2C_SMBUS_BYTE:
 521                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 522                        SMBHSTADD(priv));
 523                 if (read_write == I2C_SMBUS_WRITE)
 524                         outb_p(command, SMBHSTCMD(priv));
 525                 xact = I801_BYTE;
 526                 break;
 527         case I2C_SMBUS_BYTE_DATA:
 528                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 529                        SMBHSTADD(priv));
 530                 outb_p(command, SMBHSTCMD(priv));
 531                 if (read_write == I2C_SMBUS_WRITE)
 532                         outb_p(data->byte, SMBHSTDAT0(priv));
 533                 xact = I801_BYTE_DATA;
 534                 break;
 535         case I2C_SMBUS_WORD_DATA:
 536                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 537                        SMBHSTADD(priv));
 538                 outb_p(command, SMBHSTCMD(priv));
 539                 if (read_write == I2C_SMBUS_WRITE) {
 540                         outb_p(data->word & 0xff, SMBHSTDAT0(priv));
 541                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
 542                 }
 543                 xact = I801_WORD_DATA;
 544                 break;
 545         case I2C_SMBUS_BLOCK_DATA:
 546                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 547                        SMBHSTADD(priv));
 548                 outb_p(command, SMBHSTCMD(priv));
 549                 block = 1;
 550                 break;
 551         case I2C_SMBUS_I2C_BLOCK_DATA:
 552                 /* NB: page 240 of ICH5 datasheet shows that the R/#W
 553                  * bit should be cleared here, even when reading */
 554                 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
 555                 if (read_write == I2C_SMBUS_READ) {
 556                         /* NB: page 240 of ICH5 datasheet also shows
 557                          * that DATA1 is the cmd field when reading */
 558                         outb_p(command, SMBHSTDAT1(priv));
 559                 } else
 560                         outb_p(command, SMBHSTCMD(priv));
 561                 block = 1;
 562                 break;
 563         default:
 564                 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
 565                         size);
 566                 return -EOPNOTSUPP;
 567         }
 568
 569         if (hwpec)      /* enable/disable hardware PEC */
 570                 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
 571         else
 572                 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
 573                        SMBAUXCTL(priv));
 574
 575         if (block)
 576                 ret = i801_block_transaction(priv, data, read_write, size,
 577                                              hwpec);
 578         else
 579                 ret = i801_transaction(priv, xact | ENABLE_INT9);
 580
 581         /* Some BIOSes don't like it when PEC is enabled at reboot or resume
 582            time, so we forcibly disable it after every transaction. Turn off
 583            E32B for the same reason. */
 584         if (hwpec || block)
 585                 outb_p(inb_p(SMBAUXCTL(priv)) &
 586                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
 587
 588         if (block)
 589                 return ret;
 590         if (ret)
 591                 return ret;
 592         if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
 593                 return 0;
 594
 595         switch (xact & 0x7f) {
 596         case I801_BYTE: /* Result put in SMBHSTDAT0 */
 597         case I801_BYTE_DATA:
 598                 data->byte = inb_p(SMBHSTDAT0(priv));
 599                 break;
 600         case I801_WORD_DATA:
 601                 data->word = inb_p(SMBHSTDAT0(priv)) +
 602                              (inb_p(SMBHSTDAT1(priv)) << 8);
 603                 break;
 604         }
 605         return 0;
 606 }
 607
 608
 609 static u32 i801_func(struct i2c_adapter *adapter)
 610 {
 611         struct i801_priv *priv = i2c_get_adapdata(adapter);
 612
 613         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 614                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 615                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
 616                ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
 617                ((priv->features & FEATURE_I2C_BLOCK_READ) ?
 618                 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
 619 }
 620
 621 static const struct i2c_algorithm smbus_algorithm = {
 622         .smbus_xfer     = i801_access,
 623         .functionality  = i801_func,
 624 };
 625
 626 static const struct pci_device_id i801_ids[] = {
 627         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
 628         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
 629         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
 630         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
 631         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
 632         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
 633         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
 634         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
 635         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
 636         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
 637         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
 638         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
 639         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
 640         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
 641         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
 642         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
 643         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
 644         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
 645         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
 646         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
 647         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
 648         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
 649         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
 650         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
 651         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
 652         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
 653         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
 654         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
 655         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
 656         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
 657         { 0, }
 658 };
 659
 660 MODULE_DEVICE_TABLE(pci, i801_ids);
 661
 662 #if defined CONFIG_X86 && defined CONFIG_DMI
 663 static unsigned char apanel_addr;
 664
 665 /* Scan the system ROM for the signature "FJKEYINF" */
 666 static __init const void __iomem *bios_signature(const void __iomem *bios)
 667 {
 668         ssize_t offset;
 669         const unsigned char signature[] = "FJKEYINF";
 670
 671         for (offset = 0; offset < 0x10000; offset += 0x10) {
 672                 if (check_signature(bios + offset, signature,
 673                                     sizeof(signature)-1))
 674                         return bios + offset;
 675         }
 676         return NULL;
 677 }
 678
 679 static void __init input_apanel_init(void)
 680 {
 681         void __iomem *bios;
 682         const void __iomem *p;
 683
 684         bios = ioremap(0xF0000, 0x10000); /* Can't fail */
 685         p = bios_signature(bios);
 686         if (p) {
 687                 /* just use the first address */
 688                 apanel_addr = readb(p + 8 + 3) >> 1;
 689         }
 690         iounmap(bios);
 691 }
 692
 693 struct dmi_onboard_device_info {
 694         const char *name;
 695         u8 type;
 696         unsigned short i2c_addr;
 697         const char *i2c_type;
 698 };
 699
 700 static struct dmi_onboard_device_info __devinitdata dmi_devices[] = {
 701         { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
 702         { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
 703         { "Hades",  DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
 704 };
 705
 706 static void __devinit dmi_check_onboard_device(u8 type, const char *name,
 707                                                struct i2c_adapter *adap)
 708 {
 709         int i;
 710         struct i2c_board_info info;
 711
 712         for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
 713                 /* & ~0x80, ignore enabled/disabled bit */
 714                 if ((type & ~0x80) != dmi_devices[i].type)
 715                         continue;
 716                 if (strcasecmp(name, dmi_devices[i].name))
 717                         continue;
 718
 719                 memset(&info, 0, sizeof(struct i2c_board_info));
 720                 info.addr = dmi_devices[i].i2c_addr;
 721                 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
 722                 i2c_new_device(adap, &info);
 723                 break;
 724         }
 725 }
 726
 727 /* We use our own function to check for onboard devices instead of
 728    dmi_find_device() as some buggy BIOS's have the devices we are interested
 729    in marked as disabled */
 730 static void __devinit dmi_check_onboard_devices(const struct dmi_header *dm,
 731                                                 void *adap)
 732 {
 733         int i, count;
 734
 735         if (dm->type != 10)
 736                 return;
 737
 738         count = (dm->length - sizeof(struct dmi_header)) / 2;
 739         for (i = 0; i < count; i++) {
 740                 const u8 *d = (char *)(dm + 1) + (i * 2);
 741                 const char *name = ((char *) dm) + dm->length;
 742                 u8 type = d[0];
 743                 u8 s = d[1];
 744
 745                 if (!s)
 746                         continue;
 747                 s--;
 748                 while (s > 0 && name[0]) {
 749                         name += strlen(name) + 1;
 750                         s--;
 751                 }
 752                 if (name[0] == 0) /* Bogus string reference */
 753                         continue;
 754
 755                 dmi_check_onboard_device(type, name, adap);
 756         }
 757 }
 758
 759 /* Register optional slaves */
 760 static void __devinit i801_probe_optional_slaves(struct i801_priv *priv)
 761 {
 762         /* Only register slaves on main SMBus channel */
 763         if (priv->features & FEATURE_IDF)
 764                 return;
 765
 766         if (apanel_addr) {
 767                 struct i2c_board_info info;
 768
 769                 memset(&info, 0, sizeof(struct i2c_board_info));
 770                 info.addr = apanel_addr;
 771                 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
 772                 i2c_new_device(&priv->adapter, &info);
 773         }
 774
 775         if (dmi_name_in_vendors("FUJITSU"))
 776                 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
 777 }
 778 #else
 779 static void __init input_apanel_init(void) {}
 780 static void __devinit i801_probe_optional_slaves(struct i801_priv *priv) {}
 781 #endif  /* CONFIG_X86 && CONFIG_DMI */
 782
 783 static int __devinit i801_probe(struct pci_dev *dev,
 784                                 const struct pci_device_id *id)
 785 {
 786         unsigned char temp;
 787         int err, i;
 788         struct i801_priv *priv;
 789
 790         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 791         if (!priv)
 792                 return -ENOMEM;
 793
 794         i2c_set_adapdata(&priv->adapter, priv);
 795         priv->adapter.owner = THIS_MODULE;
 796         priv->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
 797         priv->adapter.algo = &smbus_algorithm;
 798
 799         priv->pci_dev = dev;
 800         switch (dev->device) {
 801         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
 802         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
 803         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
 804         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
 805         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
 806         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
 807                 priv->features |= FEATURE_IDF;
 808                 /* fall through */
 809         default:
 810                 priv->features |= FEATURE_I2C_BLOCK_READ;
 811                 /* fall through */
 812         case PCI_DEVICE_ID_INTEL_82801DB_3:
 813                 priv->features |= FEATURE_SMBUS_PEC;
 814                 priv->features |= FEATURE_BLOCK_BUFFER;
 815                 /* fall through */
 816         case PCI_DEVICE_ID_INTEL_82801CA_3:
 817         case PCI_DEVICE_ID_INTEL_82801BA_2:
 818         case PCI_DEVICE_ID_INTEL_82801AB_3:
 819         case PCI_DEVICE_ID_INTEL_82801AA_3:
 820                 break;
 821         }
 822
 823         /* Disable features on user request */
 824         for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
 825                 if (priv->features & disable_features & (1 << i))
 826                         dev_notice(&dev->dev, "%s disabled by user\n",
 827                                    i801_feature_names[i]);
 828         }
 829         priv->features &= ~disable_features;
 830
 831         err = pci_enable_device(dev);
 832         if (err) {
 833                 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
 834                         err);
 835                 goto exit;
 836         }
 837
 838         /* Determine the address of the SMBus area */
 839         priv->smba = pci_resource_start(dev, SMBBAR);
 840         if (!priv->smba) {
 841                 dev_err(&dev->dev, "SMBus base address uninitialized, "
 842                         "upgrade BIOS\n");
 843                 err = -ENODEV;
 844                 goto exit;
 845         }
 846
 847         err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
 848         if (err) {
 849                 err = -ENODEV;
 850                 goto exit;
 851         }
 852
 853         err = pci_request_region(dev, SMBBAR, i801_driver.name);
 854         if (err) {
 855                 dev_err(&dev->dev, "Failed to request SMBus region "
 856                         "0x%lx-0x%Lx\n", priv->smba,
 857                         (unsigned long long)pci_resource_end(dev, SMBBAR));
 858                 goto exit;
 859         }
 860
 861         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
 862         priv->original_hstcfg = temp;
 863         temp &= ~SMBHSTCFG_I2C_EN;      /* SMBus timing */
 864         if (!(temp & SMBHSTCFG_HST_EN)) {
 865                 dev_info(&dev->dev, "Enabling SMBus device\n");
 866                 temp |= SMBHSTCFG_HST_EN;
 867         }
 868         pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
 869
 870         if (temp & SMBHSTCFG_SMB_SMI_EN)
 871                 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
 872         else
 873                 dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n");
 874
 875         /* Clear special mode bits */
 876         if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
 877                 outb_p(inb_p(SMBAUXCTL(priv)) &
 878                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
 879
 880         /* set up the sysfs linkage to our parent device */
 881         priv->adapter.dev.parent = &dev->dev;
 882
 883         /* Retry up to 3 times on lost arbitration */
 884         priv->adapter.retries = 3;
 885
 886         snprintf(priv->adapter.name, sizeof(priv->adapter.name),
 887                 "SMBus I801 adapter at %04lx", priv->smba);
 888         err = i2c_add_adapter(&priv->adapter);
 889         if (err) {
 890                 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
 891                 goto exit_release;
 892         }
 893
 894         i801_probe_optional_slaves(priv);
 895
 896         pci_set_drvdata(dev, priv);
 897         return 0;
 898
 899 exit_release:
 900         pci_release_region(dev, SMBBAR);
 901 exit:
 902         kfree(priv);
 903         return err;
 904 }
 905
 906 static void __devexit i801_remove(struct pci_dev *dev)
 907 {
 908         struct i801_priv *priv = pci_get_drvdata(dev);
 909
 910         i2c_del_adapter(&priv->adapter);
 911         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
 912         pci_release_region(dev, SMBBAR);
 913         pci_set_drvdata(dev, NULL);
 914         kfree(priv);
 915         /*
 916          * do not call pci_disable_device(dev) since it can cause hard hangs on
 917          * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
 918          */
 919 }
 920
 921 #ifdef CONFIG_PM
 922 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
 923 {
 924         struct i801_priv *priv = pci_get_drvdata(dev);
 925
 926         pci_save_state(dev);
 927         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
 928         pci_set_power_state(dev, pci_choose_state(dev, mesg));
 929         return 0;
 930 }
 931
 932 static int i801_resume(struct pci_dev *dev)
 933 {
 934         pci_set_power_state(dev, PCI_D0);
 935         pci_restore_state(dev);
 936         return pci_enable_device(dev);
 937 }
 938 #else
 939 #define i801_suspend NULL
 940 #define i801_resume NULL
 941 #endif
 942
 943 static struct pci_driver i801_driver = {
 944         .name           = "i801_smbus",
 945         .id_table       = i801_ids,
 946         .probe          = i801_probe,
 947         .remove         = __devexit_p(i801_remove),
 948         .suspend        = i801_suspend,
 949         .resume         = i801_resume,
 950 };
 951
 952 static int __init i2c_i801_init(void)
 953 {
 954         if (dmi_name_in_vendors("FUJITSU"))
 955                 input_apanel_init();
 956         return pci_register_driver(&i801_driver);
 957 }
 958
 959 static void __exit i2c_i801_exit(void)
 960 {
 961         pci_unregister_driver(&i801_driver);
 962 }
 963
 964 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, "
 965               "Jean Delvare <khali@linux-fr.org>");
 966 MODULE_DESCRIPTION("I801 SMBus driver");
 967 MODULE_LICENSE("GPL");
 968
 969 module_init(i2c_i801_init);
 970 module_exit(i2c_i801_exit);