drivers/i2c/busses/i2c-i801.c

   1 /*
   2     Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
   3     Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
   4     <mdsxyz123@yahoo.com>
   5     Copyright (C) 2007, 2008   Jean Delvare <khali@linux-fr.org>
   6     Copyright (C) 2010         Intel Corporation,
   7                                David Woodhouse <dwmw2@infradead.org>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18
  19     You should have received a copy of the GNU General Public License
  20     along with this program; if not, write to the Free Software
  21     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22 */
  23
  24 /*
  25   Supports the following Intel I/O Controller Hubs (ICH):
  26
  27                                   I/O                     Block   I2C
  28                                   region  SMBus   Block   proc.   block
  29   Chip name             PCI ID    size    PEC     buffer  call    read
  30   ----------------------------------------------------------------------
  31   82801AA  (ICH)        0x2413     16      no      no      no      no
  32   82801AB  (ICH0)       0x2423     16      no      no      no      no
  33   82801BA  (ICH2)       0x2443     16      no      no      no      no
  34   82801CA  (ICH3)       0x2483     32     soft     no      no      no
  35   82801DB  (ICH4)       0x24c3     32     hard     yes     no      no
  36   82801E   (ICH5)       0x24d3     32     hard     yes     yes     yes
  37   6300ESB               0x25a4     32     hard     yes     yes     yes
  38   82801F   (ICH6)       0x266a     32     hard     yes     yes     yes
  39   6310ESB/6320ESB       0x269b     32     hard     yes     yes     yes
  40   82801G   (ICH7)       0x27da     32     hard     yes     yes     yes
  41   82801H   (ICH8)       0x283e     32     hard     yes     yes     yes
  42   82801I   (ICH9)       0x2930     32     hard     yes     yes     yes
  43   EP80579 (Tolapai)     0x5032     32     hard     yes     yes     yes
  44   ICH10                 0x3a30     32     hard     yes     yes     yes
  45   ICH10                 0x3a60     32     hard     yes     yes     yes
  46   5/3400 Series (PCH)   0x3b30     32     hard     yes     yes     yes
  47   6 Series (PCH)        0x1c22     32     hard     yes     yes     yes
  48   Patsburg (PCH)        0x1d22     32     hard     yes     yes     yes
  49   Patsburg (PCH) IDF    0x1d70     32     hard     yes     yes     yes
  50   Patsburg (PCH) IDF    0x1d71     32     hard     yes     yes     yes
  51   Patsburg (PCH) IDF    0x1d72     32     hard     yes     yes     yes
  52   DH89xxCC (PCH)        0x2330     32     hard     yes     yes     yes
  53   Panther Point (PCH)   0x1e22     32     hard     yes     yes     yes
  54   Lynx Point (PCH)      0x8c22     32     hard     yes     yes     yes
  55   Lynx Point-LP (PCH)   0x9c22     32     hard     yes     yes     yes
  56
  57   Features supported by this driver:
  58   Software PEC                     no
  59   Hardware PEC                     yes
  60   Block buffer                     yes
  61   Block process call transaction   no
  62   I2C block read transaction       yes  (doesn't use the block buffer)
  63   Slave mode                       no
  64
  65   See the file Documentation/i2c/busses/i2c-i801 for details.
  66 */
  67
  68 #include <linux/module.h>
  69 #include <linux/pci.h>
  70 #include <linux/kernel.h>
  71 #include <linux/stddef.h>
  72 #include <linux/delay.h>
  73 #include <linux/ioport.h>
  74 #include <linux/init.h>
  75 #include <linux/i2c.h>
  76 #include <linux/acpi.h>
  77 #include <linux/io.h>
  78 #include <linux/dmi.h>
  79 #include <linux/slab.h>
  80
  81 /* I801 SMBus address offsets */
  82 #define SMBHSTSTS(p)    (0 + (p)->smba)
  83 #define SMBHSTCNT(p)    (2 + (p)->smba)
  84 #define SMBHSTCMD(p)    (3 + (p)->smba)
  85 #define SMBHSTADD(p)    (4 + (p)->smba)
  86 #define SMBHSTDAT0(p)   (5 + (p)->smba)
  87 #define SMBHSTDAT1(p)   (6 + (p)->smba)
  88 #define SMBBLKDAT(p)    (7 + (p)->smba)
  89 #define SMBPEC(p)       (8 + (p)->smba)         /* ICH3 and later */
  90 #define SMBAUXSTS(p)    (12 + (p)->smba)        /* ICH4 and later */
  91 #define SMBAUXCTL(p)    (13 + (p)->smba)        /* ICH4 and later */
  92
  93 /* PCI Address Constants */
  94 #define SMBBAR          4
  95 #define SMBHSTCFG       0x040
  96
  97 /* Host configuration bits for SMBHSTCFG */
  98 #define SMBHSTCFG_HST_EN        1
  99 #define SMBHSTCFG_SMB_SMI_EN    2
 100 #define SMBHSTCFG_I2C_EN        4
 101
 102 /* Auxiliary control register bits, ICH4+ only */
 103 #define SMBAUXCTL_CRC           1
 104 #define SMBAUXCTL_E32B          2
 105
 106 /* kill bit for SMBHSTCNT */
 107 #define SMBHSTCNT_KILL          2
 108
 109 /* Other settings */
 110 #define MAX_TIMEOUT             100
 111 #define ENABLE_INT9             0       /* set to 0x01 to enable - untested */
 112
 113 /* I801 command constants */
 114 #define I801_QUICK              0x00
 115 #define I801_BYTE               0x04
 116 #define I801_BYTE_DATA          0x08
 117 #define I801_WORD_DATA          0x0C
 118 #define I801_PROC_CALL          0x10    /* unimplemented */
 119 #define I801_BLOCK_DATA         0x14
 120 #define I801_I2C_BLOCK_DATA     0x18    /* ICH5 and later */
 121 #define I801_BLOCK_LAST         0x34
 122 #define I801_I2C_BLOCK_LAST     0x38    /* ICH5 and later */
 123 #define I801_START              0x40
 124 #define I801_PEC_EN             0x80    /* ICH3 and later */
 125
 126 /* I801 Hosts Status register bits */
 127 #define SMBHSTSTS_BYTE_DONE     0x80
 128 #define SMBHSTSTS_INUSE_STS     0x40
 129 #define SMBHSTSTS_SMBALERT_STS  0x20
 130 #define SMBHSTSTS_FAILED        0x10
 131 #define SMBHSTSTS_BUS_ERR       0x08
 132 #define SMBHSTSTS_DEV_ERR       0x04
 133 #define SMBHSTSTS_INTR          0x02
 134 #define SMBHSTSTS_HOST_BUSY     0x01
 135
 136 #define STATUS_FLAGS            (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_FAILED | \
 137                                  SMBHSTSTS_BUS_ERR | SMBHSTSTS_DEV_ERR | \
 138                                  SMBHSTSTS_INTR)
 139
 140 /* Older devices have their ID defined in <linux/pci_ids.h> */
 141 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS   0x1c22
 142 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS      0x1d22
 143 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
 144 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
 145 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
 146 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
 147 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS  0x1e22
 148 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS      0x2330
 149 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
 150 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS     0x8c22
 151 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS  0x9c22
 152
 153 struct i801_priv {
 154         struct i2c_adapter adapter;
 155         unsigned long smba;
 156         unsigned char original_hstcfg;
 157         struct pci_dev *pci_dev;
 158         unsigned int features;
 159 };
 160
 161 static struct pci_driver i801_driver;
 162
 163 #define FEATURE_SMBUS_PEC       (1 << 0)
 164 #define FEATURE_BLOCK_BUFFER    (1 << 1)
 165 #define FEATURE_BLOCK_PROC      (1 << 2)
 166 #define FEATURE_I2C_BLOCK_READ  (1 << 3)
 167 /* Not really a feature, but it's convenient to handle it as such */
 168 #define FEATURE_IDF             (1 << 15)
 169
 170 static const char *i801_feature_names[] = {
 171         "SMBus PEC",
 172         "Block buffer",
 173         "Block process call",
 174         "I2C block read",
 175 };
 176
 177 static unsigned int disable_features;
 178 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
 179 MODULE_PARM_DESC(disable_features, "Disable selected driver features");
 180
 181 /* Make sure the SMBus host is ready to start transmitting.
 182    Return 0 if it is, -EBUSY if it is not. */
 183 static int i801_check_pre(struct i801_priv *priv)
 184 {
 185         int status;
 186
 187         status = inb_p(SMBHSTSTS(priv));
 188         if (status & SMBHSTSTS_HOST_BUSY) {
 189                 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
 190                 return -EBUSY;
 191         }
 192
 193         status &= STATUS_FLAGS;
 194         if (status) {
 195                 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
 196                         status);
 197                 outb_p(status, SMBHSTSTS(priv));
 198                 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
 199                 if (status) {
 200                         dev_err(&priv->pci_dev->dev,
 201                                 "Failed clearing status flags (%02x)\n",
 202                                 status);
 203                         return -EBUSY;
 204                 }
 205         }
 206
 207         return 0;
 208 }
 209
 210 /* Convert the status register to an error code, and clear it. */
 211 static int i801_check_post(struct i801_priv *priv, int status, int timeout)
 212 {
 213         int result = 0;
 214
 215         /* If the SMBus is still busy, we give up */
 216         if (timeout) {
 217                 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
 218                 /* try to stop the current command */
 219                 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
 220                 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
 221                        SMBHSTCNT(priv));
 222                 msleep(1);
 223                 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
 224                        SMBHSTCNT(priv));
 225
 226                 /* Check if it worked */
 227                 status = inb_p(SMBHSTSTS(priv));
 228                 if ((status & SMBHSTSTS_HOST_BUSY) ||
 229                     !(status & SMBHSTSTS_FAILED))
 230                         dev_err(&priv->pci_dev->dev,
 231                                 "Failed terminating the transaction\n");
 232                 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
 233                 return -ETIMEDOUT;
 234         }
 235
 236         if (status & SMBHSTSTS_FAILED) {
 237                 result = -EIO;
 238                 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
 239         }
 240         if (status & SMBHSTSTS_DEV_ERR) {
 241                 result = -ENXIO;
 242                 dev_dbg(&priv->pci_dev->dev, "No response\n");
 243         }
 244         if (status & SMBHSTSTS_BUS_ERR) {
 245                 result = -EAGAIN;
 246                 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
 247         }
 248
 249         if (result) {
 250                 /* Clear error flags */
 251                 outb_p(status & STATUS_FLAGS, SMBHSTSTS(priv));
 252                 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
 253                 if (status) {
 254                         dev_warn(&priv->pci_dev->dev, "Failed clearing status "
 255                                  "flags at end of transaction (%02x)\n",
 256                                  status);
 257                 }
 258         }
 259
 260         return result;
 261 }
 262
 263 static int i801_transaction(struct i801_priv *priv, int xact)
 264 {
 265         int status;
 266         int result;
 267         int timeout = 0;
 268
 269         result = i801_check_pre(priv);
 270         if (result < 0)
 271                 return result;
 272
 273         /* the current contents of SMBHSTCNT can be overwritten, since PEC,
 274          * INTREN, SMBSCMD are passed in xact */
 275         outb_p(xact | I801_START, SMBHSTCNT(priv));
 276
 277         /* We will always wait for a fraction of a second! */
 278         do {
 279                 msleep(1);
 280                 status = inb_p(SMBHSTSTS(priv));
 281         } while ((status & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_TIMEOUT));
 282
 283         result = i801_check_post(priv, status, timeout > MAX_TIMEOUT);
 284         if (result < 0)
 285                 return result;
 286
 287         outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 288         return 0;
 289 }
 290
 291 /* wait for INTR bit as advised by Intel */
 292 static void i801_wait_hwpec(struct i801_priv *priv)
 293 {
 294         int timeout = 0;
 295         int status;
 296
 297         do {
 298                 msleep(1);
 299                 status = inb_p(SMBHSTSTS(priv));
 300         } while ((!(status & SMBHSTSTS_INTR))
 301                  && (timeout++ < MAX_TIMEOUT));
 302
 303         if (timeout > MAX_TIMEOUT)
 304                 dev_dbg(&priv->pci_dev->dev, "PEC Timeout!\n");
 305
 306         outb_p(status, SMBHSTSTS(priv));
 307 }
 308
 309 static int i801_block_transaction_by_block(struct i801_priv *priv,
 310                                            union i2c_smbus_data *data,
 311                                            char read_write, int hwpec)
 312 {
 313         int i, len;
 314         int status;
 315
 316         inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
 317
 318         /* Use 32-byte buffer to process this transaction */
 319         if (read_write == I2C_SMBUS_WRITE) {
 320                 len = data->block[0];
 321                 outb_p(len, SMBHSTDAT0(priv));
 322                 for (i = 0; i < len; i++)
 323                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 324         }
 325
 326         status = i801_transaction(priv, I801_BLOCK_DATA | ENABLE_INT9 |
 327                                   I801_PEC_EN * hwpec);
 328         if (status)
 329                 return status;
 330
 331         if (read_write == I2C_SMBUS_READ) {
 332                 len = inb_p(SMBHSTDAT0(priv));
 333                 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
 334                         return -EPROTO;
 335
 336                 data->block[0] = len;
 337                 for (i = 0; i < len; i++)
 338                         data->block[i + 1] = inb_p(SMBBLKDAT(priv));
 339         }
 340         return 0;
 341 }
 342
 343 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
 344                                                union i2c_smbus_data *data,
 345                                                char read_write, int command,
 346                                                int hwpec)
 347 {
 348         int i, len;
 349         int smbcmd;
 350         int status;
 351         int result;
 352         int timeout;
 353
 354         result = i801_check_pre(priv);
 355         if (result < 0)
 356                 return result;
 357
 358         len = data->block[0];
 359
 360         if (read_write == I2C_SMBUS_WRITE) {
 361                 outb_p(len, SMBHSTDAT0(priv));
 362                 outb_p(data->block[1], SMBBLKDAT(priv));
 363         }
 364
 365         for (i = 1; i <= len; i++) {
 366                 if (i == len && read_write == I2C_SMBUS_READ) {
 367                         if (command == I2C_SMBUS_I2C_BLOCK_DATA)
 368                                 smbcmd = I801_I2C_BLOCK_LAST;
 369                         else
 370                                 smbcmd = I801_BLOCK_LAST;
 371                 } else {
 372                         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 373                          && read_write == I2C_SMBUS_READ)
 374                                 smbcmd = I801_I2C_BLOCK_DATA;
 375                         else
 376                                 smbcmd = I801_BLOCK_DATA;
 377                 }
 378                 outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT(priv));
 379
 380                 if (i == 1)
 381                         outb_p(inb(SMBHSTCNT(priv)) | I801_START,
 382                                SMBHSTCNT(priv));
 383
 384                 /* We will always wait for a fraction of a second! */
 385                 timeout = 0;
 386                 do {
 387                         msleep(1);
 388                         status = inb_p(SMBHSTSTS(priv));
 389                 } while ((!(status & SMBHSTSTS_BYTE_DONE))
 390                          && (timeout++ < MAX_TIMEOUT));
 391
 392                 result = i801_check_post(priv, status, timeout > MAX_TIMEOUT);
 393                 if (result < 0)
 394                         return result;
 395
 396                 if (i == 1 && read_write == I2C_SMBUS_READ
 397                  && command != I2C_SMBUS_I2C_BLOCK_DATA) {
 398                         len = inb_p(SMBHSTDAT0(priv));
 399                         if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
 400                                 dev_err(&priv->pci_dev->dev,
 401                                         "Illegal SMBus block read size %d\n",
 402                                         len);
 403                                 /* Recover */
 404                                 while (inb_p(SMBHSTSTS(priv)) &
 405                                        SMBHSTSTS_HOST_BUSY)
 406                                         outb_p(SMBHSTSTS_BYTE_DONE,
 407                                                SMBHSTSTS(priv));
 408                                 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 409                                 return -EPROTO;
 410                         }
 411                         data->block[0] = len;
 412                 }
 413
 414                 /* Retrieve/store value in SMBBLKDAT */
 415                 if (read_write == I2C_SMBUS_READ)
 416                         data->block[i] = inb_p(SMBBLKDAT(priv));
 417                 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
 418                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 419
 420                 /* signals SMBBLKDAT ready */
 421                 outb_p(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR, SMBHSTSTS(priv));
 422         }
 423
 424         return 0;
 425 }
 426
 427 static int i801_set_block_buffer_mode(struct i801_priv *priv)
 428 {
 429         outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
 430         if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
 431                 return -EIO;
 432         return 0;
 433 }
 434
 435 /* Block transaction function */
 436 static int i801_block_transaction(struct i801_priv *priv,
 437                                   union i2c_smbus_data *data, char read_write,
 438                                   int command, int hwpec)
 439 {
 440         int result = 0;
 441         unsigned char hostc;
 442
 443         if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
 444                 if (read_write == I2C_SMBUS_WRITE) {
 445                         /* set I2C_EN bit in configuration register */
 446                         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
 447                         pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
 448                                               hostc | SMBHSTCFG_I2C_EN);
 449                 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
 450                         dev_err(&priv->pci_dev->dev,
 451                                 "I2C block read is unsupported!\n");
 452                         return -EOPNOTSUPP;
 453                 }
 454         }
 455
 456         if (read_write == I2C_SMBUS_WRITE
 457          || command == I2C_SMBUS_I2C_BLOCK_DATA) {
 458                 if (data->block[0] < 1)
 459                         data->block[0] = 1;
 460                 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
 461                         data->block[0] = I2C_SMBUS_BLOCK_MAX;
 462         } else {
 463                 data->block[0] = 32;    /* max for SMBus block reads */
 464         }
 465
 466         /* Experience has shown that the block buffer can only be used for
 467            SMBus (not I2C) block transactions, even though the datasheet
 468            doesn't mention this limitation. */
 469         if ((priv->features & FEATURE_BLOCK_BUFFER)
 470          && command != I2C_SMBUS_I2C_BLOCK_DATA
 471          && i801_set_block_buffer_mode(priv) == 0)
 472                 result = i801_block_transaction_by_block(priv, data,
 473                                                          read_write, hwpec);
 474         else
 475                 result = i801_block_transaction_byte_by_byte(priv, data,
 476                                                              read_write,
 477                                                              command, hwpec);
 478
 479         if (result == 0 && hwpec)
 480                 i801_wait_hwpec(priv);
 481
 482         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 483          && read_write == I2C_SMBUS_WRITE) {
 484                 /* restore saved configuration register value */
 485                 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
 486         }
 487         return result;
 488 }
 489
 490 /* Return negative errno on error. */
 491 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
 492                        unsigned short flags, char read_write, u8 command,
 493                        int size, union i2c_smbus_data *data)
 494 {
 495         int hwpec;
 496         int block = 0;
 497         int ret, xact = 0;
 498         struct i801_priv *priv = i2c_get_adapdata(adap);
 499
 500         hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
 501                 && size != I2C_SMBUS_QUICK
 502                 && size != I2C_SMBUS_I2C_BLOCK_DATA;
 503
 504         switch (size) {
 505         case I2C_SMBUS_QUICK:
 506                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 507                        SMBHSTADD(priv));
 508                 xact = I801_QUICK;
 509                 break;
 510         case I2C_SMBUS_BYTE:
 511                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 512                        SMBHSTADD(priv));
 513                 if (read_write == I2C_SMBUS_WRITE)
 514                         outb_p(command, SMBHSTCMD(priv));
 515                 xact = I801_BYTE;
 516                 break;
 517         case I2C_SMBUS_BYTE_DATA:
 518                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 519                        SMBHSTADD(priv));
 520                 outb_p(command, SMBHSTCMD(priv));
 521                 if (read_write == I2C_SMBUS_WRITE)
 522                         outb_p(data->byte, SMBHSTDAT0(priv));
 523                 xact = I801_BYTE_DATA;
 524                 break;
 525         case I2C_SMBUS_WORD_DATA:
 526                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 527                        SMBHSTADD(priv));
 528                 outb_p(command, SMBHSTCMD(priv));
 529                 if (read_write == I2C_SMBUS_WRITE) {
 530                         outb_p(data->word & 0xff, SMBHSTDAT0(priv));
 531                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
 532                 }
 533                 xact = I801_WORD_DATA;
 534                 break;
 535         case I2C_SMBUS_BLOCK_DATA:
 536                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 537                        SMBHSTADD(priv));
 538                 outb_p(command, SMBHSTCMD(priv));
 539                 block = 1;
 540                 break;
 541         case I2C_SMBUS_I2C_BLOCK_DATA:
 542                 /* NB: page 240 of ICH5 datasheet shows that the R/#W
 543                  * bit should be cleared here, even when reading */
 544                 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
 545                 if (read_write == I2C_SMBUS_READ) {
 546                         /* NB: page 240 of ICH5 datasheet also shows
 547                          * that DATA1 is the cmd field when reading */
 548                         outb_p(command, SMBHSTDAT1(priv));
 549                 } else
 550                         outb_p(command, SMBHSTCMD(priv));
 551                 block = 1;
 552                 break;
 553         default:
 554                 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
 555                         size);
 556                 return -EOPNOTSUPP;
 557         }
 558
 559         if (hwpec)      /* enable/disable hardware PEC */
 560                 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
 561         else
 562                 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
 563                        SMBAUXCTL(priv));
 564
 565         if (block)
 566                 ret = i801_block_transaction(priv, data, read_write, size,
 567                                              hwpec);
 568         else
 569                 ret = i801_transaction(priv, xact | ENABLE_INT9);
 570
 571         /* Some BIOSes don't like it when PEC is enabled at reboot or resume
 572            time, so we forcibly disable it after every transaction. Turn off
 573            E32B for the same reason. */
 574         if (hwpec || block)
 575                 outb_p(inb_p(SMBAUXCTL(priv)) &
 576                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
 577
 578         if (block)
 579                 return ret;
 580         if (ret)
 581                 return ret;
 582         if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
 583                 return 0;
 584
 585         switch (xact & 0x7f) {
 586         case I801_BYTE: /* Result put in SMBHSTDAT0 */
 587         case I801_BYTE_DATA:
 588                 data->byte = inb_p(SMBHSTDAT0(priv));
 589                 break;
 590         case I801_WORD_DATA:
 591                 data->word = inb_p(SMBHSTDAT0(priv)) +
 592                              (inb_p(SMBHSTDAT1(priv)) << 8);
 593                 break;
 594         }
 595         return 0;
 596 }
 597
 598
 599 static u32 i801_func(struct i2c_adapter *adapter)
 600 {
 601         struct i801_priv *priv = i2c_get_adapdata(adapter);
 602
 603         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 604                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 605                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
 606                ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
 607                ((priv->features & FEATURE_I2C_BLOCK_READ) ?
 608                 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
 609 }
 610
 611 static const struct i2c_algorithm smbus_algorithm = {
 612         .smbus_xfer     = i801_access,
 613         .functionality  = i801_func,
 614 };
 615
 616 static const struct pci_device_id i801_ids[] = {
 617         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
 618         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
 619         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
 620         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
 621         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
 622         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
 623         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
 624         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
 625         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
 626         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
 627         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
 628         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
 629         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
 630         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
 631         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
 632         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
 633         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
 634         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
 635         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
 636         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
 637         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
 638         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
 639         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
 640         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
 641         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
 642         { 0, }
 643 };
 644
 645 MODULE_DEVICE_TABLE(pci, i801_ids);
 646
 647 #if defined CONFIG_X86 && defined CONFIG_DMI
 648 static unsigned char apanel_addr;
 649
 650 /* Scan the system ROM for the signature "FJKEYINF" */
 651 static __init const void __iomem *bios_signature(const void __iomem *bios)
 652 {
 653         ssize_t offset;
 654         const unsigned char signature[] = "FJKEYINF";
 655
 656         for (offset = 0; offset < 0x10000; offset += 0x10) {
 657                 if (check_signature(bios + offset, signature,
 658                                     sizeof(signature)-1))
 659                         return bios + offset;
 660         }
 661         return NULL;
 662 }
 663
 664 static void __init input_apanel_init(void)
 665 {
 666         void __iomem *bios;
 667         const void __iomem *p;
 668
 669         bios = ioremap(0xF0000, 0x10000); /* Can't fail */
 670         p = bios_signature(bios);
 671         if (p) {
 672                 /* just use the first address */
 673                 apanel_addr = readb(p + 8 + 3) >> 1;
 674         }
 675         iounmap(bios);
 676 }
 677
 678 struct dmi_onboard_device_info {
 679         const char *name;
 680         u8 type;
 681         unsigned short i2c_addr;
 682         const char *i2c_type;
 683 };
 684
 685 static struct dmi_onboard_device_info __devinitdata dmi_devices[] = {
 686         { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
 687         { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
 688         { "Hades",  DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
 689 };
 690
 691 static void __devinit dmi_check_onboard_device(u8 type, const char *name,
 692                                                struct i2c_adapter *adap)
 693 {
 694         int i;
 695         struct i2c_board_info info;
 696
 697         for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
 698                 /* & ~0x80, ignore enabled/disabled bit */
 699                 if ((type & ~0x80) != dmi_devices[i].type)
 700                         continue;
 701                 if (strcasecmp(name, dmi_devices[i].name))
 702                         continue;
 703
 704                 memset(&info, 0, sizeof(struct i2c_board_info));
 705                 info.addr = dmi_devices[i].i2c_addr;
 706                 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
 707                 i2c_new_device(adap, &info);
 708                 break;
 709         }
 710 }
 711
 712 /* We use our own function to check for onboard devices instead of
 713    dmi_find_device() as some buggy BIOS's have the devices we are interested
 714    in marked as disabled */
 715 static void __devinit dmi_check_onboard_devices(const struct dmi_header *dm,
 716                                                 void *adap)
 717 {
 718         int i, count;
 719
 720         if (dm->type != 10)
 721                 return;
 722
 723         count = (dm->length - sizeof(struct dmi_header)) / 2;
 724         for (i = 0; i < count; i++) {
 725                 const u8 *d = (char *)(dm + 1) + (i * 2);
 726                 const char *name = ((char *) dm) + dm->length;
 727                 u8 type = d[0];
 728                 u8 s = d[1];
 729
 730                 if (!s)
 731                         continue;
 732                 s--;
 733                 while (s > 0 && name[0]) {
 734                         name += strlen(name) + 1;
 735                         s--;
 736                 }
 737                 if (name[0] == 0) /* Bogus string reference */
 738                         continue;
 739
 740                 dmi_check_onboard_device(type, name, adap);
 741         }
 742 }
 743
 744 /* Register optional slaves */
 745 static void __devinit i801_probe_optional_slaves(struct i801_priv *priv)
 746 {
 747         /* Only register slaves on main SMBus channel */
 748         if (priv->features & FEATURE_IDF)
 749                 return;
 750
 751         if (apanel_addr) {
 752                 struct i2c_board_info info;
 753
 754                 memset(&info, 0, sizeof(struct i2c_board_info));
 755                 info.addr = apanel_addr;
 756                 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
 757                 i2c_new_device(&priv->adapter, &info);
 758         }
 759
 760         if (dmi_name_in_vendors("FUJITSU"))
 761                 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
 762 }
 763 #else
 764 static void __init input_apanel_init(void) {}
 765 static void __devinit i801_probe_optional_slaves(struct i801_priv *priv) {}
 766 #endif  /* CONFIG_X86 && CONFIG_DMI */
 767
 768 static int __devinit i801_probe(struct pci_dev *dev,
 769                                 const struct pci_device_id *id)
 770 {
 771         unsigned char temp;
 772         int err, i;
 773         struct i801_priv *priv;
 774
 775         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 776         if (!priv)
 777                 return -ENOMEM;
 778
 779         i2c_set_adapdata(&priv->adapter, priv);
 780         priv->adapter.owner = THIS_MODULE;
 781         priv->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
 782         priv->adapter.algo = &smbus_algorithm;
 783
 784         priv->pci_dev = dev;
 785         switch (dev->device) {
 786         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
 787         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
 788         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
 789                 priv->features |= FEATURE_IDF;
 790                 /* fall through */
 791         default:
 792                 priv->features |= FEATURE_I2C_BLOCK_READ;
 793                 /* fall through */
 794         case PCI_DEVICE_ID_INTEL_82801DB_3:
 795                 priv->features |= FEATURE_SMBUS_PEC;
 796                 priv->features |= FEATURE_BLOCK_BUFFER;
 797                 /* fall through */
 798         case PCI_DEVICE_ID_INTEL_82801CA_3:
 799         case PCI_DEVICE_ID_INTEL_82801BA_2:
 800         case PCI_DEVICE_ID_INTEL_82801AB_3:
 801         case PCI_DEVICE_ID_INTEL_82801AA_3:
 802                 break;
 803         }
 804
 805         /* Disable features on user request */
 806         for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
 807                 if (priv->features & disable_features & (1 << i))
 808                         dev_notice(&dev->dev, "%s disabled by user\n",
 809                                    i801_feature_names[i]);
 810         }
 811         priv->features &= ~disable_features;
 812
 813         err = pci_enable_device(dev);
 814         if (err) {
 815                 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
 816                         err);
 817                 goto exit;
 818         }
 819
 820         /* Determine the address of the SMBus area */
 821         priv->smba = pci_resource_start(dev, SMBBAR);
 822         if (!priv->smba) {
 823                 dev_err(&dev->dev, "SMBus base address uninitialized, "
 824                         "upgrade BIOS\n");
 825                 err = -ENODEV;
 826                 goto exit;
 827         }
 828
 829         err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
 830         if (err) {
 831                 err = -ENODEV;
 832                 goto exit;
 833         }
 834
 835         err = pci_request_region(dev, SMBBAR, i801_driver.name);
 836         if (err) {
 837                 dev_err(&dev->dev, "Failed to request SMBus region "
 838                         "0x%lx-0x%Lx\n", priv->smba,
 839                         (unsigned long long)pci_resource_end(dev, SMBBAR));
 840                 goto exit;
 841         }
 842
 843         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
 844         priv->original_hstcfg = temp;
 845         temp &= ~SMBHSTCFG_I2C_EN;      /* SMBus timing */
 846         if (!(temp & SMBHSTCFG_HST_EN)) {
 847                 dev_info(&dev->dev, "Enabling SMBus device\n");
 848                 temp |= SMBHSTCFG_HST_EN;
 849         }
 850         pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
 851
 852         if (temp & SMBHSTCFG_SMB_SMI_EN)
 853                 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
 854         else
 855                 dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n");
 856
 857         /* Clear special mode bits */
 858         if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
 859                 outb_p(inb_p(SMBAUXCTL(priv)) &
 860                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
 861
 862         /* set up the sysfs linkage to our parent device */
 863         priv->adapter.dev.parent = &dev->dev;
 864
 865         /* Retry up to 3 times on lost arbitration */
 866         priv->adapter.retries = 3;
 867
 868         snprintf(priv->adapter.name, sizeof(priv->adapter.name),
 869                 "SMBus I801 adapter at %04lx", priv->smba);
 870         err = i2c_add_adapter(&priv->adapter);
 871         if (err) {
 872                 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
 873                 goto exit_release;
 874         }
 875
 876         i801_probe_optional_slaves(priv);
 877
 878         pci_set_drvdata(dev, priv);
 879         return 0;
 880
 881 exit_release:
 882         pci_release_region(dev, SMBBAR);
 883 exit:
 884         kfree(priv);
 885         return err;
 886 }
 887
 888 static void __devexit i801_remove(struct pci_dev *dev)
 889 {
 890         struct i801_priv *priv = pci_get_drvdata(dev);
 891
 892         i2c_del_adapter(&priv->adapter);
 893         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
 894         pci_release_region(dev, SMBBAR);
 895         pci_set_drvdata(dev, NULL);
 896         kfree(priv);
 897         /*
 898          * do not call pci_disable_device(dev) since it can cause hard hangs on
 899          * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
 900          */
 901 }
 902
 903 #ifdef CONFIG_PM
 904 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
 905 {
 906         struct i801_priv *priv = pci_get_drvdata(dev);
 907
 908         pci_save_state(dev);
 909         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
 910         pci_set_power_state(dev, pci_choose_state(dev, mesg));
 911         return 0;
 912 }
 913
 914 static int i801_resume(struct pci_dev *dev)
 915 {
 916         pci_set_power_state(dev, PCI_D0);
 917         pci_restore_state(dev);
 918         return pci_enable_device(dev);
 919 }
 920 #else
 921 #define i801_suspend NULL
 922 #define i801_resume NULL
 923 #endif
 924
 925 static struct pci_driver i801_driver = {
 926         .name           = "i801_smbus",
 927         .id_table       = i801_ids,
 928         .probe          = i801_probe,
 929         .remove         = __devexit_p(i801_remove),
 930         .suspend        = i801_suspend,
 931         .resume         = i801_resume,
 932 };
 933
 934 static int __init i2c_i801_init(void)
 935 {
 936         if (dmi_name_in_vendors("FUJITSU"))
 937                 input_apanel_init();
 938         return pci_register_driver(&i801_driver);
 939 }
 940
 941 static void __exit i2c_i801_exit(void)
 942 {
 943         pci_unregister_driver(&i801_driver);
 944 }
 945
 946 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, "
 947               "Jean Delvare <khali@linux-fr.org>");
 948 MODULE_DESCRIPTION("I801 SMBus driver");
 949 MODULE_LICENSE("GPL");
 950
 951 module_init(i2c_i801_init);
 952 module_exit(i2c_i801_exit);