i2c: i801: Add device ID for Intel Wildcat Point PCH
[pandora-kernel.git] / drivers / i2c / busses / i2c-i801.c
1 /*
2     Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
3     Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
4     <mdsxyz123@yahoo.com>
5     Copyright (C) 2007, 2008   Jean Delvare <khali@linux-fr.org>
6     Copyright (C) 2010         Intel Corporation,
7                                David Woodhouse <dwmw2@infradead.org>
8
9     This program is free software; you can redistribute it and/or modify
10     it under the terms of the GNU General Public License as published by
11     the Free Software Foundation; either version 2 of the License, or
12     (at your option) any later version.
13
14     This program is distributed in the hope that it will be useful,
15     but WITHOUT ANY WARRANTY; without even the implied warranty of
16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17     GNU General Public License for more details.
18
19     You should have received a copy of the GNU General Public License
20     along with this program; if not, write to the Free Software
21     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24 /*
25  * Supports the following Intel I/O Controller Hubs (ICH):
26  *
27  *                                      I/O                     Block   I2C
28  *                                      region  SMBus   Block   proc.   block
29  * Chip name                    PCI ID  size    PEC     buffer  call    read
30  * ---------------------------------------------------------------------------
31  * 82801AA (ICH)                0x2413  16      no      no      no      no
32  * 82801AB (ICH0)               0x2423  16      no      no      no      no
33  * 82801BA (ICH2)               0x2443  16      no      no      no      no
34  * 82801CA (ICH3)               0x2483  32      soft    no      no      no
35  * 82801DB (ICH4)               0x24c3  32      hard    yes     no      no
36  * 82801E (ICH5)                0x24d3  32      hard    yes     yes     yes
37  * 6300ESB                      0x25a4  32      hard    yes     yes     yes
38  * 82801F (ICH6)                0x266a  32      hard    yes     yes     yes
39  * 6310ESB/6320ESB              0x269b  32      hard    yes     yes     yes
40  * 82801G (ICH7)                0x27da  32      hard    yes     yes     yes
41  * 82801H (ICH8)                0x283e  32      hard    yes     yes     yes
42  * 82801I (ICH9)                0x2930  32      hard    yes     yes     yes
43  * EP80579 (Tolapai)            0x5032  32      hard    yes     yes     yes
44  * ICH10                        0x3a30  32      hard    yes     yes     yes
45  * ICH10                        0x3a60  32      hard    yes     yes     yes
46  * 5/3400 Series (PCH)          0x3b30  32      hard    yes     yes     yes
47  * 6 Series (PCH)               0x1c22  32      hard    yes     yes     yes
48  * Patsburg (PCH)               0x1d22  32      hard    yes     yes     yes
49  * Patsburg (PCH) IDF           0x1d70  32      hard    yes     yes     yes
50  * Patsburg (PCH) IDF           0x1d71  32      hard    yes     yes     yes
51  * Patsburg (PCH) IDF           0x1d72  32      hard    yes     yes     yes
52  * DH89xxCC (PCH)               0x2330  32      hard    yes     yes     yes
53  * Panther Point (PCH)          0x1e22  32      hard    yes     yes     yes
54  * Lynx Point (PCH)             0x8c22  32      hard    yes     yes     yes
55  * Lynx Point-LP (PCH)          0x9c22  32      hard    yes     yes     yes
56  * Avoton (SOC)                 0x1f3c  32      hard    yes     yes     yes
57  * Wellsburg (PCH)              0x8d22  32      hard    yes     yes     yes
58  * Wellsburg (PCH) MS           0x8d7d  32      hard    yes     yes     yes
59  * Wellsburg (PCH) MS           0x8d7e  32      hard    yes     yes     yes
60  * Wellsburg (PCH) MS           0x8d7f  32      hard    yes     yes     yes
61  * Coleto Creek (PCH)           0x23b0  32      hard    yes     yes     yes
62  * Wildcat Point (PCH)          0x8ca2  32      hard    yes     yes     yes
63  * Wildcat Point-LP (PCH)       0x9ca2  32      hard    yes     yes     yes
64  * BayTrail (SOC)               0x0f12  32      hard    yes     yes     yes
65  *
66  * Features supported by this driver:
67  * Software PEC                         no
68  * Hardware PEC                         yes
69  * Block buffer                         yes
70  * Block process call transaction       no
71  * I2C block read transaction           yes (doesn't use the block buffer)
72  * Slave mode                           no
73  *
74  * See the file Documentation/i2c/busses/i2c-i801 for details.
75  */
76
77 #include <linux/module.h>
78 #include <linux/pci.h>
79 #include <linux/kernel.h>
80 #include <linux/stddef.h>
81 #include <linux/delay.h>
82 #include <linux/ioport.h>
83 #include <linux/init.h>
84 #include <linux/i2c.h>
85 #include <linux/acpi.h>
86 #include <linux/io.h>
87 #include <linux/dmi.h>
88 #include <linux/slab.h>
89
90 /* I801 SMBus address offsets */
91 #define SMBHSTSTS(p)    (0 + (p)->smba)
92 #define SMBHSTCNT(p)    (2 + (p)->smba)
93 #define SMBHSTCMD(p)    (3 + (p)->smba)
94 #define SMBHSTADD(p)    (4 + (p)->smba)
95 #define SMBHSTDAT0(p)   (5 + (p)->smba)
96 #define SMBHSTDAT1(p)   (6 + (p)->smba)
97 #define SMBBLKDAT(p)    (7 + (p)->smba)
98 #define SMBPEC(p)       (8 + (p)->smba)         /* ICH3 and later */
99 #define SMBAUXSTS(p)    (12 + (p)->smba)        /* ICH4 and later */
100 #define SMBAUXCTL(p)    (13 + (p)->smba)        /* ICH4 and later */
101
102 /* PCI Address Constants */
103 #define SMBBAR          4
104 #define SMBHSTCFG       0x040
105
106 /* Host configuration bits for SMBHSTCFG */
107 #define SMBHSTCFG_HST_EN        1
108 #define SMBHSTCFG_SMB_SMI_EN    2
109 #define SMBHSTCFG_I2C_EN        4
110
111 /* Auxiliary control register bits, ICH4+ only */
112 #define SMBAUXCTL_CRC           1
113 #define SMBAUXCTL_E32B          2
114
115 /* kill bit for SMBHSTCNT */
116 #define SMBHSTCNT_KILL          2
117
118 /* Other settings */
119 #define MAX_TIMEOUT             100
120 #define ENABLE_INT9             0       /* set to 0x01 to enable - untested */
121
122 /* I801 command constants */
123 #define I801_QUICK              0x00
124 #define I801_BYTE               0x04
125 #define I801_BYTE_DATA          0x08
126 #define I801_WORD_DATA          0x0C
127 #define I801_PROC_CALL          0x10    /* unimplemented */
128 #define I801_BLOCK_DATA         0x14
129 #define I801_I2C_BLOCK_DATA     0x18    /* ICH5 and later */
130 #define I801_BLOCK_LAST         0x34
131 #define I801_I2C_BLOCK_LAST     0x38    /* ICH5 and later */
132 #define I801_START              0x40
133 #define I801_PEC_EN             0x80    /* ICH3 and later */
134
135 /* I801 Hosts Status register bits */
136 #define SMBHSTSTS_BYTE_DONE     0x80
137 #define SMBHSTSTS_INUSE_STS     0x40
138 #define SMBHSTSTS_SMBALERT_STS  0x20
139 #define SMBHSTSTS_FAILED        0x10
140 #define SMBHSTSTS_BUS_ERR       0x08
141 #define SMBHSTSTS_DEV_ERR       0x04
142 #define SMBHSTSTS_INTR          0x02
143 #define SMBHSTSTS_HOST_BUSY     0x01
144
145 #define STATUS_FLAGS            (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_FAILED | \
146                                  SMBHSTSTS_BUS_ERR | SMBHSTSTS_DEV_ERR | \
147                                  SMBHSTSTS_INTR)
148
149 /* Older devices have their ID defined in <linux/pci_ids.h> */
150 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS              0x0f12
151 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS           0x1c22
152 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS              0x1d22
153 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
154 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0         0x1d70
155 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1         0x1d71
156 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2         0x1d72
157 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS          0x1e22
158 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS                0x1f3c
159 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS              0x2330
160 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS           0x23b0
161 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS         0x3b30
162 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS             0x8c22
163 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS          0x8ca2
164 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS             0x8d22
165 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0         0x8d7d
166 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1         0x8d7e
167 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2         0x8d7f
168 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS          0x9c22
169 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS       0x9ca2
170
171 struct i801_priv {
172         struct i2c_adapter adapter;
173         unsigned long smba;
174         unsigned char original_hstcfg;
175         struct pci_dev *pci_dev;
176         unsigned int features;
177 };
178
179 static struct pci_driver i801_driver;
180
181 #define FEATURE_SMBUS_PEC       (1 << 0)
182 #define FEATURE_BLOCK_BUFFER    (1 << 1)
183 #define FEATURE_BLOCK_PROC      (1 << 2)
184 #define FEATURE_I2C_BLOCK_READ  (1 << 3)
185 /* Not really a feature, but it's convenient to handle it as such */
186 #define FEATURE_IDF             (1 << 15)
187
188 static const char *i801_feature_names[] = {
189         "SMBus PEC",
190         "Block buffer",
191         "Block process call",
192         "I2C block read",
193 };
194
195 static unsigned int disable_features;
196 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
197 MODULE_PARM_DESC(disable_features, "Disable selected driver features");
198
199 /* Make sure the SMBus host is ready to start transmitting.
200    Return 0 if it is, -EBUSY if it is not. */
201 static int i801_check_pre(struct i801_priv *priv)
202 {
203         int status;
204
205         status = inb_p(SMBHSTSTS(priv));
206         if (status & SMBHSTSTS_HOST_BUSY) {
207                 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
208                 return -EBUSY;
209         }
210
211         status &= STATUS_FLAGS;
212         if (status) {
213                 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
214                         status);
215                 outb_p(status, SMBHSTSTS(priv));
216                 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
217                 if (status) {
218                         dev_err(&priv->pci_dev->dev,
219                                 "Failed clearing status flags (%02x)\n",
220                                 status);
221                         return -EBUSY;
222                 }
223         }
224
225         return 0;
226 }
227
228 /* Convert the status register to an error code, and clear it. */
229 static int i801_check_post(struct i801_priv *priv, int status, int timeout)
230 {
231         int result = 0;
232
233         /* If the SMBus is still busy, we give up */
234         if (timeout) {
235                 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
236                 /* try to stop the current command */
237                 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
238                 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
239                        SMBHSTCNT(priv));
240                 msleep(1);
241                 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
242                        SMBHSTCNT(priv));
243
244                 /* Check if it worked */
245                 status = inb_p(SMBHSTSTS(priv));
246                 if ((status & SMBHSTSTS_HOST_BUSY) ||
247                     !(status & SMBHSTSTS_FAILED))
248                         dev_err(&priv->pci_dev->dev,
249                                 "Failed terminating the transaction\n");
250                 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
251                 return -ETIMEDOUT;
252         }
253
254         if (status & SMBHSTSTS_FAILED) {
255                 result = -EIO;
256                 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
257         }
258         if (status & SMBHSTSTS_DEV_ERR) {
259                 result = -ENXIO;
260                 dev_dbg(&priv->pci_dev->dev, "No response\n");
261         }
262         if (status & SMBHSTSTS_BUS_ERR) {
263                 result = -EAGAIN;
264                 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
265         }
266
267         if (result) {
268                 /* Clear error flags */
269                 outb_p(status & STATUS_FLAGS, SMBHSTSTS(priv));
270                 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
271                 if (status) {
272                         dev_warn(&priv->pci_dev->dev, "Failed clearing status "
273                                  "flags at end of transaction (%02x)\n",
274                                  status);
275                 }
276         }
277
278         return result;
279 }
280
281 static int i801_transaction(struct i801_priv *priv, int xact)
282 {
283         int status;
284         int result;
285         int timeout = 0;
286
287         result = i801_check_pre(priv);
288         if (result < 0)
289                 return result;
290
291         /* the current contents of SMBHSTCNT can be overwritten, since PEC,
292          * INTREN, SMBSCMD are passed in xact */
293         outb_p(xact | I801_START, SMBHSTCNT(priv));
294
295         /* We will always wait for a fraction of a second! */
296         do {
297                 msleep(1);
298                 status = inb_p(SMBHSTSTS(priv));
299         } while ((status & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_TIMEOUT));
300
301         result = i801_check_post(priv, status, timeout > MAX_TIMEOUT);
302         if (result < 0)
303                 return result;
304
305         outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
306         return 0;
307 }
308
309 /* wait for INTR bit as advised by Intel */
310 static void i801_wait_hwpec(struct i801_priv *priv)
311 {
312         int timeout = 0;
313         int status;
314
315         do {
316                 msleep(1);
317                 status = inb_p(SMBHSTSTS(priv));
318         } while ((!(status & SMBHSTSTS_INTR))
319                  && (timeout++ < MAX_TIMEOUT));
320
321         if (timeout > MAX_TIMEOUT)
322                 dev_dbg(&priv->pci_dev->dev, "PEC Timeout!\n");
323
324         outb_p(status, SMBHSTSTS(priv));
325 }
326
327 static int i801_block_transaction_by_block(struct i801_priv *priv,
328                                            union i2c_smbus_data *data,
329                                            char read_write, int hwpec)
330 {
331         int i, len;
332         int status;
333
334         inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
335
336         /* Use 32-byte buffer to process this transaction */
337         if (read_write == I2C_SMBUS_WRITE) {
338                 len = data->block[0];
339                 outb_p(len, SMBHSTDAT0(priv));
340                 for (i = 0; i < len; i++)
341                         outb_p(data->block[i+1], SMBBLKDAT(priv));
342         }
343
344         status = i801_transaction(priv, I801_BLOCK_DATA | ENABLE_INT9 |
345                                   I801_PEC_EN * hwpec);
346         if (status)
347                 return status;
348
349         if (read_write == I2C_SMBUS_READ) {
350                 len = inb_p(SMBHSTDAT0(priv));
351                 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
352                         return -EPROTO;
353
354                 data->block[0] = len;
355                 for (i = 0; i < len; i++)
356                         data->block[i + 1] = inb_p(SMBBLKDAT(priv));
357         }
358         return 0;
359 }
360
361 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
362                                                union i2c_smbus_data *data,
363                                                char read_write, int command,
364                                                int hwpec)
365 {
366         int i, len;
367         int smbcmd;
368         int status;
369         int result;
370         int timeout;
371
372         result = i801_check_pre(priv);
373         if (result < 0)
374                 return result;
375
376         len = data->block[0];
377
378         if (read_write == I2C_SMBUS_WRITE) {
379                 outb_p(len, SMBHSTDAT0(priv));
380                 outb_p(data->block[1], SMBBLKDAT(priv));
381         }
382
383         for (i = 1; i <= len; i++) {
384                 if (i == len && read_write == I2C_SMBUS_READ) {
385                         if (command == I2C_SMBUS_I2C_BLOCK_DATA)
386                                 smbcmd = I801_I2C_BLOCK_LAST;
387                         else
388                                 smbcmd = I801_BLOCK_LAST;
389                 } else {
390                         if (command == I2C_SMBUS_I2C_BLOCK_DATA
391                          && read_write == I2C_SMBUS_READ)
392                                 smbcmd = I801_I2C_BLOCK_DATA;
393                         else
394                                 smbcmd = I801_BLOCK_DATA;
395                 }
396                 outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT(priv));
397
398                 if (i == 1)
399                         outb_p(inb(SMBHSTCNT(priv)) | I801_START,
400                                SMBHSTCNT(priv));
401
402                 /* We will always wait for a fraction of a second! */
403                 timeout = 0;
404                 do {
405                         msleep(1);
406                         status = inb_p(SMBHSTSTS(priv));
407                 } while ((!(status & SMBHSTSTS_BYTE_DONE))
408                          && (timeout++ < MAX_TIMEOUT));
409
410                 result = i801_check_post(priv, status, timeout > MAX_TIMEOUT);
411                 if (result < 0)
412                         return result;
413
414                 if (i == 1 && read_write == I2C_SMBUS_READ
415                  && command != I2C_SMBUS_I2C_BLOCK_DATA) {
416                         len = inb_p(SMBHSTDAT0(priv));
417                         if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
418                                 dev_err(&priv->pci_dev->dev,
419                                         "Illegal SMBus block read size %d\n",
420                                         len);
421                                 /* Recover */
422                                 while (inb_p(SMBHSTSTS(priv)) &
423                                        SMBHSTSTS_HOST_BUSY)
424                                         outb_p(SMBHSTSTS_BYTE_DONE,
425                                                SMBHSTSTS(priv));
426                                 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
427                                 return -EPROTO;
428                         }
429                         data->block[0] = len;
430                 }
431
432                 /* Retrieve/store value in SMBBLKDAT */
433                 if (read_write == I2C_SMBUS_READ)
434                         data->block[i] = inb_p(SMBBLKDAT(priv));
435                 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
436                         outb_p(data->block[i+1], SMBBLKDAT(priv));
437
438                 /* signals SMBBLKDAT ready */
439                 outb_p(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR, SMBHSTSTS(priv));
440         }
441
442         return 0;
443 }
444
445 static int i801_set_block_buffer_mode(struct i801_priv *priv)
446 {
447         outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
448         if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
449                 return -EIO;
450         return 0;
451 }
452
453 /* Block transaction function */
454 static int i801_block_transaction(struct i801_priv *priv,
455                                   union i2c_smbus_data *data, char read_write,
456                                   int command, int hwpec)
457 {
458         int result = 0;
459         unsigned char hostc;
460
461         if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
462                 if (read_write == I2C_SMBUS_WRITE) {
463                         /* set I2C_EN bit in configuration register */
464                         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
465                         pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
466                                               hostc | SMBHSTCFG_I2C_EN);
467                 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
468                         dev_err(&priv->pci_dev->dev,
469                                 "I2C block read is unsupported!\n");
470                         return -EOPNOTSUPP;
471                 }
472         }
473
474         if (read_write == I2C_SMBUS_WRITE
475          || command == I2C_SMBUS_I2C_BLOCK_DATA) {
476                 if (data->block[0] < 1)
477                         data->block[0] = 1;
478                 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
479                         data->block[0] = I2C_SMBUS_BLOCK_MAX;
480         } else {
481                 data->block[0] = 32;    /* max for SMBus block reads */
482         }
483
484         /* Experience has shown that the block buffer can only be used for
485            SMBus (not I2C) block transactions, even though the datasheet
486            doesn't mention this limitation. */
487         if ((priv->features & FEATURE_BLOCK_BUFFER)
488          && command != I2C_SMBUS_I2C_BLOCK_DATA
489          && i801_set_block_buffer_mode(priv) == 0)
490                 result = i801_block_transaction_by_block(priv, data,
491                                                          read_write, hwpec);
492         else
493                 result = i801_block_transaction_byte_by_byte(priv, data,
494                                                              read_write,
495                                                              command, hwpec);
496
497         if (result == 0 && hwpec)
498                 i801_wait_hwpec(priv);
499
500         if (command == I2C_SMBUS_I2C_BLOCK_DATA
501          && read_write == I2C_SMBUS_WRITE) {
502                 /* restore saved configuration register value */
503                 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
504         }
505         return result;
506 }
507
508 /* Return negative errno on error. */
509 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
510                        unsigned short flags, char read_write, u8 command,
511                        int size, union i2c_smbus_data *data)
512 {
513         int hwpec;
514         int block = 0;
515         int ret, xact = 0;
516         struct i801_priv *priv = i2c_get_adapdata(adap);
517
518         hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
519                 && size != I2C_SMBUS_QUICK
520                 && size != I2C_SMBUS_I2C_BLOCK_DATA;
521
522         switch (size) {
523         case I2C_SMBUS_QUICK:
524                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
525                        SMBHSTADD(priv));
526                 xact = I801_QUICK;
527                 break;
528         case I2C_SMBUS_BYTE:
529                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
530                        SMBHSTADD(priv));
531                 if (read_write == I2C_SMBUS_WRITE)
532                         outb_p(command, SMBHSTCMD(priv));
533                 xact = I801_BYTE;
534                 break;
535         case I2C_SMBUS_BYTE_DATA:
536                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
537                        SMBHSTADD(priv));
538                 outb_p(command, SMBHSTCMD(priv));
539                 if (read_write == I2C_SMBUS_WRITE)
540                         outb_p(data->byte, SMBHSTDAT0(priv));
541                 xact = I801_BYTE_DATA;
542                 break;
543         case I2C_SMBUS_WORD_DATA:
544                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
545                        SMBHSTADD(priv));
546                 outb_p(command, SMBHSTCMD(priv));
547                 if (read_write == I2C_SMBUS_WRITE) {
548                         outb_p(data->word & 0xff, SMBHSTDAT0(priv));
549                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
550                 }
551                 xact = I801_WORD_DATA;
552                 break;
553         case I2C_SMBUS_BLOCK_DATA:
554                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
555                        SMBHSTADD(priv));
556                 outb_p(command, SMBHSTCMD(priv));
557                 block = 1;
558                 break;
559         case I2C_SMBUS_I2C_BLOCK_DATA:
560                 /* NB: page 240 of ICH5 datasheet shows that the R/#W
561                  * bit should be cleared here, even when reading */
562                 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
563                 if (read_write == I2C_SMBUS_READ) {
564                         /* NB: page 240 of ICH5 datasheet also shows
565                          * that DATA1 is the cmd field when reading */
566                         outb_p(command, SMBHSTDAT1(priv));
567                 } else
568                         outb_p(command, SMBHSTCMD(priv));
569                 block = 1;
570                 break;
571         default:
572                 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
573                         size);
574                 return -EOPNOTSUPP;
575         }
576
577         if (hwpec)      /* enable/disable hardware PEC */
578                 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
579         else
580                 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
581                        SMBAUXCTL(priv));
582
583         if (block)
584                 ret = i801_block_transaction(priv, data, read_write, size,
585                                              hwpec);
586         else
587                 ret = i801_transaction(priv, xact | ENABLE_INT9);
588
589         /* Some BIOSes don't like it when PEC is enabled at reboot or resume
590            time, so we forcibly disable it after every transaction. Turn off
591            E32B for the same reason. */
592         if (hwpec || block)
593                 outb_p(inb_p(SMBAUXCTL(priv)) &
594                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
595
596         if (block)
597                 return ret;
598         if (ret)
599                 return ret;
600         if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
601                 return 0;
602
603         switch (xact & 0x7f) {
604         case I801_BYTE: /* Result put in SMBHSTDAT0 */
605         case I801_BYTE_DATA:
606                 data->byte = inb_p(SMBHSTDAT0(priv));
607                 break;
608         case I801_WORD_DATA:
609                 data->word = inb_p(SMBHSTDAT0(priv)) +
610                              (inb_p(SMBHSTDAT1(priv)) << 8);
611                 break;
612         }
613         return 0;
614 }
615
616
617 static u32 i801_func(struct i2c_adapter *adapter)
618 {
619         struct i801_priv *priv = i2c_get_adapdata(adapter);
620
621         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
622                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
623                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
624                ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
625                ((priv->features & FEATURE_I2C_BLOCK_READ) ?
626                 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
627 }
628
629 static const struct i2c_algorithm smbus_algorithm = {
630         .smbus_xfer     = i801_access,
631         .functionality  = i801_func,
632 };
633
634 static const struct pci_device_id i801_ids[] = {
635         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
636         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
637         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
638         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
639         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
640         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
641         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
642         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
643         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
644         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
645         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
646         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
647         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
648         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
649         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
650         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
651         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
652         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
653         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
654         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
655         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
656         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
657         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
658         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
659         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
660         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
661         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
662         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
663         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
664         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
665         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
666         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
667         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
668         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
669         { 0, }
670 };
671
672 MODULE_DEVICE_TABLE(pci, i801_ids);
673
674 #if defined CONFIG_X86 && defined CONFIG_DMI
675 static unsigned char apanel_addr;
676
677 /* Scan the system ROM for the signature "FJKEYINF" */
678 static __init const void __iomem *bios_signature(const void __iomem *bios)
679 {
680         ssize_t offset;
681         const unsigned char signature[] = "FJKEYINF";
682
683         for (offset = 0; offset < 0x10000; offset += 0x10) {
684                 if (check_signature(bios + offset, signature,
685                                     sizeof(signature)-1))
686                         return bios + offset;
687         }
688         return NULL;
689 }
690
691 static void __init input_apanel_init(void)
692 {
693         void __iomem *bios;
694         const void __iomem *p;
695
696         bios = ioremap(0xF0000, 0x10000); /* Can't fail */
697         p = bios_signature(bios);
698         if (p) {
699                 /* just use the first address */
700                 apanel_addr = readb(p + 8 + 3) >> 1;
701         }
702         iounmap(bios);
703 }
704
705 struct dmi_onboard_device_info {
706         const char *name;
707         u8 type;
708         unsigned short i2c_addr;
709         const char *i2c_type;
710 };
711
712 static struct dmi_onboard_device_info __devinitdata dmi_devices[] = {
713         { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
714         { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
715         { "Hades",  DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
716 };
717
718 static void __devinit dmi_check_onboard_device(u8 type, const char *name,
719                                                struct i2c_adapter *adap)
720 {
721         int i;
722         struct i2c_board_info info;
723
724         for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
725                 /* & ~0x80, ignore enabled/disabled bit */
726                 if ((type & ~0x80) != dmi_devices[i].type)
727                         continue;
728                 if (strcasecmp(name, dmi_devices[i].name))
729                         continue;
730
731                 memset(&info, 0, sizeof(struct i2c_board_info));
732                 info.addr = dmi_devices[i].i2c_addr;
733                 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
734                 i2c_new_device(adap, &info);
735                 break;
736         }
737 }
738
739 /* We use our own function to check for onboard devices instead of
740    dmi_find_device() as some buggy BIOS's have the devices we are interested
741    in marked as disabled */
742 static void __devinit dmi_check_onboard_devices(const struct dmi_header *dm,
743                                                 void *adap)
744 {
745         int i, count;
746
747         if (dm->type != 10)
748                 return;
749
750         count = (dm->length - sizeof(struct dmi_header)) / 2;
751         for (i = 0; i < count; i++) {
752                 const u8 *d = (char *)(dm + 1) + (i * 2);
753                 const char *name = ((char *) dm) + dm->length;
754                 u8 type = d[0];
755                 u8 s = d[1];
756
757                 if (!s)
758                         continue;
759                 s--;
760                 while (s > 0 && name[0]) {
761                         name += strlen(name) + 1;
762                         s--;
763                 }
764                 if (name[0] == 0) /* Bogus string reference */
765                         continue;
766
767                 dmi_check_onboard_device(type, name, adap);
768         }
769 }
770
771 /* Register optional slaves */
772 static void __devinit i801_probe_optional_slaves(struct i801_priv *priv)
773 {
774         /* Only register slaves on main SMBus channel */
775         if (priv->features & FEATURE_IDF)
776                 return;
777
778         if (apanel_addr) {
779                 struct i2c_board_info info;
780
781                 memset(&info, 0, sizeof(struct i2c_board_info));
782                 info.addr = apanel_addr;
783                 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
784                 i2c_new_device(&priv->adapter, &info);
785         }
786
787         if (dmi_name_in_vendors("FUJITSU"))
788                 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
789 }
790 #else
791 static void __init input_apanel_init(void) {}
792 static void __devinit i801_probe_optional_slaves(struct i801_priv *priv) {}
793 #endif  /* CONFIG_X86 && CONFIG_DMI */
794
795 static int __devinit i801_probe(struct pci_dev *dev,
796                                 const struct pci_device_id *id)
797 {
798         unsigned char temp;
799         int err, i;
800         struct i801_priv *priv;
801
802         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
803         if (!priv)
804                 return -ENOMEM;
805
806         i2c_set_adapdata(&priv->adapter, priv);
807         priv->adapter.owner = THIS_MODULE;
808         priv->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
809         priv->adapter.algo = &smbus_algorithm;
810
811         priv->pci_dev = dev;
812         switch (dev->device) {
813         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
814         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
815         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
816         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
817         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
818         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
819                 priv->features |= FEATURE_IDF;
820                 /* fall through */
821         default:
822                 priv->features |= FEATURE_I2C_BLOCK_READ;
823                 /* fall through */
824         case PCI_DEVICE_ID_INTEL_82801DB_3:
825                 priv->features |= FEATURE_SMBUS_PEC;
826                 priv->features |= FEATURE_BLOCK_BUFFER;
827                 /* fall through */
828         case PCI_DEVICE_ID_INTEL_82801CA_3:
829         case PCI_DEVICE_ID_INTEL_82801BA_2:
830         case PCI_DEVICE_ID_INTEL_82801AB_3:
831         case PCI_DEVICE_ID_INTEL_82801AA_3:
832                 break;
833         }
834
835         /* Disable features on user request */
836         for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
837                 if (priv->features & disable_features & (1 << i))
838                         dev_notice(&dev->dev, "%s disabled by user\n",
839                                    i801_feature_names[i]);
840         }
841         priv->features &= ~disable_features;
842
843         err = pci_enable_device(dev);
844         if (err) {
845                 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
846                         err);
847                 goto exit;
848         }
849
850         /* Determine the address of the SMBus area */
851         priv->smba = pci_resource_start(dev, SMBBAR);
852         if (!priv->smba) {
853                 dev_err(&dev->dev, "SMBus base address uninitialized, "
854                         "upgrade BIOS\n");
855                 err = -ENODEV;
856                 goto exit;
857         }
858
859         err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
860         if (err) {
861                 err = -ENODEV;
862                 goto exit;
863         }
864
865         err = pci_request_region(dev, SMBBAR, i801_driver.name);
866         if (err) {
867                 dev_err(&dev->dev, "Failed to request SMBus region "
868                         "0x%lx-0x%Lx\n", priv->smba,
869                         (unsigned long long)pci_resource_end(dev, SMBBAR));
870                 goto exit;
871         }
872
873         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
874         priv->original_hstcfg = temp;
875         temp &= ~SMBHSTCFG_I2C_EN;      /* SMBus timing */
876         if (!(temp & SMBHSTCFG_HST_EN)) {
877                 dev_info(&dev->dev, "Enabling SMBus device\n");
878                 temp |= SMBHSTCFG_HST_EN;
879         }
880         pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
881
882         if (temp & SMBHSTCFG_SMB_SMI_EN)
883                 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
884         else
885                 dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n");
886
887         /* Clear special mode bits */
888         if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
889                 outb_p(inb_p(SMBAUXCTL(priv)) &
890                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
891
892         /* set up the sysfs linkage to our parent device */
893         priv->adapter.dev.parent = &dev->dev;
894
895         /* Retry up to 3 times on lost arbitration */
896         priv->adapter.retries = 3;
897
898         snprintf(priv->adapter.name, sizeof(priv->adapter.name),
899                 "SMBus I801 adapter at %04lx", priv->smba);
900         err = i2c_add_adapter(&priv->adapter);
901         if (err) {
902                 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
903                 goto exit_release;
904         }
905
906         i801_probe_optional_slaves(priv);
907
908         pci_set_drvdata(dev, priv);
909         return 0;
910
911 exit_release:
912         pci_release_region(dev, SMBBAR);
913 exit:
914         kfree(priv);
915         return err;
916 }
917
918 static void __devexit i801_remove(struct pci_dev *dev)
919 {
920         struct i801_priv *priv = pci_get_drvdata(dev);
921
922         i2c_del_adapter(&priv->adapter);
923         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
924         pci_release_region(dev, SMBBAR);
925         pci_set_drvdata(dev, NULL);
926         kfree(priv);
927         /*
928          * do not call pci_disable_device(dev) since it can cause hard hangs on
929          * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
930          */
931 }
932
933 #ifdef CONFIG_PM
934 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
935 {
936         struct i801_priv *priv = pci_get_drvdata(dev);
937
938         pci_save_state(dev);
939         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
940         pci_set_power_state(dev, pci_choose_state(dev, mesg));
941         return 0;
942 }
943
944 static int i801_resume(struct pci_dev *dev)
945 {
946         pci_set_power_state(dev, PCI_D0);
947         pci_restore_state(dev);
948         return pci_enable_device(dev);
949 }
950 #else
951 #define i801_suspend NULL
952 #define i801_resume NULL
953 #endif
954
955 static struct pci_driver i801_driver = {
956         .name           = "i801_smbus",
957         .id_table       = i801_ids,
958         .probe          = i801_probe,
959         .remove         = __devexit_p(i801_remove),
960         .suspend        = i801_suspend,
961         .resume         = i801_resume,
962 };
963
964 static int __init i2c_i801_init(void)
965 {
966         if (dmi_name_in_vendors("FUJITSU"))
967                 input_apanel_init();
968         return pci_register_driver(&i801_driver);
969 }
970
971 static void __exit i2c_i801_exit(void)
972 {
973         pci_unregister_driver(&i801_driver);
974 }
975
976 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, "
977               "Jean Delvare <khali@linux-fr.org>");
978 MODULE_DESCRIPTION("I801 SMBus driver");
979 MODULE_LICENSE("GPL");
980
981 module_init(i2c_i801_init);
982 module_exit(i2c_i801_exit);