drivers/i2c/busses/i2c-i801.c

   1 /*
   2     Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
   3     Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
   4     <mdsxyz123@yahoo.com>
   5     Copyright (C) 2007 - 2012  Jean Delvare <jdelvare@suse.de>
   6     Copyright (C) 2010         Intel Corporation,
   7                                David Woodhouse <dwmw2@infradead.org>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18
  19     You should have received a copy of the GNU General Public License
  20     along with this program; if not, write to the Free Software
  21     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22 */
  23
  24 /*
  25  * Supports the following Intel I/O Controller Hubs (ICH):
  26  *
  27  *                                      I/O                     Block   I2C
  28  *                                      region  SMBus   Block   proc.   block
  29  * Chip name                    PCI ID  size    PEC     buffer  call    read
  30  * ---------------------------------------------------------------------------
  31  * 82801AA (ICH)                0x2413  16      no      no      no      no
  32  * 82801AB (ICH0)               0x2423  16      no      no      no      no
  33  * 82801BA (ICH2)               0x2443  16      no      no      no      no
  34  * 82801CA (ICH3)               0x2483  32      soft    no      no      no
  35  * 82801DB (ICH4)               0x24c3  32      hard    yes     no      no
  36  * 82801E (ICH5)                0x24d3  32      hard    yes     yes     yes
  37  * 6300ESB                      0x25a4  32      hard    yes     yes     yes
  38  * 82801F (ICH6)                0x266a  32      hard    yes     yes     yes
  39  * 6310ESB/6320ESB              0x269b  32      hard    yes     yes     yes
  40  * 82801G (ICH7)                0x27da  32      hard    yes     yes     yes
  41  * 82801H (ICH8)                0x283e  32      hard    yes     yes     yes
  42  * 82801I (ICH9)                0x2930  32      hard    yes     yes     yes
  43  * EP80579 (Tolapai)            0x5032  32      hard    yes     yes     yes
  44  * ICH10                        0x3a30  32      hard    yes     yes     yes
  45  * ICH10                        0x3a60  32      hard    yes     yes     yes
  46  * 5/3400 Series (PCH)          0x3b30  32      hard    yes     yes     yes
  47  * 6 Series (PCH)               0x1c22  32      hard    yes     yes     yes
  48  * Patsburg (PCH)               0x1d22  32      hard    yes     yes     yes
  49  * Patsburg (PCH) IDF           0x1d70  32      hard    yes     yes     yes
  50  * Patsburg (PCH) IDF           0x1d71  32      hard    yes     yes     yes
  51  * Patsburg (PCH) IDF           0x1d72  32      hard    yes     yes     yes
  52  * DH89xxCC (PCH)               0x2330  32      hard    yes     yes     yes
  53  * Panther Point (PCH)          0x1e22  32      hard    yes     yes     yes
  54  * Lynx Point (PCH)             0x8c22  32      hard    yes     yes     yes
  55  * Lynx Point-LP (PCH)          0x9c22  32      hard    yes     yes     yes
  56  * Avoton (SOC)                 0x1f3c  32      hard    yes     yes     yes
  57  * Wellsburg (PCH)              0x8d22  32      hard    yes     yes     yes
  58  * Wellsburg (PCH) MS           0x8d7d  32      hard    yes     yes     yes
  59  * Wellsburg (PCH) MS           0x8d7e  32      hard    yes     yes     yes
  60  * Wellsburg (PCH) MS           0x8d7f  32      hard    yes     yes     yes
  61  * Coleto Creek (PCH)           0x23b0  32      hard    yes     yes     yes
  62  * Wildcat Point (PCH)          0x8ca2  32      hard    yes     yes     yes
  63  * Wildcat Point-LP (PCH)       0x9ca2  32      hard    yes     yes     yes
  64  * BayTrail (SOC)               0x0f12  32      hard    yes     yes     yes
  65  *
  66  * Features supported by this driver:
  67  * Software PEC                         no
  68  * Hardware PEC                         yes
  69  * Block buffer                         yes
  70  * Block process call transaction       no
  71  * I2C block read transaction           yes (doesn't use the block buffer)
  72  * Slave mode                           no
  73  * Interrupt processing                 yes
  74  *
  75  * See the file Documentation/i2c/busses/i2c-i801 for details.
  76  */
  77
  78 #include <linux/interrupt.h>
  79 #include <linux/module.h>
  80 #include <linux/pci.h>
  81 #include <linux/kernel.h>
  82 #include <linux/stddef.h>
  83 #include <linux/delay.h>
  84 #include <linux/ioport.h>
  85 #include <linux/init.h>
  86 #include <linux/i2c.h>
  87 #include <linux/acpi.h>
  88 #include <linux/io.h>
  89 #include <linux/dmi.h>
  90 #include <linux/slab.h>
  91 #include <linux/wait.h>
  92 #include <linux/err.h>
  93
  94 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
  95                 defined CONFIG_DMI
  96 #include <linux/gpio.h>
  97 #include <linux/i2c-mux-gpio.h>
  98 #include <linux/platform_device.h>
  99 #endif
 100
 101 /* I801 SMBus address offsets */
 102 #define SMBHSTSTS(p)    (0 + (p)->smba)
 103 #define SMBHSTCNT(p)    (2 + (p)->smba)
 104 #define SMBHSTCMD(p)    (3 + (p)->smba)
 105 #define SMBHSTADD(p)    (4 + (p)->smba)
 106 #define SMBHSTDAT0(p)   (5 + (p)->smba)
 107 #define SMBHSTDAT1(p)   (6 + (p)->smba)
 108 #define SMBBLKDAT(p)    (7 + (p)->smba)
 109 #define SMBPEC(p)       (8 + (p)->smba)         /* ICH3 and later */
 110 #define SMBAUXSTS(p)    (12 + (p)->smba)        /* ICH4 and later */
 111 #define SMBAUXCTL(p)    (13 + (p)->smba)        /* ICH4 and later */
 112
 113 /* PCI Address Constants */
 114 #define SMBBAR          4
 115 #define SMBPCISTS       0x006
 116 #define SMBHSTCFG       0x040
 117
 118 /* Host status bits for SMBPCISTS */
 119 #define SMBPCISTS_INTS          0x08
 120
 121 /* Host configuration bits for SMBHSTCFG */
 122 #define SMBHSTCFG_HST_EN        1
 123 #define SMBHSTCFG_SMB_SMI_EN    2
 124 #define SMBHSTCFG_I2C_EN        4
 125
 126 /* Auxiliary control register bits, ICH4+ only */
 127 #define SMBAUXCTL_CRC           1
 128 #define SMBAUXCTL_E32B          2
 129
 130 /* Other settings */
 131 #define MAX_RETRIES             400
 132
 133 /* I801 command constants */
 134 #define I801_QUICK              0x00
 135 #define I801_BYTE               0x04
 136 #define I801_BYTE_DATA          0x08
 137 #define I801_WORD_DATA          0x0C
 138 #define I801_PROC_CALL          0x10    /* unimplemented */
 139 #define I801_BLOCK_DATA         0x14
 140 #define I801_I2C_BLOCK_DATA     0x18    /* ICH5 and later */
 141
 142 /* I801 Host Control register bits */
 143 #define SMBHSTCNT_INTREN        0x01
 144 #define SMBHSTCNT_KILL          0x02
 145 #define SMBHSTCNT_LAST_BYTE     0x20
 146 #define SMBHSTCNT_START         0x40
 147 #define SMBHSTCNT_PEC_EN        0x80    /* ICH3 and later */
 148
 149 /* I801 Hosts Status register bits */
 150 #define SMBHSTSTS_BYTE_DONE     0x80
 151 #define SMBHSTSTS_INUSE_STS     0x40
 152 #define SMBHSTSTS_SMBALERT_STS  0x20
 153 #define SMBHSTSTS_FAILED        0x10
 154 #define SMBHSTSTS_BUS_ERR       0x08
 155 #define SMBHSTSTS_DEV_ERR       0x04
 156 #define SMBHSTSTS_INTR          0x02
 157 #define SMBHSTSTS_HOST_BUSY     0x01
 158
 159 #define STATUS_ERROR_FLAGS      (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
 160                                  SMBHSTSTS_DEV_ERR)
 161
 162 #define STATUS_FLAGS            (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
 163                                  STATUS_ERROR_FLAGS)
 164
 165 /* Older devices have their ID defined in <linux/pci_ids.h> */
 166 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS              0x0f12
 167 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS           0x1c22
 168 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS              0x1d22
 169 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
 170 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0         0x1d70
 171 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1         0x1d71
 172 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2         0x1d72
 173 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS          0x1e22
 174 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS                0x1f3c
 175 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS              0x2330
 176 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS           0x23b0
 177 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS         0x3b30
 178 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS             0x8c22
 179 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS          0x8ca2
 180 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS             0x8d22
 181 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0         0x8d7d
 182 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1         0x8d7e
 183 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2         0x8d7f
 184 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS          0x9c22
 185 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS       0x9ca2
 186
 187 struct i801_mux_config {
 188         char *gpio_chip;
 189         unsigned values[3];
 190         int n_values;
 191         unsigned classes[3];
 192         unsigned gpios[2];              /* Relative to gpio_chip->base */
 193         int n_gpios;
 194 };
 195
 196 struct i801_priv {
 197         struct i2c_adapter adapter;
 198         unsigned long smba;
 199         unsigned char original_hstcfg;
 200         struct pci_dev *pci_dev;
 201         unsigned int features;
 202
 203         /* isr processing */
 204         wait_queue_head_t waitq;
 205         u8 status;
 206
 207         /* Command state used by isr for byte-by-byte block transactions */
 208         u8 cmd;
 209         bool is_read;
 210         int count;
 211         int len;
 212         u8 *data;
 213
 214 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
 215                 defined CONFIG_DMI
 216         const struct i801_mux_config *mux_drvdata;
 217         struct platform_device *mux_pdev;
 218 #endif
 219 };
 220
 221 static struct pci_driver i801_driver;
 222
 223 #define FEATURE_SMBUS_PEC       (1 << 0)
 224 #define FEATURE_BLOCK_BUFFER    (1 << 1)
 225 #define FEATURE_BLOCK_PROC      (1 << 2)
 226 #define FEATURE_I2C_BLOCK_READ  (1 << 3)
 227 #define FEATURE_IRQ             (1 << 4)
 228 /* Not really a feature, but it's convenient to handle it as such */
 229 #define FEATURE_IDF             (1 << 15)
 230
 231 static const char *i801_feature_names[] = {
 232         "SMBus PEC",
 233         "Block buffer",
 234         "Block process call",
 235         "I2C block read",
 236         "Interrupt",
 237 };
 238
 239 static unsigned int disable_features;
 240 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
 241 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
 242         "\t\t  0x01  disable SMBus PEC\n"
 243         "\t\t  0x02  disable the block buffer\n"
 244         "\t\t  0x08  disable the I2C block read functionality\n"
 245         "\t\t  0x10  don't use interrupts ");
 246
 247 /* Make sure the SMBus host is ready to start transmitting.
 248    Return 0 if it is, -EBUSY if it is not. */
 249 static int i801_check_pre(struct i801_priv *priv)
 250 {
 251         int status;
 252
 253         status = inb_p(SMBHSTSTS(priv));
 254         if (status & SMBHSTSTS_HOST_BUSY) {
 255                 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
 256                 return -EBUSY;
 257         }
 258
 259         status &= STATUS_FLAGS;
 260         if (status) {
 261                 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
 262                         status);
 263                 outb_p(status, SMBHSTSTS(priv));
 264                 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
 265                 if (status) {
 266                         dev_err(&priv->pci_dev->dev,
 267                                 "Failed clearing status flags (%02x)\n",
 268                                 status);
 269                         return -EBUSY;
 270                 }
 271         }
 272
 273         return 0;
 274 }
 275
 276 /*
 277  * Convert the status register to an error code, and clear it.
 278  * Note that status only contains the bits we want to clear, not the
 279  * actual register value.
 280  */
 281 static int i801_check_post(struct i801_priv *priv, int status)
 282 {
 283         int result = 0;
 284
 285         /*
 286          * If the SMBus is still busy, we give up
 287          * Note: This timeout condition only happens when using polling
 288          * transactions.  For interrupt operation, NAK/timeout is indicated by
 289          * DEV_ERR.
 290          */
 291         if (unlikely(status < 0)) {
 292                 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
 293                 /* try to stop the current command */
 294                 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
 295                 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
 296                        SMBHSTCNT(priv));
 297                 usleep_range(1000, 2000);
 298                 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
 299                        SMBHSTCNT(priv));
 300
 301                 /* Check if it worked */
 302                 status = inb_p(SMBHSTSTS(priv));
 303                 if ((status & SMBHSTSTS_HOST_BUSY) ||
 304                     !(status & SMBHSTSTS_FAILED))
 305                         dev_err(&priv->pci_dev->dev,
 306                                 "Failed terminating the transaction\n");
 307                 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
 308                 return -ETIMEDOUT;
 309         }
 310
 311         if (status & SMBHSTSTS_FAILED) {
 312                 result = -EIO;
 313                 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
 314         }
 315         if (status & SMBHSTSTS_DEV_ERR) {
 316                 result = -ENXIO;
 317                 dev_dbg(&priv->pci_dev->dev, "No response\n");
 318         }
 319         if (status & SMBHSTSTS_BUS_ERR) {
 320                 result = -EAGAIN;
 321                 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
 322         }
 323
 324         /* Clear status flags except BYTE_DONE, to be cleared by caller */
 325         outb_p(status, SMBHSTSTS(priv));
 326
 327         return result;
 328 }
 329
 330 /* Wait for BUSY being cleared and either INTR or an error flag being set */
 331 static int i801_wait_intr(struct i801_priv *priv)
 332 {
 333         int timeout = 0;
 334         int status;
 335
 336         /* We will always wait for a fraction of a second! */
 337         do {
 338                 usleep_range(250, 500);
 339                 status = inb_p(SMBHSTSTS(priv));
 340         } while (((status & SMBHSTSTS_HOST_BUSY) ||
 341                   !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
 342                  (timeout++ < MAX_RETRIES));
 343
 344         if (timeout > MAX_RETRIES) {
 345                 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
 346                 return -ETIMEDOUT;
 347         }
 348         return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
 349 }
 350
 351 /* Wait for either BYTE_DONE or an error flag being set */
 352 static int i801_wait_byte_done(struct i801_priv *priv)
 353 {
 354         int timeout = 0;
 355         int status;
 356
 357         /* We will always wait for a fraction of a second! */
 358         do {
 359                 usleep_range(250, 500);
 360                 status = inb_p(SMBHSTSTS(priv));
 361         } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
 362                  (timeout++ < MAX_RETRIES));
 363
 364         if (timeout > MAX_RETRIES) {
 365                 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
 366                 return -ETIMEDOUT;
 367         }
 368         return status & STATUS_ERROR_FLAGS;
 369 }
 370
 371 static int i801_transaction(struct i801_priv *priv, int xact)
 372 {
 373         int status;
 374         int result;
 375
 376         result = i801_check_pre(priv);
 377         if (result < 0)
 378                 return result;
 379
 380         if (priv->features & FEATURE_IRQ) {
 381                 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
 382                        SMBHSTCNT(priv));
 383                 wait_event(priv->waitq, (status = priv->status));
 384                 priv->status = 0;
 385                 return i801_check_post(priv, status);
 386         }
 387
 388         /* the current contents of SMBHSTCNT can be overwritten, since PEC,
 389          * SMBSCMD are passed in xact */
 390         outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
 391
 392         status = i801_wait_intr(priv);
 393         return i801_check_post(priv, status);
 394 }
 395
 396 static int i801_block_transaction_by_block(struct i801_priv *priv,
 397                                            union i2c_smbus_data *data,
 398                                            char read_write, int hwpec)
 399 {
 400         int i, len;
 401         int status;
 402
 403         inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
 404
 405         /* Use 32-byte buffer to process this transaction */
 406         if (read_write == I2C_SMBUS_WRITE) {
 407                 len = data->block[0];
 408                 outb_p(len, SMBHSTDAT0(priv));
 409                 for (i = 0; i < len; i++)
 410                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 411         }
 412
 413         status = i801_transaction(priv, I801_BLOCK_DATA |
 414                                   (hwpec ? SMBHSTCNT_PEC_EN : 0));
 415         if (status)
 416                 return status;
 417
 418         if (read_write == I2C_SMBUS_READ) {
 419                 len = inb_p(SMBHSTDAT0(priv));
 420                 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
 421                         return -EPROTO;
 422
 423                 data->block[0] = len;
 424                 for (i = 0; i < len; i++)
 425                         data->block[i + 1] = inb_p(SMBBLKDAT(priv));
 426         }
 427         return 0;
 428 }
 429
 430 static void i801_isr_byte_done(struct i801_priv *priv)
 431 {
 432         if (priv->is_read) {
 433                 /* For SMBus block reads, length is received with first byte */
 434                 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
 435                     (priv->count == 0)) {
 436                         priv->len = inb_p(SMBHSTDAT0(priv));
 437                         if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
 438                                 dev_err(&priv->pci_dev->dev,
 439                                         "Illegal SMBus block read size %d\n",
 440                                         priv->len);
 441                                 /* FIXME: Recover */
 442                                 priv->len = I2C_SMBUS_BLOCK_MAX;
 443                         } else {
 444                                 dev_dbg(&priv->pci_dev->dev,
 445                                         "SMBus block read size is %d\n",
 446                                         priv->len);
 447                         }
 448                         priv->data[-1] = priv->len;
 449                 }
 450
 451                 /* Read next byte */
 452                 if (priv->count < priv->len)
 453                         priv->data[priv->count++] = inb(SMBBLKDAT(priv));
 454                 else
 455                         dev_dbg(&priv->pci_dev->dev,
 456                                 "Discarding extra byte on block read\n");
 457
 458                 /* Set LAST_BYTE for last byte of read transaction */
 459                 if (priv->count == priv->len - 1)
 460                         outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
 461                                SMBHSTCNT(priv));
 462         } else if (priv->count < priv->len - 1) {
 463                 /* Write next byte, except for IRQ after last byte */
 464                 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
 465         }
 466
 467         /* Clear BYTE_DONE to continue with next byte */
 468         outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 469 }
 470
 471 /*
 472  * There are two kinds of interrupts:
 473  *
 474  * 1) i801 signals transaction completion with one of these interrupts:
 475  *      INTR - Success
 476  *      DEV_ERR - Invalid command, NAK or communication timeout
 477  *      BUS_ERR - SMI# transaction collision
 478  *      FAILED - transaction was canceled due to a KILL request
 479  *    When any of these occur, update ->status and wake up the waitq.
 480  *    ->status must be cleared before kicking off the next transaction.
 481  *
 482  * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
 483  *    occurs for each byte of a byte-by-byte to prepare the next byte.
 484  */
 485 static irqreturn_t i801_isr(int irq, void *dev_id)
 486 {
 487         struct i801_priv *priv = dev_id;
 488         u16 pcists;
 489         u8 status;
 490
 491         /* Confirm this is our interrupt */
 492         pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
 493         if (!(pcists & SMBPCISTS_INTS))
 494                 return IRQ_NONE;
 495
 496         status = inb_p(SMBHSTSTS(priv));
 497         if (status != 0x42)
 498                 dev_dbg(&priv->pci_dev->dev, "irq: status = %02x\n", status);
 499
 500         if (status & SMBHSTSTS_BYTE_DONE)
 501                 i801_isr_byte_done(priv);
 502
 503         /*
 504          * Clear irq sources and report transaction result.
 505          * ->status must be cleared before the next transaction is started.
 506          */
 507         status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
 508         if (status) {
 509                 outb_p(status, SMBHSTSTS(priv));
 510                 priv->status |= status;
 511                 wake_up(&priv->waitq);
 512         }
 513
 514         return IRQ_HANDLED;
 515 }
 516
 517 /*
 518  * For "byte-by-byte" block transactions:
 519  *   I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
 520  *   I2C read uses cmd=I801_I2C_BLOCK_DATA
 521  */
 522 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
 523                                                union i2c_smbus_data *data,
 524                                                char read_write, int command,
 525                                                int hwpec)
 526 {
 527         int i, len;
 528         int smbcmd;
 529         int status;
 530         int result;
 531
 532         result = i801_check_pre(priv);
 533         if (result < 0)
 534                 return result;
 535
 536         len = data->block[0];
 537
 538         if (read_write == I2C_SMBUS_WRITE) {
 539                 outb_p(len, SMBHSTDAT0(priv));
 540                 outb_p(data->block[1], SMBBLKDAT(priv));
 541         }
 542
 543         if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
 544             read_write == I2C_SMBUS_READ)
 545                 smbcmd = I801_I2C_BLOCK_DATA;
 546         else
 547                 smbcmd = I801_BLOCK_DATA;
 548
 549         if (priv->features & FEATURE_IRQ) {
 550                 priv->is_read = (read_write == I2C_SMBUS_READ);
 551                 if (len == 1 && priv->is_read)
 552                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 553                 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
 554                 priv->len = len;
 555                 priv->count = 0;
 556                 priv->data = &data->block[1];
 557
 558                 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
 559                 wait_event(priv->waitq, (status = priv->status));
 560                 priv->status = 0;
 561                 return i801_check_post(priv, status);
 562         }
 563
 564         for (i = 1; i <= len; i++) {
 565                 if (i == len && read_write == I2C_SMBUS_READ)
 566                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 567                 outb_p(smbcmd, SMBHSTCNT(priv));
 568
 569                 if (i == 1)
 570                         outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
 571                                SMBHSTCNT(priv));
 572
 573                 status = i801_wait_byte_done(priv);
 574                 if (status)
 575                         goto exit;
 576
 577                 if (i == 1 && read_write == I2C_SMBUS_READ
 578                  && command != I2C_SMBUS_I2C_BLOCK_DATA) {
 579                         len = inb_p(SMBHSTDAT0(priv));
 580                         if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
 581                                 dev_err(&priv->pci_dev->dev,
 582                                         "Illegal SMBus block read size %d\n",
 583                                         len);
 584                                 /* Recover */
 585                                 while (inb_p(SMBHSTSTS(priv)) &
 586                                        SMBHSTSTS_HOST_BUSY)
 587                                         outb_p(SMBHSTSTS_BYTE_DONE,
 588                                                SMBHSTSTS(priv));
 589                                 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 590                                 return -EPROTO;
 591                         }
 592                         data->block[0] = len;
 593                 }
 594
 595                 /* Retrieve/store value in SMBBLKDAT */
 596                 if (read_write == I2C_SMBUS_READ)
 597                         data->block[i] = inb_p(SMBBLKDAT(priv));
 598                 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
 599                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 600
 601                 /* signals SMBBLKDAT ready */
 602                 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 603         }
 604
 605         status = i801_wait_intr(priv);
 606 exit:
 607         return i801_check_post(priv, status);
 608 }
 609
 610 static int i801_set_block_buffer_mode(struct i801_priv *priv)
 611 {
 612         outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
 613         if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
 614                 return -EIO;
 615         return 0;
 616 }
 617
 618 /* Block transaction function */
 619 static int i801_block_transaction(struct i801_priv *priv,
 620                                   union i2c_smbus_data *data, char read_write,
 621                                   int command, int hwpec)
 622 {
 623         int result = 0;
 624         unsigned char hostc;
 625
 626         if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
 627                 if (read_write == I2C_SMBUS_WRITE) {
 628                         /* set I2C_EN bit in configuration register */
 629                         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
 630                         pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
 631                                               hostc | SMBHSTCFG_I2C_EN);
 632                 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
 633                         dev_err(&priv->pci_dev->dev,
 634                                 "I2C block read is unsupported!\n");
 635                         return -EOPNOTSUPP;
 636                 }
 637         }
 638
 639         if (read_write == I2C_SMBUS_WRITE
 640          || command == I2C_SMBUS_I2C_BLOCK_DATA) {
 641                 if (data->block[0] < 1)
 642                         data->block[0] = 1;
 643                 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
 644                         data->block[0] = I2C_SMBUS_BLOCK_MAX;
 645         } else {
 646                 data->block[0] = 32;    /* max for SMBus block reads */
 647         }
 648
 649         /* Experience has shown that the block buffer can only be used for
 650            SMBus (not I2C) block transactions, even though the datasheet
 651            doesn't mention this limitation. */
 652         if ((priv->features & FEATURE_BLOCK_BUFFER)
 653          && command != I2C_SMBUS_I2C_BLOCK_DATA
 654          && i801_set_block_buffer_mode(priv) == 0)
 655                 result = i801_block_transaction_by_block(priv, data,
 656                                                          read_write, hwpec);
 657         else
 658                 result = i801_block_transaction_byte_by_byte(priv, data,
 659                                                              read_write,
 660                                                              command, hwpec);
 661
 662         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 663          && read_write == I2C_SMBUS_WRITE) {
 664                 /* restore saved configuration register value */
 665                 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
 666         }
 667         return result;
 668 }
 669
 670 /* Return negative errno on error. */
 671 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
 672                        unsigned short flags, char read_write, u8 command,
 673                        int size, union i2c_smbus_data *data)
 674 {
 675         int hwpec;
 676         int block = 0;
 677         int ret, xact = 0;
 678         struct i801_priv *priv = i2c_get_adapdata(adap);
 679
 680         hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
 681                 && size != I2C_SMBUS_QUICK
 682                 && size != I2C_SMBUS_I2C_BLOCK_DATA;
 683
 684         switch (size) {
 685         case I2C_SMBUS_QUICK:
 686                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 687                        SMBHSTADD(priv));
 688                 xact = I801_QUICK;
 689                 break;
 690         case I2C_SMBUS_BYTE:
 691                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 692                        SMBHSTADD(priv));
 693                 if (read_write == I2C_SMBUS_WRITE)
 694                         outb_p(command, SMBHSTCMD(priv));
 695                 xact = I801_BYTE;
 696                 break;
 697         case I2C_SMBUS_BYTE_DATA:
 698                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 699                        SMBHSTADD(priv));
 700                 outb_p(command, SMBHSTCMD(priv));
 701                 if (read_write == I2C_SMBUS_WRITE)
 702                         outb_p(data->byte, SMBHSTDAT0(priv));
 703                 xact = I801_BYTE_DATA;
 704                 break;
 705         case I2C_SMBUS_WORD_DATA:
 706                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 707                        SMBHSTADD(priv));
 708                 outb_p(command, SMBHSTCMD(priv));
 709                 if (read_write == I2C_SMBUS_WRITE) {
 710                         outb_p(data->word & 0xff, SMBHSTDAT0(priv));
 711                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
 712                 }
 713                 xact = I801_WORD_DATA;
 714                 break;
 715         case I2C_SMBUS_BLOCK_DATA:
 716                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 717                        SMBHSTADD(priv));
 718                 outb_p(command, SMBHSTCMD(priv));
 719                 block = 1;
 720                 break;
 721         case I2C_SMBUS_I2C_BLOCK_DATA:
 722                 /* NB: page 240 of ICH5 datasheet shows that the R/#W
 723                  * bit should be cleared here, even when reading */
 724                 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
 725                 if (read_write == I2C_SMBUS_READ) {
 726                         /* NB: page 240 of ICH5 datasheet also shows
 727                          * that DATA1 is the cmd field when reading */
 728                         outb_p(command, SMBHSTDAT1(priv));
 729                 } else
 730                         outb_p(command, SMBHSTCMD(priv));
 731                 block = 1;
 732                 break;
 733         default:
 734                 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
 735                         size);
 736                 return -EOPNOTSUPP;
 737         }
 738
 739         if (hwpec)      /* enable/disable hardware PEC */
 740                 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
 741         else
 742                 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
 743                        SMBAUXCTL(priv));
 744
 745         if (block)
 746                 ret = i801_block_transaction(priv, data, read_write, size,
 747                                              hwpec);
 748         else
 749                 ret = i801_transaction(priv, xact);
 750
 751         /* Some BIOSes don't like it when PEC is enabled at reboot or resume
 752            time, so we forcibly disable it after every transaction. Turn off
 753            E32B for the same reason. */
 754         if (hwpec || block)
 755                 outb_p(inb_p(SMBAUXCTL(priv)) &
 756                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
 757
 758         if (block)
 759                 return ret;
 760         if (ret)
 761                 return ret;
 762         if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
 763                 return 0;
 764
 765         switch (xact & 0x7f) {
 766         case I801_BYTE: /* Result put in SMBHSTDAT0 */
 767         case I801_BYTE_DATA:
 768                 data->byte = inb_p(SMBHSTDAT0(priv));
 769                 break;
 770         case I801_WORD_DATA:
 771                 data->word = inb_p(SMBHSTDAT0(priv)) +
 772                              (inb_p(SMBHSTDAT1(priv)) << 8);
 773                 break;
 774         }
 775         return 0;
 776 }
 777
 778
 779 static u32 i801_func(struct i2c_adapter *adapter)
 780 {
 781         struct i801_priv *priv = i2c_get_adapdata(adapter);
 782
 783         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 784                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 785                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
 786                ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
 787                ((priv->features & FEATURE_I2C_BLOCK_READ) ?
 788                 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
 789 }
 790
 791 static const struct i2c_algorithm smbus_algorithm = {
 792         .smbus_xfer     = i801_access,
 793         .functionality  = i801_func,
 794 };
 795
 796 static const struct pci_device_id i801_ids[] = {
 797         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
 798         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
 799         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
 800         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
 801         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
 802         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
 803         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
 804         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
 805         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
 806         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
 807         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
 808         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
 809         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
 810         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
 811         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
 812         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
 813         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
 814         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
 815         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
 816         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
 817         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
 818         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
 819         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
 820         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
 821         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
 822         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
 823         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
 824         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
 825         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
 826         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
 827         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
 828         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
 829         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
 830         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
 831         { 0, }
 832 };
 833
 834 MODULE_DEVICE_TABLE(pci, i801_ids);
 835
 836 #if defined CONFIG_X86 && defined CONFIG_DMI
 837 static unsigned char apanel_addr;
 838
 839 /* Scan the system ROM for the signature "FJKEYINF" */
 840 static __init const void __iomem *bios_signature(const void __iomem *bios)
 841 {
 842         ssize_t offset;
 843         const unsigned char signature[] = "FJKEYINF";
 844
 845         for (offset = 0; offset < 0x10000; offset += 0x10) {
 846                 if (check_signature(bios + offset, signature,
 847                                     sizeof(signature)-1))
 848                         return bios + offset;
 849         }
 850         return NULL;
 851 }
 852
 853 static void __init input_apanel_init(void)
 854 {
 855         void __iomem *bios;
 856         const void __iomem *p;
 857
 858         bios = ioremap(0xF0000, 0x10000); /* Can't fail */
 859         p = bios_signature(bios);
 860         if (p) {
 861                 /* just use the first address */
 862                 apanel_addr = readb(p + 8 + 3) >> 1;
 863         }
 864         iounmap(bios);
 865 }
 866
 867 struct dmi_onboard_device_info {
 868         const char *name;
 869         u8 type;
 870         unsigned short i2c_addr;
 871         const char *i2c_type;
 872 };
 873
 874 static const struct dmi_onboard_device_info dmi_devices[] = {
 875         { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
 876         { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
 877         { "Hades",  DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
 878 };
 879
 880 static void dmi_check_onboard_device(u8 type, const char *name,
 881                                      struct i2c_adapter *adap)
 882 {
 883         int i;
 884         struct i2c_board_info info;
 885
 886         for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
 887                 /* & ~0x80, ignore enabled/disabled bit */
 888                 if ((type & ~0x80) != dmi_devices[i].type)
 889                         continue;
 890                 if (strcasecmp(name, dmi_devices[i].name))
 891                         continue;
 892
 893                 memset(&info, 0, sizeof(struct i2c_board_info));
 894                 info.addr = dmi_devices[i].i2c_addr;
 895                 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
 896                 i2c_new_device(adap, &info);
 897                 break;
 898         }
 899 }
 900
 901 /* We use our own function to check for onboard devices instead of
 902    dmi_find_device() as some buggy BIOS's have the devices we are interested
 903    in marked as disabled */
 904 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
 905 {
 906         int i, count;
 907
 908         if (dm->type != 10)
 909                 return;
 910
 911         count = (dm->length - sizeof(struct dmi_header)) / 2;
 912         for (i = 0; i < count; i++) {
 913                 const u8 *d = (char *)(dm + 1) + (i * 2);
 914                 const char *name = ((char *) dm) + dm->length;
 915                 u8 type = d[0];
 916                 u8 s = d[1];
 917
 918                 if (!s)
 919                         continue;
 920                 s--;
 921                 while (s > 0 && name[0]) {
 922                         name += strlen(name) + 1;
 923                         s--;
 924                 }
 925                 if (name[0] == 0) /* Bogus string reference */
 926                         continue;
 927
 928                 dmi_check_onboard_device(type, name, adap);
 929         }
 930 }
 931
 932 /* Register optional slaves */
 933 static void i801_probe_optional_slaves(struct i801_priv *priv)
 934 {
 935         /* Only register slaves on main SMBus channel */
 936         if (priv->features & FEATURE_IDF)
 937                 return;
 938
 939         if (apanel_addr) {
 940                 struct i2c_board_info info;
 941
 942                 memset(&info, 0, sizeof(struct i2c_board_info));
 943                 info.addr = apanel_addr;
 944                 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
 945                 i2c_new_device(&priv->adapter, &info);
 946         }
 947
 948         if (dmi_name_in_vendors("FUJITSU"))
 949                 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
 950 }
 951 #else
 952 static void __init input_apanel_init(void) {}
 953 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
 954 #endif  /* CONFIG_X86 && CONFIG_DMI */
 955
 956 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
 957                 defined CONFIG_DMI
 958 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
 959         .gpio_chip = "gpio_ich",
 960         .values = { 0x02, 0x03 },
 961         .n_values = 2,
 962         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
 963         .gpios = { 52, 53 },
 964         .n_gpios = 2,
 965 };
 966
 967 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
 968         .gpio_chip = "gpio_ich",
 969         .values = { 0x02, 0x03, 0x01 },
 970         .n_values = 3,
 971         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
 972         .gpios = { 52, 53 },
 973         .n_gpios = 2,
 974 };
 975
 976 static const struct dmi_system_id mux_dmi_table[] = {
 977         {
 978                 .matches = {
 979                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
 980                         DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
 981                 },
 982                 .driver_data = &i801_mux_config_asus_z8_d12,
 983         },
 984         {
 985                 .matches = {
 986                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
 987                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
 988                 },
 989                 .driver_data = &i801_mux_config_asus_z8_d12,
 990         },
 991         {
 992                 .matches = {
 993                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
 994                         DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
 995                 },
 996                 .driver_data = &i801_mux_config_asus_z8_d12,
 997         },
 998         {
 999                 .matches = {
1000                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1001                         DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1002                 },
1003                 .driver_data = &i801_mux_config_asus_z8_d12,
1004         },
1005         {
1006                 .matches = {
1007                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1008                         DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1009                 },
1010                 .driver_data = &i801_mux_config_asus_z8_d12,
1011         },
1012         {
1013                 .matches = {
1014                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1015                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1016                 },
1017                 .driver_data = &i801_mux_config_asus_z8_d12,
1018         },
1019         {
1020                 .matches = {
1021                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1022                         DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1023                 },
1024                 .driver_data = &i801_mux_config_asus_z8_d18,
1025         },
1026         {
1027                 .matches = {
1028                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1029                         DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1030                 },
1031                 .driver_data = &i801_mux_config_asus_z8_d18,
1032         },
1033         {
1034                 .matches = {
1035                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1036                         DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1037                 },
1038                 .driver_data = &i801_mux_config_asus_z8_d12,
1039         },
1040         { }
1041 };
1042
1043 /* Setup multiplexing if needed */
1044 static int i801_add_mux(struct i801_priv *priv)
1045 {
1046         struct device *dev = &priv->adapter.dev;
1047         const struct i801_mux_config *mux_config;
1048         struct i2c_mux_gpio_platform_data gpio_data;
1049         int err;
1050
1051         if (!priv->mux_drvdata)
1052                 return 0;
1053         mux_config = priv->mux_drvdata;
1054
1055         /* Prepare the platform data */
1056         memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1057         gpio_data.parent = priv->adapter.nr;
1058         gpio_data.values = mux_config->values;
1059         gpio_data.n_values = mux_config->n_values;
1060         gpio_data.classes = mux_config->classes;
1061         gpio_data.gpio_chip = mux_config->gpio_chip;
1062         gpio_data.gpios = mux_config->gpios;
1063         gpio_data.n_gpios = mux_config->n_gpios;
1064         gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1065
1066         /* Register the mux device */
1067         priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1068                                 PLATFORM_DEVID_AUTO, &gpio_data,
1069                                 sizeof(struct i2c_mux_gpio_platform_data));
1070         if (IS_ERR(priv->mux_pdev)) {
1071                 err = PTR_ERR(priv->mux_pdev);
1072                 priv->mux_pdev = NULL;
1073                 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1074                 return err;
1075         }
1076
1077         return 0;
1078 }
1079
1080 static void i801_del_mux(struct i801_priv *priv)
1081 {
1082         if (priv->mux_pdev)
1083                 platform_device_unregister(priv->mux_pdev);
1084 }
1085
1086 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1087 {
1088         const struct dmi_system_id *id;
1089         const struct i801_mux_config *mux_config;
1090         unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1091         int i;
1092
1093         id = dmi_first_match(mux_dmi_table);
1094         if (id) {
1095                 /* Remove branch classes from trunk */
1096                 mux_config = id->driver_data;
1097                 for (i = 0; i < mux_config->n_values; i++)
1098                         class &= ~mux_config->classes[i];
1099
1100                 /* Remember for later */
1101                 priv->mux_drvdata = mux_config;
1102         }
1103
1104         return class;
1105 }
1106 #else
1107 static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1108 static inline void i801_del_mux(struct i801_priv *priv) { }
1109
1110 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1111 {
1112         return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1113 }
1114 #endif
1115
1116 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1117 {
1118         unsigned char temp;
1119         int err, i;
1120         struct i801_priv *priv;
1121
1122         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1123         if (!priv)
1124                 return -ENOMEM;
1125
1126         i2c_set_adapdata(&priv->adapter, priv);
1127         priv->adapter.owner = THIS_MODULE;
1128         priv->adapter.class = i801_get_adapter_class(priv);
1129         priv->adapter.algo = &smbus_algorithm;
1130
1131         priv->pci_dev = dev;
1132         switch (dev->device) {
1133         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1134         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1135         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1136         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1137         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1138         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1139                 priv->features |= FEATURE_IDF;
1140                 /* fall through */
1141         default:
1142                 priv->features |= FEATURE_I2C_BLOCK_READ;
1143                 priv->features |= FEATURE_IRQ;
1144                 /* fall through */
1145         case PCI_DEVICE_ID_INTEL_82801DB_3:
1146                 priv->features |= FEATURE_SMBUS_PEC;
1147                 priv->features |= FEATURE_BLOCK_BUFFER;
1148                 /* fall through */
1149         case PCI_DEVICE_ID_INTEL_82801CA_3:
1150         case PCI_DEVICE_ID_INTEL_82801BA_2:
1151         case PCI_DEVICE_ID_INTEL_82801AB_3:
1152         case PCI_DEVICE_ID_INTEL_82801AA_3:
1153                 break;
1154         }
1155
1156         /* Disable features on user request */
1157         for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1158                 if (priv->features & disable_features & (1 << i))
1159                         dev_notice(&dev->dev, "%s disabled by user\n",
1160                                    i801_feature_names[i]);
1161         }
1162         priv->features &= ~disable_features;
1163
1164         err = pci_enable_device(dev);
1165         if (err) {
1166                 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1167                         err);
1168                 goto exit;
1169         }
1170
1171         /* Determine the address of the SMBus area */
1172         priv->smba = pci_resource_start(dev, SMBBAR);
1173         if (!priv->smba) {
1174                 dev_err(&dev->dev, "SMBus base address uninitialized, "
1175                         "upgrade BIOS\n");
1176                 err = -ENODEV;
1177                 goto exit;
1178         }
1179
1180         err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
1181         if (err) {
1182                 err = -ENODEV;
1183                 goto exit;
1184         }
1185
1186         err = pci_request_region(dev, SMBBAR, i801_driver.name);
1187         if (err) {
1188                 dev_err(&dev->dev, "Failed to request SMBus region "
1189                         "0x%lx-0x%Lx\n", priv->smba,
1190                         (unsigned long long)pci_resource_end(dev, SMBBAR));
1191                 goto exit;
1192         }
1193
1194         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
1195         priv->original_hstcfg = temp;
1196         temp &= ~SMBHSTCFG_I2C_EN;      /* SMBus timing */
1197         if (!(temp & SMBHSTCFG_HST_EN)) {
1198                 dev_info(&dev->dev, "Enabling SMBus device\n");
1199                 temp |= SMBHSTCFG_HST_EN;
1200         }
1201         pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
1202
1203         if (temp & SMBHSTCFG_SMB_SMI_EN) {
1204                 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1205                 /* Disable SMBus interrupt feature if SMBus using SMI# */
1206                 priv->features &= ~FEATURE_IRQ;
1207         }
1208
1209         /* Clear special mode bits */
1210         if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1211                 outb_p(inb_p(SMBAUXCTL(priv)) &
1212                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1213
1214         if (priv->features & FEATURE_IRQ) {
1215                 init_waitqueue_head(&priv->waitq);
1216
1217                 err = request_irq(dev->irq, i801_isr, IRQF_SHARED,
1218                                   i801_driver.name, priv);
1219                 if (err) {
1220                         dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1221                                 dev->irq, err);
1222                         goto exit_release;
1223                 }
1224                 dev_info(&dev->dev, "SMBus using PCI Interrupt\n");
1225         }
1226
1227         /* set up the sysfs linkage to our parent device */
1228         priv->adapter.dev.parent = &dev->dev;
1229
1230         /* Retry up to 3 times on lost arbitration */
1231         priv->adapter.retries = 3;
1232
1233         snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1234                 "SMBus I801 adapter at %04lx", priv->smba);
1235         err = i2c_add_adapter(&priv->adapter);
1236         if (err) {
1237                 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
1238                 goto exit_free_irq;
1239         }
1240
1241         i801_probe_optional_slaves(priv);
1242         /* We ignore errors - multiplexing is optional */
1243         i801_add_mux(priv);
1244
1245         pci_set_drvdata(dev, priv);
1246
1247         return 0;
1248
1249 exit_free_irq:
1250         if (priv->features & FEATURE_IRQ)
1251                 free_irq(dev->irq, priv);
1252 exit_release:
1253         pci_release_region(dev, SMBBAR);
1254 exit:
1255         kfree(priv);
1256         return err;
1257 }
1258
1259 static void i801_remove(struct pci_dev *dev)
1260 {
1261         struct i801_priv *priv = pci_get_drvdata(dev);
1262
1263         i801_del_mux(priv);
1264         i2c_del_adapter(&priv->adapter);
1265         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1266
1267         if (priv->features & FEATURE_IRQ)
1268                 free_irq(dev->irq, priv);
1269         pci_release_region(dev, SMBBAR);
1270
1271         kfree(priv);
1272         /*
1273          * do not call pci_disable_device(dev) since it can cause hard hangs on
1274          * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1275          */
1276 }
1277
1278 #ifdef CONFIG_PM
1279 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
1280 {
1281         struct i801_priv *priv = pci_get_drvdata(dev);
1282
1283         pci_save_state(dev);
1284         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1285         pci_set_power_state(dev, pci_choose_state(dev, mesg));
1286         return 0;
1287 }
1288
1289 static int i801_resume(struct pci_dev *dev)
1290 {
1291         pci_set_power_state(dev, PCI_D0);
1292         pci_restore_state(dev);
1293         return pci_enable_device(dev);
1294 }
1295 #else
1296 #define i801_suspend NULL
1297 #define i801_resume NULL
1298 #endif
1299
1300 static struct pci_driver i801_driver = {
1301         .name           = "i801_smbus",
1302         .id_table       = i801_ids,
1303         .probe          = i801_probe,
1304         .remove         = i801_remove,
1305         .suspend        = i801_suspend,
1306         .resume         = i801_resume,
1307 };
1308
1309 static int __init i2c_i801_init(void)
1310 {
1311         if (dmi_name_in_vendors("FUJITSU"))
1312                 input_apanel_init();
1313         return pci_register_driver(&i801_driver);
1314 }
1315
1316 static void __exit i2c_i801_exit(void)
1317 {
1318         pci_unregister_driver(&i801_driver);
1319 }
1320
1321 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>");
1322 MODULE_DESCRIPTION("I801 SMBus driver");
1323 MODULE_LICENSE("GPL");
1324
1325 module_init(i2c_i801_init);
1326 module_exit(i2c_i801_exit);