drivers/i2c/busses/i2c-eg20t.c

   1 /*
   2  * Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, write to the Free Software
  15  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/delay.h>
  21 #include <linux/init.h>
  22 #include <linux/errno.h>
  23 #include <linux/i2c.h>
  24 #include <linux/fs.h>
  25 #include <linux/io.h>
  26 #include <linux/types.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/jiffies.h>
  29 #include <linux/pci.h>
  30 #include <linux/mutex.h>
  31 #include <linux/ktime.h>
  32 #include <linux/slab.h>
  33
  34 #define PCH_EVENT_SET   0       /* I2C Interrupt Event Set Status */
  35 #define PCH_EVENT_NONE  1       /* I2C Interrupt Event Clear Status */
  36 #define PCH_MAX_CLK             100000  /* Maximum Clock speed in MHz */
  37 #define PCH_BUFFER_MODE_ENABLE  0x0002  /* flag for Buffer mode enable */
  38 #define PCH_EEPROM_SW_RST_MODE_ENABLE   0x0008  /* EEPROM SW RST enable flag */
  39
  40 #define PCH_I2CSADR     0x00    /* I2C slave address register */
  41 #define PCH_I2CCTL      0x04    /* I2C control register */
  42 #define PCH_I2CSR       0x08    /* I2C status register */
  43 #define PCH_I2CDR       0x0C    /* I2C data register */
  44 #define PCH_I2CMON      0x10    /* I2C bus monitor register */
  45 #define PCH_I2CBC       0x14    /* I2C bus transfer rate setup counter */
  46 #define PCH_I2CMOD      0x18    /* I2C mode register */
  47 #define PCH_I2CBUFSLV   0x1C    /* I2C buffer mode slave address register */
  48 #define PCH_I2CBUFSUB   0x20    /* I2C buffer mode subaddress register */
  49 #define PCH_I2CBUFFOR   0x24    /* I2C buffer mode format register */
  50 #define PCH_I2CBUFCTL   0x28    /* I2C buffer mode control register */
  51 #define PCH_I2CBUFMSK   0x2C    /* I2C buffer mode interrupt mask register */
  52 #define PCH_I2CBUFSTA   0x30    /* I2C buffer mode status register */
  53 #define PCH_I2CBUFLEV   0x34    /* I2C buffer mode level register */
  54 #define PCH_I2CESRFOR   0x38    /* EEPROM software reset mode format register */
  55 #define PCH_I2CESRCTL   0x3C    /* EEPROM software reset mode ctrl register */
  56 #define PCH_I2CESRMSK   0x40    /* EEPROM software reset mode */
  57 #define PCH_I2CESRSTA   0x44    /* EEPROM software reset mode status register */
  58 #define PCH_I2CTMR      0x48    /* I2C timer register */
  59 #define PCH_I2CSRST     0xFC    /* I2C reset register */
  60 #define PCH_I2CNF       0xF8    /* I2C noise filter register */
  61
  62 #define BUS_IDLE_TIMEOUT        20
  63 #define PCH_I2CCTL_I2CMEN       0x0080
  64 #define TEN_BIT_ADDR_DEFAULT    0xF000
  65 #define TEN_BIT_ADDR_MASK       0xF0
  66 #define PCH_START               0x0020
  67 #define PCH_ESR_START           0x0001
  68 #define PCH_BUFF_START          0x1
  69 #define PCH_REPSTART            0x0004
  70 #define PCH_ACK                 0x0008
  71 #define PCH_GETACK              0x0001
  72 #define CLR_REG                 0x0
  73 #define I2C_RD                  0x1
  74 #define I2CMCF_BIT              0x0080
  75 #define I2CMIF_BIT              0x0002
  76 #define I2CMAL_BIT              0x0010
  77 #define I2CBMFI_BIT             0x0001
  78 #define I2CBMAL_BIT             0x0002
  79 #define I2CBMNA_BIT             0x0004
  80 #define I2CBMTO_BIT             0x0008
  81 #define I2CBMIS_BIT             0x0010
  82 #define I2CESRFI_BIT            0X0001
  83 #define I2CESRTO_BIT            0x0002
  84 #define I2CESRFIIE_BIT          0x1
  85 #define I2CESRTOIE_BIT          0x2
  86 #define I2CBMDZ_BIT             0x0040
  87 #define I2CBMAG_BIT             0x0020
  88 #define I2CMBB_BIT              0x0020
  89 #define BUFFER_MODE_MASK        (I2CBMFI_BIT | I2CBMAL_BIT | I2CBMNA_BIT | \
  90                                 I2CBMTO_BIT | I2CBMIS_BIT)
  91 #define I2C_ADDR_MSK            0xFF
  92 #define I2C_MSB_2B_MSK          0x300
  93 #define FAST_MODE_CLK           400
  94 #define FAST_MODE_EN            0x0001
  95 #define SUB_ADDR_LEN_MAX        4
  96 #define BUF_LEN_MAX             32
  97 #define PCH_BUFFER_MODE         0x1
  98 #define EEPROM_SW_RST_MODE      0x0002
  99 #define NORMAL_INTR_ENBL        0x0300
 100 #define EEPROM_RST_INTR_ENBL    (I2CESRFIIE_BIT | I2CESRTOIE_BIT)
 101 #define EEPROM_RST_INTR_DISBL   0x0
 102 #define BUFFER_MODE_INTR_ENBL   0x001F
 103 #define BUFFER_MODE_INTR_DISBL  0x0
 104 #define NORMAL_MODE             0x0
 105 #define BUFFER_MODE             0x1
 106 #define EEPROM_SR_MODE          0x2
 107 #define I2C_TX_MODE             0x0010
 108 #define PCH_BUF_TX              0xFFF7
 109 #define PCH_BUF_RD              0x0008
 110 #define I2C_ERROR_MASK  (I2CESRTO_EVENT | I2CBMIS_EVENT | I2CBMTO_EVENT | \
 111                         I2CBMNA_EVENT | I2CBMAL_EVENT | I2CMAL_EVENT)
 112 #define I2CMAL_EVENT            0x0001
 113 #define I2CMCF_EVENT            0x0002
 114 #define I2CBMFI_EVENT           0x0004
 115 #define I2CBMAL_EVENT           0x0008
 116 #define I2CBMNA_EVENT           0x0010
 117 #define I2CBMTO_EVENT           0x0020
 118 #define I2CBMIS_EVENT           0x0040
 119 #define I2CESRFI_EVENT          0x0080
 120 #define I2CESRTO_EVENT          0x0100
 121 #define PCI_DEVICE_ID_PCH_I2C   0x8817
 122
 123 #define pch_dbg(adap, fmt, arg...)  \
 124         dev_dbg(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
 125
 126 #define pch_err(adap, fmt, arg...)  \
 127         dev_err(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
 128
 129 #define pch_pci_err(pdev, fmt, arg...)  \
 130         dev_err(&pdev->dev, "%s :" fmt, __func__, ##arg)
 131
 132 #define pch_pci_dbg(pdev, fmt, arg...)  \
 133         dev_dbg(&pdev->dev, "%s :" fmt, __func__, ##arg)
 134
 135 /*
 136 Set the number of I2C instance max
 137 Intel EG20T PCH :               1ch
 138 OKI SEMICONDUCTOR ML7213 IOH :  2ch
 139 */
 140 #define PCH_I2C_MAX_DEV                 2
 141
 142 /**
 143  * struct i2c_algo_pch_data - for I2C driver functionalities
 144  * @pch_adapter:                stores the reference to i2c_adapter structure
 145  * @p_adapter_info:             stores the reference to adapter_info structure
 146  * @pch_base_address:           specifies the remapped base address
 147  * @pch_buff_mode_en:           specifies if buffer mode is enabled
 148  * @pch_event_flag:             specifies occurrence of interrupt events
 149  * @pch_i2c_xfer_in_progress:   specifies whether the transfer is completed
 150  */
 151 struct i2c_algo_pch_data {
 152         struct i2c_adapter pch_adapter;
 153         struct adapter_info *p_adapter_info;
 154         void __iomem *pch_base_address;
 155         int pch_buff_mode_en;
 156         u32 pch_event_flag;
 157         bool pch_i2c_xfer_in_progress;
 158 };
 159
 160 /**
 161  * struct adapter_info - This structure holds the adapter information for the
 162                          PCH i2c controller
 163  * @pch_data:           stores a list of i2c_algo_pch_data
 164  * @pch_i2c_suspended:  specifies whether the system is suspended or not
 165  *                      perhaps with more lines and words.
 166  * @ch_num:             specifies the number of i2c instance
 167  *
 168  * pch_data has as many elements as maximum I2C channels
 169  */
 170 struct adapter_info {
 171         struct i2c_algo_pch_data pch_data[PCH_I2C_MAX_DEV];
 172         bool pch_i2c_suspended;
 173         int ch_num;
 174 };
 175
 176
 177 static int pch_i2c_speed = 100; /* I2C bus speed in Kbps */
 178 static int pch_clk = 50000;     /* specifies I2C clock speed in KHz */
 179 static wait_queue_head_t pch_event;
 180 static DEFINE_MUTEX(pch_mutex);
 181
 182 /* Definition for ML7213 by OKI SEMICONDUCTOR */
 183 #define PCI_VENDOR_ID_ROHM              0x10DB
 184 #define PCI_DEVICE_ID_ML7213_I2C        0x802D
 185 #define PCI_DEVICE_ID_ML7223_I2C        0x8010
 186
 187 static struct pci_device_id __devinitdata pch_pcidev_id[] = {
 188         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH_I2C),   1, },
 189         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_I2C), 2, },
 190         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_I2C), 1, },
 191         {0,}
 192 };
 193
 194 static irqreturn_t pch_i2c_handler(int irq, void *pData);
 195
 196 static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask)
 197 {
 198         u32 val;
 199         val = ioread32(addr + offset);
 200         val |= bitmask;
 201         iowrite32(val, addr + offset);
 202 }
 203
 204 static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask)
 205 {
 206         u32 val;
 207         val = ioread32(addr + offset);
 208         val &= (~bitmask);
 209         iowrite32(val, addr + offset);
 210 }
 211
 212 /**
 213  * pch_i2c_init() - hardware initialization of I2C module
 214  * @adap:       Pointer to struct i2c_algo_pch_data.
 215  */
 216 static void pch_i2c_init(struct i2c_algo_pch_data *adap)
 217 {
 218         void __iomem *p = adap->pch_base_address;
 219         u32 pch_i2cbc;
 220         u32 pch_i2ctmr;
 221         u32 reg_value;
 222
 223         /* reset I2C controller */
 224         iowrite32(0x01, p + PCH_I2CSRST);
 225         msleep(20);
 226         iowrite32(0x0, p + PCH_I2CSRST);
 227
 228         /* Initialize I2C registers */
 229         iowrite32(0x21, p + PCH_I2CNF);
 230
 231         pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_I2CCTL_I2CMEN);
 232
 233         if (pch_i2c_speed != 400)
 234                 pch_i2c_speed = 100;
 235
 236         reg_value = PCH_I2CCTL_I2CMEN;
 237         if (pch_i2c_speed == FAST_MODE_CLK) {
 238                 reg_value |= FAST_MODE_EN;
 239                 pch_dbg(adap, "Fast mode enabled\n");
 240         }
 241
 242         if (pch_clk > PCH_MAX_CLK)
 243                 pch_clk = 62500;
 244
 245         pch_i2cbc = (pch_clk + (pch_i2c_speed * 4)) / pch_i2c_speed * 8;
 246         /* Set transfer speed in I2CBC */
 247         iowrite32(pch_i2cbc, p + PCH_I2CBC);
 248
 249         pch_i2ctmr = (pch_clk) / 8;
 250         iowrite32(pch_i2ctmr, p + PCH_I2CTMR);
 251
 252         reg_value |= NORMAL_INTR_ENBL;  /* Enable interrupts in normal mode */
 253         iowrite32(reg_value, p + PCH_I2CCTL);
 254
 255         pch_dbg(adap,
 256                 "I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
 257                 ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr);
 258
 259         init_waitqueue_head(&pch_event);
 260 }
 261
 262 static inline bool ktime_lt(const ktime_t cmp1, const ktime_t cmp2)
 263 {
 264         return cmp1.tv64 < cmp2.tv64;
 265 }
 266
 267 /**
 268  * pch_i2c_wait_for_bus_idle() - check the status of bus.
 269  * @adap:       Pointer to struct i2c_algo_pch_data.
 270  * @timeout:    waiting time counter (us).
 271  */
 272 static s32 pch_i2c_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
 273                                      s32 timeout)
 274 {
 275         void __iomem *p = adap->pch_base_address;
 276
 277         /* MAX timeout value is timeout*1000*1000nsec */
 278         ktime_t ns_val = ktime_add_ns(ktime_get(), timeout*1000*1000);
 279         do {
 280                 if ((ioread32(p + PCH_I2CSR) & I2CMBB_BIT) == 0)
 281                         break;
 282                 msleep(20);
 283         } while (ktime_lt(ktime_get(), ns_val));
 284
 285         pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR));
 286
 287         if (timeout == 0) {
 288                 pch_err(adap, "%s: Timeout Error.return%d\n", __func__, -ETIME);
 289                 return -ETIME;
 290         }
 291
 292         return 0;
 293 }
 294
 295 /**
 296  * pch_i2c_start() - Generate I2C start condition in normal mode.
 297  * @adap:       Pointer to struct i2c_algo_pch_data.
 298  *
 299  * Generate I2C start condition in normal mode by setting I2CCTL.I2CMSTA to 1.
 300  */
 301 static void pch_i2c_start(struct i2c_algo_pch_data *adap)
 302 {
 303         void __iomem *p = adap->pch_base_address;
 304         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 305         pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
 306 }
 307
 308 /**
 309  * pch_i2c_wait_for_xfer_complete() - initiates a wait for the tx complete event
 310  * @adap:       Pointer to struct i2c_algo_pch_data.
 311  */
 312 static s32 pch_i2c_wait_for_xfer_complete(struct i2c_algo_pch_data *adap)
 313 {
 314         s32 ret;
 315         ret = wait_event_timeout(pch_event,
 316                         (adap->pch_event_flag != 0), msecs_to_jiffies(50));
 317         if (ret < 0) {
 318                 pch_err(adap, "timeout: %x\n", adap->pch_event_flag);
 319                 return ret;
 320         }
 321
 322         if (ret == 0) {
 323                 pch_err(adap, "timeout: %x\n", adap->pch_event_flag);
 324                 return -ETIMEDOUT;
 325         }
 326
 327         if (adap->pch_event_flag & I2C_ERROR_MASK) {
 328                 pch_err(adap, "error bits set: %x\n", adap->pch_event_flag);
 329                 return -EIO;
 330         }
 331
 332         adap->pch_event_flag = 0;
 333
 334         return 0;
 335 }
 336
 337 /**
 338  * pch_i2c_getack() - to confirm ACK/NACK
 339  * @adap:       Pointer to struct i2c_algo_pch_data.
 340  */
 341 static s32 pch_i2c_getack(struct i2c_algo_pch_data *adap)
 342 {
 343         u32 reg_val;
 344         void __iomem *p = adap->pch_base_address;
 345         reg_val = ioread32(p + PCH_I2CSR) & PCH_GETACK;
 346
 347         if (reg_val != 0) {
 348                 pch_err(adap, "return%d\n", -EPROTO);
 349                 return -EPROTO;
 350         }
 351
 352         return 0;
 353 }
 354
 355 /**
 356  * pch_i2c_stop() - generate stop condition in normal mode.
 357  * @adap:       Pointer to struct i2c_algo_pch_data.
 358  */
 359 static void pch_i2c_stop(struct i2c_algo_pch_data *adap)
 360 {
 361         void __iomem *p = adap->pch_base_address;
 362         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 363         /* clear the start bit */
 364         pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
 365 }
 366
 367 /**
 368  * pch_i2c_repstart() - generate repeated start condition in normal mode
 369  * @adap:       Pointer to struct i2c_algo_pch_data.
 370  */
 371 static void pch_i2c_repstart(struct i2c_algo_pch_data *adap)
 372 {
 373         void __iomem *p = adap->pch_base_address;
 374         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 375         pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_REPSTART);
 376 }
 377
 378 /**
 379  * pch_i2c_writebytes() - write data to I2C bus in normal mode
 380  * @i2c_adap:   Pointer to the struct i2c_adapter.
 381  * @last:       specifies whether last message or not.
 382  *              In the case of compound mode it will be 1 for last message,
 383  *              otherwise 0.
 384  * @first:      specifies whether first message or not.
 385  *              1 for first message otherwise 0.
 386  */
 387 static s32 pch_i2c_writebytes(struct i2c_adapter *i2c_adap,
 388                               struct i2c_msg *msgs, u32 last, u32 first)
 389 {
 390         struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
 391         u8 *buf;
 392         u32 length;
 393         u32 addr;
 394         u32 addr_2_msb;
 395         u32 addr_8_lsb;
 396         s32 wrcount;
 397         void __iomem *p = adap->pch_base_address;
 398
 399         length = msgs->len;
 400         buf = msgs->buf;
 401         addr = msgs->addr;
 402
 403         /* enable master tx */
 404         pch_setbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
 405
 406         pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n", ioread32(p + PCH_I2CCTL),
 407                 length);
 408
 409         if (first) {
 410                 if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
 411                         return -ETIME;
 412         }
 413
 414         if (msgs->flags & I2C_M_TEN) {
 415                 addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7);
 416                 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
 417                 if (first)
 418                         pch_i2c_start(adap);
 419                 if (pch_i2c_wait_for_xfer_complete(adap) == 0 &&
 420                     pch_i2c_getack(adap) == 0) {
 421                         addr_8_lsb = (addr & I2C_ADDR_MSK);
 422                         iowrite32(addr_8_lsb, p + PCH_I2CDR);
 423                 } else {
 424                         pch_i2c_stop(adap);
 425                         return -ETIME;
 426                 }
 427         } else {
 428                 /* set 7 bit slave address and R/W bit as 0 */
 429                 iowrite32(addr << 1, p + PCH_I2CDR);
 430                 if (first)
 431                         pch_i2c_start(adap);
 432         }
 433
 434         if ((pch_i2c_wait_for_xfer_complete(adap) == 0) &&
 435             (pch_i2c_getack(adap) == 0)) {
 436                 for (wrcount = 0; wrcount < length; ++wrcount) {
 437                         /* write buffer value to I2C data register */
 438                         iowrite32(buf[wrcount], p + PCH_I2CDR);
 439                         pch_dbg(adap, "writing %x to Data register\n",
 440                                 buf[wrcount]);
 441
 442                         if (pch_i2c_wait_for_xfer_complete(adap) != 0)
 443                                 return -ETIME;
 444
 445                         if (pch_i2c_getack(adap))
 446                                 return -EIO;
 447                 }
 448
 449                 /* check if this is the last message */
 450                 if (last)
 451                         pch_i2c_stop(adap);
 452                 else
 453                         pch_i2c_repstart(adap);
 454         } else {
 455                 pch_i2c_stop(adap);
 456                 return -EIO;
 457         }
 458
 459         pch_dbg(adap, "return=%d\n", wrcount);
 460
 461         return wrcount;
 462 }
 463
 464 /**
 465  * pch_i2c_sendack() - send ACK
 466  * @adap:       Pointer to struct i2c_algo_pch_data.
 467  */
 468 static void pch_i2c_sendack(struct i2c_algo_pch_data *adap)
 469 {
 470         void __iomem *p = adap->pch_base_address;
 471         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 472         pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
 473 }
 474
 475 /**
 476  * pch_i2c_sendnack() - send NACK
 477  * @adap:       Pointer to struct i2c_algo_pch_data.
 478  */
 479 static void pch_i2c_sendnack(struct i2c_algo_pch_data *adap)
 480 {
 481         void __iomem *p = adap->pch_base_address;
 482         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 483         pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
 484 }
 485
 486 /**
 487  * pch_i2c_readbytes() - read data  from I2C bus in normal mode.
 488  * @i2c_adap:   Pointer to the struct i2c_adapter.
 489  * @msgs:       Pointer to i2c_msg structure.
 490  * @last:       specifies whether last message or not.
 491  * @first:      specifies whether first message or not.
 492  */
 493 static s32 pch_i2c_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
 494                              u32 last, u32 first)
 495 {
 496         struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
 497
 498         u8 *buf;
 499         u32 count;
 500         u32 length;
 501         u32 addr;
 502         u32 addr_2_msb;
 503         void __iomem *p = adap->pch_base_address;
 504
 505         length = msgs->len;
 506         buf = msgs->buf;
 507         addr = msgs->addr;
 508
 509         /* enable master reception */
 510         pch_clrbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
 511
 512         if (first) {
 513                 if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
 514                         return -ETIME;
 515         }
 516
 517         if (msgs->flags & I2C_M_TEN) {
 518                 addr_2_msb = (((addr & I2C_MSB_2B_MSK) >> 7) | (I2C_RD));
 519                 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
 520
 521         } else {
 522                 /* 7 address bits + R/W bit */
 523                 addr = (((addr) << 1) | (I2C_RD));
 524                 iowrite32(addr, p + PCH_I2CDR);
 525         }
 526
 527         /* check if it is the first message */
 528         if (first)
 529                 pch_i2c_start(adap);
 530
 531         if ((pch_i2c_wait_for_xfer_complete(adap) == 0) &&
 532             (pch_i2c_getack(adap) == 0)) {
 533                 pch_dbg(adap, "return %d\n", 0);
 534
 535                 if (length == 0) {
 536                         pch_i2c_stop(adap);
 537                         ioread32(p + PCH_I2CDR); /* Dummy read needs */
 538
 539                         count = length;
 540                 } else {
 541                         int read_index;
 542                         int loop;
 543                         pch_i2c_sendack(adap);
 544
 545                         /* Dummy read */
 546                         for (loop = 1, read_index = 0; loop < length; loop++) {
 547                                 buf[read_index] = ioread32(p + PCH_I2CDR);
 548
 549                                 if (loop != 1)
 550                                         read_index++;
 551
 552                                 if (pch_i2c_wait_for_xfer_complete(adap) != 0) {
 553                                         pch_i2c_stop(adap);
 554                                         return -ETIME;
 555                                 }
 556                         }       /* end for */
 557
 558                         pch_i2c_sendnack(adap);
 559
 560                         buf[read_index] = ioread32(p + PCH_I2CDR);
 561
 562                         if (length != 1)
 563                                 read_index++;
 564
 565                         if (pch_i2c_wait_for_xfer_complete(adap) == 0) {
 566                                 if (last)
 567                                         pch_i2c_stop(adap);
 568                                 else
 569                                         pch_i2c_repstart(adap);
 570
 571                                 buf[read_index++] = ioread32(p + PCH_I2CDR);
 572                                 count = read_index;
 573                         } else {
 574                                 count = -ETIME;
 575                         }
 576
 577                 }
 578         } else {
 579                 count = -ETIME;
 580                 pch_i2c_stop(adap);
 581         }
 582
 583         return count;
 584 }
 585
 586 /**
 587  * pch_i2c_cb() - Interrupt handler Call back function
 588  * @adap:       Pointer to struct i2c_algo_pch_data.
 589  */
 590 static void pch_i2c_cb(struct i2c_algo_pch_data *adap)
 591 {
 592         u32 sts;
 593         void __iomem *p = adap->pch_base_address;
 594
 595         sts = ioread32(p + PCH_I2CSR);
 596         sts &= (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT);
 597         if (sts & I2CMAL_BIT)
 598                 adap->pch_event_flag |= I2CMAL_EVENT;
 599
 600         if (sts & I2CMCF_BIT)
 601                 adap->pch_event_flag |= I2CMCF_EVENT;
 602
 603         /* clear the applicable bits */
 604         pch_clrbit(adap->pch_base_address, PCH_I2CSR, sts);
 605
 606         pch_dbg(adap, "PCH_I2CSR = %x\n", ioread32(p + PCH_I2CSR));
 607
 608         wake_up(&pch_event);
 609 }
 610
 611 /**
 612  * pch_i2c_handler() - interrupt handler for the PCH I2C controller
 613  * @irq:        irq number.
 614  * @pData:      cookie passed back to the handler function.
 615  */
 616 static irqreturn_t pch_i2c_handler(int irq, void *pData)
 617 {
 618         u32 reg_val;
 619         int flag;
 620         int i;
 621         struct adapter_info *adap_info = pData;
 622         void __iomem *p;
 623         u32 mode;
 624
 625         for (i = 0, flag = 0; i < adap_info->ch_num; i++) {
 626                 p = adap_info->pch_data[i].pch_base_address;
 627                 mode = ioread32(p + PCH_I2CMOD);
 628                 mode &= BUFFER_MODE | EEPROM_SR_MODE;
 629                 if (mode != NORMAL_MODE) {
 630                         pch_err(adap_info->pch_data,
 631                                 "I2C-%d mode(%d) is not supported\n", mode, i);
 632                         continue;
 633                 }
 634                 reg_val = ioread32(p + PCH_I2CSR);
 635                 if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT)) {
 636                         pch_i2c_cb(&adap_info->pch_data[i]);
 637                         flag = 1;
 638                 }
 639         }
 640
 641         return flag ? IRQ_HANDLED : IRQ_NONE;
 642 }
 643
 644 /**
 645  * pch_i2c_xfer() - Reading adnd writing data through I2C bus
 646  * @i2c_adap:   Pointer to the struct i2c_adapter.
 647  * @msgs:       Pointer to i2c_msg structure.
 648  * @num:        number of messages.
 649  */
 650 static s32 pch_i2c_xfer(struct i2c_adapter *i2c_adap,
 651                         struct i2c_msg *msgs, s32 num)
 652 {
 653         struct i2c_msg *pmsg;
 654         u32 i = 0;
 655         u32 status;
 656         u32 msglen;
 657         u32 subaddrlen;
 658         s32 ret;
 659
 660         struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
 661
 662         ret = mutex_lock_interruptible(&pch_mutex);
 663         if (ret)
 664                 return -ERESTARTSYS;
 665
 666         if (adap->p_adapter_info->pch_i2c_suspended) {
 667                 mutex_unlock(&pch_mutex);
 668                 return -EBUSY;
 669         }
 670
 671         pch_dbg(adap, "adap->p_adapter_info->pch_i2c_suspended is %d\n",
 672                 adap->p_adapter_info->pch_i2c_suspended);
 673         /* transfer not completed */
 674         adap->pch_i2c_xfer_in_progress = true;
 675
 676         pmsg = &msgs[0];
 677         pmsg->flags |= adap->pch_buff_mode_en;
 678         status = pmsg->flags;
 679         pch_dbg(adap,
 680                 "After invoking I2C_MODE_SEL :flag= 0x%x\n", status);
 681         /* calculate sub address length and message length */
 682         /* these are applicable only for buffer mode */
 683         subaddrlen = pmsg->buf[0];
 684         /* calculate actual message length excluding
 685          * the sub address fields */
 686         msglen = (pmsg->len) - (subaddrlen + 1);
 687         if (status & (I2C_M_RD)) {
 688                 pch_dbg(adap, "invoking pch_i2c_readbytes\n");
 689                 ret = pch_i2c_readbytes(i2c_adap, pmsg, (i + 1 == num),
 690                                    (i == 0));
 691         } else {
 692                 pch_dbg(adap, "invoking pch_i2c_writebytes\n");
 693                 ret = pch_i2c_writebytes(i2c_adap, pmsg, (i + 1 == num),
 694                                     (i == 0));
 695         }
 696
 697         adap->pch_i2c_xfer_in_progress = false; /* transfer completed */
 698
 699         mutex_unlock(&pch_mutex);
 700
 701         return ret;
 702 }
 703
 704 /**
 705  * pch_i2c_func() - return the functionality of the I2C driver
 706  * @adap:       Pointer to struct i2c_algo_pch_data.
 707  */
 708 static u32 pch_i2c_func(struct i2c_adapter *adap)
 709 {
 710         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
 711 }
 712
 713 static struct i2c_algorithm pch_algorithm = {
 714         .master_xfer = pch_i2c_xfer,
 715         .functionality = pch_i2c_func
 716 };
 717
 718 /**
 719  * pch_i2c_disbl_int() - Disable PCH I2C interrupts
 720  * @adap:       Pointer to struct i2c_algo_pch_data.
 721  */
 722 static void pch_i2c_disbl_int(struct i2c_algo_pch_data *adap)
 723 {
 724         void __iomem *p = adap->pch_base_address;
 725
 726         pch_clrbit(adap->pch_base_address, PCH_I2CCTL, NORMAL_INTR_ENBL);
 727
 728         iowrite32(EEPROM_RST_INTR_DISBL, p + PCH_I2CESRMSK);
 729
 730         iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK);
 731 }
 732
 733 static int __devinit pch_i2c_probe(struct pci_dev *pdev,
 734                                    const struct pci_device_id *id)
 735 {
 736         void __iomem *base_addr;
 737         int ret;
 738         int i, j;
 739         struct adapter_info *adap_info;
 740         struct i2c_adapter *pch_adap;
 741
 742         pch_pci_dbg(pdev, "Entered.\n");
 743
 744         adap_info = kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
 745         if (adap_info == NULL) {
 746                 pch_pci_err(pdev, "Memory allocation FAILED\n");
 747                 return -ENOMEM;
 748         }
 749
 750         ret = pci_enable_device(pdev);
 751         if (ret) {
 752                 pch_pci_err(pdev, "pci_enable_device FAILED\n");
 753                 goto err_pci_enable;
 754         }
 755
 756         ret = pci_request_regions(pdev, KBUILD_MODNAME);
 757         if (ret) {
 758                 pch_pci_err(pdev, "pci_request_regions FAILED\n");
 759                 goto err_pci_req;
 760         }
 761
 762         base_addr = pci_iomap(pdev, 1, 0);
 763
 764         if (base_addr == NULL) {
 765                 pch_pci_err(pdev, "pci_iomap FAILED\n");
 766                 ret = -ENOMEM;
 767                 goto err_pci_iomap;
 768         }
 769
 770         /* Set the number of I2C channel instance */
 771         adap_info->ch_num = id->driver_data;
 772
 773         for (i = 0; i < adap_info->ch_num; i++) {
 774                 pch_adap = &adap_info->pch_data[i].pch_adapter;
 775                 adap_info->pch_i2c_suspended = false;
 776
 777                 adap_info->pch_data[i].p_adapter_info = adap_info;
 778
 779                 pch_adap->owner = THIS_MODULE;
 780                 pch_adap->class = I2C_CLASS_HWMON;
 781                 strcpy(pch_adap->name, KBUILD_MODNAME);
 782                 pch_adap->algo = &pch_algorithm;
 783                 pch_adap->algo_data = &adap_info->pch_data[i];
 784
 785                 /* base_addr + offset; */
 786                 adap_info->pch_data[i].pch_base_address = base_addr + 0x100 * i;
 787
 788                 pch_adap->dev.parent = &pdev->dev;
 789
 790                 ret = i2c_add_adapter(pch_adap);
 791                 if (ret) {
 792                         pch_pci_err(pdev, "i2c_add_adapter[ch:%d] FAILED\n", i);
 793                         goto err_i2c_add_adapter;
 794                 }
 795
 796                 pch_i2c_init(&adap_info->pch_data[i]);
 797         }
 798         ret = request_irq(pdev->irq, pch_i2c_handler, IRQF_SHARED,
 799                   KBUILD_MODNAME, adap_info);
 800         if (ret) {
 801                 pch_pci_err(pdev, "request_irq FAILED\n");
 802                 goto err_i2c_add_adapter;
 803         }
 804
 805         pci_set_drvdata(pdev, adap_info);
 806         pch_pci_dbg(pdev, "returns %d.\n", ret);
 807         return 0;
 808
 809 err_i2c_add_adapter:
 810         for (j = 0; j < i; j++)
 811                 i2c_del_adapter(&adap_info->pch_data[j].pch_adapter);
 812         pci_iounmap(pdev, base_addr);
 813 err_pci_iomap:
 814         pci_release_regions(pdev);
 815 err_pci_req:
 816         pci_disable_device(pdev);
 817 err_pci_enable:
 818         kfree(adap_info);
 819         return ret;
 820 }
 821
 822 static void __devexit pch_i2c_remove(struct pci_dev *pdev)
 823 {
 824         int i;
 825         struct adapter_info *adap_info = pci_get_drvdata(pdev);
 826
 827         free_irq(pdev->irq, adap_info);
 828
 829         for (i = 0; i < adap_info->ch_num; i++) {
 830                 pch_i2c_disbl_int(&adap_info->pch_data[i]);
 831                 i2c_del_adapter(&adap_info->pch_data[i].pch_adapter);
 832         }
 833
 834         if (adap_info->pch_data[0].pch_base_address)
 835                 pci_iounmap(pdev, adap_info->pch_data[0].pch_base_address);
 836
 837         for (i = 0; i < adap_info->ch_num; i++)
 838                 adap_info->pch_data[i].pch_base_address = 0;
 839
 840         pci_set_drvdata(pdev, NULL);
 841
 842         pci_release_regions(pdev);
 843
 844         pci_disable_device(pdev);
 845         kfree(adap_info);
 846 }
 847
 848 #ifdef CONFIG_PM
 849 static int pch_i2c_suspend(struct pci_dev *pdev, pm_message_t state)
 850 {
 851         int ret;
 852         int i;
 853         struct adapter_info *adap_info = pci_get_drvdata(pdev);
 854         void __iomem *p = adap_info->pch_data[0].pch_base_address;
 855
 856         adap_info->pch_i2c_suspended = true;
 857
 858         for (i = 0; i < adap_info->ch_num; i++) {
 859                 while ((adap_info->pch_data[i].pch_i2c_xfer_in_progress)) {
 860                         /* Wait until all channel transfers are completed */
 861                         msleep(20);
 862                 }
 863         }
 864
 865         /* Disable the i2c interrupts */
 866         for (i = 0; i < adap_info->ch_num; i++)
 867                 pch_i2c_disbl_int(&adap_info->pch_data[i]);
 868
 869         pch_pci_dbg(pdev, "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
 870                 "invoked function pch_i2c_disbl_int successfully\n",
 871                 ioread32(p + PCH_I2CSR), ioread32(p + PCH_I2CBUFSTA),
 872                 ioread32(p + PCH_I2CESRSTA));
 873
 874         ret = pci_save_state(pdev);
 875
 876         if (ret) {
 877                 pch_pci_err(pdev, "pci_save_state\n");
 878                 return ret;
 879         }
 880
 881         pci_enable_wake(pdev, PCI_D3hot, 0);
 882         pci_disable_device(pdev);
 883         pci_set_power_state(pdev, pci_choose_state(pdev, state));
 884
 885         return 0;
 886 }
 887
 888 static int pch_i2c_resume(struct pci_dev *pdev)
 889 {
 890         int i;
 891         struct adapter_info *adap_info = pci_get_drvdata(pdev);
 892
 893         pci_set_power_state(pdev, PCI_D0);
 894         pci_restore_state(pdev);
 895
 896         if (pci_enable_device(pdev) < 0) {
 897                 pch_pci_err(pdev, "pch_i2c_resume:pci_enable_device FAILED\n");
 898                 return -EIO;
 899         }
 900
 901         pci_enable_wake(pdev, PCI_D3hot, 0);
 902
 903         for (i = 0; i < adap_info->ch_num; i++)
 904                 pch_i2c_init(&adap_info->pch_data[i]);
 905
 906         adap_info->pch_i2c_suspended = false;
 907
 908         return 0;
 909 }
 910 #else
 911 #define pch_i2c_suspend NULL
 912 #define pch_i2c_resume NULL
 913 #endif
 914
 915 static struct pci_driver pch_pcidriver = {
 916         .name = KBUILD_MODNAME,
 917         .id_table = pch_pcidev_id,
 918         .probe = pch_i2c_probe,
 919         .remove = __devexit_p(pch_i2c_remove),
 920         .suspend = pch_i2c_suspend,
 921         .resume = pch_i2c_resume
 922 };
 923
 924 static int __init pch_pci_init(void)
 925 {
 926         return pci_register_driver(&pch_pcidriver);
 927 }
 928 module_init(pch_pci_init);
 929
 930 static void __exit pch_pci_exit(void)
 931 {
 932         pci_unregister_driver(&pch_pcidriver);
 933 }
 934 module_exit(pch_pci_exit);
 935
 936 MODULE_DESCRIPTION("Intel EG20T PCH/OKI SEMICONDUCTOR ML7213 IOH I2C Driver");
 937 MODULE_LICENSE("GPL");
 938 MODULE_AUTHOR("Tomoya MORINAGA. <tomoya-linux@dsn.okisemi.com>");
 939 module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR));
 940 module_param(pch_clk, int, (S_IRUSR | S_IWUSR));