drivers/i2c/busses/i2c-eg20t.c

   1 /*
   2  * Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, write to the Free Software
  15  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/delay.h>
  21 #include <linux/init.h>
  22 #include <linux/errno.h>
  23 #include <linux/i2c.h>
  24 #include <linux/fs.h>
  25 #include <linux/io.h>
  26 #include <linux/types.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/jiffies.h>
  29 #include <linux/pci.h>
  30 #include <linux/mutex.h>
  31 #include <linux/ktime.h>
  32 #include <linux/slab.h>
  33
  34 #define PCH_EVENT_SET   0       /* I2C Interrupt Event Set Status */
  35 #define PCH_EVENT_NONE  1       /* I2C Interrupt Event Clear Status */
  36 #define PCH_MAX_CLK             100000  /* Maximum Clock speed in MHz */
  37 #define PCH_BUFFER_MODE_ENABLE  0x0002  /* flag for Buffer mode enable */
  38 #define PCH_EEPROM_SW_RST_MODE_ENABLE   0x0008  /* EEPROM SW RST enable flag */
  39
  40 #define PCH_I2CSADR     0x00    /* I2C slave address register */
  41 #define PCH_I2CCTL      0x04    /* I2C control register */
  42 #define PCH_I2CSR       0x08    /* I2C status register */
  43 #define PCH_I2CDR       0x0C    /* I2C data register */
  44 #define PCH_I2CMON      0x10    /* I2C bus monitor register */
  45 #define PCH_I2CBC       0x14    /* I2C bus transfer rate setup counter */
  46 #define PCH_I2CMOD      0x18    /* I2C mode register */
  47 #define PCH_I2CBUFSLV   0x1C    /* I2C buffer mode slave address register */
  48 #define PCH_I2CBUFSUB   0x20    /* I2C buffer mode subaddress register */
  49 #define PCH_I2CBUFFOR   0x24    /* I2C buffer mode format register */
  50 #define PCH_I2CBUFCTL   0x28    /* I2C buffer mode control register */
  51 #define PCH_I2CBUFMSK   0x2C    /* I2C buffer mode interrupt mask register */
  52 #define PCH_I2CBUFSTA   0x30    /* I2C buffer mode status register */
  53 #define PCH_I2CBUFLEV   0x34    /* I2C buffer mode level register */
  54 #define PCH_I2CESRFOR   0x38    /* EEPROM software reset mode format register */
  55 #define PCH_I2CESRCTL   0x3C    /* EEPROM software reset mode ctrl register */
  56 #define PCH_I2CESRMSK   0x40    /* EEPROM software reset mode */
  57 #define PCH_I2CESRSTA   0x44    /* EEPROM software reset mode status register */
  58 #define PCH_I2CTMR      0x48    /* I2C timer register */
  59 #define PCH_I2CSRST     0xFC    /* I2C reset register */
  60 #define PCH_I2CNF       0xF8    /* I2C noise filter register */
  61
  62 #define BUS_IDLE_TIMEOUT        20
  63 #define PCH_I2CCTL_I2CMEN       0x0080
  64 #define TEN_BIT_ADDR_DEFAULT    0xF000
  65 #define TEN_BIT_ADDR_MASK       0xF0
  66 #define PCH_START               0x0020
  67 #define PCH_ESR_START           0x0001
  68 #define PCH_BUFF_START          0x1
  69 #define PCH_REPSTART            0x0004
  70 #define PCH_ACK                 0x0008
  71 #define PCH_GETACK              0x0001
  72 #define CLR_REG                 0x0
  73 #define I2C_RD                  0x1
  74 #define I2CMCF_BIT              0x0080
  75 #define I2CMIF_BIT              0x0002
  76 #define I2CMAL_BIT              0x0010
  77 #define I2CBMFI_BIT             0x0001
  78 #define I2CBMAL_BIT             0x0002
  79 #define I2CBMNA_BIT             0x0004
  80 #define I2CBMTO_BIT             0x0008
  81 #define I2CBMIS_BIT             0x0010
  82 #define I2CESRFI_BIT            0X0001
  83 #define I2CESRTO_BIT            0x0002
  84 #define I2CESRFIIE_BIT          0x1
  85 #define I2CESRTOIE_BIT          0x2
  86 #define I2CBMDZ_BIT             0x0040
  87 #define I2CBMAG_BIT             0x0020
  88 #define I2CMBB_BIT              0x0020
  89 #define BUFFER_MODE_MASK        (I2CBMFI_BIT | I2CBMAL_BIT | I2CBMNA_BIT | \
  90                                 I2CBMTO_BIT | I2CBMIS_BIT)
  91 #define I2C_ADDR_MSK            0xFF
  92 #define I2C_MSB_2B_MSK          0x300
  93 #define FAST_MODE_CLK           400
  94 #define FAST_MODE_EN            0x0001
  95 #define SUB_ADDR_LEN_MAX        4
  96 #define BUF_LEN_MAX             32
  97 #define PCH_BUFFER_MODE         0x1
  98 #define EEPROM_SW_RST_MODE      0x0002
  99 #define NORMAL_INTR_ENBL        0x0300
 100 #define EEPROM_RST_INTR_ENBL    (I2CESRFIIE_BIT | I2CESRTOIE_BIT)
 101 #define EEPROM_RST_INTR_DISBL   0x0
 102 #define BUFFER_MODE_INTR_ENBL   0x001F
 103 #define BUFFER_MODE_INTR_DISBL  0x0
 104 #define NORMAL_MODE             0x0
 105 #define BUFFER_MODE             0x1
 106 #define EEPROM_SR_MODE          0x2
 107 #define I2C_TX_MODE             0x0010
 108 #define PCH_BUF_TX              0xFFF7
 109 #define PCH_BUF_RD              0x0008
 110 #define I2C_ERROR_MASK  (I2CESRTO_EVENT | I2CBMIS_EVENT | I2CBMTO_EVENT | \
 111                         I2CBMNA_EVENT | I2CBMAL_EVENT | I2CMAL_EVENT)
 112 #define I2CMAL_EVENT            0x0001
 113 #define I2CMCF_EVENT            0x0002
 114 #define I2CBMFI_EVENT           0x0004
 115 #define I2CBMAL_EVENT           0x0008
 116 #define I2CBMNA_EVENT           0x0010
 117 #define I2CBMTO_EVENT           0x0020
 118 #define I2CBMIS_EVENT           0x0040
 119 #define I2CESRFI_EVENT          0x0080
 120 #define I2CESRTO_EVENT          0x0100
 121 #define PCI_DEVICE_ID_PCH_I2C   0x8817
 122
 123 #define pch_dbg(adap, fmt, arg...)  \
 124         dev_dbg(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
 125
 126 #define pch_err(adap, fmt, arg...)  \
 127         dev_err(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
 128
 129 #define pch_pci_err(pdev, fmt, arg...)  \
 130         dev_err(&pdev->dev, "%s :" fmt, __func__, ##arg)
 131
 132 #define pch_pci_dbg(pdev, fmt, arg...)  \
 133         dev_dbg(&pdev->dev, "%s :" fmt, __func__, ##arg)
 134
 135 /*
 136 Set the number of I2C instance max
 137 Intel EG20T PCH :               1ch
 138 OKI SEMICONDUCTOR ML7213 IOH :  2ch
 139 */
 140 #define PCH_I2C_MAX_DEV                 2
 141
 142 /**
 143  * struct i2c_algo_pch_data - for I2C driver functionalities
 144  * @pch_adapter:                stores the reference to i2c_adapter structure
 145  * @p_adapter_info:             stores the reference to adapter_info structure
 146  * @pch_base_address:           specifies the remapped base address
 147  * @pch_buff_mode_en:           specifies if buffer mode is enabled
 148  * @pch_event_flag:             specifies occurrence of interrupt events
 149  * @pch_i2c_xfer_in_progress:   specifies whether the transfer is completed
 150  */
 151 struct i2c_algo_pch_data {
 152         struct i2c_adapter pch_adapter;
 153         struct adapter_info *p_adapter_info;
 154         void __iomem *pch_base_address;
 155         int pch_buff_mode_en;
 156         u32 pch_event_flag;
 157         bool pch_i2c_xfer_in_progress;
 158 };
 159
 160 /**
 161  * struct adapter_info - This structure holds the adapter information for the
 162                          PCH i2c controller
 163  * @pch_data:           stores a list of i2c_algo_pch_data
 164  * @pch_i2c_suspended:  specifies whether the system is suspended or not
 165  *                      perhaps with more lines and words.
 166  * @ch_num:             specifies the number of i2c instance
 167  *
 168  * pch_data has as many elements as maximum I2C channels
 169  */
 170 struct adapter_info {
 171         struct i2c_algo_pch_data pch_data[PCH_I2C_MAX_DEV];
 172         bool pch_i2c_suspended;
 173         int ch_num;
 174 };
 175
 176
 177 static int pch_i2c_speed = 100; /* I2C bus speed in Kbps */
 178 static int pch_clk = 50000;     /* specifies I2C clock speed in KHz */
 179 static wait_queue_head_t pch_event;
 180 static DEFINE_MUTEX(pch_mutex);
 181
 182 /* Definition for ML7213 by OKI SEMICONDUCTOR */
 183 #define PCI_VENDOR_ID_ROHM              0x10DB
 184 #define PCI_DEVICE_ID_ML7213_I2C        0x802D
 185
 186 static struct pci_device_id __devinitdata pch_pcidev_id[] = {
 187         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH_I2C),   1, },
 188         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_I2C), 2, },
 189         {0,}
 190 };
 191
 192 static irqreturn_t pch_i2c_handler(int irq, void *pData);
 193
 194 static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask)
 195 {
 196         u32 val;
 197         val = ioread32(addr + offset);
 198         val |= bitmask;
 199         iowrite32(val, addr + offset);
 200 }
 201
 202 static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask)
 203 {
 204         u32 val;
 205         val = ioread32(addr + offset);
 206         val &= (~bitmask);
 207         iowrite32(val, addr + offset);
 208 }
 209
 210 /**
 211  * pch_i2c_init() - hardware initialization of I2C module
 212  * @adap:       Pointer to struct i2c_algo_pch_data.
 213  */
 214 static void pch_i2c_init(struct i2c_algo_pch_data *adap)
 215 {
 216         void __iomem *p = adap->pch_base_address;
 217         u32 pch_i2cbc;
 218         u32 pch_i2ctmr;
 219         u32 reg_value;
 220
 221         /* reset I2C controller */
 222         iowrite32(0x01, p + PCH_I2CSRST);
 223         msleep(20);
 224         iowrite32(0x0, p + PCH_I2CSRST);
 225
 226         /* Initialize I2C registers */
 227         iowrite32(0x21, p + PCH_I2CNF);
 228
 229         pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_I2CCTL_I2CMEN);
 230
 231         if (pch_i2c_speed != 400)
 232                 pch_i2c_speed = 100;
 233
 234         reg_value = PCH_I2CCTL_I2CMEN;
 235         if (pch_i2c_speed == FAST_MODE_CLK) {
 236                 reg_value |= FAST_MODE_EN;
 237                 pch_dbg(adap, "Fast mode enabled\n");
 238         }
 239
 240         if (pch_clk > PCH_MAX_CLK)
 241                 pch_clk = 62500;
 242
 243         pch_i2cbc = (pch_clk + (pch_i2c_speed * 4)) / pch_i2c_speed * 8;
 244         /* Set transfer speed in I2CBC */
 245         iowrite32(pch_i2cbc, p + PCH_I2CBC);
 246
 247         pch_i2ctmr = (pch_clk) / 8;
 248         iowrite32(pch_i2ctmr, p + PCH_I2CTMR);
 249
 250         reg_value |= NORMAL_INTR_ENBL;  /* Enable interrupts in normal mode */
 251         iowrite32(reg_value, p + PCH_I2CCTL);
 252
 253         pch_dbg(adap,
 254                 "I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
 255                 ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr);
 256
 257         init_waitqueue_head(&pch_event);
 258 }
 259
 260 static inline bool ktime_lt(const ktime_t cmp1, const ktime_t cmp2)
 261 {
 262         return cmp1.tv64 < cmp2.tv64;
 263 }
 264
 265 /**
 266  * pch_i2c_wait_for_bus_idle() - check the status of bus.
 267  * @adap:       Pointer to struct i2c_algo_pch_data.
 268  * @timeout:    waiting time counter (us).
 269  */
 270 static s32 pch_i2c_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
 271                                      s32 timeout)
 272 {
 273         void __iomem *p = adap->pch_base_address;
 274
 275         /* MAX timeout value is timeout*1000*1000nsec */
 276         ktime_t ns_val = ktime_add_ns(ktime_get(), timeout*1000*1000);
 277         do {
 278                 if ((ioread32(p + PCH_I2CSR) & I2CMBB_BIT) == 0)
 279                         break;
 280                 msleep(20);
 281         } while (ktime_lt(ktime_get(), ns_val));
 282
 283         pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR));
 284
 285         if (timeout == 0) {
 286                 pch_err(adap, "%s: Timeout Error.return%d\n", __func__, -ETIME);
 287                 return -ETIME;
 288         }
 289
 290         return 0;
 291 }
 292
 293 /**
 294  * pch_i2c_start() - Generate I2C start condition in normal mode.
 295  * @adap:       Pointer to struct i2c_algo_pch_data.
 296  *
 297  * Generate I2C start condition in normal mode by setting I2CCTL.I2CMSTA to 1.
 298  */
 299 static void pch_i2c_start(struct i2c_algo_pch_data *adap)
 300 {
 301         void __iomem *p = adap->pch_base_address;
 302         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 303         pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
 304 }
 305
 306 /**
 307  * pch_i2c_wait_for_xfer_complete() - initiates a wait for the tx complete event
 308  * @adap:       Pointer to struct i2c_algo_pch_data.
 309  */
 310 static s32 pch_i2c_wait_for_xfer_complete(struct i2c_algo_pch_data *adap)
 311 {
 312         s32 ret;
 313         ret = wait_event_timeout(pch_event,
 314                         (adap->pch_event_flag != 0), msecs_to_jiffies(50));
 315         if (ret < 0) {
 316                 pch_err(adap, "timeout: %x\n", adap->pch_event_flag);
 317                 return ret;
 318         }
 319
 320         if (ret == 0) {
 321                 pch_err(adap, "timeout: %x\n", adap->pch_event_flag);
 322                 return -ETIMEDOUT;
 323         }
 324
 325         if (adap->pch_event_flag & I2C_ERROR_MASK) {
 326                 pch_err(adap, "error bits set: %x\n", adap->pch_event_flag);
 327                 return -EIO;
 328         }
 329
 330         adap->pch_event_flag = 0;
 331
 332         return 0;
 333 }
 334
 335 /**
 336  * pch_i2c_getack() - to confirm ACK/NACK
 337  * @adap:       Pointer to struct i2c_algo_pch_data.
 338  */
 339 static s32 pch_i2c_getack(struct i2c_algo_pch_data *adap)
 340 {
 341         u32 reg_val;
 342         void __iomem *p = adap->pch_base_address;
 343         reg_val = ioread32(p + PCH_I2CSR) & PCH_GETACK;
 344
 345         if (reg_val != 0) {
 346                 pch_err(adap, "return%d\n", -EPROTO);
 347                 return -EPROTO;
 348         }
 349
 350         return 0;
 351 }
 352
 353 /**
 354  * pch_i2c_stop() - generate stop condition in normal mode.
 355  * @adap:       Pointer to struct i2c_algo_pch_data.
 356  */
 357 static void pch_i2c_stop(struct i2c_algo_pch_data *adap)
 358 {
 359         void __iomem *p = adap->pch_base_address;
 360         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 361         /* clear the start bit */
 362         pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
 363 }
 364
 365 /**
 366  * pch_i2c_repstart() - generate repeated start condition in normal mode
 367  * @adap:       Pointer to struct i2c_algo_pch_data.
 368  */
 369 static void pch_i2c_repstart(struct i2c_algo_pch_data *adap)
 370 {
 371         void __iomem *p = adap->pch_base_address;
 372         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 373         pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_REPSTART);
 374 }
 375
 376 /**
 377  * pch_i2c_writebytes() - write data to I2C bus in normal mode
 378  * @i2c_adap:   Pointer to the struct i2c_adapter.
 379  * @last:       specifies whether last message or not.
 380  *              In the case of compound mode it will be 1 for last message,
 381  *              otherwise 0.
 382  * @first:      specifies whether first message or not.
 383  *              1 for first message otherwise 0.
 384  */
 385 static s32 pch_i2c_writebytes(struct i2c_adapter *i2c_adap,
 386                               struct i2c_msg *msgs, u32 last, u32 first)
 387 {
 388         struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
 389         u8 *buf;
 390         u32 length;
 391         u32 addr;
 392         u32 addr_2_msb;
 393         u32 addr_8_lsb;
 394         s32 wrcount;
 395         void __iomem *p = adap->pch_base_address;
 396
 397         length = msgs->len;
 398         buf = msgs->buf;
 399         addr = msgs->addr;
 400
 401         /* enable master tx */
 402         pch_setbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
 403
 404         pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n", ioread32(p + PCH_I2CCTL),
 405                 length);
 406
 407         if (first) {
 408                 if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
 409                         return -ETIME;
 410         }
 411
 412         if (msgs->flags & I2C_M_TEN) {
 413                 addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7);
 414                 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
 415                 if (first)
 416                         pch_i2c_start(adap);
 417                 if (pch_i2c_wait_for_xfer_complete(adap) == 0 &&
 418                     pch_i2c_getack(adap) == 0) {
 419                         addr_8_lsb = (addr & I2C_ADDR_MSK);
 420                         iowrite32(addr_8_lsb, p + PCH_I2CDR);
 421                 } else {
 422                         pch_i2c_stop(adap);
 423                         return -ETIME;
 424                 }
 425         } else {
 426                 /* set 7 bit slave address and R/W bit as 0 */
 427                 iowrite32(addr << 1, p + PCH_I2CDR);
 428                 if (first)
 429                         pch_i2c_start(adap);
 430         }
 431
 432         if ((pch_i2c_wait_for_xfer_complete(adap) == 0) &&
 433             (pch_i2c_getack(adap) == 0)) {
 434                 for (wrcount = 0; wrcount < length; ++wrcount) {
 435                         /* write buffer value to I2C data register */
 436                         iowrite32(buf[wrcount], p + PCH_I2CDR);
 437                         pch_dbg(adap, "writing %x to Data register\n",
 438                                 buf[wrcount]);
 439
 440                         if (pch_i2c_wait_for_xfer_complete(adap) != 0)
 441                                 return -ETIME;
 442
 443                         if (pch_i2c_getack(adap))
 444                                 return -EIO;
 445                 }
 446
 447                 /* check if this is the last message */
 448                 if (last)
 449                         pch_i2c_stop(adap);
 450                 else
 451                         pch_i2c_repstart(adap);
 452         } else {
 453                 pch_i2c_stop(adap);
 454                 return -EIO;
 455         }
 456
 457         pch_dbg(adap, "return=%d\n", wrcount);
 458
 459         return wrcount;
 460 }
 461
 462 /**
 463  * pch_i2c_sendack() - send ACK
 464  * @adap:       Pointer to struct i2c_algo_pch_data.
 465  */
 466 static void pch_i2c_sendack(struct i2c_algo_pch_data *adap)
 467 {
 468         void __iomem *p = adap->pch_base_address;
 469         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 470         pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
 471 }
 472
 473 /**
 474  * pch_i2c_sendnack() - send NACK
 475  * @adap:       Pointer to struct i2c_algo_pch_data.
 476  */
 477 static void pch_i2c_sendnack(struct i2c_algo_pch_data *adap)
 478 {
 479         void __iomem *p = adap->pch_base_address;
 480         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 481         pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
 482 }
 483
 484 /**
 485  * pch_i2c_readbytes() - read data  from I2C bus in normal mode.
 486  * @i2c_adap:   Pointer to the struct i2c_adapter.
 487  * @msgs:       Pointer to i2c_msg structure.
 488  * @last:       specifies whether last message or not.
 489  * @first:      specifies whether first message or not.
 490  */
 491 static s32 pch_i2c_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
 492                              u32 last, u32 first)
 493 {
 494         struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
 495
 496         u8 *buf;
 497         u32 count;
 498         u32 length;
 499         u32 addr;
 500         u32 addr_2_msb;
 501         void __iomem *p = adap->pch_base_address;
 502
 503         length = msgs->len;
 504         buf = msgs->buf;
 505         addr = msgs->addr;
 506
 507         /* enable master reception */
 508         pch_clrbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
 509
 510         if (first) {
 511                 if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
 512                         return -ETIME;
 513         }
 514
 515         if (msgs->flags & I2C_M_TEN) {
 516                 addr_2_msb = (((addr & I2C_MSB_2B_MSK) >> 7) | (I2C_RD));
 517                 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
 518
 519         } else {
 520                 /* 7 address bits + R/W bit */
 521                 addr = (((addr) << 1) | (I2C_RD));
 522                 iowrite32(addr, p + PCH_I2CDR);
 523         }
 524
 525         /* check if it is the first message */
 526         if (first)
 527                 pch_i2c_start(adap);
 528
 529         if ((pch_i2c_wait_for_xfer_complete(adap) == 0) &&
 530             (pch_i2c_getack(adap) == 0)) {
 531                 pch_dbg(adap, "return %d\n", 0);
 532
 533                 if (length == 0) {
 534                         pch_i2c_stop(adap);
 535                         ioread32(p + PCH_I2CDR); /* Dummy read needs */
 536
 537                         count = length;
 538                 } else {
 539                         int read_index;
 540                         int loop;
 541                         pch_i2c_sendack(adap);
 542
 543                         /* Dummy read */
 544                         for (loop = 1, read_index = 0; loop < length; loop++) {
 545                                 buf[read_index] = ioread32(p + PCH_I2CDR);
 546
 547                                 if (loop != 1)
 548                                         read_index++;
 549
 550                                 if (pch_i2c_wait_for_xfer_complete(adap) != 0) {
 551                                         pch_i2c_stop(adap);
 552                                         return -ETIME;
 553                                 }
 554                         }       /* end for */
 555
 556                         pch_i2c_sendnack(adap);
 557
 558                         buf[read_index] = ioread32(p + PCH_I2CDR);
 559
 560                         if (length != 1)
 561                                 read_index++;
 562
 563                         if (pch_i2c_wait_for_xfer_complete(adap) == 0) {
 564                                 if (last)
 565                                         pch_i2c_stop(adap);
 566                                 else
 567                                         pch_i2c_repstart(adap);
 568
 569                                 buf[read_index++] = ioread32(p + PCH_I2CDR);
 570                                 count = read_index;
 571                         } else {
 572                                 count = -ETIME;
 573                         }
 574
 575                 }
 576         } else {
 577                 count = -ETIME;
 578                 pch_i2c_stop(adap);
 579         }
 580
 581         return count;
 582 }
 583
 584 /**
 585  * pch_i2c_cb() - Interrupt handler Call back function
 586  * @adap:       Pointer to struct i2c_algo_pch_data.
 587  */
 588 static void pch_i2c_cb(struct i2c_algo_pch_data *adap)
 589 {
 590         u32 sts;
 591         void __iomem *p = adap->pch_base_address;
 592
 593         sts = ioread32(p + PCH_I2CSR);
 594         sts &= (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT);
 595         if (sts & I2CMAL_BIT)
 596                 adap->pch_event_flag |= I2CMAL_EVENT;
 597
 598         if (sts & I2CMCF_BIT)
 599                 adap->pch_event_flag |= I2CMCF_EVENT;
 600
 601         /* clear the applicable bits */
 602         pch_clrbit(adap->pch_base_address, PCH_I2CSR, sts);
 603
 604         pch_dbg(adap, "PCH_I2CSR = %x\n", ioread32(p + PCH_I2CSR));
 605
 606         wake_up(&pch_event);
 607 }
 608
 609 /**
 610  * pch_i2c_handler() - interrupt handler for the PCH I2C controller
 611  * @irq:        irq number.
 612  * @pData:      cookie passed back to the handler function.
 613  */
 614 static irqreturn_t pch_i2c_handler(int irq, void *pData)
 615 {
 616         u32 reg_val;
 617         int flag;
 618         int i;
 619         struct adapter_info *adap_info = pData;
 620         void __iomem *p;
 621         u32 mode;
 622
 623         for (i = 0, flag = 0; i < adap_info->ch_num; i++) {
 624                 p = adap_info->pch_data[i].pch_base_address;
 625                 mode = ioread32(p + PCH_I2CMOD);
 626                 mode &= BUFFER_MODE | EEPROM_SR_MODE;
 627                 if (mode != NORMAL_MODE) {
 628                         pch_err(adap_info->pch_data,
 629                                 "I2C-%d mode(%d) is not supported\n", mode, i);
 630                         continue;
 631                 }
 632                 reg_val = ioread32(p + PCH_I2CSR);
 633                 if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT)) {
 634                         pch_i2c_cb(&adap_info->pch_data[i]);
 635                         flag = 1;
 636                 }
 637         }
 638
 639         return flag ? IRQ_HANDLED : IRQ_NONE;
 640 }
 641
 642 /**
 643  * pch_i2c_xfer() - Reading adnd writing data through I2C bus
 644  * @i2c_adap:   Pointer to the struct i2c_adapter.
 645  * @msgs:       Pointer to i2c_msg structure.
 646  * @num:        number of messages.
 647  */
 648 static s32 pch_i2c_xfer(struct i2c_adapter *i2c_adap,
 649                         struct i2c_msg *msgs, s32 num)
 650 {
 651         struct i2c_msg *pmsg;
 652         u32 i = 0;
 653         u32 status;
 654         u32 msglen;
 655         u32 subaddrlen;
 656         s32 ret;
 657
 658         struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
 659
 660         ret = mutex_lock_interruptible(&pch_mutex);
 661         if (ret)
 662                 return -ERESTARTSYS;
 663
 664         if (adap->p_adapter_info->pch_i2c_suspended) {
 665                 mutex_unlock(&pch_mutex);
 666                 return -EBUSY;
 667         }
 668
 669         pch_dbg(adap, "adap->p_adapter_info->pch_i2c_suspended is %d\n",
 670                 adap->p_adapter_info->pch_i2c_suspended);
 671         /* transfer not completed */
 672         adap->pch_i2c_xfer_in_progress = true;
 673
 674         pmsg = &msgs[0];
 675         pmsg->flags |= adap->pch_buff_mode_en;
 676         status = pmsg->flags;
 677         pch_dbg(adap,
 678                 "After invoking I2C_MODE_SEL :flag= 0x%x\n", status);
 679         /* calculate sub address length and message length */
 680         /* these are applicable only for buffer mode */
 681         subaddrlen = pmsg->buf[0];
 682         /* calculate actual message length excluding
 683          * the sub address fields */
 684         msglen = (pmsg->len) - (subaddrlen + 1);
 685         if (status & (I2C_M_RD)) {
 686                 pch_dbg(adap, "invoking pch_i2c_readbytes\n");
 687                 ret = pch_i2c_readbytes(i2c_adap, pmsg, (i + 1 == num),
 688                                    (i == 0));
 689         } else {
 690                 pch_dbg(adap, "invoking pch_i2c_writebytes\n");
 691                 ret = pch_i2c_writebytes(i2c_adap, pmsg, (i + 1 == num),
 692                                     (i == 0));
 693         }
 694
 695         adap->pch_i2c_xfer_in_progress = false; /* transfer completed */
 696
 697         mutex_unlock(&pch_mutex);
 698
 699         return ret;
 700 }
 701
 702 /**
 703  * pch_i2c_func() - return the functionality of the I2C driver
 704  * @adap:       Pointer to struct i2c_algo_pch_data.
 705  */
 706 static u32 pch_i2c_func(struct i2c_adapter *adap)
 707 {
 708         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
 709 }
 710
 711 static struct i2c_algorithm pch_algorithm = {
 712         .master_xfer = pch_i2c_xfer,
 713         .functionality = pch_i2c_func
 714 };
 715
 716 /**
 717  * pch_i2c_disbl_int() - Disable PCH I2C interrupts
 718  * @adap:       Pointer to struct i2c_algo_pch_data.
 719  */
 720 static void pch_i2c_disbl_int(struct i2c_algo_pch_data *adap)
 721 {
 722         void __iomem *p = adap->pch_base_address;
 723
 724         pch_clrbit(adap->pch_base_address, PCH_I2CCTL, NORMAL_INTR_ENBL);
 725
 726         iowrite32(EEPROM_RST_INTR_DISBL, p + PCH_I2CESRMSK);
 727
 728         iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK);
 729 }
 730
 731 static int __devinit pch_i2c_probe(struct pci_dev *pdev,
 732                                    const struct pci_device_id *id)
 733 {
 734         void __iomem *base_addr;
 735         int ret;
 736         int i, j;
 737         struct adapter_info *adap_info;
 738         struct i2c_adapter *pch_adap;
 739
 740         pch_pci_dbg(pdev, "Entered.\n");
 741
 742         adap_info = kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
 743         if (adap_info == NULL) {
 744                 pch_pci_err(pdev, "Memory allocation FAILED\n");
 745                 return -ENOMEM;
 746         }
 747
 748         ret = pci_enable_device(pdev);
 749         if (ret) {
 750                 pch_pci_err(pdev, "pci_enable_device FAILED\n");
 751                 goto err_pci_enable;
 752         }
 753
 754         ret = pci_request_regions(pdev, KBUILD_MODNAME);
 755         if (ret) {
 756                 pch_pci_err(pdev, "pci_request_regions FAILED\n");
 757                 goto err_pci_req;
 758         }
 759
 760         base_addr = pci_iomap(pdev, 1, 0);
 761
 762         if (base_addr == NULL) {
 763                 pch_pci_err(pdev, "pci_iomap FAILED\n");
 764                 ret = -ENOMEM;
 765                 goto err_pci_iomap;
 766         }
 767
 768         /* Set the number of I2C channel instance */
 769         adap_info->ch_num = id->driver_data;
 770
 771         for (i = 0; i < adap_info->ch_num; i++) {
 772                 pch_adap = &adap_info->pch_data[i].pch_adapter;
 773                 adap_info->pch_i2c_suspended = false;
 774
 775                 adap_info->pch_data[i].p_adapter_info = adap_info;
 776
 777                 pch_adap->owner = THIS_MODULE;
 778                 pch_adap->class = I2C_CLASS_HWMON;
 779                 strcpy(pch_adap->name, KBUILD_MODNAME);
 780                 pch_adap->algo = &pch_algorithm;
 781                 pch_adap->algo_data = &adap_info->pch_data[i];
 782
 783                 /* base_addr + offset; */
 784                 adap_info->pch_data[i].pch_base_address = base_addr + 0x100 * i;
 785
 786                 pch_adap->dev.parent = &pdev->dev;
 787
 788                 ret = i2c_add_adapter(pch_adap);
 789                 if (ret) {
 790                         pch_pci_err(pdev, "i2c_add_adapter[ch:%d] FAILED\n", i);
 791                         goto err_i2c_add_adapter;
 792                 }
 793
 794                 pch_i2c_init(&adap_info->pch_data[i]);
 795         }
 796         ret = request_irq(pdev->irq, pch_i2c_handler, IRQF_SHARED,
 797                   KBUILD_MODNAME, adap_info);
 798         if (ret) {
 799                 pch_pci_err(pdev, "request_irq FAILED\n");
 800                 goto err_i2c_add_adapter;
 801         }
 802
 803         pci_set_drvdata(pdev, adap_info);
 804         pch_pci_dbg(pdev, "returns %d.\n", ret);
 805         return 0;
 806
 807 err_i2c_add_adapter:
 808         for (j = 0; j < i; j++)
 809                 i2c_del_adapter(&adap_info->pch_data[j].pch_adapter);
 810         pci_iounmap(pdev, base_addr);
 811 err_pci_iomap:
 812         pci_release_regions(pdev);
 813 err_pci_req:
 814         pci_disable_device(pdev);
 815 err_pci_enable:
 816         kfree(adap_info);
 817         return ret;
 818 }
 819
 820 static void __devexit pch_i2c_remove(struct pci_dev *pdev)
 821 {
 822         int i;
 823         struct adapter_info *adap_info = pci_get_drvdata(pdev);
 824
 825         free_irq(pdev->irq, adap_info);
 826
 827         for (i = 0; i < adap_info->ch_num; i++) {
 828                 pch_i2c_disbl_int(&adap_info->pch_data[i]);
 829                 i2c_del_adapter(&adap_info->pch_data[i].pch_adapter);
 830         }
 831
 832         if (adap_info->pch_data[0].pch_base_address)
 833                 pci_iounmap(pdev, adap_info->pch_data[0].pch_base_address);
 834
 835         for (i = 0; i < adap_info->ch_num; i++)
 836                 adap_info->pch_data[i].pch_base_address = 0;
 837
 838         pci_set_drvdata(pdev, NULL);
 839
 840         pci_release_regions(pdev);
 841
 842         pci_disable_device(pdev);
 843         kfree(adap_info);
 844 }
 845
 846 #ifdef CONFIG_PM
 847 static int pch_i2c_suspend(struct pci_dev *pdev, pm_message_t state)
 848 {
 849         int ret;
 850         int i;
 851         struct adapter_info *adap_info = pci_get_drvdata(pdev);
 852         void __iomem *p = adap_info->pch_data[0].pch_base_address;
 853
 854         adap_info->pch_i2c_suspended = true;
 855
 856         for (i = 0; i < adap_info->ch_num; i++) {
 857                 while ((adap_info->pch_data[i].pch_i2c_xfer_in_progress)) {
 858                         /* Wait until all channel transfers are completed */
 859                         msleep(20);
 860                 }
 861         }
 862
 863         /* Disable the i2c interrupts */
 864         for (i = 0; i < adap_info->ch_num; i++)
 865                 pch_i2c_disbl_int(&adap_info->pch_data[i]);
 866
 867         pch_pci_dbg(pdev, "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
 868                 "invoked function pch_i2c_disbl_int successfully\n",
 869                 ioread32(p + PCH_I2CSR), ioread32(p + PCH_I2CBUFSTA),
 870                 ioread32(p + PCH_I2CESRSTA));
 871
 872         ret = pci_save_state(pdev);
 873
 874         if (ret) {
 875                 pch_pci_err(pdev, "pci_save_state\n");
 876                 return ret;
 877         }
 878
 879         pci_enable_wake(pdev, PCI_D3hot, 0);
 880         pci_disable_device(pdev);
 881         pci_set_power_state(pdev, pci_choose_state(pdev, state));
 882
 883         return 0;
 884 }
 885
 886 static int pch_i2c_resume(struct pci_dev *pdev)
 887 {
 888         int i;
 889         struct adapter_info *adap_info = pci_get_drvdata(pdev);
 890
 891         pci_set_power_state(pdev, PCI_D0);
 892         pci_restore_state(pdev);
 893
 894         if (pci_enable_device(pdev) < 0) {
 895                 pch_pci_err(pdev, "pch_i2c_resume:pci_enable_device FAILED\n");
 896                 return -EIO;
 897         }
 898
 899         pci_enable_wake(pdev, PCI_D3hot, 0);
 900
 901         for (i = 0; i < adap_info->ch_num; i++)
 902                 pch_i2c_init(&adap_info->pch_data[i]);
 903
 904         adap_info->pch_i2c_suspended = false;
 905
 906         return 0;
 907 }
 908 #else
 909 #define pch_i2c_suspend NULL
 910 #define pch_i2c_resume NULL
 911 #endif
 912
 913 static struct pci_driver pch_pcidriver = {
 914         .name = KBUILD_MODNAME,
 915         .id_table = pch_pcidev_id,
 916         .probe = pch_i2c_probe,
 917         .remove = __devexit_p(pch_i2c_remove),
 918         .suspend = pch_i2c_suspend,
 919         .resume = pch_i2c_resume
 920 };
 921
 922 static int __init pch_pci_init(void)
 923 {
 924         return pci_register_driver(&pch_pcidriver);
 925 }
 926 module_init(pch_pci_init);
 927
 928 static void __exit pch_pci_exit(void)
 929 {
 930         pci_unregister_driver(&pch_pcidriver);
 931 }
 932 module_exit(pch_pci_exit);
 933
 934 MODULE_DESCRIPTION("Intel EG20T PCH/OKI SEMICONDUCTOR ML7213 IOH I2C Driver");
 935 MODULE_LICENSE("GPL");
 936 MODULE_AUTHOR("Tomoya MORINAGA. <tomoya-linux@dsn.okisemi.com>");
 937 module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR));
 938 module_param(pch_clk, int, (S_IRUSR | S_IWUSR));