drivers/i2c/busses/i2c-davinci.c

   1 /*
   2  * TI DAVINCI I2C adapter driver.
   3  *
   4  * Copyright (C) 2006 Texas Instruments.
   5  * Copyright (C) 2007 MontaVista Software Inc.
   6  *
   7  * Updated by Vinod & Sudhakar Feb 2005
   8  *
   9  * ----------------------------------------------------------------------------
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24  * ----------------------------------------------------------------------------
  25  *
  26  */
  27 #include <linux/kernel.h>
  28 #include <linux/module.h>
  29 #include <linux/delay.h>
  30 #include <linux/i2c.h>
  31 #include <linux/clk.h>
  32 #include <linux/errno.h>
  33 #include <linux/sched.h>
  34 #include <linux/err.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/platform_device.h>
  37 #include <linux/io.h>
  38 #include <linux/slab.h>
  39 #include <linux/cpufreq.h>
  40 #include <linux/gpio.h>
  41
  42 #include <mach/hardware.h>
  43 #include <mach/i2c.h>
  44
  45 /* ----- global defines ----------------------------------------------- */
  46
  47 #define DAVINCI_I2C_TIMEOUT     (1*HZ)
  48 #define DAVINCI_I2C_MAX_TRIES   2
  49 #define I2C_DAVINCI_INTR_ALL    (DAVINCI_I2C_IMR_AAS | \
  50                                  DAVINCI_I2C_IMR_SCD | \
  51                                  DAVINCI_I2C_IMR_ARDY | \
  52                                  DAVINCI_I2C_IMR_NACK | \
  53                                  DAVINCI_I2C_IMR_AL)
  54
  55 #define DAVINCI_I2C_OAR_REG     0x00
  56 #define DAVINCI_I2C_IMR_REG     0x04
  57 #define DAVINCI_I2C_STR_REG     0x08
  58 #define DAVINCI_I2C_CLKL_REG    0x0c
  59 #define DAVINCI_I2C_CLKH_REG    0x10
  60 #define DAVINCI_I2C_CNT_REG     0x14
  61 #define DAVINCI_I2C_DRR_REG     0x18
  62 #define DAVINCI_I2C_SAR_REG     0x1c
  63 #define DAVINCI_I2C_DXR_REG     0x20
  64 #define DAVINCI_I2C_MDR_REG     0x24
  65 #define DAVINCI_I2C_IVR_REG     0x28
  66 #define DAVINCI_I2C_EMDR_REG    0x2c
  67 #define DAVINCI_I2C_PSC_REG     0x30
  68
  69 #define DAVINCI_I2C_IVR_AAS     0x07
  70 #define DAVINCI_I2C_IVR_SCD     0x06
  71 #define DAVINCI_I2C_IVR_XRDY    0x05
  72 #define DAVINCI_I2C_IVR_RDR     0x04
  73 #define DAVINCI_I2C_IVR_ARDY    0x03
  74 #define DAVINCI_I2C_IVR_NACK    0x02
  75 #define DAVINCI_I2C_IVR_AL      0x01
  76
  77 #define DAVINCI_I2C_STR_BB      BIT(12)
  78 #define DAVINCI_I2C_STR_RSFULL  BIT(11)
  79 #define DAVINCI_I2C_STR_SCD     BIT(5)
  80 #define DAVINCI_I2C_STR_ARDY    BIT(2)
  81 #define DAVINCI_I2C_STR_NACK    BIT(1)
  82 #define DAVINCI_I2C_STR_AL      BIT(0)
  83
  84 #define DAVINCI_I2C_MDR_NACK    BIT(15)
  85 #define DAVINCI_I2C_MDR_STT     BIT(13)
  86 #define DAVINCI_I2C_MDR_STP     BIT(11)
  87 #define DAVINCI_I2C_MDR_MST     BIT(10)
  88 #define DAVINCI_I2C_MDR_TRX     BIT(9)
  89 #define DAVINCI_I2C_MDR_XA      BIT(8)
  90 #define DAVINCI_I2C_MDR_RM      BIT(7)
  91 #define DAVINCI_I2C_MDR_IRS     BIT(5)
  92
  93 #define DAVINCI_I2C_IMR_AAS     BIT(6)
  94 #define DAVINCI_I2C_IMR_SCD     BIT(5)
  95 #define DAVINCI_I2C_IMR_XRDY    BIT(4)
  96 #define DAVINCI_I2C_IMR_RRDY    BIT(3)
  97 #define DAVINCI_I2C_IMR_ARDY    BIT(2)
  98 #define DAVINCI_I2C_IMR_NACK    BIT(1)
  99 #define DAVINCI_I2C_IMR_AL      BIT(0)
 100
 101 struct davinci_i2c_dev {
 102         struct device           *dev;
 103         void __iomem            *base;
 104         struct completion       cmd_complete;
 105         struct clk              *clk;
 106         int                     cmd_err;
 107         u8                      *buf;
 108         size_t                  buf_len;
 109         int                     irq;
 110         int                     stop;
 111         u8                      terminate;
 112         struct i2c_adapter      adapter;
 113 #ifdef CONFIG_CPU_FREQ
 114         struct completion       xfr_complete;
 115         struct notifier_block   freq_transition;
 116 #endif
 117 };
 118
 119 /* default platform data to use if not supplied in the platform_device */
 120 static struct davinci_i2c_platform_data davinci_i2c_platform_data_default = {
 121         .bus_freq       = 100,
 122         .bus_delay      = 0,
 123 };
 124
 125 static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev,
 126                                          int reg, u16 val)
 127 {
 128         __raw_writew(val, i2c_dev->base + reg);
 129 }
 130
 131 static inline u16 davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg)
 132 {
 133         return __raw_readw(i2c_dev->base + reg);
 134 }
 135
 136 /* Generate a pulse on the i2c clock pin. */
 137 static void generic_i2c_clock_pulse(unsigned int scl_pin)
 138 {
 139         u16 i;
 140
 141         if (scl_pin) {
 142                 /* Send high and low on the SCL line */
 143                 for (i = 0; i < 9; i++) {
 144                         gpio_set_value(scl_pin, 0);
 145                         udelay(20);
 146                         gpio_set_value(scl_pin, 1);
 147                         udelay(20);
 148                 }
 149         }
 150 }
 151
 152 /* This routine does i2c bus recovery as specified in the
 153  * i2c protocol Rev. 03 section 3.16 titled "Bus clear"
 154  */
 155 static void i2c_recover_bus(struct davinci_i2c_dev *dev)
 156 {
 157         u32 flag = 0;
 158         struct davinci_i2c_platform_data *pdata = dev->dev->platform_data;
 159
 160         dev_err(dev->dev, "initiating i2c bus recovery\n");
 161         /* Send NACK to the slave */
 162         flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
 163         flag |=  DAVINCI_I2C_MDR_NACK;
 164         /* write the data into mode register */
 165         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
 166         if (pdata)
 167                 generic_i2c_clock_pulse(pdata->scl_pin);
 168         /* Send STOP */
 169         flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
 170         flag |= DAVINCI_I2C_MDR_STP;
 171         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
 172 }
 173
 174 static inline void davinci_i2c_reset_ctrl(struct davinci_i2c_dev *i2c_dev,
 175                                                                 int val)
 176 {
 177         u16 w;
 178
 179         w = davinci_i2c_read_reg(i2c_dev, DAVINCI_I2C_MDR_REG);
 180         if (!val)       /* put I2C into reset */
 181                 w &= ~DAVINCI_I2C_MDR_IRS;
 182         else            /* take I2C out of reset */
 183                 w |= DAVINCI_I2C_MDR_IRS;
 184
 185         davinci_i2c_write_reg(i2c_dev, DAVINCI_I2C_MDR_REG, w);
 186 }
 187
 188 static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev)
 189 {
 190         struct davinci_i2c_platform_data *pdata = dev->dev->platform_data;
 191         u16 psc;
 192         u32 clk;
 193         u32 d;
 194         u32 clkh;
 195         u32 clkl;
 196         u32 input_clock = clk_get_rate(dev->clk);
 197
 198         /* NOTE: I2C Clock divider programming info
 199          * As per I2C specs the following formulas provide prescaler
 200          * and low/high divider values
 201          * input clk --> PSC Div -----------> ICCL/H Div --> output clock
 202          *                       module clk
 203          *
 204          * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ]
 205          *
 206          * Thus,
 207          * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d;
 208          *
 209          * where if PSC == 0, d = 7,
 210          *       if PSC == 1, d = 6
 211          *       if PSC > 1 , d = 5
 212          */
 213
 214         /* get minimum of 7 MHz clock, but max of 12 MHz */
 215         psc = (input_clock / 7000000) - 1;
 216         if ((input_clock / (psc + 1)) > 12000000)
 217                 psc++;  /* better to run under spec than over */
 218         d = (psc >= 2) ? 5 : 7 - psc;
 219
 220         clk = ((input_clock / (psc + 1)) / (pdata->bus_freq * 1000)) - (d << 1);
 221         clkh = clk >> 1;
 222         clkl = clk - clkh;
 223
 224         davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc);
 225         davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh);
 226         davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl);
 227
 228         dev_dbg(dev->dev, "input_clock = %d, CLK = %d\n", input_clock, clk);
 229 }
 230
 231 /*
 232  * This function configures I2C and brings I2C out of reset.
 233  * This function is called during I2C init function. This function
 234  * also gets called if I2C encounters any errors.
 235  */
 236 static int i2c_davinci_init(struct davinci_i2c_dev *dev)
 237 {
 238         struct davinci_i2c_platform_data *pdata = dev->dev->platform_data;
 239
 240         if (!pdata)
 241                 pdata = &davinci_i2c_platform_data_default;
 242
 243         /* put I2C into reset */
 244         davinci_i2c_reset_ctrl(dev, 0);
 245
 246         /* compute clock dividers */
 247         i2c_davinci_calc_clk_dividers(dev);
 248
 249         /* Respond at reserved "SMBus Host" slave address" (and zero);
 250          * we seem to have no option to not respond...
 251          */
 252         davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, 0x08);
 253
 254         dev_dbg(dev->dev, "PSC  = %d\n",
 255                 davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG));
 256         dev_dbg(dev->dev, "CLKL = %d\n",
 257                 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG));
 258         dev_dbg(dev->dev, "CLKH = %d\n",
 259                 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG));
 260         dev_dbg(dev->dev, "bus_freq = %dkHz, bus_delay = %d\n",
 261                 pdata->bus_freq, pdata->bus_delay);
 262
 263         /* Take the I2C module out of reset: */
 264         davinci_i2c_reset_ctrl(dev, 1);
 265
 266         /* Enable interrupts */
 267         davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL);
 268
 269         return 0;
 270 }
 271
 272 /*
 273  * Waiting for bus not busy
 274  */
 275 static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev,
 276                                          char allow_sleep)
 277 {
 278         unsigned long timeout;
 279         static u16 to_cnt;
 280
 281         timeout = jiffies + dev->adapter.timeout;
 282         while (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG)
 283                & DAVINCI_I2C_STR_BB) {
 284                 if (to_cnt <= DAVINCI_I2C_MAX_TRIES) {
 285                         if (time_after(jiffies, timeout)) {
 286                                 dev_warn(dev->dev,
 287                                 "timeout waiting for bus ready\n");
 288                                 to_cnt++;
 289                                 return -ETIMEDOUT;
 290                         } else {
 291                                 to_cnt = 0;
 292                                 i2c_recover_bus(dev);
 293                                 i2c_davinci_init(dev);
 294                         }
 295                 }
 296                 if (allow_sleep)
 297                         schedule_timeout(1);
 298         }
 299
 300         return 0;
 301 }
 302
 303 /*
 304  * Low level master read/write transaction. This function is called
 305  * from i2c_davinci_xfer.
 306  */
 307 static int
 308 i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
 309 {
 310         struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
 311         struct davinci_i2c_platform_data *pdata = dev->dev->platform_data;
 312         u32 flag;
 313         u16 w;
 314         int r;
 315
 316         if (!pdata)
 317                 pdata = &davinci_i2c_platform_data_default;
 318         /* Introduce a delay, required for some boards (e.g Davinci EVM) */
 319         if (pdata->bus_delay)
 320                 udelay(pdata->bus_delay);
 321
 322         /* set the slave address */
 323         davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr);
 324
 325         dev->buf = msg->buf;
 326         dev->buf_len = msg->len;
 327         dev->stop = stop;
 328
 329         davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len);
 330
 331         INIT_COMPLETION(dev->cmd_complete);
 332         dev->cmd_err = 0;
 333
 334         /* Take I2C out of reset and configure it as master */
 335         flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST;
 336
 337         /* if the slave address is ten bit address, enable XA bit */
 338         if (msg->flags & I2C_M_TEN)
 339                 flag |= DAVINCI_I2C_MDR_XA;
 340         if (!(msg->flags & I2C_M_RD))
 341                 flag |= DAVINCI_I2C_MDR_TRX;
 342         if (msg->len == 0)
 343                 flag |= DAVINCI_I2C_MDR_RM;
 344
 345         /* Enable receive or transmit interrupts */
 346         w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG);
 347         if (msg->flags & I2C_M_RD)
 348                 w |= DAVINCI_I2C_IMR_RRDY;
 349         else
 350                 w |= DAVINCI_I2C_IMR_XRDY;
 351         davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w);
 352
 353         dev->terminate = 0;
 354
 355         /*
 356          * Write mode register first as needed for correct behaviour
 357          * on OMAP-L138, but don't set STT yet to avoid a race with XRDY
 358          * occurring before we have loaded DXR
 359          */
 360         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
 361
 362         /*
 363          * First byte should be set here, not after interrupt,
 364          * because transmit-data-ready interrupt can come before
 365          * NACK-interrupt during sending of previous message and
 366          * ICDXR may have wrong data
 367          * It also saves us one interrupt, slightly faster
 368          */
 369         if ((!(msg->flags & I2C_M_RD)) && dev->buf_len) {
 370                 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, *dev->buf++);
 371                 dev->buf_len--;
 372         }
 373
 374         /* Set STT to begin transmit now DXR is loaded */
 375         flag |= DAVINCI_I2C_MDR_STT;
 376         if (stop && msg->len != 0)
 377                 flag |= DAVINCI_I2C_MDR_STP;
 378         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
 379
 380         r = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
 381                                                       dev->adapter.timeout);
 382         if (r == 0) {
 383                 dev_err(dev->dev, "controller timed out\n");
 384                 i2c_recover_bus(dev);
 385                 i2c_davinci_init(dev);
 386                 dev->buf_len = 0;
 387                 return -ETIMEDOUT;
 388         }
 389         if (dev->buf_len) {
 390                 /* This should be 0 if all bytes were transferred
 391                  * or dev->cmd_err denotes an error.
 392                  * A signal may have aborted the transfer.
 393                  */
 394                 if (r >= 0) {
 395                         dev_err(dev->dev, "abnormal termination buf_len=%i\n",
 396                                 dev->buf_len);
 397                         r = -EREMOTEIO;
 398                 }
 399                 dev->terminate = 1;
 400                 wmb();
 401                 dev->buf_len = 0;
 402         }
 403         if (r < 0)
 404                 return r;
 405
 406         /* no error */
 407         if (likely(!dev->cmd_err))
 408                 return msg->len;
 409
 410         /* We have an error */
 411         if (dev->cmd_err & DAVINCI_I2C_STR_AL) {
 412                 i2c_davinci_init(dev);
 413                 return -EIO;
 414         }
 415
 416         if (dev->cmd_err & DAVINCI_I2C_STR_NACK) {
 417                 if (msg->flags & I2C_M_IGNORE_NAK)
 418                         return msg->len;
 419                 if (stop) {
 420                         w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
 421                         w |= DAVINCI_I2C_MDR_STP;
 422                         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
 423                 }
 424                 return -EREMOTEIO;
 425         }
 426         return -EIO;
 427 }
 428
 429 /*
 430  * Prepare controller for a transaction and call i2c_davinci_xfer_msg
 431  */
 432 static int
 433 i2c_davinci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 434 {
 435         struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
 436         int i;
 437         int ret;
 438
 439         dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
 440
 441         ret = i2c_davinci_wait_bus_not_busy(dev, 1);
 442         if (ret < 0) {
 443                 dev_warn(dev->dev, "timeout waiting for bus ready\n");
 444                 return ret;
 445         }
 446
 447         for (i = 0; i < num; i++) {
 448                 ret = i2c_davinci_xfer_msg(adap, &msgs[i], (i == (num - 1)));
 449                 dev_dbg(dev->dev, "%s [%d/%d] ret: %d\n", __func__, i + 1, num,
 450                         ret);
 451                 if (ret < 0)
 452                         return ret;
 453         }
 454
 455 #ifdef CONFIG_CPU_FREQ
 456         complete(&dev->xfr_complete);
 457 #endif
 458
 459         return num;
 460 }
 461
 462 static u32 i2c_davinci_func(struct i2c_adapter *adap)
 463 {
 464         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 465 }
 466
 467 static void terminate_read(struct davinci_i2c_dev *dev)
 468 {
 469         u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
 470         w |= DAVINCI_I2C_MDR_NACK;
 471         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
 472
 473         /* Throw away data */
 474         davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG);
 475         if (!dev->terminate)
 476                 dev_err(dev->dev, "RDR IRQ while no data requested\n");
 477 }
 478 static void terminate_write(struct davinci_i2c_dev *dev)
 479 {
 480         u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
 481         w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP;
 482         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
 483
 484         if (!dev->terminate)
 485                 dev_dbg(dev->dev, "TDR IRQ while no data to send\n");
 486 }
 487
 488 /*
 489  * Interrupt service routine. This gets called whenever an I2C interrupt
 490  * occurs.
 491  */
 492 static irqreturn_t i2c_davinci_isr(int this_irq, void *dev_id)
 493 {
 494         struct davinci_i2c_dev *dev = dev_id;
 495         u32 stat;
 496         int count = 0;
 497         u16 w;
 498
 499         while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) {
 500                 dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat);
 501                 if (count++ == 100) {
 502                         dev_warn(dev->dev, "Too much work in one IRQ\n");
 503                         break;
 504                 }
 505
 506                 switch (stat) {
 507                 case DAVINCI_I2C_IVR_AL:
 508                         /* Arbitration lost, must retry */
 509                         dev->cmd_err |= DAVINCI_I2C_STR_AL;
 510                         dev->buf_len = 0;
 511                         complete(&dev->cmd_complete);
 512                         break;
 513
 514                 case DAVINCI_I2C_IVR_NACK:
 515                         dev->cmd_err |= DAVINCI_I2C_STR_NACK;
 516                         dev->buf_len = 0;
 517                         complete(&dev->cmd_complete);
 518                         break;
 519
 520                 case DAVINCI_I2C_IVR_ARDY:
 521                         davinci_i2c_write_reg(dev,
 522                                 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY);
 523                         if (((dev->buf_len == 0) && (dev->stop != 0)) ||
 524                             (dev->cmd_err & DAVINCI_I2C_STR_NACK)) {
 525                                 w = davinci_i2c_read_reg(dev,
 526                                                          DAVINCI_I2C_MDR_REG);
 527                                 w |= DAVINCI_I2C_MDR_STP;
 528                                 davinci_i2c_write_reg(dev,
 529                                                       DAVINCI_I2C_MDR_REG, w);
 530                         }
 531                         complete(&dev->cmd_complete);
 532                         break;
 533
 534                 case DAVINCI_I2C_IVR_RDR:
 535                         if (dev->buf_len) {
 536                                 *dev->buf++ =
 537                                     davinci_i2c_read_reg(dev,
 538                                                          DAVINCI_I2C_DRR_REG);
 539                                 dev->buf_len--;
 540                                 if (dev->buf_len)
 541                                         continue;
 542
 543                                 davinci_i2c_write_reg(dev,
 544                                         DAVINCI_I2C_STR_REG,
 545                                         DAVINCI_I2C_IMR_RRDY);
 546                         } else {
 547                                 /* signal can terminate transfer */
 548                                 terminate_read(dev);
 549                         }
 550                         break;
 551
 552                 case DAVINCI_I2C_IVR_XRDY:
 553                         if (dev->buf_len) {
 554                                 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG,
 555                                                       *dev->buf++);
 556                                 dev->buf_len--;
 557                                 if (dev->buf_len)
 558                                         continue;
 559
 560                                 w = davinci_i2c_read_reg(dev,
 561                                                          DAVINCI_I2C_IMR_REG);
 562                                 w &= ~DAVINCI_I2C_IMR_XRDY;
 563                                 davinci_i2c_write_reg(dev,
 564                                                       DAVINCI_I2C_IMR_REG,
 565                                                       w);
 566                         } else {
 567                                 /* signal can terminate transfer */
 568                                 terminate_write(dev);
 569                         }
 570                         break;
 571
 572                 case DAVINCI_I2C_IVR_SCD:
 573                         davinci_i2c_write_reg(dev,
 574                                 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD);
 575                         complete(&dev->cmd_complete);
 576                         break;
 577
 578                 case DAVINCI_I2C_IVR_AAS:
 579                         dev_dbg(dev->dev, "Address as slave interrupt\n");
 580                         break;
 581
 582                 default:
 583                         dev_warn(dev->dev, "Unrecognized irq stat %d\n", stat);
 584                         break;
 585                 }
 586         }
 587
 588         return count ? IRQ_HANDLED : IRQ_NONE;
 589 }
 590
 591 #ifdef CONFIG_CPU_FREQ
 592 static int i2c_davinci_cpufreq_transition(struct notifier_block *nb,
 593                                      unsigned long val, void *data)
 594 {
 595         struct davinci_i2c_dev *dev;
 596
 597         dev = container_of(nb, struct davinci_i2c_dev, freq_transition);
 598         if (val == CPUFREQ_PRECHANGE) {
 599                 wait_for_completion(&dev->xfr_complete);
 600                 davinci_i2c_reset_ctrl(dev, 0);
 601         } else if (val == CPUFREQ_POSTCHANGE) {
 602                 i2c_davinci_calc_clk_dividers(dev);
 603                 davinci_i2c_reset_ctrl(dev, 1);
 604         }
 605
 606         return 0;
 607 }
 608
 609 static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev)
 610 {
 611         dev->freq_transition.notifier_call = i2c_davinci_cpufreq_transition;
 612
 613         return cpufreq_register_notifier(&dev->freq_transition,
 614                                          CPUFREQ_TRANSITION_NOTIFIER);
 615 }
 616
 617 static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev)
 618 {
 619         cpufreq_unregister_notifier(&dev->freq_transition,
 620                                     CPUFREQ_TRANSITION_NOTIFIER);
 621 }
 622 #else
 623 static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev)
 624 {
 625         return 0;
 626 }
 627
 628 static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev)
 629 {
 630 }
 631 #endif
 632
 633 static struct i2c_algorithm i2c_davinci_algo = {
 634         .master_xfer    = i2c_davinci_xfer,
 635         .functionality  = i2c_davinci_func,
 636 };
 637
 638 static int davinci_i2c_probe(struct platform_device *pdev)
 639 {
 640         struct davinci_i2c_dev *dev;
 641         struct i2c_adapter *adap;
 642         struct resource *mem, *irq, *ioarea;
 643         int r;
 644
 645         /* NOTE: driver uses the static register mapping */
 646         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 647         if (!mem) {
 648                 dev_err(&pdev->dev, "no mem resource?\n");
 649                 return -ENODEV;
 650         }
 651
 652         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 653         if (!irq) {
 654                 dev_err(&pdev->dev, "no irq resource?\n");
 655                 return -ENODEV;
 656         }
 657
 658         ioarea = request_mem_region(mem->start, resource_size(mem),
 659                                     pdev->name);
 660         if (!ioarea) {
 661                 dev_err(&pdev->dev, "I2C region already claimed\n");
 662                 return -EBUSY;
 663         }
 664
 665         dev = kzalloc(sizeof(struct davinci_i2c_dev), GFP_KERNEL);
 666         if (!dev) {
 667                 r = -ENOMEM;
 668                 goto err_release_region;
 669         }
 670
 671         init_completion(&dev->cmd_complete);
 672 #ifdef CONFIG_CPU_FREQ
 673         init_completion(&dev->xfr_complete);
 674 #endif
 675         dev->dev = get_device(&pdev->dev);
 676         dev->irq = irq->start;
 677         platform_set_drvdata(pdev, dev);
 678
 679         dev->clk = clk_get(&pdev->dev, NULL);
 680         if (IS_ERR(dev->clk)) {
 681                 r = -ENODEV;
 682                 goto err_free_mem;
 683         }
 684         clk_enable(dev->clk);
 685
 686         dev->base = ioremap(mem->start, resource_size(mem));
 687         if (!dev->base) {
 688                 r = -EBUSY;
 689                 goto err_mem_ioremap;
 690         }
 691
 692         i2c_davinci_init(dev);
 693
 694         r = request_irq(dev->irq, i2c_davinci_isr, 0, pdev->name, dev);
 695         if (r) {
 696                 dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
 697                 goto err_unuse_clocks;
 698         }
 699
 700         r = i2c_davinci_cpufreq_register(dev);
 701         if (r) {
 702                 dev_err(&pdev->dev, "failed to register cpufreq\n");
 703                 goto err_free_irq;
 704         }
 705
 706         adap = &dev->adapter;
 707         i2c_set_adapdata(adap, dev);
 708         adap->owner = THIS_MODULE;
 709         adap->class = I2C_CLASS_HWMON;
 710         strlcpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name));
 711         adap->algo = &i2c_davinci_algo;
 712         adap->dev.parent = &pdev->dev;
 713         adap->timeout = DAVINCI_I2C_TIMEOUT;
 714
 715         adap->nr = pdev->id;
 716         r = i2c_add_numbered_adapter(adap);
 717         if (r) {
 718                 dev_err(&pdev->dev, "failure adding adapter\n");
 719                 goto err_free_irq;
 720         }
 721
 722         return 0;
 723
 724 err_free_irq:
 725         free_irq(dev->irq, dev);
 726 err_unuse_clocks:
 727         iounmap(dev->base);
 728 err_mem_ioremap:
 729         clk_disable(dev->clk);
 730         clk_put(dev->clk);
 731         dev->clk = NULL;
 732 err_free_mem:
 733         platform_set_drvdata(pdev, NULL);
 734         put_device(&pdev->dev);
 735         kfree(dev);
 736 err_release_region:
 737         release_mem_region(mem->start, resource_size(mem));
 738
 739         return r;
 740 }
 741
 742 static int davinci_i2c_remove(struct platform_device *pdev)
 743 {
 744         struct davinci_i2c_dev *dev = platform_get_drvdata(pdev);
 745         struct resource *mem;
 746
 747         i2c_davinci_cpufreq_deregister(dev);
 748
 749         platform_set_drvdata(pdev, NULL);
 750         i2c_del_adapter(&dev->adapter);
 751         put_device(&pdev->dev);
 752
 753         clk_disable(dev->clk);
 754         clk_put(dev->clk);
 755         dev->clk = NULL;
 756
 757         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, 0);
 758         free_irq(IRQ_I2C, dev);
 759         iounmap(dev->base);
 760         kfree(dev);
 761
 762         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 763         release_mem_region(mem->start, resource_size(mem));
 764         return 0;
 765 }
 766
 767 #ifdef CONFIG_PM
 768 static int davinci_i2c_suspend(struct device *dev)
 769 {
 770         struct platform_device *pdev = to_platform_device(dev);
 771         struct davinci_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
 772
 773         /* put I2C into reset */
 774         davinci_i2c_reset_ctrl(i2c_dev, 0);
 775         clk_disable(i2c_dev->clk);
 776
 777         return 0;
 778 }
 779
 780 static int davinci_i2c_resume(struct device *dev)
 781 {
 782         struct platform_device *pdev = to_platform_device(dev);
 783         struct davinci_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
 784
 785         clk_enable(i2c_dev->clk);
 786         /* take I2C out of reset */
 787         davinci_i2c_reset_ctrl(i2c_dev, 1);
 788
 789         return 0;
 790 }
 791
 792 static const struct dev_pm_ops davinci_i2c_pm = {
 793         .suspend        = davinci_i2c_suspend,
 794         .resume         = davinci_i2c_resume,
 795 };
 796
 797 #define davinci_i2c_pm_ops (&davinci_i2c_pm)
 798 #else
 799 #define davinci_i2c_pm_ops NULL
 800 #endif
 801
 802 /* work with hotplug and coldplug */
 803 MODULE_ALIAS("platform:i2c_davinci");
 804
 805 static struct platform_driver davinci_i2c_driver = {
 806         .probe          = davinci_i2c_probe,
 807         .remove         = davinci_i2c_remove,
 808         .driver         = {
 809                 .name   = "i2c_davinci",
 810                 .owner  = THIS_MODULE,
 811                 .pm     = davinci_i2c_pm_ops,
 812         },
 813 };
 814
 815 /* I2C may be needed to bring up other drivers */
 816 static int __init davinci_i2c_init_driver(void)
 817 {
 818         return platform_driver_register(&davinci_i2c_driver);
 819 }
 820 subsys_initcall(davinci_i2c_init_driver);
 821
 822 static void __exit davinci_i2c_exit_driver(void)
 823 {
 824         platform_driver_unregister(&davinci_i2c_driver);
 825 }
 826 module_exit(davinci_i2c_exit_driver);
 827
 828 MODULE_AUTHOR("Texas Instruments India");
 829 MODULE_DESCRIPTION("TI DaVinci I2C bus adapter");
 830 MODULE_LICENSE("GPL");