drivers/i2c/busses/i2c-bfin-twi.c

   1 /*
   2  * Blackfin On-Chip Two Wire Interface Driver
   3  *
   4  * Copyright 2005-2007 Analog Devices Inc.
   5  *
   6  * Enter bugs at http://blackfin.uclinux.org/
   7  *
   8  * Licensed under the GPL-2 or later.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/kernel.h>
  13 #include <linux/init.h>
  14 #include <linux/i2c.h>
  15 #include <linux/slab.h>
  16 #include <linux/io.h>
  17 #include <linux/mm.h>
  18 #include <linux/timer.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/completion.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/delay.h>
  24
  25 #include <asm/blackfin.h>
  26 #include <asm/portmux.h>
  27 #include <asm/irq.h>
  28
  29 /* SMBus mode*/
  30 #define TWI_I2C_MODE_STANDARD           1
  31 #define TWI_I2C_MODE_STANDARDSUB        2
  32 #define TWI_I2C_MODE_COMBINED           3
  33 #define TWI_I2C_MODE_REPEAT             4
  34
  35 struct bfin_twi_iface {
  36         int                     irq;
  37         spinlock_t              lock;
  38         char                    read_write;
  39         u8                      command;
  40         u8                      *transPtr;
  41         int                     readNum;
  42         int                     writeNum;
  43         int                     cur_mode;
  44         int                     manual_stop;
  45         int                     result;
  46         struct i2c_adapter      adap;
  47         struct completion       complete;
  48         struct i2c_msg          *pmsg;
  49         int                     msg_num;
  50         int                     cur_msg;
  51         u16                     saved_clkdiv;
  52         u16                     saved_control;
  53         void __iomem            *regs_base;
  54 };
  55
  56
  57 #define DEFINE_TWI_REG(reg, off) \
  58 static inline u16 read_##reg(struct bfin_twi_iface *iface) \
  59         { return bfin_read16(iface->regs_base + (off)); } \
  60 static inline void write_##reg(struct bfin_twi_iface *iface, u16 v) \
  61         { bfin_write16(iface->regs_base + (off), v); }
  62
  63 DEFINE_TWI_REG(CLKDIV, 0x00)
  64 DEFINE_TWI_REG(CONTROL, 0x04)
  65 DEFINE_TWI_REG(SLAVE_CTL, 0x08)
  66 DEFINE_TWI_REG(SLAVE_STAT, 0x0C)
  67 DEFINE_TWI_REG(SLAVE_ADDR, 0x10)
  68 DEFINE_TWI_REG(MASTER_CTL, 0x14)
  69 DEFINE_TWI_REG(MASTER_STAT, 0x18)
  70 DEFINE_TWI_REG(MASTER_ADDR, 0x1C)
  71 DEFINE_TWI_REG(INT_STAT, 0x20)
  72 DEFINE_TWI_REG(INT_MASK, 0x24)
  73 DEFINE_TWI_REG(FIFO_CTL, 0x28)
  74 DEFINE_TWI_REG(FIFO_STAT, 0x2C)
  75 DEFINE_TWI_REG(XMT_DATA8, 0x80)
  76 DEFINE_TWI_REG(XMT_DATA16, 0x84)
  77 DEFINE_TWI_REG(RCV_DATA8, 0x88)
  78 DEFINE_TWI_REG(RCV_DATA16, 0x8C)
  79
  80 static const u16 pin_req[2][3] = {
  81         {P_TWI0_SCL, P_TWI0_SDA, 0},
  82         {P_TWI1_SCL, P_TWI1_SDA, 0},
  83 };
  84
  85 static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface,
  86                                         unsigned short twi_int_status)
  87 {
  88         unsigned short mast_stat = read_MASTER_STAT(iface);
  89
  90         if (twi_int_status & XMTSERV) {
  91                 /* Transmit next data */
  92                 if (iface->writeNum > 0) {
  93                         SSYNC();
  94                         write_XMT_DATA8(iface, *(iface->transPtr++));
  95                         iface->writeNum--;
  96                 }
  97                 /* start receive immediately after complete sending in
  98                  * combine mode.
  99                  */
 100                 else if (iface->cur_mode == TWI_I2C_MODE_COMBINED)
 101                         write_MASTER_CTL(iface,
 102                                 read_MASTER_CTL(iface) | MDIR | RSTART);
 103                 else if (iface->manual_stop)
 104                         write_MASTER_CTL(iface,
 105                                 read_MASTER_CTL(iface) | STOP);
 106                 else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
 107                          iface->cur_msg + 1 < iface->msg_num) {
 108                         if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD)
 109                                 write_MASTER_CTL(iface,
 110                                         read_MASTER_CTL(iface) | RSTART | MDIR);
 111                         else
 112                                 write_MASTER_CTL(iface,
 113                                         (read_MASTER_CTL(iface) | RSTART) & ~MDIR);
 114                 }
 115         }
 116         if (twi_int_status & RCVSERV) {
 117                 if (iface->readNum > 0) {
 118                         /* Receive next data */
 119                         *(iface->transPtr) = read_RCV_DATA8(iface);
 120                         if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
 121                                 /* Change combine mode into sub mode after
 122                                  * read first data.
 123                                  */
 124                                 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 125                                 /* Get read number from first byte in block
 126                                  * combine mode.
 127                                  */
 128                                 if (iface->readNum == 1 && iface->manual_stop)
 129                                         iface->readNum = *iface->transPtr + 1;
 130                         }
 131                         iface->transPtr++;
 132                         iface->readNum--;
 133                 } else if (iface->manual_stop) {
 134                         write_MASTER_CTL(iface,
 135                                 read_MASTER_CTL(iface) | STOP);
 136                 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
 137                            iface->cur_msg + 1 < iface->msg_num) {
 138                         if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD)
 139                                 write_MASTER_CTL(iface,
 140                                         read_MASTER_CTL(iface) | RSTART | MDIR);
 141                         else
 142                                 write_MASTER_CTL(iface,
 143                                         (read_MASTER_CTL(iface) | RSTART) & ~MDIR);
 144                 }
 145         }
 146         if (twi_int_status & MERR) {
 147                 write_INT_MASK(iface, 0);
 148                 write_MASTER_STAT(iface, 0x3e);
 149                 write_MASTER_CTL(iface, 0);
 150                 iface->result = -EIO;
 151
 152                 if (mast_stat & LOSTARB)
 153                         dev_dbg(&iface->adap.dev, "Lost Arbitration\n");
 154                 if (mast_stat & ANAK)
 155                         dev_dbg(&iface->adap.dev, "Address Not Acknowledged\n");
 156                 if (mast_stat & DNAK)
 157                         dev_dbg(&iface->adap.dev, "Data Not Acknowledged\n");
 158                 if (mast_stat & BUFRDERR)
 159                         dev_dbg(&iface->adap.dev, "Buffer Read Error\n");
 160                 if (mast_stat & BUFWRERR)
 161                         dev_dbg(&iface->adap.dev, "Buffer Write Error\n");
 162
 163                 /* Faulty slave devices, may drive SDA low after a transfer
 164                  * finishes. To release the bus this code generates up to 9
 165                  * extra clocks until SDA is released.
 166                  */
 167
 168                 if (read_MASTER_STAT(iface) & SDASEN) {
 169                         int cnt = 9;
 170                         do {
 171                                 write_MASTER_CTL(iface, SCLOVR);
 172                                 udelay(6);
 173                                 write_MASTER_CTL(iface, 0);
 174                                 udelay(6);
 175                         } while ((read_MASTER_STAT(iface) & SDASEN) && cnt--);
 176
 177                         write_MASTER_CTL(iface, SDAOVR | SCLOVR);
 178                         udelay(6);
 179                         write_MASTER_CTL(iface, SDAOVR);
 180                         udelay(6);
 181                         write_MASTER_CTL(iface, 0);
 182                 }
 183
 184                 /* If it is a quick transfer, only address without data,
 185                  * not an err, return 1.
 186                  */
 187                 if (iface->cur_mode == TWI_I2C_MODE_STANDARD &&
 188                         iface->transPtr == NULL &&
 189                         (twi_int_status & MCOMP) && (mast_stat & DNAK))
 190                         iface->result = 1;
 191
 192                 complete(&iface->complete);
 193                 return;
 194         }
 195         if (twi_int_status & MCOMP) {
 196                 if ((read_MASTER_CTL(iface) & MEN) == 0 &&
 197                         (iface->cur_mode == TWI_I2C_MODE_REPEAT ||
 198                         iface->cur_mode == TWI_I2C_MODE_COMBINED)) {
 199                         iface->result = -1;
 200                         write_INT_MASK(iface, 0);
 201                         write_MASTER_CTL(iface, 0);
 202                 } else if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
 203                         if (iface->readNum == 0) {
 204                                 /* set the read number to 1 and ask for manual
 205                                  * stop in block combine mode
 206                                  */
 207                                 iface->readNum = 1;
 208                                 iface->manual_stop = 1;
 209                                 write_MASTER_CTL(iface,
 210                                         read_MASTER_CTL(iface) | (0xff << 6));
 211                         } else {
 212                                 /* set the readd number in other
 213                                  * combine mode.
 214                                  */
 215                                 write_MASTER_CTL(iface,
 216                                         (read_MASTER_CTL(iface) &
 217                                         (~(0xff << 6))) |
 218                                         (iface->readNum << 6));
 219                         }
 220                         /* remove restart bit and enable master receive */
 221                         write_MASTER_CTL(iface,
 222                                 read_MASTER_CTL(iface) & ~RSTART);
 223                 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
 224                                 iface->cur_msg+1 < iface->msg_num) {
 225                         iface->cur_msg++;
 226                         iface->transPtr = iface->pmsg[iface->cur_msg].buf;
 227                         iface->writeNum = iface->readNum =
 228                                 iface->pmsg[iface->cur_msg].len;
 229                         /* Set Transmit device address */
 230                         write_MASTER_ADDR(iface,
 231                                 iface->pmsg[iface->cur_msg].addr);
 232                         if (iface->pmsg[iface->cur_msg].flags & I2C_M_RD)
 233                                 iface->read_write = I2C_SMBUS_READ;
 234                         else {
 235                                 iface->read_write = I2C_SMBUS_WRITE;
 236                                 /* Transmit first data */
 237                                 if (iface->writeNum > 0) {
 238                                         write_XMT_DATA8(iface,
 239                                                 *(iface->transPtr++));
 240                                         iface->writeNum--;
 241                                 }
 242                         }
 243
 244                         if (iface->pmsg[iface->cur_msg].len <= 255)
 245                                         write_MASTER_CTL(iface,
 246                                         (read_MASTER_CTL(iface) &
 247                                         (~(0xff << 6))) |
 248                                 (iface->pmsg[iface->cur_msg].len << 6));
 249                         else {
 250                                 write_MASTER_CTL(iface,
 251                                         (read_MASTER_CTL(iface) |
 252                                         (0xff << 6)));
 253                                 iface->manual_stop = 1;
 254                         }
 255                         /* remove restart bit and enable master receive */
 256                         write_MASTER_CTL(iface,
 257                                 read_MASTER_CTL(iface) & ~RSTART);
 258                 } else {
 259                         iface->result = 1;
 260                         write_INT_MASK(iface, 0);
 261                         write_MASTER_CTL(iface, 0);
 262                 }
 263         }
 264         complete(&iface->complete);
 265 }
 266
 267 /* Interrupt handler */
 268 static irqreturn_t bfin_twi_interrupt_entry(int irq, void *dev_id)
 269 {
 270         struct bfin_twi_iface *iface = dev_id;
 271         unsigned long flags;
 272         unsigned short twi_int_status;
 273
 274         spin_lock_irqsave(&iface->lock, flags);
 275         while (1) {
 276                 twi_int_status = read_INT_STAT(iface);
 277                 if (!twi_int_status)
 278                         break;
 279                 /* Clear interrupt status */
 280                 write_INT_STAT(iface, twi_int_status);
 281                 bfin_twi_handle_interrupt(iface, twi_int_status);
 282                 SSYNC();
 283         }
 284         spin_unlock_irqrestore(&iface->lock, flags);
 285         return IRQ_HANDLED;
 286 }
 287
 288 /*
 289  * One i2c master transfer
 290  */
 291 static int bfin_twi_do_master_xfer(struct i2c_adapter *adap,
 292                                 struct i2c_msg *msgs, int num)
 293 {
 294         struct bfin_twi_iface *iface = adap->algo_data;
 295         struct i2c_msg *pmsg;
 296         int rc = 0;
 297
 298         if (!(read_CONTROL(iface) & TWI_ENA))
 299                 return -ENXIO;
 300
 301         while (read_MASTER_STAT(iface) & BUSBUSY)
 302                 yield();
 303
 304         iface->pmsg = msgs;
 305         iface->msg_num = num;
 306         iface->cur_msg = 0;
 307
 308         pmsg = &msgs[0];
 309         if (pmsg->flags & I2C_M_TEN) {
 310                 dev_err(&adap->dev, "10 bits addr not supported!\n");
 311                 return -EINVAL;
 312         }
 313
 314         iface->cur_mode = TWI_I2C_MODE_REPEAT;
 315         iface->manual_stop = 0;
 316         iface->transPtr = pmsg->buf;
 317         iface->writeNum = iface->readNum = pmsg->len;
 318         iface->result = 0;
 319         init_completion(&(iface->complete));
 320         /* Set Transmit device address */
 321         write_MASTER_ADDR(iface, pmsg->addr);
 322
 323         /* FIFO Initiation. Data in FIFO should be
 324          *  discarded before start a new operation.
 325          */
 326         write_FIFO_CTL(iface, 0x3);
 327         SSYNC();
 328         write_FIFO_CTL(iface, 0);
 329         SSYNC();
 330
 331         if (pmsg->flags & I2C_M_RD)
 332                 iface->read_write = I2C_SMBUS_READ;
 333         else {
 334                 iface->read_write = I2C_SMBUS_WRITE;
 335                 /* Transmit first data */
 336                 if (iface->writeNum > 0) {
 337                         write_XMT_DATA8(iface, *(iface->transPtr++));
 338                         iface->writeNum--;
 339                         SSYNC();
 340                 }
 341         }
 342
 343         /* clear int stat */
 344         write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
 345
 346         /* Interrupt mask . Enable XMT, RCV interrupt */
 347         write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
 348         SSYNC();
 349
 350         if (pmsg->len <= 255)
 351                 write_MASTER_CTL(iface, pmsg->len << 6);
 352         else {
 353                 write_MASTER_CTL(iface, 0xff << 6);
 354                 iface->manual_stop = 1;
 355         }
 356
 357         /* Master enable */
 358         write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
 359                 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
 360                 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
 361         SSYNC();
 362
 363         while (!iface->result) {
 364                 if (!wait_for_completion_timeout(&iface->complete,
 365                         adap->timeout)) {
 366                         iface->result = -1;
 367                         dev_err(&adap->dev, "master transfer timeout\n");
 368                 }
 369         }
 370
 371         if (iface->result == 1)
 372                 rc = iface->cur_msg + 1;
 373         else
 374                 rc = iface->result;
 375
 376         return rc;
 377 }
 378
 379 /*
 380  * Generic i2c master transfer entrypoint
 381  */
 382 static int bfin_twi_master_xfer(struct i2c_adapter *adap,
 383                                 struct i2c_msg *msgs, int num)
 384 {
 385         return bfin_twi_do_master_xfer(adap, msgs, num);
 386 }
 387
 388 /*
 389  * One I2C SMBus transfer
 390  */
 391 int bfin_twi_do_smbus_xfer(struct i2c_adapter *adap, u16 addr,
 392                         unsigned short flags, char read_write,
 393                         u8 command, int size, union i2c_smbus_data *data)
 394 {
 395         struct bfin_twi_iface *iface = adap->algo_data;
 396         int rc = 0;
 397
 398         if (!(read_CONTROL(iface) & TWI_ENA))
 399                 return -ENXIO;
 400
 401         while (read_MASTER_STAT(iface) & BUSBUSY)
 402                 yield();
 403
 404         iface->writeNum = 0;
 405         iface->readNum = 0;
 406
 407         /* Prepare datas & select mode */
 408         switch (size) {
 409         case I2C_SMBUS_QUICK:
 410                 iface->transPtr = NULL;
 411                 iface->cur_mode = TWI_I2C_MODE_STANDARD;
 412                 break;
 413         case I2C_SMBUS_BYTE:
 414                 if (data == NULL)
 415                         iface->transPtr = NULL;
 416                 else {
 417                         if (read_write == I2C_SMBUS_READ)
 418                                 iface->readNum = 1;
 419                         else
 420                                 iface->writeNum = 1;
 421                         iface->transPtr = &data->byte;
 422                 }
 423                 iface->cur_mode = TWI_I2C_MODE_STANDARD;
 424                 break;
 425         case I2C_SMBUS_BYTE_DATA:
 426                 if (read_write == I2C_SMBUS_READ) {
 427                         iface->readNum = 1;
 428                         iface->cur_mode = TWI_I2C_MODE_COMBINED;
 429                 } else {
 430                         iface->writeNum = 1;
 431                         iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 432                 }
 433                 iface->transPtr = &data->byte;
 434                 break;
 435         case I2C_SMBUS_WORD_DATA:
 436                 if (read_write == I2C_SMBUS_READ) {
 437                         iface->readNum = 2;
 438                         iface->cur_mode = TWI_I2C_MODE_COMBINED;
 439                 } else {
 440                         iface->writeNum = 2;
 441                         iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 442                 }
 443                 iface->transPtr = (u8 *)&data->word;
 444                 break;
 445         case I2C_SMBUS_PROC_CALL:
 446                 iface->writeNum = 2;
 447                 iface->readNum = 2;
 448                 iface->cur_mode = TWI_I2C_MODE_COMBINED;
 449                 iface->transPtr = (u8 *)&data->word;
 450                 break;
 451         case I2C_SMBUS_BLOCK_DATA:
 452                 if (read_write == I2C_SMBUS_READ) {
 453                         iface->readNum = 0;
 454                         iface->cur_mode = TWI_I2C_MODE_COMBINED;
 455                 } else {
 456                         iface->writeNum = data->block[0] + 1;
 457                         iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 458                 }
 459                 iface->transPtr = data->block;
 460                 break;
 461         case I2C_SMBUS_I2C_BLOCK_DATA:
 462                 if (read_write == I2C_SMBUS_READ) {
 463                         iface->readNum = data->block[0];
 464                         iface->cur_mode = TWI_I2C_MODE_COMBINED;
 465                 } else {
 466                         iface->writeNum = data->block[0];
 467                         iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 468                 }
 469                 iface->transPtr = (u8 *)&data->block[1];
 470                 break;
 471         default:
 472                 return -1;
 473         }
 474
 475         iface->result = 0;
 476         iface->manual_stop = 0;
 477         iface->read_write = read_write;
 478         iface->command = command;
 479         init_completion(&(iface->complete));
 480
 481         /* FIFO Initiation. Data in FIFO should be discarded before
 482          * start a new operation.
 483          */
 484         write_FIFO_CTL(iface, 0x3);
 485         SSYNC();
 486         write_FIFO_CTL(iface, 0);
 487
 488         /* clear int stat */
 489         write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
 490
 491         /* Set Transmit device address */
 492         write_MASTER_ADDR(iface, addr);
 493         SSYNC();
 494
 495         switch (iface->cur_mode) {
 496         case TWI_I2C_MODE_STANDARDSUB:
 497                 write_XMT_DATA8(iface, iface->command);
 498                 write_INT_MASK(iface, MCOMP | MERR |
 499                         ((iface->read_write == I2C_SMBUS_READ) ?
 500                         RCVSERV : XMTSERV));
 501                 SSYNC();
 502
 503                 if (iface->writeNum + 1 <= 255)
 504                         write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
 505                 else {
 506                         write_MASTER_CTL(iface, 0xff << 6);
 507                         iface->manual_stop = 1;
 508                 }
 509                 /* Master enable */
 510                 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
 511                         ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
 512                 break;
 513         case TWI_I2C_MODE_COMBINED:
 514                 write_XMT_DATA8(iface, iface->command);
 515                 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
 516                 SSYNC();
 517
 518                 if (iface->writeNum > 0)
 519                         write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
 520                 else
 521                         write_MASTER_CTL(iface, 0x1 << 6);
 522                 /* Master enable */
 523                 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
 524                         ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
 525                 break;
 526         default:
 527                 write_MASTER_CTL(iface, 0);
 528                 if (size != I2C_SMBUS_QUICK) {
 529                         /* Don't access xmit data register when this is a
 530                          * read operation.
 531                          */
 532                         if (iface->read_write != I2C_SMBUS_READ) {
 533                                 if (iface->writeNum > 0) {
 534                                         write_XMT_DATA8(iface,
 535                                                 *(iface->transPtr++));
 536                                         if (iface->writeNum <= 255)
 537                                                 write_MASTER_CTL(iface,
 538                                                         iface->writeNum << 6);
 539                                         else {
 540                                                 write_MASTER_CTL(iface,
 541                                                         0xff << 6);
 542                                                 iface->manual_stop = 1;
 543                                         }
 544                                         iface->writeNum--;
 545                                 } else {
 546                                         write_XMT_DATA8(iface, iface->command);
 547                                         write_MASTER_CTL(iface, 1 << 6);
 548                                 }
 549                         } else {
 550                                 if (iface->readNum > 0 && iface->readNum <= 255)
 551                                         write_MASTER_CTL(iface,
 552                                                 iface->readNum << 6);
 553                                 else if (iface->readNum > 255) {
 554                                         write_MASTER_CTL(iface, 0xff << 6);
 555                                         iface->manual_stop = 1;
 556                                 } else
 557                                         break;
 558                         }
 559                 }
 560                 write_INT_MASK(iface, MCOMP | MERR |
 561                         ((iface->read_write == I2C_SMBUS_READ) ?
 562                         RCVSERV : XMTSERV));
 563                 SSYNC();
 564
 565                 /* Master enable */
 566                 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
 567                         ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
 568                         ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
 569                 break;
 570         }
 571         SSYNC();
 572
 573         while (!iface->result) {
 574                 if (!wait_for_completion_timeout(&iface->complete,
 575                         adap->timeout)) {
 576                         iface->result = -1;
 577                         dev_err(&adap->dev, "smbus transfer timeout\n");
 578                 }
 579         }
 580
 581         rc = (iface->result >= 0) ? 0 : -1;
 582
 583         return rc;
 584 }
 585
 586 /*
 587  * Generic I2C SMBus transfer entrypoint
 588  */
 589 int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
 590                         unsigned short flags, char read_write,
 591                         u8 command, int size, union i2c_smbus_data *data)
 592 {
 593         return bfin_twi_do_smbus_xfer(adap, addr, flags,
 594                         read_write, command, size, data);
 595 }
 596
 597 /*
 598  * Return what the adapter supports
 599  */
 600 static u32 bfin_twi_functionality(struct i2c_adapter *adap)
 601 {
 602         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 603                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 604                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL |
 605                I2C_FUNC_I2C | I2C_FUNC_SMBUS_I2C_BLOCK;
 606 }
 607
 608 static struct i2c_algorithm bfin_twi_algorithm = {
 609         .master_xfer   = bfin_twi_master_xfer,
 610         .smbus_xfer    = bfin_twi_smbus_xfer,
 611         .functionality = bfin_twi_functionality,
 612 };
 613
 614 static int i2c_bfin_twi_suspend(struct platform_device *pdev, pm_message_t state)
 615 {
 616         struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
 617
 618         iface->saved_clkdiv = read_CLKDIV(iface);
 619         iface->saved_control = read_CONTROL(iface);
 620
 621         free_irq(iface->irq, iface);
 622
 623         /* Disable TWI */
 624         write_CONTROL(iface, iface->saved_control & ~TWI_ENA);
 625
 626         return 0;
 627 }
 628
 629 static int i2c_bfin_twi_resume(struct platform_device *pdev)
 630 {
 631         struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
 632
 633         int rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
 634                 IRQF_DISABLED, pdev->name, iface);
 635         if (rc) {
 636                 dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
 637                 return -ENODEV;
 638         }
 639
 640         /* Resume TWI interface clock as specified */
 641         write_CLKDIV(iface, iface->saved_clkdiv);
 642
 643         /* Resume TWI */
 644         write_CONTROL(iface, iface->saved_control);
 645
 646         return 0;
 647 }
 648
 649 static int i2c_bfin_twi_probe(struct platform_device *pdev)
 650 {
 651         struct bfin_twi_iface *iface;
 652         struct i2c_adapter *p_adap;
 653         struct resource *res;
 654         int rc;
 655         unsigned int clkhilow;
 656
 657         iface = kzalloc(sizeof(struct bfin_twi_iface), GFP_KERNEL);
 658         if (!iface) {
 659                 dev_err(&pdev->dev, "Cannot allocate memory\n");
 660                 rc = -ENOMEM;
 661                 goto out_error_nomem;
 662         }
 663
 664         spin_lock_init(&(iface->lock));
 665
 666         /* Find and map our resources */
 667         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 668         if (res == NULL) {
 669                 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
 670                 rc = -ENOENT;
 671                 goto out_error_get_res;
 672         }
 673
 674         iface->regs_base = ioremap(res->start, resource_size(res));
 675         if (iface->regs_base == NULL) {
 676                 dev_err(&pdev->dev, "Cannot map IO\n");
 677                 rc = -ENXIO;
 678                 goto out_error_ioremap;
 679         }
 680
 681         iface->irq = platform_get_irq(pdev, 0);
 682         if (iface->irq < 0) {
 683                 dev_err(&pdev->dev, "No IRQ specified\n");
 684                 rc = -ENOENT;
 685                 goto out_error_no_irq;
 686         }
 687
 688         p_adap = &iface->adap;
 689         p_adap->nr = pdev->id;
 690         strlcpy(p_adap->name, pdev->name, sizeof(p_adap->name));
 691         p_adap->algo = &bfin_twi_algorithm;
 692         p_adap->algo_data = iface;
 693         p_adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
 694         p_adap->dev.parent = &pdev->dev;
 695         p_adap->timeout = 5 * HZ;
 696         p_adap->retries = 3;
 697
 698         rc = peripheral_request_list(pin_req[pdev->id], "i2c-bfin-twi");
 699         if (rc) {
 700                 dev_err(&pdev->dev, "Can't setup pin mux!\n");
 701                 goto out_error_pin_mux;
 702         }
 703
 704         rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
 705                 IRQF_DISABLED, pdev->name, iface);
 706         if (rc) {
 707                 dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
 708                 rc = -ENODEV;
 709                 goto out_error_req_irq;
 710         }
 711
 712         /* Set TWI internal clock as 10MHz */
 713         write_CONTROL(iface, ((get_sclk() / 1000 / 1000 + 5) / 10) & 0x7F);
 714
 715         /*
 716          * We will not end up with a CLKDIV=0 because no one will specify
 717          * 20kHz SCL or less in Kconfig now. (5 * 1000 / 20 = 250)
 718          */
 719         clkhilow = ((10 * 1000 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ) + 1) / 2;
 720
 721         /* Set Twi interface clock as specified */
 722         write_CLKDIV(iface, (clkhilow << 8) | clkhilow);
 723
 724         /* Enable TWI */
 725         write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA);
 726         SSYNC();
 727
 728         rc = i2c_add_numbered_adapter(p_adap);
 729         if (rc < 0) {
 730                 dev_err(&pdev->dev, "Can't add i2c adapter!\n");
 731                 goto out_error_add_adapter;
 732         }
 733
 734         platform_set_drvdata(pdev, iface);
 735
 736         dev_info(&pdev->dev, "Blackfin BF5xx on-chip I2C TWI Contoller, "
 737                 "regs_base@%p\n", iface->regs_base);
 738
 739         return 0;
 740
 741 out_error_add_adapter:
 742         free_irq(iface->irq, iface);
 743 out_error_req_irq:
 744 out_error_no_irq:
 745         peripheral_free_list(pin_req[pdev->id]);
 746 out_error_pin_mux:
 747         iounmap(iface->regs_base);
 748 out_error_ioremap:
 749 out_error_get_res:
 750         kfree(iface);
 751 out_error_nomem:
 752         return rc;
 753 }
 754
 755 static int i2c_bfin_twi_remove(struct platform_device *pdev)
 756 {
 757         struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
 758
 759         platform_set_drvdata(pdev, NULL);
 760
 761         i2c_del_adapter(&(iface->adap));
 762         free_irq(iface->irq, iface);
 763         peripheral_free_list(pin_req[pdev->id]);
 764         iounmap(iface->regs_base);
 765         kfree(iface);
 766
 767         return 0;
 768 }
 769
 770 static struct platform_driver i2c_bfin_twi_driver = {
 771         .probe          = i2c_bfin_twi_probe,
 772         .remove         = i2c_bfin_twi_remove,
 773         .suspend        = i2c_bfin_twi_suspend,
 774         .resume         = i2c_bfin_twi_resume,
 775         .driver         = {
 776                 .name   = "i2c-bfin-twi",
 777                 .owner  = THIS_MODULE,
 778         },
 779 };
 780
 781 static int __init i2c_bfin_twi_init(void)
 782 {
 783         return platform_driver_register(&i2c_bfin_twi_driver);
 784 }
 785
 786 static void __exit i2c_bfin_twi_exit(void)
 787 {
 788         platform_driver_unregister(&i2c_bfin_twi_driver);
 789 }
 790
 791 subsys_initcall(i2c_bfin_twi_init);
 792 module_exit(i2c_bfin_twi_exit);
 793
 794 MODULE_AUTHOR("Bryan Wu, Sonic Zhang");
 795 MODULE_DESCRIPTION("Blackfin BF5xx on-chip I2C TWI Contoller Driver");
 796 MODULE_LICENSE("GPL");
 797 MODULE_ALIAS("platform:i2c-bfin-twi");