drivers/i2c/busses/i2c-bfin-twi.c

   1 /*
   2  * Blackfin On-Chip Two Wire Interface Driver
   3  *
   4  * Copyright 2005-2007 Analog Devices Inc.
   5  *
   6  * Enter bugs at http://blackfin.uclinux.org/
   7  *
   8  * Licensed under the GPL-2 or later.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/kernel.h>
  13 #include <linux/init.h>
  14 #include <linux/i2c.h>
  15 #include <linux/slab.h>
  16 #include <linux/io.h>
  17 #include <linux/mm.h>
  18 #include <linux/timer.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/completion.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/delay.h>
  24
  25 #include <asm/blackfin.h>
  26 #include <asm/portmux.h>
  27 #include <asm/irq.h>
  28
  29 /* SMBus mode*/
  30 #define TWI_I2C_MODE_STANDARD           1
  31 #define TWI_I2C_MODE_STANDARDSUB        2
  32 #define TWI_I2C_MODE_COMBINED           3
  33 #define TWI_I2C_MODE_REPEAT             4
  34
  35 struct bfin_twi_iface {
  36         int                     irq;
  37         spinlock_t              lock;
  38         char                    read_write;
  39         u8                      command;
  40         u8                      *transPtr;
  41         int                     readNum;
  42         int                     writeNum;
  43         int                     cur_mode;
  44         int                     manual_stop;
  45         int                     result;
  46         struct i2c_adapter      adap;
  47         struct completion       complete;
  48         struct i2c_msg          *pmsg;
  49         int                     msg_num;
  50         int                     cur_msg;
  51         u16                     saved_clkdiv;
  52         u16                     saved_control;
  53         void __iomem            *regs_base;
  54 };
  55
  56
  57 #define DEFINE_TWI_REG(reg, off) \
  58 static inline u16 read_##reg(struct bfin_twi_iface *iface) \
  59         { return bfin_read16(iface->regs_base + (off)); } \
  60 static inline void write_##reg(struct bfin_twi_iface *iface, u16 v) \
  61         { bfin_write16(iface->regs_base + (off), v); }
  62
  63 DEFINE_TWI_REG(CLKDIV, 0x00)
  64 DEFINE_TWI_REG(CONTROL, 0x04)
  65 DEFINE_TWI_REG(SLAVE_CTL, 0x08)
  66 DEFINE_TWI_REG(SLAVE_STAT, 0x0C)
  67 DEFINE_TWI_REG(SLAVE_ADDR, 0x10)
  68 DEFINE_TWI_REG(MASTER_CTL, 0x14)
  69 DEFINE_TWI_REG(MASTER_STAT, 0x18)
  70 DEFINE_TWI_REG(MASTER_ADDR, 0x1C)
  71 DEFINE_TWI_REG(INT_STAT, 0x20)
  72 DEFINE_TWI_REG(INT_MASK, 0x24)
  73 DEFINE_TWI_REG(FIFO_CTL, 0x28)
  74 DEFINE_TWI_REG(FIFO_STAT, 0x2C)
  75 DEFINE_TWI_REG(XMT_DATA8, 0x80)
  76 DEFINE_TWI_REG(XMT_DATA16, 0x84)
  77 DEFINE_TWI_REG(RCV_DATA8, 0x88)
  78 DEFINE_TWI_REG(RCV_DATA16, 0x8C)
  79
  80 static const u16 pin_req[2][3] = {
  81         {P_TWI0_SCL, P_TWI0_SDA, 0},
  82         {P_TWI1_SCL, P_TWI1_SDA, 0},
  83 };
  84
  85 static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface,
  86                                         unsigned short twi_int_status)
  87 {
  88         unsigned short mast_stat = read_MASTER_STAT(iface);
  89
  90         if (twi_int_status & XMTSERV) {
  91                 /* Transmit next data */
  92                 if (iface->writeNum > 0) {
  93                         SSYNC();
  94                         write_XMT_DATA8(iface, *(iface->transPtr++));
  95                         iface->writeNum--;
  96                 }
  97                 /* start receive immediately after complete sending in
  98                  * combine mode.
  99                  */
 100                 else if (iface->cur_mode == TWI_I2C_MODE_COMBINED)
 101                         write_MASTER_CTL(iface,
 102                                 read_MASTER_CTL(iface) | MDIR | RSTART);
 103                 else if (iface->manual_stop)
 104                         write_MASTER_CTL(iface,
 105                                 read_MASTER_CTL(iface) | STOP);
 106                 else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
 107                          iface->cur_msg + 1 < iface->msg_num) {
 108                         if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD)
 109                                 write_MASTER_CTL(iface,
 110                                         read_MASTER_CTL(iface) | RSTART | MDIR);
 111                         else
 112                                 write_MASTER_CTL(iface,
 113                                         (read_MASTER_CTL(iface) | RSTART) & ~MDIR);
 114                 }
 115         }
 116         if (twi_int_status & RCVSERV) {
 117                 if (iface->readNum > 0) {
 118                         /* Receive next data */
 119                         *(iface->transPtr) = read_RCV_DATA8(iface);
 120                         if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
 121                                 /* Change combine mode into sub mode after
 122                                  * read first data.
 123                                  */
 124                                 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 125                                 /* Get read number from first byte in block
 126                                  * combine mode.
 127                                  */
 128                                 if (iface->readNum == 1 && iface->manual_stop)
 129                                         iface->readNum = *iface->transPtr + 1;
 130                         }
 131                         iface->transPtr++;
 132                         iface->readNum--;
 133                 } else if (iface->manual_stop) {
 134                         write_MASTER_CTL(iface,
 135                                 read_MASTER_CTL(iface) | STOP);
 136                 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
 137                            iface->cur_msg + 1 < iface->msg_num) {
 138                         if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD)
 139                                 write_MASTER_CTL(iface,
 140                                         read_MASTER_CTL(iface) | RSTART | MDIR);
 141                         else
 142                                 write_MASTER_CTL(iface,
 143                                         (read_MASTER_CTL(iface) | RSTART) & ~MDIR);
 144                 }
 145         }
 146         if (twi_int_status & MERR) {
 147                 write_INT_MASK(iface, 0);
 148                 write_MASTER_STAT(iface, 0x3e);
 149                 write_MASTER_CTL(iface, 0);
 150                 iface->result = -EIO;
 151
 152                 if (mast_stat & LOSTARB)
 153                         dev_dbg(&iface->adap.dev, "Lost Arbitration\n");
 154                 if (mast_stat & ANAK)
 155                         dev_dbg(&iface->adap.dev, "Address Not Acknowledged\n");
 156                 if (mast_stat & DNAK)
 157                         dev_dbg(&iface->adap.dev, "Data Not Acknowledged\n");
 158                 if (mast_stat & BUFRDERR)
 159                         dev_dbg(&iface->adap.dev, "Buffer Read Error\n");
 160                 if (mast_stat & BUFWRERR)
 161                         dev_dbg(&iface->adap.dev, "Buffer Write Error\n");
 162
 163                 /* Faulty slave devices, may drive SDA low after a transfer
 164                  * finishes. To release the bus this code generates up to 9
 165                  * extra clocks until SDA is released.
 166                  */
 167
 168                 if (read_MASTER_STAT(iface) & SDASEN) {
 169                         int cnt = 9;
 170                         do {
 171                                 write_MASTER_CTL(iface, SCLOVR);
 172                                 udelay(6);
 173                                 write_MASTER_CTL(iface, 0);
 174                                 udelay(6);
 175                         } while ((read_MASTER_STAT(iface) & SDASEN) && cnt--);
 176
 177                         write_MASTER_CTL(iface, SDAOVR | SCLOVR);
 178                         udelay(6);
 179                         write_MASTER_CTL(iface, SDAOVR);
 180                         udelay(6);
 181                         write_MASTER_CTL(iface, 0);
 182                 }
 183
 184                 /* If it is a quick transfer, only address without data,
 185                  * not an err, return 1.
 186                  */
 187                 if (iface->cur_mode == TWI_I2C_MODE_STANDARD &&
 188                         iface->transPtr == NULL &&
 189                         (twi_int_status & MCOMP) && (mast_stat & DNAK))
 190                         iface->result = 1;
 191
 192                 complete(&iface->complete);
 193                 return;
 194         }
 195         if (twi_int_status & MCOMP) {
 196                 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
 197                         if (iface->readNum == 0) {
 198                                 /* set the read number to 1 and ask for manual
 199                                  * stop in block combine mode
 200                                  */
 201                                 iface->readNum = 1;
 202                                 iface->manual_stop = 1;
 203                                 write_MASTER_CTL(iface,
 204                                         read_MASTER_CTL(iface) | (0xff << 6));
 205                         } else {
 206                                 /* set the readd number in other
 207                                  * combine mode.
 208                                  */
 209                                 write_MASTER_CTL(iface,
 210                                         (read_MASTER_CTL(iface) &
 211                                         (~(0xff << 6))) |
 212                                         (iface->readNum << 6));
 213                         }
 214                         /* remove restart bit and enable master receive */
 215                         write_MASTER_CTL(iface,
 216                                 read_MASTER_CTL(iface) & ~RSTART);
 217                 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
 218                                 iface->cur_msg+1 < iface->msg_num) {
 219                         iface->cur_msg++;
 220                         iface->transPtr = iface->pmsg[iface->cur_msg].buf;
 221                         iface->writeNum = iface->readNum =
 222                                 iface->pmsg[iface->cur_msg].len;
 223                         /* Set Transmit device address */
 224                         write_MASTER_ADDR(iface,
 225                                 iface->pmsg[iface->cur_msg].addr);
 226                         if (iface->pmsg[iface->cur_msg].flags & I2C_M_RD)
 227                                 iface->read_write = I2C_SMBUS_READ;
 228                         else {
 229                                 iface->read_write = I2C_SMBUS_WRITE;
 230                                 /* Transmit first data */
 231                                 if (iface->writeNum > 0) {
 232                                         write_XMT_DATA8(iface,
 233                                                 *(iface->transPtr++));
 234                                         iface->writeNum--;
 235                                 }
 236                         }
 237
 238                         if (iface->pmsg[iface->cur_msg].len <= 255)
 239                                         write_MASTER_CTL(iface,
 240                                         (read_MASTER_CTL(iface) &
 241                                         (~(0xff << 6))) |
 242                                 (iface->pmsg[iface->cur_msg].len << 6));
 243                         else {
 244                                 write_MASTER_CTL(iface,
 245                                         (read_MASTER_CTL(iface) |
 246                                         (0xff << 6)));
 247                                 iface->manual_stop = 1;
 248                         }
 249                         /* remove restart bit and enable master receive */
 250                         write_MASTER_CTL(iface,
 251                                 read_MASTER_CTL(iface) & ~RSTART);
 252                 } else {
 253                         iface->result = 1;
 254                         write_INT_MASK(iface, 0);
 255                         write_MASTER_CTL(iface, 0);
 256                 }
 257         }
 258         complete(&iface->complete);
 259 }
 260
 261 /* Interrupt handler */
 262 static irqreturn_t bfin_twi_interrupt_entry(int irq, void *dev_id)
 263 {
 264         struct bfin_twi_iface *iface = dev_id;
 265         unsigned long flags;
 266         unsigned short twi_int_status;
 267
 268         spin_lock_irqsave(&iface->lock, flags);
 269         while (1) {
 270                 twi_int_status = read_INT_STAT(iface);
 271                 if (!twi_int_status)
 272                         break;
 273                 /* Clear interrupt status */
 274                 write_INT_STAT(iface, twi_int_status);
 275                 bfin_twi_handle_interrupt(iface, twi_int_status);
 276                 SSYNC();
 277         }
 278         spin_unlock_irqrestore(&iface->lock, flags);
 279         return IRQ_HANDLED;
 280 }
 281
 282 /*
 283  * One i2c master transfer
 284  */
 285 static int bfin_twi_do_master_xfer(struct i2c_adapter *adap,
 286                                 struct i2c_msg *msgs, int num)
 287 {
 288         struct bfin_twi_iface *iface = adap->algo_data;
 289         struct i2c_msg *pmsg;
 290         int rc = 0;
 291
 292         if (!(read_CONTROL(iface) & TWI_ENA))
 293                 return -ENXIO;
 294
 295         while (read_MASTER_STAT(iface) & BUSBUSY)
 296                 yield();
 297
 298         iface->pmsg = msgs;
 299         iface->msg_num = num;
 300         iface->cur_msg = 0;
 301
 302         pmsg = &msgs[0];
 303         if (pmsg->flags & I2C_M_TEN) {
 304                 dev_err(&adap->dev, "10 bits addr not supported!\n");
 305                 return -EINVAL;
 306         }
 307
 308         iface->cur_mode = TWI_I2C_MODE_REPEAT;
 309         iface->manual_stop = 0;
 310         iface->transPtr = pmsg->buf;
 311         iface->writeNum = iface->readNum = pmsg->len;
 312         iface->result = 0;
 313         init_completion(&(iface->complete));
 314         /* Set Transmit device address */
 315         write_MASTER_ADDR(iface, pmsg->addr);
 316
 317         /* FIFO Initiation. Data in FIFO should be
 318          *  discarded before start a new operation.
 319          */
 320         write_FIFO_CTL(iface, 0x3);
 321         SSYNC();
 322         write_FIFO_CTL(iface, 0);
 323         SSYNC();
 324
 325         if (pmsg->flags & I2C_M_RD)
 326                 iface->read_write = I2C_SMBUS_READ;
 327         else {
 328                 iface->read_write = I2C_SMBUS_WRITE;
 329                 /* Transmit first data */
 330                 if (iface->writeNum > 0) {
 331                         write_XMT_DATA8(iface, *(iface->transPtr++));
 332                         iface->writeNum--;
 333                         SSYNC();
 334                 }
 335         }
 336
 337         /* clear int stat */
 338         write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
 339
 340         /* Interrupt mask . Enable XMT, RCV interrupt */
 341         write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
 342         SSYNC();
 343
 344         if (pmsg->len <= 255)
 345                 write_MASTER_CTL(iface, pmsg->len << 6);
 346         else {
 347                 write_MASTER_CTL(iface, 0xff << 6);
 348                 iface->manual_stop = 1;
 349         }
 350
 351         /* Master enable */
 352         write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
 353                 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
 354                 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
 355         SSYNC();
 356
 357         while (!iface->result) {
 358                 if (!wait_for_completion_timeout(&iface->complete,
 359                         adap->timeout)) {
 360                         iface->result = -1;
 361                         dev_err(&adap->dev, "master transfer timeout\n");
 362                 }
 363         }
 364
 365         if (iface->result == 1)
 366                 rc = iface->cur_msg + 1;
 367         else
 368                 rc = iface->result;
 369
 370         return rc;
 371 }
 372
 373 /*
 374  * Generic i2c master transfer entrypoint
 375  */
 376 static int bfin_twi_master_xfer(struct i2c_adapter *adap,
 377                                 struct i2c_msg *msgs, int num)
 378 {
 379         return bfin_twi_do_master_xfer(adap, msgs, num);
 380 }
 381
 382 /*
 383  * One I2C SMBus transfer
 384  */
 385 int bfin_twi_do_smbus_xfer(struct i2c_adapter *adap, u16 addr,
 386                         unsigned short flags, char read_write,
 387                         u8 command, int size, union i2c_smbus_data *data)
 388 {
 389         struct bfin_twi_iface *iface = adap->algo_data;
 390         int rc = 0;
 391
 392         if (!(read_CONTROL(iface) & TWI_ENA))
 393                 return -ENXIO;
 394
 395         while (read_MASTER_STAT(iface) & BUSBUSY)
 396                 yield();
 397
 398         iface->writeNum = 0;
 399         iface->readNum = 0;
 400
 401         /* Prepare datas & select mode */
 402         switch (size) {
 403         case I2C_SMBUS_QUICK:
 404                 iface->transPtr = NULL;
 405                 iface->cur_mode = TWI_I2C_MODE_STANDARD;
 406                 break;
 407         case I2C_SMBUS_BYTE:
 408                 if (data == NULL)
 409                         iface->transPtr = NULL;
 410                 else {
 411                         if (read_write == I2C_SMBUS_READ)
 412                                 iface->readNum = 1;
 413                         else
 414                                 iface->writeNum = 1;
 415                         iface->transPtr = &data->byte;
 416                 }
 417                 iface->cur_mode = TWI_I2C_MODE_STANDARD;
 418                 break;
 419         case I2C_SMBUS_BYTE_DATA:
 420                 if (read_write == I2C_SMBUS_READ) {
 421                         iface->readNum = 1;
 422                         iface->cur_mode = TWI_I2C_MODE_COMBINED;
 423                 } else {
 424                         iface->writeNum = 1;
 425                         iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 426                 }
 427                 iface->transPtr = &data->byte;
 428                 break;
 429         case I2C_SMBUS_WORD_DATA:
 430                 if (read_write == I2C_SMBUS_READ) {
 431                         iface->readNum = 2;
 432                         iface->cur_mode = TWI_I2C_MODE_COMBINED;
 433                 } else {
 434                         iface->writeNum = 2;
 435                         iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 436                 }
 437                 iface->transPtr = (u8 *)&data->word;
 438                 break;
 439         case I2C_SMBUS_PROC_CALL:
 440                 iface->writeNum = 2;
 441                 iface->readNum = 2;
 442                 iface->cur_mode = TWI_I2C_MODE_COMBINED;
 443                 iface->transPtr = (u8 *)&data->word;
 444                 break;
 445         case I2C_SMBUS_BLOCK_DATA:
 446                 if (read_write == I2C_SMBUS_READ) {
 447                         iface->readNum = 0;
 448                         iface->cur_mode = TWI_I2C_MODE_COMBINED;
 449                 } else {
 450                         iface->writeNum = data->block[0] + 1;
 451                         iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 452                 }
 453                 iface->transPtr = data->block;
 454                 break;
 455         case I2C_SMBUS_I2C_BLOCK_DATA:
 456                 if (read_write == I2C_SMBUS_READ) {
 457                         iface->readNum = data->block[0];
 458                         iface->cur_mode = TWI_I2C_MODE_COMBINED;
 459                 } else {
 460                         iface->writeNum = data->block[0];
 461                         iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 462                 }
 463                 iface->transPtr = (u8 *)&data->block[1];
 464                 break;
 465         default:
 466                 return -1;
 467         }
 468
 469         iface->result = 0;
 470         iface->manual_stop = 0;
 471         iface->read_write = read_write;
 472         iface->command = command;
 473         init_completion(&(iface->complete));
 474
 475         /* FIFO Initiation. Data in FIFO should be discarded before
 476          * start a new operation.
 477          */
 478         write_FIFO_CTL(iface, 0x3);
 479         SSYNC();
 480         write_FIFO_CTL(iface, 0);
 481
 482         /* clear int stat */
 483         write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
 484
 485         /* Set Transmit device address */
 486         write_MASTER_ADDR(iface, addr);
 487         SSYNC();
 488
 489         switch (iface->cur_mode) {
 490         case TWI_I2C_MODE_STANDARDSUB:
 491                 write_XMT_DATA8(iface, iface->command);
 492                 write_INT_MASK(iface, MCOMP | MERR |
 493                         ((iface->read_write == I2C_SMBUS_READ) ?
 494                         RCVSERV : XMTSERV));
 495                 SSYNC();
 496
 497                 if (iface->writeNum + 1 <= 255)
 498                         write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
 499                 else {
 500                         write_MASTER_CTL(iface, 0xff << 6);
 501                         iface->manual_stop = 1;
 502                 }
 503                 /* Master enable */
 504                 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
 505                         ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
 506                 break;
 507         case TWI_I2C_MODE_COMBINED:
 508                 write_XMT_DATA8(iface, iface->command);
 509                 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
 510                 SSYNC();
 511
 512                 if (iface->writeNum > 0)
 513                         write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
 514                 else
 515                         write_MASTER_CTL(iface, 0x1 << 6);
 516                 /* Master enable */
 517                 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
 518                         ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
 519                 break;
 520         default:
 521                 write_MASTER_CTL(iface, 0);
 522                 if (size != I2C_SMBUS_QUICK) {
 523                         /* Don't access xmit data register when this is a
 524                          * read operation.
 525                          */
 526                         if (iface->read_write != I2C_SMBUS_READ) {
 527                                 if (iface->writeNum > 0) {
 528                                         write_XMT_DATA8(iface,
 529                                                 *(iface->transPtr++));
 530                                         if (iface->writeNum <= 255)
 531                                                 write_MASTER_CTL(iface,
 532                                                         iface->writeNum << 6);
 533                                         else {
 534                                                 write_MASTER_CTL(iface,
 535                                                         0xff << 6);
 536                                                 iface->manual_stop = 1;
 537                                         }
 538                                         iface->writeNum--;
 539                                 } else {
 540                                         write_XMT_DATA8(iface, iface->command);
 541                                         write_MASTER_CTL(iface, 1 << 6);
 542                                 }
 543                         } else {
 544                                 if (iface->readNum > 0 && iface->readNum <= 255)
 545                                         write_MASTER_CTL(iface,
 546                                                 iface->readNum << 6);
 547                                 else if (iface->readNum > 255) {
 548                                         write_MASTER_CTL(iface, 0xff << 6);
 549                                         iface->manual_stop = 1;
 550                                 } else
 551                                         break;
 552                         }
 553                 }
 554                 write_INT_MASK(iface, MCOMP | MERR |
 555                         ((iface->read_write == I2C_SMBUS_READ) ?
 556                         RCVSERV : XMTSERV));
 557                 SSYNC();
 558
 559                 /* Master enable */
 560                 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
 561                         ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
 562                         ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
 563                 break;
 564         }
 565         SSYNC();
 566
 567         while (!iface->result) {
 568                 if (!wait_for_completion_timeout(&iface->complete,
 569                         adap->timeout)) {
 570                         iface->result = -1;
 571                         dev_err(&adap->dev, "smbus transfer timeout\n");
 572                 }
 573         }
 574
 575         rc = (iface->result >= 0) ? 0 : -1;
 576
 577         return rc;
 578 }
 579
 580 /*
 581  * Generic I2C SMBus transfer entrypoint
 582  */
 583 int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
 584                         unsigned short flags, char read_write,
 585                         u8 command, int size, union i2c_smbus_data *data)
 586 {
 587         return bfin_twi_do_smbus_xfer(adap, addr, flags,
 588                         read_write, command, size, data);
 589 }
 590
 591 /*
 592  * Return what the adapter supports
 593  */
 594 static u32 bfin_twi_functionality(struct i2c_adapter *adap)
 595 {
 596         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 597                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 598                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL |
 599                I2C_FUNC_I2C | I2C_FUNC_SMBUS_I2C_BLOCK;
 600 }
 601
 602 static struct i2c_algorithm bfin_twi_algorithm = {
 603         .master_xfer   = bfin_twi_master_xfer,
 604         .smbus_xfer    = bfin_twi_smbus_xfer,
 605         .functionality = bfin_twi_functionality,
 606 };
 607
 608 static int i2c_bfin_twi_suspend(struct platform_device *pdev, pm_message_t state)
 609 {
 610         struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
 611
 612         iface->saved_clkdiv = read_CLKDIV(iface);
 613         iface->saved_control = read_CONTROL(iface);
 614
 615         free_irq(iface->irq, iface);
 616
 617         /* Disable TWI */
 618         write_CONTROL(iface, iface->saved_control & ~TWI_ENA);
 619
 620         return 0;
 621 }
 622
 623 static int i2c_bfin_twi_resume(struct platform_device *pdev)
 624 {
 625         struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
 626
 627         int rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
 628                 IRQF_DISABLED, pdev->name, iface);
 629         if (rc) {
 630                 dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
 631                 return -ENODEV;
 632         }
 633
 634         /* Resume TWI interface clock as specified */
 635         write_CLKDIV(iface, iface->saved_clkdiv);
 636
 637         /* Resume TWI */
 638         write_CONTROL(iface, iface->saved_control);
 639
 640         return 0;
 641 }
 642
 643 static int i2c_bfin_twi_probe(struct platform_device *pdev)
 644 {
 645         struct bfin_twi_iface *iface;
 646         struct i2c_adapter *p_adap;
 647         struct resource *res;
 648         int rc;
 649         unsigned int clkhilow;
 650
 651         iface = kzalloc(sizeof(struct bfin_twi_iface), GFP_KERNEL);
 652         if (!iface) {
 653                 dev_err(&pdev->dev, "Cannot allocate memory\n");
 654                 rc = -ENOMEM;
 655                 goto out_error_nomem;
 656         }
 657
 658         spin_lock_init(&(iface->lock));
 659
 660         /* Find and map our resources */
 661         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 662         if (res == NULL) {
 663                 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
 664                 rc = -ENOENT;
 665                 goto out_error_get_res;
 666         }
 667
 668         iface->regs_base = ioremap(res->start, resource_size(res));
 669         if (iface->regs_base == NULL) {
 670                 dev_err(&pdev->dev, "Cannot map IO\n");
 671                 rc = -ENXIO;
 672                 goto out_error_ioremap;
 673         }
 674
 675         iface->irq = platform_get_irq(pdev, 0);
 676         if (iface->irq < 0) {
 677                 dev_err(&pdev->dev, "No IRQ specified\n");
 678                 rc = -ENOENT;
 679                 goto out_error_no_irq;
 680         }
 681
 682         p_adap = &iface->adap;
 683         p_adap->nr = pdev->id;
 684         strlcpy(p_adap->name, pdev->name, sizeof(p_adap->name));
 685         p_adap->algo = &bfin_twi_algorithm;
 686         p_adap->algo_data = iface;
 687         p_adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
 688         p_adap->dev.parent = &pdev->dev;
 689         p_adap->timeout = 5 * HZ;
 690         p_adap->retries = 3;
 691
 692         rc = peripheral_request_list(pin_req[pdev->id], "i2c-bfin-twi");
 693         if (rc) {
 694                 dev_err(&pdev->dev, "Can't setup pin mux!\n");
 695                 goto out_error_pin_mux;
 696         }
 697
 698         rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
 699                 IRQF_DISABLED, pdev->name, iface);
 700         if (rc) {
 701                 dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
 702                 rc = -ENODEV;
 703                 goto out_error_req_irq;
 704         }
 705
 706         /* Set TWI internal clock as 10MHz */
 707         write_CONTROL(iface, ((get_sclk() / 1000 / 1000 + 5) / 10) & 0x7F);
 708
 709         /*
 710          * We will not end up with a CLKDIV=0 because no one will specify
 711          * 20kHz SCL or less in Kconfig now. (5 * 1000 / 20 = 250)
 712          */
 713         clkhilow = ((10 * 1000 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ) + 1) / 2;
 714
 715         /* Set Twi interface clock as specified */
 716         write_CLKDIV(iface, (clkhilow << 8) | clkhilow);
 717
 718         /* Enable TWI */
 719         write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA);
 720         SSYNC();
 721
 722         rc = i2c_add_numbered_adapter(p_adap);
 723         if (rc < 0) {
 724                 dev_err(&pdev->dev, "Can't add i2c adapter!\n");
 725                 goto out_error_add_adapter;
 726         }
 727
 728         platform_set_drvdata(pdev, iface);
 729
 730         dev_info(&pdev->dev, "Blackfin BF5xx on-chip I2C TWI Contoller, "
 731                 "regs_base@%p\n", iface->regs_base);
 732
 733         return 0;
 734
 735 out_error_add_adapter:
 736         free_irq(iface->irq, iface);
 737 out_error_req_irq:
 738 out_error_no_irq:
 739         peripheral_free_list(pin_req[pdev->id]);
 740 out_error_pin_mux:
 741         iounmap(iface->regs_base);
 742 out_error_ioremap:
 743 out_error_get_res:
 744         kfree(iface);
 745 out_error_nomem:
 746         return rc;
 747 }
 748
 749 static int i2c_bfin_twi_remove(struct platform_device *pdev)
 750 {
 751         struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
 752
 753         platform_set_drvdata(pdev, NULL);
 754
 755         i2c_del_adapter(&(iface->adap));
 756         free_irq(iface->irq, iface);
 757         peripheral_free_list(pin_req[pdev->id]);
 758         iounmap(iface->regs_base);
 759         kfree(iface);
 760
 761         return 0;
 762 }
 763
 764 static struct platform_driver i2c_bfin_twi_driver = {
 765         .probe          = i2c_bfin_twi_probe,
 766         .remove         = i2c_bfin_twi_remove,
 767         .suspend        = i2c_bfin_twi_suspend,
 768         .resume         = i2c_bfin_twi_resume,
 769         .driver         = {
 770                 .name   = "i2c-bfin-twi",
 771                 .owner  = THIS_MODULE,
 772         },
 773 };
 774
 775 static int __init i2c_bfin_twi_init(void)
 776 {
 777         return platform_driver_register(&i2c_bfin_twi_driver);
 778 }
 779
 780 static void __exit i2c_bfin_twi_exit(void)
 781 {
 782         platform_driver_unregister(&i2c_bfin_twi_driver);
 783 }
 784
 785 subsys_initcall(i2c_bfin_twi_init);
 786 module_exit(i2c_bfin_twi_exit);
 787
 788 MODULE_AUTHOR("Bryan Wu, Sonic Zhang");
 789 MODULE_DESCRIPTION("Blackfin BF5xx on-chip I2C TWI Contoller Driver");
 790 MODULE_LICENSE("GPL");
 791 MODULE_ALIAS("platform:i2c-bfin-twi");