1 /**************************************************************************
3 * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include "vmwgfx_drv.h"
31 #define VMW_FENCE_WRAP (1 << 24)
33 irqreturn_t vmw_irq_handler(DRM_IRQ_ARGS)
35 struct drm_device *dev = (struct drm_device *)arg;
36 struct vmw_private *dev_priv = vmw_priv(dev);
39 spin_lock(&dev_priv->irq_lock);
40 status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
41 spin_unlock(&dev_priv->irq_lock);
43 if (status & SVGA_IRQFLAG_ANY_FENCE)
44 wake_up_all(&dev_priv->fence_queue);
45 if (status & SVGA_IRQFLAG_FIFO_PROGRESS)
46 wake_up_all(&dev_priv->fifo_queue);
49 outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
56 static bool vmw_fifo_idle(struct vmw_private *dev_priv, uint32_t sequence)
60 mutex_lock(&dev_priv->hw_mutex);
61 busy = vmw_read(dev_priv, SVGA_REG_BUSY);
62 mutex_unlock(&dev_priv->hw_mutex);
67 void vmw_update_sequence(struct vmw_private *dev_priv,
68 struct vmw_fifo_state *fifo_state)
70 __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
72 uint32_t sequence = ioread32(fifo_mem + SVGA_FIFO_FENCE);
74 if (dev_priv->last_read_sequence != sequence) {
75 dev_priv->last_read_sequence = sequence;
76 vmw_fence_pull(&fifo_state->fence_queue, sequence);
80 bool vmw_fence_signaled(struct vmw_private *dev_priv,
83 struct vmw_fifo_state *fifo_state;
86 if (likely(dev_priv->last_read_sequence - sequence < VMW_FENCE_WRAP))
89 fifo_state = &dev_priv->fifo;
90 vmw_update_sequence(dev_priv, fifo_state);
91 if (likely(dev_priv->last_read_sequence - sequence < VMW_FENCE_WRAP))
94 if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE) &&
95 vmw_fifo_idle(dev_priv, sequence))
99 * Then check if the sequence is higher than what we've actually
100 * emitted. Then the fence is stale and signaled.
103 ret = ((atomic_read(&dev_priv->fence_seq) - sequence)
109 int vmw_fallback_wait(struct vmw_private *dev_priv,
114 unsigned long timeout)
116 struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
121 unsigned long end_jiffies = jiffies + timeout;
122 bool (*wait_condition)(struct vmw_private *, uint32_t);
125 wait_condition = (fifo_idle) ? &vmw_fifo_idle :
129 * Block command submission while waiting for idle.
133 down_read(&fifo_state->rwsem);
134 signal_seq = atomic_read(&dev_priv->fence_seq);
138 prepare_to_wait(&dev_priv->fence_queue, &__wait,
140 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
141 if (wait_condition(dev_priv, sequence))
143 if (time_after_eq(jiffies, end_jiffies)) {
144 DRM_ERROR("SVGA device lockup.\n");
149 else if ((++count & 0x0F) == 0) {
151 * FIXME: Use schedule_hr_timeout here for
152 * newer kernels and lower CPU utilization.
155 __set_current_state(TASK_RUNNING);
157 __set_current_state((interruptible) ?
159 TASK_UNINTERRUPTIBLE);
161 if (interruptible && signal_pending(current)) {
166 finish_wait(&dev_priv->fence_queue, &__wait);
167 if (ret == 0 && fifo_idle) {
168 __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
169 iowrite32(signal_seq, fifo_mem + SVGA_FIFO_FENCE);
171 wake_up_all(&dev_priv->fence_queue);
173 up_read(&fifo_state->rwsem);
178 int vmw_wait_fence(struct vmw_private *dev_priv,
179 bool lazy, uint32_t sequence,
180 bool interruptible, unsigned long timeout)
183 unsigned long irq_flags;
184 struct vmw_fifo_state *fifo = &dev_priv->fifo;
186 if (likely(dev_priv->last_read_sequence - sequence < VMW_FENCE_WRAP))
189 if (likely(vmw_fence_signaled(dev_priv, sequence)))
192 vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC);
194 if (!(fifo->capabilities & SVGA_FIFO_CAP_FENCE))
195 return vmw_fallback_wait(dev_priv, lazy, true, sequence,
196 interruptible, timeout);
198 if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
199 return vmw_fallback_wait(dev_priv, lazy, false, sequence,
200 interruptible, timeout);
202 mutex_lock(&dev_priv->hw_mutex);
203 if (atomic_add_return(1, &dev_priv->fence_queue_waiters) > 0) {
204 spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
205 outl(SVGA_IRQFLAG_ANY_FENCE,
206 dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
207 vmw_write(dev_priv, SVGA_REG_IRQMASK,
208 vmw_read(dev_priv, SVGA_REG_IRQMASK) |
209 SVGA_IRQFLAG_ANY_FENCE);
210 spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
212 mutex_unlock(&dev_priv->hw_mutex);
215 ret = wait_event_interruptible_timeout
216 (dev_priv->fence_queue,
217 vmw_fence_signaled(dev_priv, sequence),
220 ret = wait_event_timeout
221 (dev_priv->fence_queue,
222 vmw_fence_signaled(dev_priv, sequence),
225 if (unlikely(ret == 0))
227 else if (likely(ret > 0))
230 mutex_lock(&dev_priv->hw_mutex);
231 if (atomic_dec_and_test(&dev_priv->fence_queue_waiters)) {
232 spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
233 vmw_write(dev_priv, SVGA_REG_IRQMASK,
234 vmw_read(dev_priv, SVGA_REG_IRQMASK) &
235 ~SVGA_IRQFLAG_ANY_FENCE);
236 spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
238 mutex_unlock(&dev_priv->hw_mutex);
243 void vmw_irq_preinstall(struct drm_device *dev)
245 struct vmw_private *dev_priv = vmw_priv(dev);
248 if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
251 spin_lock_init(&dev_priv->irq_lock);
252 status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
253 outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
256 int vmw_irq_postinstall(struct drm_device *dev)
261 void vmw_irq_uninstall(struct drm_device *dev)
263 struct vmw_private *dev_priv = vmw_priv(dev);
266 if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
269 mutex_lock(&dev_priv->hw_mutex);
270 vmw_write(dev_priv, SVGA_REG_IRQMASK, 0);
271 mutex_unlock(&dev_priv->hw_mutex);
273 status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
274 outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
277 #define VMW_FENCE_WAIT_TIMEOUT 3*HZ;
279 int vmw_fence_wait_ioctl(struct drm_device *dev, void *data,
280 struct drm_file *file_priv)
282 struct drm_vmw_fence_wait_arg *arg =
283 (struct drm_vmw_fence_wait_arg *)data;
284 unsigned long timeout;
286 if (!arg->cookie_valid) {
287 arg->cookie_valid = 1;
288 arg->kernel_cookie = jiffies + VMW_FENCE_WAIT_TIMEOUT;
292 if (time_after_eq(timeout, (unsigned long)arg->kernel_cookie))
295 timeout = (unsigned long)arg->kernel_cookie - timeout;
296 return vmw_wait_fence(vmw_priv(dev), true, arg->sequence, true, timeout);