1 /**************************************************************************
3 * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #include "vmwgfx_drv.h"
30 #include "ttm/ttm_placement.h"
32 bool vmw_fifo_have_3d(struct vmw_private *dev_priv)
34 __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
35 uint32_t fifo_min, hwversion;
36 const struct vmw_fifo_state *fifo = &dev_priv->fifo;
38 if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
41 fifo_min = ioread32(fifo_mem + SVGA_FIFO_MIN);
42 if (fifo_min <= SVGA_FIFO_3D_HWVERSION * sizeof(unsigned int))
45 hwversion = ioread32(fifo_mem +
46 ((fifo->capabilities &
47 SVGA_FIFO_CAP_3D_HWVERSION_REVISED) ?
48 SVGA_FIFO_3D_HWVERSION_REVISED :
49 SVGA_FIFO_3D_HWVERSION));
54 if (hwversion < SVGA3D_HWVERSION_WS8_B1)
57 /* Non-Screen Object path does not support surfaces */
58 if (!dev_priv->sou_priv)
64 bool vmw_fifo_have_pitchlock(struct vmw_private *dev_priv)
66 __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
69 if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
72 caps = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES);
73 if (caps & SVGA_FIFO_CAP_PITCHLOCK)
79 int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
81 __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
86 fifo->static_buffer_size = VMWGFX_FIFO_STATIC_SIZE;
87 fifo->static_buffer = vmalloc(fifo->static_buffer_size);
88 if (unlikely(fifo->static_buffer == NULL))
91 fifo->dynamic_buffer = NULL;
92 fifo->reserved_size = 0;
93 fifo->using_bounce_buffer = false;
95 mutex_init(&fifo->fifo_mutex);
96 init_rwsem(&fifo->rwsem);
99 * Allow mapping the first page read-only to user-space.
102 DRM_INFO("width %d\n", vmw_read(dev_priv, SVGA_REG_WIDTH));
103 DRM_INFO("height %d\n", vmw_read(dev_priv, SVGA_REG_HEIGHT));
104 DRM_INFO("bpp %d\n", vmw_read(dev_priv, SVGA_REG_BITS_PER_PIXEL));
106 mutex_lock(&dev_priv->hw_mutex);
107 dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE);
108 dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE);
109 dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES);
110 vmw_write(dev_priv, SVGA_REG_ENABLE, 1);
113 if (dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)
114 min = vmw_read(dev_priv, SVGA_REG_MEM_REGS);
120 iowrite32(min, fifo_mem + SVGA_FIFO_MIN);
121 iowrite32(dev_priv->mmio_size, fifo_mem + SVGA_FIFO_MAX);
123 iowrite32(min, fifo_mem + SVGA_FIFO_NEXT_CMD);
124 iowrite32(min, fifo_mem + SVGA_FIFO_STOP);
125 iowrite32(0, fifo_mem + SVGA_FIFO_BUSY);
128 vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1);
129 mutex_unlock(&dev_priv->hw_mutex);
131 max = ioread32(fifo_mem + SVGA_FIFO_MAX);
132 min = ioread32(fifo_mem + SVGA_FIFO_MIN);
133 fifo->capabilities = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES);
135 DRM_INFO("Fifo max 0x%08x min 0x%08x cap 0x%08x\n",
138 (unsigned int) fifo->capabilities);
140 atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno);
141 iowrite32(dev_priv->last_read_seqno, fifo_mem + SVGA_FIFO_FENCE);
142 vmw_marker_queue_init(&fifo->marker_queue);
143 return vmw_fifo_send_fence(dev_priv, &dummy);
146 void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason)
148 __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
150 mutex_lock(&dev_priv->hw_mutex);
152 if (unlikely(ioread32(fifo_mem + SVGA_FIFO_BUSY) == 0)) {
153 iowrite32(1, fifo_mem + SVGA_FIFO_BUSY);
154 vmw_write(dev_priv, SVGA_REG_SYNC, reason);
157 mutex_unlock(&dev_priv->hw_mutex);
160 void vmw_fifo_release(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
162 __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
164 mutex_lock(&dev_priv->hw_mutex);
166 vmw_write(dev_priv, SVGA_REG_SYNC, SVGA_SYNC_GENERIC);
167 while (vmw_read(dev_priv, SVGA_REG_BUSY) != 0)
170 dev_priv->last_read_seqno = ioread32(fifo_mem + SVGA_FIFO_FENCE);
172 vmw_write(dev_priv, SVGA_REG_CONFIG_DONE,
173 dev_priv->config_done_state);
174 vmw_write(dev_priv, SVGA_REG_ENABLE,
175 dev_priv->enable_state);
176 vmw_write(dev_priv, SVGA_REG_TRACES,
177 dev_priv->traces_state);
179 mutex_unlock(&dev_priv->hw_mutex);
180 vmw_marker_queue_takedown(&fifo->marker_queue);
182 if (likely(fifo->static_buffer != NULL)) {
183 vfree(fifo->static_buffer);
184 fifo->static_buffer = NULL;
187 if (likely(fifo->dynamic_buffer != NULL)) {
188 vfree(fifo->dynamic_buffer);
189 fifo->dynamic_buffer = NULL;
193 static bool vmw_fifo_is_full(struct vmw_private *dev_priv, uint32_t bytes)
195 __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
196 uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX);
197 uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
198 uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN);
199 uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP);
201 return ((max - next_cmd) + (stop - min) <= bytes);
204 static int vmw_fifo_wait_noirq(struct vmw_private *dev_priv,
205 uint32_t bytes, bool interruptible,
206 unsigned long timeout)
209 unsigned long end_jiffies = jiffies + timeout;
212 DRM_INFO("Fifo wait noirq.\n");
215 prepare_to_wait(&dev_priv->fifo_queue, &__wait,
217 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
218 if (!vmw_fifo_is_full(dev_priv, bytes))
220 if (time_after_eq(jiffies, end_jiffies)) {
222 DRM_ERROR("SVGA device lockup.\n");
226 if (interruptible && signal_pending(current)) {
231 finish_wait(&dev_priv->fifo_queue, &__wait);
232 wake_up_all(&dev_priv->fifo_queue);
233 DRM_INFO("Fifo noirq exit.\n");
237 static int vmw_fifo_wait(struct vmw_private *dev_priv,
238 uint32_t bytes, bool interruptible,
239 unsigned long timeout)
242 unsigned long irq_flags;
244 if (likely(!vmw_fifo_is_full(dev_priv, bytes)))
247 vmw_fifo_ping_host(dev_priv, SVGA_SYNC_FIFOFULL);
248 if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
249 return vmw_fifo_wait_noirq(dev_priv, bytes,
250 interruptible, timeout);
252 mutex_lock(&dev_priv->hw_mutex);
253 if (atomic_add_return(1, &dev_priv->fifo_queue_waiters) > 0) {
254 spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
255 outl(SVGA_IRQFLAG_FIFO_PROGRESS,
256 dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
257 dev_priv->irq_mask |= SVGA_IRQFLAG_FIFO_PROGRESS;
258 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
259 spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
261 mutex_unlock(&dev_priv->hw_mutex);
264 ret = wait_event_interruptible_timeout
265 (dev_priv->fifo_queue,
266 !vmw_fifo_is_full(dev_priv, bytes), timeout);
268 ret = wait_event_timeout
269 (dev_priv->fifo_queue,
270 !vmw_fifo_is_full(dev_priv, bytes), timeout);
272 if (unlikely(ret == 0))
274 else if (likely(ret > 0))
277 mutex_lock(&dev_priv->hw_mutex);
278 if (atomic_dec_and_test(&dev_priv->fifo_queue_waiters)) {
279 spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
280 dev_priv->irq_mask &= ~SVGA_IRQFLAG_FIFO_PROGRESS;
281 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
282 spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
284 mutex_unlock(&dev_priv->hw_mutex);
290 * Reserve @bytes number of bytes in the fifo.
292 * This function will return NULL (error) on two conditions:
293 * If it timeouts waiting for fifo space, or if @bytes is larger than the
294 * available fifo space.
297 * Pointer to the fifo, or null on error (possible hardware hang).
299 void *vmw_fifo_reserve(struct vmw_private *dev_priv, uint32_t bytes)
301 struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
302 __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
306 uint32_t reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
309 mutex_lock(&fifo_state->fifo_mutex);
310 max = ioread32(fifo_mem + SVGA_FIFO_MAX);
311 min = ioread32(fifo_mem + SVGA_FIFO_MIN);
312 next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
314 if (unlikely(bytes >= (max - min)))
317 BUG_ON(fifo_state->reserved_size != 0);
318 BUG_ON(fifo_state->dynamic_buffer != NULL);
320 fifo_state->reserved_size = bytes;
323 uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP);
324 bool need_bounce = false;
325 bool reserve_in_place = false;
327 if (next_cmd >= stop) {
328 if (likely((next_cmd + bytes < max ||
329 (next_cmd + bytes == max && stop > min))))
330 reserve_in_place = true;
332 else if (vmw_fifo_is_full(dev_priv, bytes)) {
333 ret = vmw_fifo_wait(dev_priv, bytes,
335 if (unlikely(ret != 0))
342 if (likely((next_cmd + bytes < stop)))
343 reserve_in_place = true;
345 ret = vmw_fifo_wait(dev_priv, bytes,
347 if (unlikely(ret != 0))
352 if (reserve_in_place) {
353 if (reserveable || bytes <= sizeof(uint32_t)) {
354 fifo_state->using_bounce_buffer = false;
357 iowrite32(bytes, fifo_mem +
359 return fifo_mem + (next_cmd >> 2);
366 fifo_state->using_bounce_buffer = true;
367 if (bytes < fifo_state->static_buffer_size)
368 return fifo_state->static_buffer;
370 fifo_state->dynamic_buffer = vmalloc(bytes);
371 if (!fifo_state->dynamic_buffer)
373 return fifo_state->dynamic_buffer;
378 fifo_state->reserved_size = 0;
379 mutex_unlock(&fifo_state->fifo_mutex);
383 static void vmw_fifo_res_copy(struct vmw_fifo_state *fifo_state,
384 __le32 __iomem *fifo_mem,
386 uint32_t max, uint32_t min, uint32_t bytes)
388 uint32_t chunk_size = max - next_cmd;
390 uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
391 fifo_state->dynamic_buffer : fifo_state->static_buffer;
393 if (bytes < chunk_size)
396 iowrite32(bytes, fifo_mem + SVGA_FIFO_RESERVED);
398 memcpy_toio(fifo_mem + (next_cmd >> 2), buffer, chunk_size);
399 rest = bytes - chunk_size;
401 memcpy_toio(fifo_mem + (min >> 2), buffer + (chunk_size >> 2),
405 static void vmw_fifo_slow_copy(struct vmw_fifo_state *fifo_state,
406 __le32 __iomem *fifo_mem,
408 uint32_t max, uint32_t min, uint32_t bytes)
410 uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
411 fifo_state->dynamic_buffer : fifo_state->static_buffer;
414 iowrite32(*buffer++, fifo_mem + (next_cmd >> 2));
415 next_cmd += sizeof(uint32_t);
416 if (unlikely(next_cmd == max))
419 iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
421 bytes -= sizeof(uint32_t);
425 void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes)
427 struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
428 __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
429 uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
430 uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX);
431 uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN);
432 bool reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
434 BUG_ON((bytes & 3) != 0);
435 BUG_ON(bytes > fifo_state->reserved_size);
437 fifo_state->reserved_size = 0;
439 if (fifo_state->using_bounce_buffer) {
441 vmw_fifo_res_copy(fifo_state, fifo_mem,
442 next_cmd, max, min, bytes);
444 vmw_fifo_slow_copy(fifo_state, fifo_mem,
445 next_cmd, max, min, bytes);
447 if (fifo_state->dynamic_buffer) {
448 vfree(fifo_state->dynamic_buffer);
449 fifo_state->dynamic_buffer = NULL;
454 down_write(&fifo_state->rwsem);
455 if (fifo_state->using_bounce_buffer || reserveable) {
458 next_cmd -= max - min;
460 iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
464 iowrite32(0, fifo_mem + SVGA_FIFO_RESERVED);
466 up_write(&fifo_state->rwsem);
467 vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC);
468 mutex_unlock(&fifo_state->fifo_mutex);
471 int vmw_fifo_send_fence(struct vmw_private *dev_priv, uint32_t *seqno)
473 struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
474 struct svga_fifo_cmd_fence *cmd_fence;
477 uint32_t bytes = sizeof(__le32) + sizeof(*cmd_fence);
479 fm = vmw_fifo_reserve(dev_priv, bytes);
480 if (unlikely(fm == NULL)) {
481 *seqno = atomic_read(&dev_priv->marker_seq);
483 (void)vmw_fallback_wait(dev_priv, false, true, *seqno,
489 *seqno = atomic_add_return(1, &dev_priv->marker_seq);
490 } while (*seqno == 0);
492 if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE)) {
495 * Don't request hardware to send a fence. The
496 * waiting code in vmwgfx_irq.c will emulate this.
499 vmw_fifo_commit(dev_priv, 0);
503 *(__le32 *) fm = cpu_to_le32(SVGA_CMD_FENCE);
504 cmd_fence = (struct svga_fifo_cmd_fence *)
505 ((unsigned long)fm + sizeof(__le32));
507 iowrite32(*seqno, &cmd_fence->fence);
508 vmw_fifo_commit(dev_priv, bytes);
509 (void) vmw_marker_push(&fifo_state->marker_queue, *seqno);
510 vmw_update_seqno(dev_priv, fifo_state);
517 * vmw_fifo_emit_dummy_query - emits a dummy query to the fifo.
519 * @dev_priv: The device private structure.
520 * @cid: The hardware context id used for the query.
522 * This function is used to emit a dummy occlusion query with
523 * no primitives rendered between query begin and query end.
524 * It's used to provide a query barrier, in order to know that when
525 * this query is finished, all preceding queries are also finished.
527 * A Query results structure should have been initialized at the start
528 * of the dev_priv->dummy_query_bo buffer object. And that buffer object
529 * must also be either reserved or pinned when this function is called.
531 * Returns -ENOMEM on failure to reserve fifo space.
533 int vmw_fifo_emit_dummy_query(struct vmw_private *dev_priv,
537 * A query wait without a preceding query end will
538 * actually finish all queries for this cid
539 * without writing to the query result structure.
542 struct ttm_buffer_object *bo = dev_priv->dummy_query_bo;
544 SVGA3dCmdHeader header;
545 SVGA3dCmdWaitForQuery body;
548 cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));
550 if (unlikely(cmd == NULL)) {
551 DRM_ERROR("Out of fifo space for dummy query.\n");
555 cmd->header.id = SVGA_3D_CMD_WAIT_FOR_QUERY;
556 cmd->header.size = sizeof(cmd->body);
558 cmd->body.type = SVGA3D_QUERYTYPE_OCCLUSION;
560 if (bo->mem.mem_type == TTM_PL_VRAM) {
561 cmd->body.guestResult.gmrId = SVGA_GMR_FRAMEBUFFER;
562 cmd->body.guestResult.offset = bo->offset;
564 cmd->body.guestResult.gmrId = bo->mem.start;
565 cmd->body.guestResult.offset = 0;
568 vmw_fifo_commit(dev_priv, sizeof(*cmd));