drivers/gpu/drm/radeon/rv770.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/firmware.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/slab.h>
  31 #include "drmP.h"
  32 #include "radeon.h"
  33 #include "radeon_asic.h"
  34 #include "radeon_drm.h"
  35 #include "rv770d.h"
  36 #include "atom.h"
  37 #include "avivod.h"
  38
  39 #define R700_PFP_UCODE_SIZE 848
  40 #define R700_PM4_UCODE_SIZE 1360
  41
  42 static void rv770_gpu_init(struct radeon_device *rdev);
  43 void rv770_fini(struct radeon_device *rdev);
  44 static void rv770_pcie_gen2_enable(struct radeon_device *rdev);
  45
  46 u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
  47 {
  48         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
  49         u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
  50         int i;
  51
  52         /* Lock the graphics update lock */
  53         tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
  54         WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
  55
  56         /* update the scanout addresses */
  57         if (radeon_crtc->crtc_id) {
  58                 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
  59                 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
  60         } else {
  61                 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
  62                 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
  63         }
  64         WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
  65                (u32)crtc_base);
  66         WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
  67                (u32)crtc_base);
  68
  69         /* Wait for update_pending to go high. */
  70         for (i = 0; i < rdev->usec_timeout; i++) {
  71                 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
  72                         break;
  73                 udelay(1);
  74         }
  75         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
  76
  77         /* Unlock the lock, so double-buffering can take place inside vblank */
  78         tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
  79         WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
  80
  81         /* Return current update_pending status: */
  82         return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING;
  83 }
  84
  85 /* get temperature in millidegrees */
  86 int rv770_get_temp(struct radeon_device *rdev)
  87 {
  88         u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
  89                 ASIC_T_SHIFT;
  90         int actual_temp;
  91
  92         if (temp & 0x400)
  93                 actual_temp = -256;
  94         else if (temp & 0x200)
  95                 actual_temp = 255;
  96         else if (temp & 0x100) {
  97                 actual_temp = temp & 0x1ff;
  98                 actual_temp |= ~0x1ff;
  99         } else
 100                 actual_temp = temp & 0xff;
 101
 102         return (actual_temp * 1000) / 2;
 103 }
 104
 105 void rv770_pm_misc(struct radeon_device *rdev)
 106 {
 107         int req_ps_idx = rdev->pm.requested_power_state_index;
 108         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 109         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 110         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 111
 112         if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
 113                 /* 0xff01 is a flag rather then an actual voltage */
 114                 if (voltage->voltage == 0xff01)
 115                         return;
 116                 if (voltage->voltage != rdev->pm.current_vddc) {
 117                         radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
 118                         rdev->pm.current_vddc = voltage->voltage;
 119                         DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
 120                 }
 121         }
 122 }
 123
 124 /*
 125  * GART
 126  */
 127 int rv770_pcie_gart_enable(struct radeon_device *rdev)
 128 {
 129         u32 tmp;
 130         int r, i;
 131
 132         if (rdev->gart.robj == NULL) {
 133                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 134                 return -EINVAL;
 135         }
 136         r = radeon_gart_table_vram_pin(rdev);
 137         if (r)
 138                 return r;
 139         radeon_gart_restore(rdev);
 140         /* Setup L2 cache */
 141         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 142                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 143                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 144         WREG32(VM_L2_CNTL2, 0);
 145         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 146         /* Setup TLB control */
 147         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 148                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 149                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
 150                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 151         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 152         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 153         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 154         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 155         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 156         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 157         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 158         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 159         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 160         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 161         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 162                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 163         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 164                         (u32)(rdev->dummy_page.addr >> 12));
 165         for (i = 1; i < 7; i++)
 166                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 167
 168         r600_pcie_gart_tlb_flush(rdev);
 169         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 170                  (unsigned)(rdev->mc.gtt_size >> 20),
 171                  (unsigned long long)rdev->gart.table_addr);
 172         rdev->gart.ready = true;
 173         return 0;
 174 }
 175
 176 void rv770_pcie_gart_disable(struct radeon_device *rdev)
 177 {
 178         u32 tmp;
 179         int i;
 180
 181         /* Disable all tables */
 182         for (i = 0; i < 7; i++)
 183                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 184
 185         /* Setup L2 cache */
 186         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 187                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 188         WREG32(VM_L2_CNTL2, 0);
 189         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 190         /* Setup TLB control */
 191         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 192         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 193         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 194         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 195         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 196         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 197         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 198         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 199         radeon_gart_table_vram_unpin(rdev);
 200 }
 201
 202 void rv770_pcie_gart_fini(struct radeon_device *rdev)
 203 {
 204         radeon_gart_fini(rdev);
 205         rv770_pcie_gart_disable(rdev);
 206         radeon_gart_table_vram_free(rdev);
 207 }
 208
 209
 210 void rv770_agp_enable(struct radeon_device *rdev)
 211 {
 212         u32 tmp;
 213         int i;
 214
 215         /* Setup L2 cache */
 216         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 217                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 218                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 219         WREG32(VM_L2_CNTL2, 0);
 220         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 221         /* Setup TLB control */
 222         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 223                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 224                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
 225                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 226         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 227         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 228         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 229         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 230         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 231         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 232         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 233         for (i = 0; i < 7; i++)
 234                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 235 }
 236
 237 static void rv770_mc_program(struct radeon_device *rdev)
 238 {
 239         struct rv515_mc_save save;
 240         u32 tmp;
 241         int i, j;
 242
 243         /* Initialize HDP */
 244         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
 245                 WREG32((0x2c14 + j), 0x00000000);
 246                 WREG32((0x2c18 + j), 0x00000000);
 247                 WREG32((0x2c1c + j), 0x00000000);
 248                 WREG32((0x2c20 + j), 0x00000000);
 249                 WREG32((0x2c24 + j), 0x00000000);
 250         }
 251         /* r7xx hw bug.  Read from HDP_DEBUG1 rather
 252          * than writing to HDP_REG_COHERENCY_FLUSH_CNTL
 253          */
 254         tmp = RREG32(HDP_DEBUG1);
 255
 256         rv515_mc_stop(rdev, &save);
 257         if (r600_mc_wait_for_idle(rdev)) {
 258                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 259         }
 260         /* Lockout access through VGA aperture*/
 261         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
 262         /* Update configuration */
 263         if (rdev->flags & RADEON_IS_AGP) {
 264                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
 265                         /* VRAM before AGP */
 266                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 267                                 rdev->mc.vram_start >> 12);
 268                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 269                                 rdev->mc.gtt_end >> 12);
 270                 } else {
 271                         /* VRAM after AGP */
 272                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 273                                 rdev->mc.gtt_start >> 12);
 274                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 275                                 rdev->mc.vram_end >> 12);
 276                 }
 277         } else {
 278                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 279                         rdev->mc.vram_start >> 12);
 280                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 281                         rdev->mc.vram_end >> 12);
 282         }
 283         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
 284         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
 285         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
 286         WREG32(MC_VM_FB_LOCATION, tmp);
 287         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
 288         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
 289         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
 290         if (rdev->flags & RADEON_IS_AGP) {
 291                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
 292                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
 293                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
 294         } else {
 295                 WREG32(MC_VM_AGP_BASE, 0);
 296                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
 297                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
 298         }
 299         if (r600_mc_wait_for_idle(rdev)) {
 300                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 301         }
 302         rv515_mc_resume(rdev, &save);
 303         /* we need to own VRAM, so turn off the VGA renderer here
 304          * to stop it overwriting our objects */
 305         rv515_vga_render_disable(rdev);
 306 }
 307
 308
 309 /*
 310  * CP.
 311  */
 312 void r700_cp_stop(struct radeon_device *rdev)
 313 {
 314         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
 315         WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
 316         WREG32(SCRATCH_UMSK, 0);
 317 }
 318
 319 static int rv770_cp_load_microcode(struct radeon_device *rdev)
 320 {
 321         const __be32 *fw_data;
 322         int i;
 323
 324         if (!rdev->me_fw || !rdev->pfp_fw)
 325                 return -EINVAL;
 326
 327         r700_cp_stop(rdev);
 328         WREG32(CP_RB_CNTL,
 329 #ifdef __BIG_ENDIAN
 330                BUF_SWAP_32BIT |
 331 #endif
 332                RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
 333
 334         /* Reset cp */
 335         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
 336         RREG32(GRBM_SOFT_RESET);
 337         mdelay(15);
 338         WREG32(GRBM_SOFT_RESET, 0);
 339
 340         fw_data = (const __be32 *)rdev->pfp_fw->data;
 341         WREG32(CP_PFP_UCODE_ADDR, 0);
 342         for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
 343                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
 344         WREG32(CP_PFP_UCODE_ADDR, 0);
 345
 346         fw_data = (const __be32 *)rdev->me_fw->data;
 347         WREG32(CP_ME_RAM_WADDR, 0);
 348         for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
 349                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
 350
 351         WREG32(CP_PFP_UCODE_ADDR, 0);
 352         WREG32(CP_ME_RAM_WADDR, 0);
 353         WREG32(CP_ME_RAM_RADDR, 0);
 354         return 0;
 355 }
 356
 357 void r700_cp_fini(struct radeon_device *rdev)
 358 {
 359         r700_cp_stop(rdev);
 360         radeon_ring_fini(rdev);
 361 }
 362
 363 /*
 364  * Core functions
 365  */
 366 static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
 367                                              u32 num_tile_pipes,
 368                                              u32 num_backends,
 369                                              u32 backend_disable_mask)
 370 {
 371         u32 backend_map = 0;
 372         u32 enabled_backends_mask;
 373         u32 enabled_backends_count;
 374         u32 cur_pipe;
 375         u32 swizzle_pipe[R7XX_MAX_PIPES];
 376         u32 cur_backend;
 377         u32 i;
 378         bool force_no_swizzle;
 379
 380         if (num_tile_pipes > R7XX_MAX_PIPES)
 381                 num_tile_pipes = R7XX_MAX_PIPES;
 382         if (num_tile_pipes < 1)
 383                 num_tile_pipes = 1;
 384         if (num_backends > R7XX_MAX_BACKENDS)
 385                 num_backends = R7XX_MAX_BACKENDS;
 386         if (num_backends < 1)
 387                 num_backends = 1;
 388
 389         enabled_backends_mask = 0;
 390         enabled_backends_count = 0;
 391         for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
 392                 if (((backend_disable_mask >> i) & 1) == 0) {
 393                         enabled_backends_mask |= (1 << i);
 394                         ++enabled_backends_count;
 395                 }
 396                 if (enabled_backends_count == num_backends)
 397                         break;
 398         }
 399
 400         if (enabled_backends_count == 0) {
 401                 enabled_backends_mask = 1;
 402                 enabled_backends_count = 1;
 403         }
 404
 405         if (enabled_backends_count != num_backends)
 406                 num_backends = enabled_backends_count;
 407
 408         switch (rdev->family) {
 409         case CHIP_RV770:
 410         case CHIP_RV730:
 411                 force_no_swizzle = false;
 412                 break;
 413         case CHIP_RV710:
 414         case CHIP_RV740:
 415         default:
 416                 force_no_swizzle = true;
 417                 break;
 418         }
 419
 420         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
 421         switch (num_tile_pipes) {
 422         case 1:
 423                 swizzle_pipe[0] = 0;
 424                 break;
 425         case 2:
 426                 swizzle_pipe[0] = 0;
 427                 swizzle_pipe[1] = 1;
 428                 break;
 429         case 3:
 430                 if (force_no_swizzle) {
 431                         swizzle_pipe[0] = 0;
 432                         swizzle_pipe[1] = 1;
 433                         swizzle_pipe[2] = 2;
 434                 } else {
 435                         swizzle_pipe[0] = 0;
 436                         swizzle_pipe[1] = 2;
 437                         swizzle_pipe[2] = 1;
 438                 }
 439                 break;
 440         case 4:
 441                 if (force_no_swizzle) {
 442                         swizzle_pipe[0] = 0;
 443                         swizzle_pipe[1] = 1;
 444                         swizzle_pipe[2] = 2;
 445                         swizzle_pipe[3] = 3;
 446                 } else {
 447                         swizzle_pipe[0] = 0;
 448                         swizzle_pipe[1] = 2;
 449                         swizzle_pipe[2] = 3;
 450                         swizzle_pipe[3] = 1;
 451                 }
 452                 break;
 453         case 5:
 454                 if (force_no_swizzle) {
 455                         swizzle_pipe[0] = 0;
 456                         swizzle_pipe[1] = 1;
 457                         swizzle_pipe[2] = 2;
 458                         swizzle_pipe[3] = 3;
 459                         swizzle_pipe[4] = 4;
 460                 } else {
 461                         swizzle_pipe[0] = 0;
 462                         swizzle_pipe[1] = 2;
 463                         swizzle_pipe[2] = 4;
 464                         swizzle_pipe[3] = 1;
 465                         swizzle_pipe[4] = 3;
 466                 }
 467                 break;
 468         case 6:
 469                 if (force_no_swizzle) {
 470                         swizzle_pipe[0] = 0;
 471                         swizzle_pipe[1] = 1;
 472                         swizzle_pipe[2] = 2;
 473                         swizzle_pipe[3] = 3;
 474                         swizzle_pipe[4] = 4;
 475                         swizzle_pipe[5] = 5;
 476                 } else {
 477                         swizzle_pipe[0] = 0;
 478                         swizzle_pipe[1] = 2;
 479                         swizzle_pipe[2] = 4;
 480                         swizzle_pipe[3] = 5;
 481                         swizzle_pipe[4] = 3;
 482                         swizzle_pipe[5] = 1;
 483                 }
 484                 break;
 485         case 7:
 486                 if (force_no_swizzle) {
 487                         swizzle_pipe[0] = 0;
 488                         swizzle_pipe[1] = 1;
 489                         swizzle_pipe[2] = 2;
 490                         swizzle_pipe[3] = 3;
 491                         swizzle_pipe[4] = 4;
 492                         swizzle_pipe[5] = 5;
 493                         swizzle_pipe[6] = 6;
 494                 } else {
 495                         swizzle_pipe[0] = 0;
 496                         swizzle_pipe[1] = 2;
 497                         swizzle_pipe[2] = 4;
 498                         swizzle_pipe[3] = 6;
 499                         swizzle_pipe[4] = 3;
 500                         swizzle_pipe[5] = 1;
 501                         swizzle_pipe[6] = 5;
 502                 }
 503                 break;
 504         case 8:
 505                 if (force_no_swizzle) {
 506                         swizzle_pipe[0] = 0;
 507                         swizzle_pipe[1] = 1;
 508                         swizzle_pipe[2] = 2;
 509                         swizzle_pipe[3] = 3;
 510                         swizzle_pipe[4] = 4;
 511                         swizzle_pipe[5] = 5;
 512                         swizzle_pipe[6] = 6;
 513                         swizzle_pipe[7] = 7;
 514                 } else {
 515                         swizzle_pipe[0] = 0;
 516                         swizzle_pipe[1] = 2;
 517                         swizzle_pipe[2] = 4;
 518                         swizzle_pipe[3] = 6;
 519                         swizzle_pipe[4] = 3;
 520                         swizzle_pipe[5] = 1;
 521                         swizzle_pipe[6] = 7;
 522                         swizzle_pipe[7] = 5;
 523                 }
 524                 break;
 525         }
 526
 527         cur_backend = 0;
 528         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
 529                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
 530                         cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
 531
 532                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
 533
 534                 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
 535         }
 536
 537         return backend_map;
 538 }
 539
 540 static void rv770_gpu_init(struct radeon_device *rdev)
 541 {
 542         int i, j, num_qd_pipes;
 543         u32 ta_aux_cntl;
 544         u32 sx_debug_1;
 545         u32 smx_dc_ctl0;
 546         u32 db_debug3;
 547         u32 num_gs_verts_per_thread;
 548         u32 vgt_gs_per_es;
 549         u32 gs_prim_buffer_depth = 0;
 550         u32 sq_ms_fifo_sizes;
 551         u32 sq_config;
 552         u32 sq_thread_resource_mgmt;
 553         u32 hdp_host_path_cntl;
 554         u32 sq_dyn_gpr_size_simd_ab_0;
 555         u32 backend_map;
 556         u32 gb_tiling_config = 0;
 557         u32 cc_rb_backend_disable = 0;
 558         u32 cc_gc_shader_pipe_config = 0;
 559         u32 mc_arb_ramcfg;
 560         u32 db_debug4;
 561
 562         /* setup chip specs */
 563         switch (rdev->family) {
 564         case CHIP_RV770:
 565                 rdev->config.rv770.max_pipes = 4;
 566                 rdev->config.rv770.max_tile_pipes = 8;
 567                 rdev->config.rv770.max_simds = 10;
 568                 rdev->config.rv770.max_backends = 4;
 569                 rdev->config.rv770.max_gprs = 256;
 570                 rdev->config.rv770.max_threads = 248;
 571                 rdev->config.rv770.max_stack_entries = 512;
 572                 rdev->config.rv770.max_hw_contexts = 8;
 573                 rdev->config.rv770.max_gs_threads = 16 * 2;
 574                 rdev->config.rv770.sx_max_export_size = 128;
 575                 rdev->config.rv770.sx_max_export_pos_size = 16;
 576                 rdev->config.rv770.sx_max_export_smx_size = 112;
 577                 rdev->config.rv770.sq_num_cf_insts = 2;
 578
 579                 rdev->config.rv770.sx_num_of_sets = 7;
 580                 rdev->config.rv770.sc_prim_fifo_size = 0xF9;
 581                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
 582                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
 583                 break;
 584         case CHIP_RV730:
 585                 rdev->config.rv770.max_pipes = 2;
 586                 rdev->config.rv770.max_tile_pipes = 4;
 587                 rdev->config.rv770.max_simds = 8;
 588                 rdev->config.rv770.max_backends = 2;
 589                 rdev->config.rv770.max_gprs = 128;
 590                 rdev->config.rv770.max_threads = 248;
 591                 rdev->config.rv770.max_stack_entries = 256;
 592                 rdev->config.rv770.max_hw_contexts = 8;
 593                 rdev->config.rv770.max_gs_threads = 16 * 2;
 594                 rdev->config.rv770.sx_max_export_size = 256;
 595                 rdev->config.rv770.sx_max_export_pos_size = 32;
 596                 rdev->config.rv770.sx_max_export_smx_size = 224;
 597                 rdev->config.rv770.sq_num_cf_insts = 2;
 598
 599                 rdev->config.rv770.sx_num_of_sets = 7;
 600                 rdev->config.rv770.sc_prim_fifo_size = 0xf9;
 601                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
 602                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
 603                 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
 604                         rdev->config.rv770.sx_max_export_pos_size -= 16;
 605                         rdev->config.rv770.sx_max_export_smx_size += 16;
 606                 }
 607                 break;
 608         case CHIP_RV710:
 609                 rdev->config.rv770.max_pipes = 2;
 610                 rdev->config.rv770.max_tile_pipes = 2;
 611                 rdev->config.rv770.max_simds = 2;
 612                 rdev->config.rv770.max_backends = 1;
 613                 rdev->config.rv770.max_gprs = 256;
 614                 rdev->config.rv770.max_threads = 192;
 615                 rdev->config.rv770.max_stack_entries = 256;
 616                 rdev->config.rv770.max_hw_contexts = 4;
 617                 rdev->config.rv770.max_gs_threads = 8 * 2;
 618                 rdev->config.rv770.sx_max_export_size = 128;
 619                 rdev->config.rv770.sx_max_export_pos_size = 16;
 620                 rdev->config.rv770.sx_max_export_smx_size = 112;
 621                 rdev->config.rv770.sq_num_cf_insts = 1;
 622
 623                 rdev->config.rv770.sx_num_of_sets = 7;
 624                 rdev->config.rv770.sc_prim_fifo_size = 0x40;
 625                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
 626                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
 627                 break;
 628         case CHIP_RV740:
 629                 rdev->config.rv770.max_pipes = 4;
 630                 rdev->config.rv770.max_tile_pipes = 4;
 631                 rdev->config.rv770.max_simds = 8;
 632                 rdev->config.rv770.max_backends = 4;
 633                 rdev->config.rv770.max_gprs = 256;
 634                 rdev->config.rv770.max_threads = 248;
 635                 rdev->config.rv770.max_stack_entries = 512;
 636                 rdev->config.rv770.max_hw_contexts = 8;
 637                 rdev->config.rv770.max_gs_threads = 16 * 2;
 638                 rdev->config.rv770.sx_max_export_size = 256;
 639                 rdev->config.rv770.sx_max_export_pos_size = 32;
 640                 rdev->config.rv770.sx_max_export_smx_size = 224;
 641                 rdev->config.rv770.sq_num_cf_insts = 2;
 642
 643                 rdev->config.rv770.sx_num_of_sets = 7;
 644                 rdev->config.rv770.sc_prim_fifo_size = 0x100;
 645                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
 646                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
 647
 648                 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
 649                         rdev->config.rv770.sx_max_export_pos_size -= 16;
 650                         rdev->config.rv770.sx_max_export_smx_size += 16;
 651                 }
 652                 break;
 653         default:
 654                 break;
 655         }
 656
 657         /* Initialize HDP */
 658         j = 0;
 659         for (i = 0; i < 32; i++) {
 660                 WREG32((0x2c14 + j), 0x00000000);
 661                 WREG32((0x2c18 + j), 0x00000000);
 662                 WREG32((0x2c1c + j), 0x00000000);
 663                 WREG32((0x2c20 + j), 0x00000000);
 664                 WREG32((0x2c24 + j), 0x00000000);
 665                 j += 0x18;
 666         }
 667
 668         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
 669
 670         /* setup tiling, simd, pipe config */
 671         mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
 672
 673         switch (rdev->config.rv770.max_tile_pipes) {
 674         case 1:
 675         default:
 676                 gb_tiling_config |= PIPE_TILING(0);
 677                 break;
 678         case 2:
 679                 gb_tiling_config |= PIPE_TILING(1);
 680                 break;
 681         case 4:
 682                 gb_tiling_config |= PIPE_TILING(2);
 683                 break;
 684         case 8:
 685                 gb_tiling_config |= PIPE_TILING(3);
 686                 break;
 687         }
 688         rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes;
 689
 690         if (rdev->family == CHIP_RV770)
 691                 gb_tiling_config |= BANK_TILING(1);
 692         else
 693                 gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
 694         rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
 695         gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
 696         if ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT)
 697                 rdev->config.rv770.tiling_group_size = 512;
 698         else
 699                 rdev->config.rv770.tiling_group_size = 256;
 700         if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
 701                 gb_tiling_config |= ROW_TILING(3);
 702                 gb_tiling_config |= SAMPLE_SPLIT(3);
 703         } else {
 704                 gb_tiling_config |=
 705                         ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
 706                 gb_tiling_config |=
 707                         SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
 708         }
 709
 710         gb_tiling_config |= BANK_SWAPS(1);
 711
 712         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
 713         cc_rb_backend_disable |=
 714                 BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK);
 715
 716         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
 717         cc_gc_shader_pipe_config |=
 718                 INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK);
 719         cc_gc_shader_pipe_config |=
 720                 INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK);
 721
 722         if (rdev->family == CHIP_RV740)
 723                 backend_map = 0x28;
 724         else
 725                 backend_map = r700_get_tile_pipe_to_backend_map(rdev,
 726                                                                 rdev->config.rv770.max_tile_pipes,
 727                                                                 (R7XX_MAX_BACKENDS -
 728                                                                  r600_count_pipe_bits((cc_rb_backend_disable &
 729                                                                                        R7XX_MAX_BACKENDS_MASK) >> 16)),
 730                                                                 (cc_rb_backend_disable >> 16));
 731
 732         rdev->config.rv770.tile_config = gb_tiling_config;
 733         rdev->config.rv770.backend_map = backend_map;
 734         gb_tiling_config |= BACKEND_MAP(backend_map);
 735
 736         WREG32(GB_TILING_CONFIG, gb_tiling_config);
 737         WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
 738         WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
 739
 740         WREG32(CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);
 741         WREG32(CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);
 742         WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
 743         WREG32(CC_SYS_RB_BACKEND_DISABLE,  cc_rb_backend_disable);
 744
 745         WREG32(CGTS_SYS_TCC_DISABLE, 0);
 746         WREG32(CGTS_TCC_DISABLE, 0);
 747         WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
 748         WREG32(CGTS_USER_TCC_DISABLE, 0);
 749
 750         num_qd_pipes =
 751                 R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
 752         WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
 753         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
 754
 755         /* set HW defaults for 3D engine */
 756         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
 757                                      ROQ_IB2_START(0x2b)));
 758
 759         WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
 760
 761         ta_aux_cntl = RREG32(TA_CNTL_AUX);
 762         WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO);
 763
 764         sx_debug_1 = RREG32(SX_DEBUG_1);
 765         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
 766         WREG32(SX_DEBUG_1, sx_debug_1);
 767
 768         smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
 769         smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
 770         smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
 771         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
 772
 773         if (rdev->family != CHIP_RV740)
 774                 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
 775                                        GS_FLUSH_CTL(4) |
 776                                        ACK_FLUSH_CTL(3) |
 777                                        SYNC_FLUSH_CTL));
 778
 779         db_debug3 = RREG32(DB_DEBUG3);
 780         db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
 781         switch (rdev->family) {
 782         case CHIP_RV770:
 783         case CHIP_RV740:
 784                 db_debug3 |= DB_CLK_OFF_DELAY(0x1f);
 785                 break;
 786         case CHIP_RV710:
 787         case CHIP_RV730:
 788         default:
 789                 db_debug3 |= DB_CLK_OFF_DELAY(2);
 790                 break;
 791         }
 792         WREG32(DB_DEBUG3, db_debug3);
 793
 794         if (rdev->family != CHIP_RV770) {
 795                 db_debug4 = RREG32(DB_DEBUG4);
 796                 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
 797                 WREG32(DB_DEBUG4, db_debug4);
 798         }
 799
 800         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
 801                                         POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
 802                                         SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
 803
 804         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
 805                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
 806                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
 807
 808         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
 809
 810         WREG32(VGT_NUM_INSTANCES, 1);
 811
 812         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
 813
 814         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
 815
 816         WREG32(CP_PERFMON_CNTL, 0);
 817
 818         sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
 819                             DONE_FIFO_HIWATER(0xe0) |
 820                             ALU_UPDATE_FIFO_HIWATER(0x8));
 821         switch (rdev->family) {
 822         case CHIP_RV770:
 823         case CHIP_RV730:
 824         case CHIP_RV710:
 825                 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
 826                 break;
 827         case CHIP_RV740:
 828         default:
 829                 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
 830                 break;
 831         }
 832         WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
 833
 834         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
 835          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
 836          */
 837         sq_config = RREG32(SQ_CONFIG);
 838         sq_config &= ~(PS_PRIO(3) |
 839                        VS_PRIO(3) |
 840                        GS_PRIO(3) |
 841                        ES_PRIO(3));
 842         sq_config |= (DX9_CONSTS |
 843                       VC_ENABLE |
 844                       EXPORT_SRC_C |
 845                       PS_PRIO(0) |
 846                       VS_PRIO(1) |
 847                       GS_PRIO(2) |
 848                       ES_PRIO(3));
 849         if (rdev->family == CHIP_RV710)
 850                 /* no vertex cache */
 851                 sq_config &= ~VC_ENABLE;
 852
 853         WREG32(SQ_CONFIG, sq_config);
 854
 855         WREG32(SQ_GPR_RESOURCE_MGMT_1,  (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
 856                                          NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
 857                                          NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
 858
 859         WREG32(SQ_GPR_RESOURCE_MGMT_2,  (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
 860                                          NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
 861
 862         sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
 863                                    NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
 864                                    NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
 865         if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
 866                 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
 867         else
 868                 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
 869         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
 870
 871         WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
 872                                                      NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
 873
 874         WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
 875                                                      NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
 876
 877         sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
 878                                      SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
 879                                      SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
 880                                      SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
 881
 882         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
 883         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
 884         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
 885         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
 886         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
 887         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
 888         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
 889         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
 890
 891         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
 892                                           FORCE_EOV_MAX_REZ_CNT(255)));
 893
 894         if (rdev->family == CHIP_RV710)
 895                 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
 896                                                 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
 897         else
 898                 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
 899                                                 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
 900
 901         switch (rdev->family) {
 902         case CHIP_RV770:
 903         case CHIP_RV730:
 904         case CHIP_RV740:
 905                 gs_prim_buffer_depth = 384;
 906                 break;
 907         case CHIP_RV710:
 908                 gs_prim_buffer_depth = 128;
 909                 break;
 910         default:
 911                 break;
 912         }
 913
 914         num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
 915         vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
 916         /* Max value for this is 256 */
 917         if (vgt_gs_per_es > 256)
 918                 vgt_gs_per_es = 256;
 919
 920         WREG32(VGT_ES_PER_GS, 128);
 921         WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
 922         WREG32(VGT_GS_PER_VS, 2);
 923
 924         /* more default values. 2D/3D driver should adjust as needed */
 925         WREG32(VGT_GS_VERTEX_REUSE, 16);
 926         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
 927         WREG32(VGT_STRMOUT_EN, 0);
 928         WREG32(SX_MISC, 0);
 929         WREG32(PA_SC_MODE_CNTL, 0);
 930         WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
 931         WREG32(PA_SC_AA_CONFIG, 0);
 932         WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
 933         WREG32(PA_SC_LINE_STIPPLE, 0);
 934         WREG32(SPI_INPUT_Z, 0);
 935         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
 936         WREG32(CB_COLOR7_FRAG, 0);
 937
 938         /* clear render buffer base addresses */
 939         WREG32(CB_COLOR0_BASE, 0);
 940         WREG32(CB_COLOR1_BASE, 0);
 941         WREG32(CB_COLOR2_BASE, 0);
 942         WREG32(CB_COLOR3_BASE, 0);
 943         WREG32(CB_COLOR4_BASE, 0);
 944         WREG32(CB_COLOR5_BASE, 0);
 945         WREG32(CB_COLOR6_BASE, 0);
 946         WREG32(CB_COLOR7_BASE, 0);
 947
 948         WREG32(TCP_CNTL, 0);
 949
 950         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
 951         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
 952
 953         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
 954
 955         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
 956                                           NUM_CLIP_SEQ(3)));
 957
 958 }
 959
 960 void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
 961 {
 962         u64 size_bf, size_af;
 963
 964         if (mc->mc_vram_size > 0xE0000000) {
 965                 /* leave room for at least 512M GTT */
 966                 dev_warn(rdev->dev, "limiting VRAM\n");
 967                 mc->real_vram_size = 0xE0000000;
 968                 mc->mc_vram_size = 0xE0000000;
 969         }
 970         if (rdev->flags & RADEON_IS_AGP) {
 971                 size_bf = mc->gtt_start;
 972                 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
 973                 if (size_bf > size_af) {
 974                         if (mc->mc_vram_size > size_bf) {
 975                                 dev_warn(rdev->dev, "limiting VRAM\n");
 976                                 mc->real_vram_size = size_bf;
 977                                 mc->mc_vram_size = size_bf;
 978                         }
 979                         mc->vram_start = mc->gtt_start - mc->mc_vram_size;
 980                 } else {
 981                         if (mc->mc_vram_size > size_af) {
 982                                 dev_warn(rdev->dev, "limiting VRAM\n");
 983                                 mc->real_vram_size = size_af;
 984                                 mc->mc_vram_size = size_af;
 985                         }
 986                         mc->vram_start = mc->gtt_end;
 987                 }
 988                 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 989                 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
 990                                 mc->mc_vram_size >> 20, mc->vram_start,
 991                                 mc->vram_end, mc->real_vram_size >> 20);
 992         } else {
 993                 radeon_vram_location(rdev, &rdev->mc, 0);
 994                 rdev->mc.gtt_base_align = 0;
 995                 radeon_gtt_location(rdev, mc);
 996         }
 997 }
 998
 999 int rv770_mc_init(struct radeon_device *rdev)
1000 {
1001         u32 tmp;
1002         int chansize, numchan;
1003
1004         /* Get VRAM informations */
1005         rdev->mc.vram_is_ddr = true;
1006         tmp = RREG32(MC_ARB_RAMCFG);
1007         if (tmp & CHANSIZE_OVERRIDE) {
1008                 chansize = 16;
1009         } else if (tmp & CHANSIZE_MASK) {
1010                 chansize = 64;
1011         } else {
1012                 chansize = 32;
1013         }
1014         tmp = RREG32(MC_SHARED_CHMAP);
1015         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1016         case 0:
1017         default:
1018                 numchan = 1;
1019                 break;
1020         case 1:
1021                 numchan = 2;
1022                 break;
1023         case 2:
1024                 numchan = 4;
1025                 break;
1026         case 3:
1027                 numchan = 8;
1028                 break;
1029         }
1030         rdev->mc.vram_width = numchan * chansize;
1031         /* Could aper size report 0 ? */
1032         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1033         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1034         /* Setup GPU memory space */
1035         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1036         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1037         rdev->mc.visible_vram_size = rdev->mc.aper_size;
1038         r700_vram_gtt_location(rdev, &rdev->mc);
1039         radeon_update_bandwidth_info(rdev);
1040
1041         return 0;
1042 }
1043
1044 static int rv770_startup(struct radeon_device *rdev)
1045 {
1046         int r;
1047
1048         /* enable pcie gen2 link */
1049         rv770_pcie_gen2_enable(rdev);
1050
1051         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1052                 r = r600_init_microcode(rdev);
1053                 if (r) {
1054                         DRM_ERROR("Failed to load firmware!\n");
1055                         return r;
1056                 }
1057         }
1058
1059         r = r600_vram_scratch_init(rdev);
1060         if (r)
1061                 return r;
1062
1063         rv770_mc_program(rdev);
1064         if (rdev->flags & RADEON_IS_AGP) {
1065                 rv770_agp_enable(rdev);
1066         } else {
1067                 r = rv770_pcie_gart_enable(rdev);
1068                 if (r)
1069                         return r;
1070         }
1071
1072         rv770_gpu_init(rdev);
1073         r = r600_blit_init(rdev);
1074         if (r) {
1075                 r600_blit_fini(rdev);
1076                 rdev->asic->copy = NULL;
1077                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1078         }
1079
1080         /* allocate wb buffer */
1081         r = radeon_wb_init(rdev);
1082         if (r)
1083                 return r;
1084
1085         /* Enable IRQ */
1086         r = r600_irq_init(rdev);
1087         if (r) {
1088                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1089                 radeon_irq_kms_fini(rdev);
1090                 return r;
1091         }
1092         r600_irq_set(rdev);
1093
1094         r = radeon_ring_init(rdev, rdev->cp.ring_size);
1095         if (r)
1096                 return r;
1097         r = rv770_cp_load_microcode(rdev);
1098         if (r)
1099                 return r;
1100         r = r600_cp_resume(rdev);
1101         if (r)
1102                 return r;
1103
1104         return 0;
1105 }
1106
1107 int rv770_resume(struct radeon_device *rdev)
1108 {
1109         int r;
1110
1111         /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1112          * posting will perform necessary task to bring back GPU into good
1113          * shape.
1114          */
1115         /* post card */
1116         atom_asic_init(rdev->mode_info.atom_context);
1117
1118         r = rv770_startup(rdev);
1119         if (r) {
1120                 DRM_ERROR("r600 startup failed on resume\n");
1121                 return r;
1122         }
1123
1124         r = r600_ib_test(rdev);
1125         if (r) {
1126                 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
1127                 return r;
1128         }
1129
1130         r = r600_audio_init(rdev);
1131         if (r) {
1132                 dev_err(rdev->dev, "radeon: audio init failed\n");
1133                 return r;
1134         }
1135
1136         return r;
1137
1138 }
1139
1140 int rv770_suspend(struct radeon_device *rdev)
1141 {
1142         r600_audio_fini(rdev);
1143         /* FIXME: we should wait for ring to be empty */
1144         r700_cp_stop(rdev);
1145         rdev->cp.ready = false;
1146         r600_irq_suspend(rdev);
1147         radeon_wb_disable(rdev);
1148         rv770_pcie_gart_disable(rdev);
1149         r600_blit_suspend(rdev);
1150
1151         return 0;
1152 }
1153
1154 /* Plan is to move initialization in that function and use
1155  * helper function so that radeon_device_init pretty much
1156  * do nothing more than calling asic specific function. This
1157  * should also allow to remove a bunch of callback function
1158  * like vram_info.
1159  */
1160 int rv770_init(struct radeon_device *rdev)
1161 {
1162         int r;
1163
1164         /* This don't do much */
1165         r = radeon_gem_init(rdev);
1166         if (r)
1167                 return r;
1168         /* Read BIOS */
1169         if (!radeon_get_bios(rdev)) {
1170                 if (ASIC_IS_AVIVO(rdev))
1171                         return -EINVAL;
1172         }
1173         /* Must be an ATOMBIOS */
1174         if (!rdev->is_atom_bios) {
1175                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
1176                 return -EINVAL;
1177         }
1178         r = radeon_atombios_init(rdev);
1179         if (r)
1180                 return r;
1181         /* Post card if necessary */
1182         if (!radeon_card_posted(rdev)) {
1183                 if (!rdev->bios) {
1184                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1185                         return -EINVAL;
1186                 }
1187                 DRM_INFO("GPU not posted. posting now...\n");
1188                 atom_asic_init(rdev->mode_info.atom_context);
1189         }
1190         /* Initialize scratch registers */
1191         r600_scratch_init(rdev);
1192         /* Initialize surface registers */
1193         radeon_surface_init(rdev);
1194         /* Initialize clocks */
1195         radeon_get_clock_info(rdev->ddev);
1196         /* Fence driver */
1197         r = radeon_fence_driver_init(rdev);
1198         if (r)
1199                 return r;
1200         /* initialize AGP */
1201         if (rdev->flags & RADEON_IS_AGP) {
1202                 r = radeon_agp_init(rdev);
1203                 if (r)
1204                         radeon_agp_disable(rdev);
1205         }
1206         r = rv770_mc_init(rdev);
1207         if (r)
1208                 return r;
1209         /* Memory manager */
1210         r = radeon_bo_init(rdev);
1211         if (r)
1212                 return r;
1213
1214         r = radeon_irq_kms_init(rdev);
1215         if (r)
1216                 return r;
1217
1218         rdev->cp.ring_obj = NULL;
1219         r600_ring_init(rdev, 1024 * 1024);
1220
1221         rdev->ih.ring_obj = NULL;
1222         r600_ih_ring_init(rdev, 64 * 1024);
1223
1224         r = r600_pcie_gart_init(rdev);
1225         if (r)
1226                 return r;
1227
1228         rdev->accel_working = true;
1229         r = rv770_startup(rdev);
1230         if (r) {
1231                 dev_err(rdev->dev, "disabling GPU acceleration\n");
1232                 r700_cp_fini(rdev);
1233                 r600_irq_fini(rdev);
1234                 radeon_wb_fini(rdev);
1235                 radeon_irq_kms_fini(rdev);
1236                 rv770_pcie_gart_fini(rdev);
1237                 rdev->accel_working = false;
1238         }
1239         if (rdev->accel_working) {
1240                 r = radeon_ib_pool_init(rdev);
1241                 if (r) {
1242                         dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1243                         rdev->accel_working = false;
1244                 } else {
1245                         r = r600_ib_test(rdev);
1246                         if (r) {
1247                                 dev_err(rdev->dev, "IB test failed (%d).\n", r);
1248                                 rdev->accel_working = false;
1249                         }
1250                 }
1251         }
1252
1253         r = r600_audio_init(rdev);
1254         if (r) {
1255                 dev_err(rdev->dev, "radeon: audio init failed\n");
1256                 return r;
1257         }
1258
1259         return 0;
1260 }
1261
1262 void rv770_fini(struct radeon_device *rdev)
1263 {
1264         r600_blit_fini(rdev);
1265         r700_cp_fini(rdev);
1266         r600_irq_fini(rdev);
1267         radeon_wb_fini(rdev);
1268         radeon_ib_pool_fini(rdev);
1269         radeon_irq_kms_fini(rdev);
1270         rv770_pcie_gart_fini(rdev);
1271         r600_vram_scratch_fini(rdev);
1272         radeon_gem_fini(rdev);
1273         radeon_fence_driver_fini(rdev);
1274         radeon_agp_fini(rdev);
1275         radeon_bo_fini(rdev);
1276         radeon_atombios_fini(rdev);
1277         kfree(rdev->bios);
1278         rdev->bios = NULL;
1279 }
1280
1281 static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
1282 {
1283         u32 link_width_cntl, lanes, speed_cntl, tmp;
1284         u16 link_cntl2;
1285
1286         if (radeon_pcie_gen2 == 0)
1287                 return;
1288
1289         if (rdev->flags & RADEON_IS_IGP)
1290                 return;
1291
1292         if (!(rdev->flags & RADEON_IS_PCIE))
1293                 return;
1294
1295         /* x2 cards have a special sequence */
1296         if (ASIC_IS_X2(rdev))
1297                 return;
1298
1299         /* advertise upconfig capability */
1300         link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1301         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
1302         WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1303         link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1304         if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
1305                 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
1306                 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
1307                                      LC_RECONFIG_ARC_MISSING_ESCAPE);
1308                 link_width_cntl |= lanes | LC_RECONFIG_NOW |
1309                         LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT;
1310                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1311         } else {
1312                 link_width_cntl |= LC_UPCONFIGURE_DIS;
1313                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1314         }
1315
1316         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1317         if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
1318             (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
1319
1320                 tmp = RREG32(0x541c);
1321                 WREG32(0x541c, tmp | 0x8);
1322                 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
1323                 link_cntl2 = RREG16(0x4088);
1324                 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
1325                 link_cntl2 |= 0x2;
1326                 WREG16(0x4088, link_cntl2);
1327                 WREG32(MM_CFGREGS_CNTL, 0);
1328
1329                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1330                 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
1331                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1332
1333                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1334                 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
1335                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1336
1337                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1338                 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
1339                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1340
1341                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1342                 speed_cntl |= LC_GEN2_EN_STRAP;
1343                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1344
1345         } else {
1346                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1347                 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
1348                 if (1)
1349                         link_width_cntl |= LC_UPCONFIGURE_DIS;
1350                 else
1351                         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
1352                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1353         }
1354 }