drivers/gpu/drm/radeon/rv515r.h

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #ifndef RV515R_H
  29 #define RV515R_H
  30
  31 /* RV515 registers */
  32 #define PCIE_INDEX                      0x0030
  33 #define PCIE_DATA                       0x0034
  34 #define MC_IND_INDEX                    0x0070
  35 #define         MC_IND_WR_EN                            (1 << 24)
  36 #define MC_IND_DATA                     0x0074
  37 #define RBBM_SOFT_RESET                 0x00F0
  38 #define CONFIG_MEMSIZE                  0x00F8
  39 #define HDP_FB_LOCATION                 0x0134
  40 #define CP_CSQ_CNTL                     0x0740
  41 #define CP_CSQ_MODE                     0x0744
  42 #define CP_CSQ_ADDR                     0x07F0
  43 #define CP_CSQ_DATA                     0x07F4
  44 #define CP_CSQ_STAT                     0x07F8
  45 #define CP_CSQ2_STAT                    0x07FC
  46 #define RBBM_STATUS                     0x0E40
  47 #define DST_PIPE_CONFIG                 0x170C
  48 #define WAIT_UNTIL                      0x1720
  49 #define         WAIT_2D_IDLE                            (1 << 14)
  50 #define         WAIT_3D_IDLE                            (1 << 15)
  51 #define         WAIT_2D_IDLECLEAN                       (1 << 16)
  52 #define         WAIT_3D_IDLECLEAN                       (1 << 17)
  53 #define ISYNC_CNTL                      0x1724
  54 #define         ISYNC_ANY2D_IDLE3D                      (1 << 0)
  55 #define         ISYNC_ANY3D_IDLE2D                      (1 << 1)
  56 #define         ISYNC_TRIG2D_IDLE3D                     (1 << 2)
  57 #define         ISYNC_TRIG3D_IDLE2D                     (1 << 3)
  58 #define         ISYNC_WAIT_IDLEGUI                      (1 << 4)
  59 #define         ISYNC_CPSCRATCH_IDLEGUI                 (1 << 5)
  60 #define VAP_INDEX_OFFSET                0x208C
  61 #define VAP_PVS_STATE_FLUSH_REG         0x2284
  62 #define GB_ENABLE                       0x4008
  63 #define GB_MSPOS0                       0x4010
  64 #define         MS_X0_SHIFT                             0
  65 #define         MS_Y0_SHIFT                             4
  66 #define         MS_X1_SHIFT                             8
  67 #define         MS_Y1_SHIFT                             12
  68 #define         MS_X2_SHIFT                             16
  69 #define         MS_Y2_SHIFT                             20
  70 #define         MSBD0_Y_SHIFT                           24
  71 #define         MSBD0_X_SHIFT                           28
  72 #define GB_MSPOS1                       0x4014
  73 #define         MS_X3_SHIFT                             0
  74 #define         MS_Y3_SHIFT                             4
  75 #define         MS_X4_SHIFT                             8
  76 #define         MS_Y4_SHIFT                             12
  77 #define         MS_X5_SHIFT                             16
  78 #define         MS_Y5_SHIFT                             20
  79 #define         MSBD1_SHIFT                             24
  80 #define GB_TILE_CONFIG                  0x4018
  81 #define         ENABLE_TILING                           (1 << 0)
  82 #define         PIPE_COUNT_MASK                         0x0000000E
  83 #define         PIPE_COUNT_SHIFT                        1
  84 #define         TILE_SIZE_8                             (0 << 4)
  85 #define         TILE_SIZE_16                            (1 << 4)
  86 #define         TILE_SIZE_32                            (2 << 4)
  87 #define         SUBPIXEL_1_12                           (0 << 16)
  88 #define         SUBPIXEL_1_16                           (1 << 16)
  89 #define GB_SELECT                       0x401C
  90 #define GB_AA_CONFIG                    0x4020
  91 #define GB_PIPE_SELECT                  0x402C
  92 #define GA_ENHANCE                      0x4274
  93 #define         GA_DEADLOCK_CNTL                        (1 << 0)
  94 #define         GA_FASTSYNC_CNTL                        (1 << 1)
  95 #define GA_POLY_MODE                    0x4288
  96 #define         FRONT_PTYPE_POINT                       (0 << 4)
  97 #define         FRONT_PTYPE_LINE                        (1 << 4)
  98 #define         FRONT_PTYPE_TRIANGE                     (2 << 4)
  99 #define         BACK_PTYPE_POINT                        (0 << 7)
 100 #define         BACK_PTYPE_LINE                         (1 << 7)
 101 #define         BACK_PTYPE_TRIANGE                      (2 << 7)
 102 #define GA_ROUND_MODE                   0x428C
 103 #define         GEOMETRY_ROUND_TRUNC                    (0 << 0)
 104 #define         GEOMETRY_ROUND_NEAREST                  (1 << 0)
 105 #define         COLOR_ROUND_TRUNC                       (0 << 2)
 106 #define         COLOR_ROUND_NEAREST                     (1 << 2)
 107 #define SU_REG_DEST                     0x42C8
 108 #define RB3D_DSTCACHE_CTLSTAT           0x4E4C
 109 #define         RB3D_DC_FLUSH                           (2 << 0)
 110 #define         RB3D_DC_FREE                            (2 << 2)
 111 #define         RB3D_DC_FINISH                          (1 << 4)
 112 #define ZB_ZCACHE_CTLSTAT               0x4F18
 113 #define         ZC_FLUSH                                (1 << 0)
 114 #define         ZC_FREE                                 (1 << 1)
 115 #define DC_LB_MEMORY_SPLIT              0x6520
 116 #define         DC_LB_MEMORY_SPLIT_MASK                 0x00000003
 117 #define         DC_LB_MEMORY_SPLIT_SHIFT                0
 118 #define         DC_LB_MEMORY_SPLIT_D1HALF_D2HALF        0
 119 #define         DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q          1
 120 #define         DC_LB_MEMORY_SPLIT_D1_ONLY              2
 121 #define         DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q          3
 122 #define         DC_LB_MEMORY_SPLIT_SHIFT_MODE           (1 << 2)
 123 #define         DC_LB_DISP1_END_ADR_SHIFT               4
 124 #define         DC_LB_DISP1_END_ADR_MASK                0x00007FF0
 125 #define D1MODE_PRIORITY_A_CNT           0x6548
 126 #define         MODE_PRIORITY_MARK_MASK                 0x00007FFF
 127 #define         MODE_PRIORITY_OFF                       (1 << 16)
 128 #define         MODE_PRIORITY_ALWAYS_ON                 (1 << 20)
 129 #define         MODE_PRIORITY_FORCE_MASK                (1 << 24)
 130 #define D1MODE_PRIORITY_B_CNT           0x654C
 131 #define LB_MAX_REQ_OUTSTANDING          0x6D58
 132 #define         LB_D1_MAX_REQ_OUTSTANDING_MASK          0x0000000F
 133 #define         LB_D1_MAX_REQ_OUTSTANDING_SHIFT         0
 134 #define         LB_D2_MAX_REQ_OUTSTANDING_MASK          0x000F0000
 135 #define         LB_D2_MAX_REQ_OUTSTANDING_SHIFT         16
 136 #define D2MODE_PRIORITY_A_CNT           0x6D48
 137 #define D2MODE_PRIORITY_B_CNT           0x6D4C
 138
 139 /* ix[MC] registers */
 140 #define MC_FB_LOCATION                  0x01
 141 #define         MC_FB_START_MASK                        0x0000FFFF
 142 #define         MC_FB_START_SHIFT                       0
 143 #define         MC_FB_TOP_MASK                          0xFFFF0000
 144 #define         MC_FB_TOP_SHIFT                         16
 145 #define MC_AGP_LOCATION                 0x02
 146 #define         MC_AGP_START_MASK                       0x0000FFFF
 147 #define         MC_AGP_START_SHIFT                      0
 148 #define         MC_AGP_TOP_MASK                         0xFFFF0000
 149 #define         MC_AGP_TOP_SHIFT                        16
 150 #define MC_AGP_BASE                     0x03
 151 #define MC_AGP_BASE_2                   0x04
 152 #define MC_CNTL                         0x5
 153 #define         MEM_NUM_CHANNELS_MASK                   0x00000003
 154 #define MC_STATUS                       0x08
 155 #define         MC_STATUS_IDLE                          (1 << 4)
 156 #define MC_MISC_LAT_TIMER               0x09
 157 #define         MC_CPR_INIT_LAT_MASK                    0x0000000F
 158 #define         MC_VF_INIT_LAT_MASK                     0x000000F0
 159 #define         MC_DISP0R_INIT_LAT_MASK                 0x00000F00
 160 #define         MC_DISP0R_INIT_LAT_SHIFT                8
 161 #define         MC_DISP1R_INIT_LAT_MASK                 0x0000F000
 162 #define         MC_DISP1R_INIT_LAT_SHIFT                12
 163 #define         MC_FIXED_INIT_LAT_MASK                  0x000F0000
 164 #define         MC_E2R_INIT_LAT_MASK                    0x00F00000
 165 #define         SAME_PAGE_PRIO_MASK                     0x0F000000
 166 #define         MC_GLOBW_INIT_LAT_MASK                  0xF0000000
 167
 168
 169 #endif
 170