drivers/gpu/drm/radeon/radeon_object.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <linux/list.h>
  33 #include <linux/slab.h>
  34 #include <drm/drmP.h>
  35 #include "radeon_drm.h"
  36 #include "radeon.h"
  37 #include "radeon_trace.h"
  38
  39
  40 int radeon_ttm_init(struct radeon_device *rdev);
  41 void radeon_ttm_fini(struct radeon_device *rdev);
  42 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
  43
  44 /*
  45  * To exclude mutual BO access we rely on bo_reserve exclusion, as all
  46  * function are calling it.
  47  */
  48
  49 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
  50 {
  51         struct radeon_bo *bo;
  52
  53         bo = container_of(tbo, struct radeon_bo, tbo);
  54         mutex_lock(&bo->rdev->gem.mutex);
  55         list_del_init(&bo->list);
  56         mutex_unlock(&bo->rdev->gem.mutex);
  57         radeon_bo_clear_surface_reg(bo);
  58         drm_gem_object_release(&bo->gem_base);
  59         kfree(bo);
  60 }
  61
  62 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
  63 {
  64         if (bo->destroy == &radeon_ttm_bo_destroy)
  65                 return true;
  66         return false;
  67 }
  68
  69 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
  70 {
  71         u32 c = 0;
  72
  73         rbo->placement.fpfn = 0;
  74         rbo->placement.lpfn = 0;
  75         rbo->placement.placement = rbo->placements;
  76         rbo->placement.busy_placement = rbo->placements;
  77         if (domain & RADEON_GEM_DOMAIN_VRAM)
  78                 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
  79                                         TTM_PL_FLAG_VRAM;
  80         if (domain & RADEON_GEM_DOMAIN_GTT)
  81                 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
  82         if (domain & RADEON_GEM_DOMAIN_CPU)
  83                 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
  84         if (!c)
  85                 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
  86         rbo->placement.num_placement = c;
  87         rbo->placement.num_busy_placement = c;
  88 }
  89
  90 int radeon_bo_create(struct radeon_device *rdev,
  91                      unsigned long size, int byte_align, bool kernel, u32 domain,
  92                      struct radeon_bo **bo_ptr)
  93 {
  94         struct radeon_bo *bo;
  95         enum ttm_bo_type type;
  96         unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
  97         unsigned long max_size = 0;
  98         int r;
  99
 100         size = ALIGN(size, PAGE_SIZE);
 101
 102         if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
 103                 rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
 104         }
 105         if (kernel) {
 106                 type = ttm_bo_type_kernel;
 107         } else {
 108                 type = ttm_bo_type_device;
 109         }
 110         *bo_ptr = NULL;
 111
 112         /* maximun bo size is the minimun btw visible vram and gtt size */
 113         max_size = min(rdev->mc.visible_vram_size, rdev->mc.gtt_size);
 114         if ((page_align << PAGE_SHIFT) >= max_size) {
 115                 printk(KERN_WARNING "%s:%d alloc size %ldM bigger than %ldMb limit\n",
 116                         __func__, __LINE__, page_align  >> (20 - PAGE_SHIFT), max_size >> 20);
 117                 return -ENOMEM;
 118         }
 119
 120 retry:
 121         bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
 122         if (bo == NULL)
 123                 return -ENOMEM;
 124         r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
 125         if (unlikely(r)) {
 126                 kfree(bo);
 127                 return r;
 128         }
 129         bo->rdev = rdev;
 130         bo->gem_base.driver_private = NULL;
 131         bo->surface_reg = -1;
 132         INIT_LIST_HEAD(&bo->list);
 133         radeon_ttm_placement_from_domain(bo, domain);
 134         /* Kernel allocation are uninterruptible */
 135         mutex_lock(&rdev->vram_mutex);
 136         r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
 137                         &bo->placement, page_align, 0, !kernel, NULL, size,
 138                         &radeon_ttm_bo_destroy);
 139         mutex_unlock(&rdev->vram_mutex);
 140         if (unlikely(r != 0)) {
 141                 if (r != -ERESTARTSYS) {
 142                         if (domain == RADEON_GEM_DOMAIN_VRAM) {
 143                                 domain |= RADEON_GEM_DOMAIN_GTT;
 144                                 goto retry;
 145                         }
 146                         dev_err(rdev->dev,
 147                                 "object_init failed for (%lu, 0x%08X)\n",
 148                                 size, domain);
 149                 }
 150                 return r;
 151         }
 152         *bo_ptr = bo;
 153
 154         trace_radeon_bo_create(bo);
 155
 156         return 0;
 157 }
 158
 159 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
 160 {
 161         bool is_iomem;
 162         int r;
 163
 164         if (bo->kptr) {
 165                 if (ptr) {
 166                         *ptr = bo->kptr;
 167                 }
 168                 return 0;
 169         }
 170         r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
 171         if (r) {
 172                 return r;
 173         }
 174         bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
 175         if (ptr) {
 176                 *ptr = bo->kptr;
 177         }
 178         radeon_bo_check_tiling(bo, 0, 0);
 179         return 0;
 180 }
 181
 182 void radeon_bo_kunmap(struct radeon_bo *bo)
 183 {
 184         if (bo->kptr == NULL)
 185                 return;
 186         bo->kptr = NULL;
 187         radeon_bo_check_tiling(bo, 0, 0);
 188         ttm_bo_kunmap(&bo->kmap);
 189 }
 190
 191 void radeon_bo_unref(struct radeon_bo **bo)
 192 {
 193         struct ttm_buffer_object *tbo;
 194         struct radeon_device *rdev;
 195
 196         if ((*bo) == NULL)
 197                 return;
 198         rdev = (*bo)->rdev;
 199         tbo = &((*bo)->tbo);
 200         mutex_lock(&rdev->vram_mutex);
 201         ttm_bo_unref(&tbo);
 202         mutex_unlock(&rdev->vram_mutex);
 203         if (tbo == NULL)
 204                 *bo = NULL;
 205 }
 206
 207 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
 208                              u64 *gpu_addr)
 209 {
 210         int r, i;
 211
 212         if (bo->pin_count) {
 213                 bo->pin_count++;
 214                 if (gpu_addr)
 215                         *gpu_addr = radeon_bo_gpu_offset(bo);
 216                 WARN_ON_ONCE(max_offset != 0);
 217                 return 0;
 218         }
 219         radeon_ttm_placement_from_domain(bo, domain);
 220         if (domain == RADEON_GEM_DOMAIN_VRAM) {
 221                 /* force to pin into visible video ram */
 222                 bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
 223         }
 224         if (max_offset) {
 225                 u64 lpfn = max_offset >> PAGE_SHIFT;
 226
 227                 if (!bo->placement.lpfn)
 228                         bo->placement.lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT;
 229
 230                 if (lpfn < bo->placement.lpfn)
 231                         bo->placement.lpfn = lpfn;
 232         }
 233         for (i = 0; i < bo->placement.num_placement; i++)
 234                 bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
 235         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
 236         if (likely(r == 0)) {
 237                 bo->pin_count = 1;
 238                 if (gpu_addr != NULL)
 239                         *gpu_addr = radeon_bo_gpu_offset(bo);
 240         }
 241         if (unlikely(r != 0))
 242                 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
 243         return r;
 244 }
 245
 246 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
 247 {
 248         return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
 249 }
 250
 251 int radeon_bo_unpin(struct radeon_bo *bo)
 252 {
 253         int r, i;
 254
 255         if (!bo->pin_count) {
 256                 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
 257                 return 0;
 258         }
 259         bo->pin_count--;
 260         if (bo->pin_count)
 261                 return 0;
 262         for (i = 0; i < bo->placement.num_placement; i++)
 263                 bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
 264         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
 265         if (unlikely(r != 0))
 266                 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
 267         return r;
 268 }
 269
 270 int radeon_bo_evict_vram(struct radeon_device *rdev)
 271 {
 272         /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
 273         if (0 && (rdev->flags & RADEON_IS_IGP)) {
 274                 if (rdev->mc.igp_sideport_enabled == false)
 275                         /* Useless to evict on IGP chips */
 276                         return 0;
 277         }
 278         return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
 279 }
 280
 281 void radeon_bo_force_delete(struct radeon_device *rdev)
 282 {
 283         struct radeon_bo *bo, *n;
 284
 285         if (list_empty(&rdev->gem.objects)) {
 286                 return;
 287         }
 288         dev_err(rdev->dev, "Userspace still has active objects !\n");
 289         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
 290                 mutex_lock(&rdev->ddev->struct_mutex);
 291                 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
 292                         &bo->gem_base, bo, (unsigned long)bo->gem_base.size,
 293                         *((unsigned long *)&bo->gem_base.refcount));
 294                 mutex_lock(&bo->rdev->gem.mutex);
 295                 list_del_init(&bo->list);
 296                 mutex_unlock(&bo->rdev->gem.mutex);
 297                 /* this should unref the ttm bo */
 298                 drm_gem_object_unreference(&bo->gem_base);
 299                 mutex_unlock(&rdev->ddev->struct_mutex);
 300         }
 301 }
 302
 303 int radeon_bo_init(struct radeon_device *rdev)
 304 {
 305         /* Add an MTRR for the VRAM */
 306         rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
 307                         MTRR_TYPE_WRCOMB, 1);
 308         DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
 309                 rdev->mc.mc_vram_size >> 20,
 310                 (unsigned long long)rdev->mc.aper_size >> 20);
 311         DRM_INFO("RAM width %dbits %cDR\n",
 312                         rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
 313         return radeon_ttm_init(rdev);
 314 }
 315
 316 void radeon_bo_fini(struct radeon_device *rdev)
 317 {
 318         radeon_ttm_fini(rdev);
 319 }
 320
 321 void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
 322                                 struct list_head *head)
 323 {
 324         if (lobj->wdomain) {
 325                 list_add(&lobj->tv.head, head);
 326         } else {
 327                 list_add_tail(&lobj->tv.head, head);
 328         }
 329 }
 330
 331 int radeon_bo_list_validate(struct list_head *head)
 332 {
 333         struct radeon_bo_list *lobj;
 334         struct radeon_bo *bo;
 335         u32 domain;
 336         int r;
 337
 338         r = ttm_eu_reserve_buffers(head);
 339         if (unlikely(r != 0)) {
 340                 return r;
 341         }
 342         list_for_each_entry(lobj, head, tv.head) {
 343                 bo = lobj->bo;
 344                 if (!bo->pin_count) {
 345                         domain = lobj->wdomain ? lobj->wdomain : lobj->rdomain;
 346
 347                 retry:
 348                         radeon_ttm_placement_from_domain(bo, domain);
 349                         r = ttm_bo_validate(&bo->tbo, &bo->placement,
 350                                                 true, false, false);
 351                         if (unlikely(r)) {
 352                                 if (r != -ERESTARTSYS && domain == RADEON_GEM_DOMAIN_VRAM) {
 353                                         domain |= RADEON_GEM_DOMAIN_GTT;
 354                                         goto retry;
 355                                 }
 356                                 return r;
 357                         }
 358                 }
 359                 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
 360                 lobj->tiling_flags = bo->tiling_flags;
 361         }
 362         return 0;
 363 }
 364
 365 int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
 366                              struct vm_area_struct *vma)
 367 {
 368         return ttm_fbdev_mmap(vma, &bo->tbo);
 369 }
 370
 371 int radeon_bo_get_surface_reg(struct radeon_bo *bo)
 372 {
 373         struct radeon_device *rdev = bo->rdev;
 374         struct radeon_surface_reg *reg;
 375         struct radeon_bo *old_object;
 376         int steal;
 377         int i;
 378
 379         BUG_ON(!atomic_read(&bo->tbo.reserved));
 380
 381         if (!bo->tiling_flags)
 382                 return 0;
 383
 384         if (bo->surface_reg >= 0) {
 385                 reg = &rdev->surface_regs[bo->surface_reg];
 386                 i = bo->surface_reg;
 387                 goto out;
 388         }
 389
 390         steal = -1;
 391         for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
 392
 393                 reg = &rdev->surface_regs[i];
 394                 if (!reg->bo)
 395                         break;
 396
 397                 old_object = reg->bo;
 398                 if (old_object->pin_count == 0)
 399                         steal = i;
 400         }
 401
 402         /* if we are all out */
 403         if (i == RADEON_GEM_MAX_SURFACES) {
 404                 if (steal == -1)
 405                         return -ENOMEM;
 406                 /* find someone with a surface reg and nuke their BO */
 407                 reg = &rdev->surface_regs[steal];
 408                 old_object = reg->bo;
 409                 /* blow away the mapping */
 410                 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
 411                 ttm_bo_unmap_virtual(&old_object->tbo);
 412                 old_object->surface_reg = -1;
 413                 i = steal;
 414         }
 415
 416         bo->surface_reg = i;
 417         reg->bo = bo;
 418
 419 out:
 420         radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
 421                                bo->tbo.mem.start << PAGE_SHIFT,
 422                                bo->tbo.num_pages << PAGE_SHIFT);
 423         return 0;
 424 }
 425
 426 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
 427 {
 428         struct radeon_device *rdev = bo->rdev;
 429         struct radeon_surface_reg *reg;
 430
 431         if (bo->surface_reg == -1)
 432                 return;
 433
 434         reg = &rdev->surface_regs[bo->surface_reg];
 435         radeon_clear_surface_reg(rdev, bo->surface_reg);
 436
 437         reg->bo = NULL;
 438         bo->surface_reg = -1;
 439 }
 440
 441 int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
 442                                 uint32_t tiling_flags, uint32_t pitch)
 443 {
 444         int r;
 445
 446         r = radeon_bo_reserve(bo, false);
 447         if (unlikely(r != 0))
 448                 return r;
 449         bo->tiling_flags = tiling_flags;
 450         bo->pitch = pitch;
 451         radeon_bo_unreserve(bo);
 452         return 0;
 453 }
 454
 455 void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
 456                                 uint32_t *tiling_flags,
 457                                 uint32_t *pitch)
 458 {
 459         BUG_ON(!atomic_read(&bo->tbo.reserved));
 460         if (tiling_flags)
 461                 *tiling_flags = bo->tiling_flags;
 462         if (pitch)
 463                 *pitch = bo->pitch;
 464 }
 465
 466 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
 467                                 bool force_drop)
 468 {
 469         BUG_ON(!atomic_read(&bo->tbo.reserved));
 470
 471         if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
 472                 return 0;
 473
 474         if (force_drop) {
 475                 radeon_bo_clear_surface_reg(bo);
 476                 return 0;
 477         }
 478
 479         if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
 480                 if (!has_moved)
 481                         return 0;
 482
 483                 if (bo->surface_reg >= 0)
 484                         radeon_bo_clear_surface_reg(bo);
 485                 return 0;
 486         }
 487
 488         if ((bo->surface_reg >= 0) && !has_moved)
 489                 return 0;
 490
 491         return radeon_bo_get_surface_reg(bo);
 492 }
 493
 494 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
 495                            struct ttm_mem_reg *mem)
 496 {
 497         struct radeon_bo *rbo;
 498         if (!radeon_ttm_bo_is_radeon_bo(bo))
 499                 return;
 500         rbo = container_of(bo, struct radeon_bo, tbo);
 501         radeon_bo_check_tiling(rbo, 0, 1);
 502 }
 503
 504 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 505 {
 506         struct radeon_device *rdev;
 507         struct radeon_bo *rbo;
 508         unsigned long offset, size;
 509         int r;
 510
 511         if (!radeon_ttm_bo_is_radeon_bo(bo))
 512                 return 0;
 513         rbo = container_of(bo, struct radeon_bo, tbo);
 514         radeon_bo_check_tiling(rbo, 0, 0);
 515         rdev = rbo->rdev;
 516         if (bo->mem.mem_type == TTM_PL_VRAM) {
 517                 size = bo->mem.num_pages << PAGE_SHIFT;
 518                 offset = bo->mem.start << PAGE_SHIFT;
 519                 if ((offset + size) > rdev->mc.visible_vram_size) {
 520                         /* hurrah the memory is not visible ! */
 521                         radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
 522                         rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
 523                         r = ttm_bo_validate(bo, &rbo->placement, false, true, false);
 524                         if (unlikely(r != 0))
 525                                 return r;
 526                         offset = bo->mem.start << PAGE_SHIFT;
 527                         /* this should not happen */
 528                         if ((offset + size) > rdev->mc.visible_vram_size)
 529                                 return -EINVAL;
 530                 }
 531         }
 532         return 0;
 533 }
 534
 535 int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait)
 536 {
 537         int r;
 538
 539         r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0);
 540         if (unlikely(r != 0))
 541                 return r;
 542         spin_lock(&bo->tbo.bdev->fence_lock);
 543         if (mem_type)
 544                 *mem_type = bo->tbo.mem.mem_type;
 545         if (bo->tbo.sync_obj)
 546                 r = ttm_bo_wait(&bo->tbo, true, true, no_wait);
 547         spin_unlock(&bo->tbo.bdev->fence_lock);
 548         ttm_bo_unreserve(&bo->tbo);
 549         return r;
 550 }
 551
 552
 553 /**
 554  * radeon_bo_reserve - reserve bo
 555  * @bo:         bo structure
 556  * @no_wait:            don't sleep while trying to reserve (return -EBUSY)
 557  *
 558  * Returns:
 559  * -EBUSY: buffer is busy and @no_wait is true
 560  * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
 561  * a signal. Release all buffer reservations and return to user-space.
 562  */
 563 int radeon_bo_reserve(struct radeon_bo *bo, bool no_wait)
 564 {
 565         int r;
 566
 567         r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0);
 568         if (unlikely(r != 0)) {
 569                 if (r != -ERESTARTSYS)
 570                         dev_err(bo->rdev->dev, "%p reserve failed\n", bo);
 571                 return r;
 572         }
 573         return 0;
 574 }