drivers/gpu/drm/radeon/radeon_legacy_crtc.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc_helper.h>
  28 #include <drm/radeon_drm.h>
  29 #include <drm/drm_fixed.h>
  30 #include "radeon.h"
  31 #include "atom.h"
  32
  33 static void radeon_overscan_setup(struct drm_crtc *crtc,
  34                                   struct drm_display_mode *mode)
  35 {
  36         struct drm_device *dev = crtc->dev;
  37         struct radeon_device *rdev = dev->dev_private;
  38         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  39
  40         WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0);
  41         WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0);
  42         WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0);
  43 }
  44
  45 static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
  46                                        struct drm_display_mode *mode)
  47 {
  48         struct drm_device *dev = crtc->dev;
  49         struct radeon_device *rdev = dev->dev_private;
  50         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  51         int xres = mode->hdisplay;
  52         int yres = mode->vdisplay;
  53         bool hscale = true, vscale = true;
  54         int hsync_wid;
  55         int vsync_wid;
  56         int hsync_start;
  57         int blank_width;
  58         u32 scale, inc, crtc_more_cntl;
  59         u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active;
  60         u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp;
  61         u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp;
  62         struct drm_display_mode *native_mode = &radeon_crtc->native_mode;
  63
  64         fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &
  65                 (RADEON_VERT_STRETCH_RESERVED |
  66                  RADEON_VERT_AUTO_RATIO_INC);
  67         fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) &
  68                 (RADEON_HORZ_FP_LOOP_STRETCH |
  69                  RADEON_HORZ_AUTO_RATIO_INC);
  70
  71         crtc_more_cntl = 0;
  72         if ((rdev->family == CHIP_RS100) ||
  73             (rdev->family == CHIP_RS200)) {
  74                 /* This is to workaround the asic bug for RMX, some versions
  75                    of BIOS dosen't have this register initialized correctly. */
  76                 crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
  77         }
  78
  79
  80         fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
  81                                 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
  82
  83         hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
  84         if (!hsync_wid)
  85                 hsync_wid = 1;
  86         hsync_start = mode->crtc_hsync_start - 8;
  87
  88         fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
  89                               | ((hsync_wid & 0x3f) << 16)
  90                               | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
  91                                  ? RADEON_CRTC_H_SYNC_POL
  92                                  : 0));
  93
  94         fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
  95                                 | ((mode->crtc_vdisplay - 1) << 16));
  96
  97         vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
  98         if (!vsync_wid)
  99                 vsync_wid = 1;
 100
 101         fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
 102                               | ((vsync_wid & 0x1f) << 16)
 103                               | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 104                                  ? RADEON_CRTC_V_SYNC_POL
 105                                  : 0));
 106
 107         fp_horz_vert_active = 0;
 108
 109         if (native_mode->hdisplay == 0 ||
 110             native_mode->vdisplay == 0) {
 111                 hscale = false;
 112                 vscale = false;
 113         } else {
 114                 if (xres > native_mode->hdisplay)
 115                         xres = native_mode->hdisplay;
 116                 if (yres > native_mode->vdisplay)
 117                         yres = native_mode->vdisplay;
 118
 119                 if (xres == native_mode->hdisplay)
 120                         hscale = false;
 121                 if (yres == native_mode->vdisplay)
 122                         vscale = false;
 123         }
 124
 125         switch (radeon_crtc->rmx_type) {
 126         case RMX_FULL:
 127         case RMX_ASPECT:
 128                 if (!hscale)
 129                         fp_horz_stretch |= ((xres/8-1) << 16);
 130                 else {
 131                         inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
 132                         scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
 133                                 / native_mode->hdisplay + 1;
 134                         fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) |
 135                                         RADEON_HORZ_STRETCH_BLEND |
 136                                         RADEON_HORZ_STRETCH_ENABLE |
 137                                         ((native_mode->hdisplay/8-1) << 16));
 138                 }
 139
 140                 if (!vscale)
 141                         fp_vert_stretch |= ((yres-1) << 12);
 142                 else {
 143                         inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
 144                         scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
 145                                 / native_mode->vdisplay + 1;
 146                         fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) |
 147                                         RADEON_VERT_STRETCH_ENABLE |
 148                                         RADEON_VERT_STRETCH_BLEND |
 149                                         ((native_mode->vdisplay-1) << 12));
 150                 }
 151                 break;
 152         case RMX_CENTER:
 153                 fp_horz_stretch |= ((xres/8-1) << 16);
 154                 fp_vert_stretch |= ((yres-1) << 12);
 155
 156                 crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN |
 157                                 RADEON_CRTC_AUTO_VERT_CENTER_EN);
 158
 159                 blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8;
 160                 if (blank_width > 110)
 161                         blank_width = 110;
 162
 163                 fp_crtc_h_total_disp = (((blank_width) & 0x3ff)
 164                                 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 165
 166                 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
 167                 if (!hsync_wid)
 168                         hsync_wid = 1;
 169
 170                 fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff)
 171                                 | ((hsync_wid & 0x3f) << 16)
 172                                 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
 173                                         ? RADEON_CRTC_H_SYNC_POL
 174                                         : 0));
 175
 176                 fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff)
 177                                 | ((mode->crtc_vdisplay - 1) << 16));
 178
 179                 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
 180                 if (!vsync_wid)
 181                         vsync_wid = 1;
 182
 183                 fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff)
 184                                         | ((vsync_wid & 0x1f) << 16)
 185                                         | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 186                                                 ? RADEON_CRTC_V_SYNC_POL
 187                                                 : 0)));
 188
 189                 fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) |
 190                                 (((native_mode->hdisplay / 8) & 0x1ff) << 16));
 191                 break;
 192         case RMX_OFF:
 193         default:
 194                 fp_horz_stretch |= ((xres/8-1) << 16);
 195                 fp_vert_stretch |= ((yres-1) << 12);
 196                 break;
 197         }
 198
 199         WREG32(RADEON_FP_HORZ_STRETCH,      fp_horz_stretch);
 200         WREG32(RADEON_FP_VERT_STRETCH,      fp_vert_stretch);
 201         WREG32(RADEON_CRTC_MORE_CNTL,       crtc_more_cntl);
 202         WREG32(RADEON_FP_HORZ_VERT_ACTIVE,  fp_horz_vert_active);
 203         WREG32(RADEON_FP_H_SYNC_STRT_WID,   fp_h_sync_strt_wid);
 204         WREG32(RADEON_FP_V_SYNC_STRT_WID,   fp_v_sync_strt_wid);
 205         WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);
 206         WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);
 207 }
 208
 209 void radeon_restore_common_regs(struct drm_device *dev)
 210 {
 211         /* don't need this yet */
 212 }
 213
 214 static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)
 215 {
 216         struct radeon_device *rdev = dev->dev_private;
 217         int i = 0;
 218
 219         /* FIXME: Certain revisions of R300 can't recover here.  Not sure of
 220            the cause yet, but this workaround will mask the problem for now.
 221            Other chips usually will pass at the very first test, so the
 222            workaround shouldn't have any effect on them. */
 223         for (i = 0;
 224              (i < 10000 &&
 225               RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
 226              i++);
 227 }
 228
 229 static void radeon_pll_write_update(struct drm_device *dev)
 230 {
 231         struct radeon_device *rdev = dev->dev_private;
 232
 233         while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
 234
 235         WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 236                            RADEON_PPLL_ATOMIC_UPDATE_W,
 237                            ~(RADEON_PPLL_ATOMIC_UPDATE_W));
 238 }
 239
 240 static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev)
 241 {
 242         struct radeon_device *rdev = dev->dev_private;
 243         int i = 0;
 244
 245
 246         /* FIXME: Certain revisions of R300 can't recover here.  Not sure of
 247            the cause yet, but this workaround will mask the problem for now.
 248            Other chips usually will pass at the very first test, so the
 249            workaround shouldn't have any effect on them. */
 250         for (i = 0;
 251              (i < 10000 &&
 252               RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
 253              i++);
 254 }
 255
 256 static void radeon_pll2_write_update(struct drm_device *dev)
 257 {
 258         struct radeon_device *rdev = dev->dev_private;
 259
 260         while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
 261
 262         WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
 263                            RADEON_P2PLL_ATOMIC_UPDATE_W,
 264                            ~(RADEON_P2PLL_ATOMIC_UPDATE_W));
 265 }
 266
 267 static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,
 268                                        uint16_t fb_div)
 269 {
 270         unsigned int vcoFreq;
 271
 272         if (!ref_div)
 273                 return 1;
 274
 275         vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div;
 276
 277         /*
 278          * This is horribly crude: the VCO frequency range is divided into
 279          * 3 parts, each part having a fixed PLL gain value.
 280          */
 281         if (vcoFreq >= 30000)
 282                 /*
 283                  * [300..max] MHz : 7
 284                  */
 285                 return 7;
 286         else if (vcoFreq >= 18000)
 287                 /*
 288                  * [180..300) MHz : 4
 289                  */
 290                 return 4;
 291         else
 292                 /*
 293                  * [0..180) MHz : 1
 294                  */
 295                 return 1;
 296 }
 297
 298 void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
 299 {
 300         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 301         struct drm_device *dev = crtc->dev;
 302         struct radeon_device *rdev = dev->dev_private;
 303         uint32_t mask;
 304
 305         if (radeon_crtc->crtc_id)
 306                 mask = (RADEON_CRTC2_DISP_DIS |
 307                         RADEON_CRTC2_VSYNC_DIS |
 308                         RADEON_CRTC2_HSYNC_DIS |
 309                         RADEON_CRTC2_DISP_REQ_EN_B);
 310         else
 311                 mask = (RADEON_CRTC_DISPLAY_DIS |
 312                         RADEON_CRTC_VSYNC_DIS |
 313                         RADEON_CRTC_HSYNC_DIS);
 314
 315         switch (mode) {
 316         case DRM_MODE_DPMS_ON:
 317                 radeon_crtc->enabled = true;
 318                 /* adjust pm to dpms changes BEFORE enabling crtcs */
 319                 radeon_pm_compute_clocks(rdev);
 320                 if (radeon_crtc->crtc_id)
 321                         WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask));
 322                 else {
 323                         WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
 324                                                                          RADEON_CRTC_DISP_REQ_EN_B));
 325                         WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask);
 326                 }
 327                 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
 328                 radeon_crtc_load_lut(crtc);
 329                 break;
 330         case DRM_MODE_DPMS_STANDBY:
 331         case DRM_MODE_DPMS_SUSPEND:
 332         case DRM_MODE_DPMS_OFF:
 333                 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
 334                 if (radeon_crtc->crtc_id)
 335                         WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask));
 336                 else {
 337                         WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
 338                                                                                     RADEON_CRTC_DISP_REQ_EN_B));
 339                         WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask);
 340                 }
 341                 radeon_crtc->enabled = false;
 342                 /* adjust pm to dpms changes AFTER disabling crtcs */
 343                 radeon_pm_compute_clocks(rdev);
 344                 break;
 345         }
 346 }
 347
 348 int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 349                          struct drm_framebuffer *old_fb)
 350 {
 351         return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
 352 }
 353
 354 int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
 355                                 struct drm_framebuffer *fb,
 356                                 int x, int y, enum mode_set_atomic state)
 357 {
 358         return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
 359 }
 360
 361 int radeon_crtc_do_set_base(struct drm_crtc *crtc,
 362                          struct drm_framebuffer *fb,
 363                          int x, int y, int atomic)
 364 {
 365         struct drm_device *dev = crtc->dev;
 366         struct radeon_device *rdev = dev->dev_private;
 367         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 368         struct radeon_framebuffer *radeon_fb;
 369         struct drm_framebuffer *target_fb;
 370         struct drm_gem_object *obj;
 371         struct radeon_bo *rbo;
 372         uint64_t base;
 373         uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
 374         uint32_t crtc_pitch, pitch_pixels;
 375         uint32_t tiling_flags;
 376         int format;
 377         uint32_t gen_cntl_reg, gen_cntl_val;
 378         int r;
 379
 380         DRM_DEBUG_KMS("\n");
 381         /* no fb bound */
 382         if (!atomic && !crtc->fb) {
 383                 DRM_DEBUG_KMS("No FB bound\n");
 384                 return 0;
 385         }
 386
 387         if (atomic) {
 388                 radeon_fb = to_radeon_framebuffer(fb);
 389                 target_fb = fb;
 390         }
 391         else {
 392                 radeon_fb = to_radeon_framebuffer(crtc->fb);
 393                 target_fb = crtc->fb;
 394         }
 395
 396         switch (target_fb->bits_per_pixel) {
 397         case 8:
 398                 format = 2;
 399                 break;
 400         case 15:      /*  555 */
 401                 format = 3;
 402                 break;
 403         case 16:      /*  565 */
 404                 format = 4;
 405                 break;
 406         case 24:      /*  RGB */
 407                 format = 5;
 408                 break;
 409         case 32:      /* xRGB */
 410                 format = 6;
 411                 break;
 412         default:
 413                 return false;
 414         }
 415
 416         /* Pin framebuffer & get tilling informations */
 417         obj = radeon_fb->obj;
 418         rbo = obj->driver_private;
 419         r = radeon_bo_reserve(rbo, false);
 420         if (unlikely(r != 0))
 421                 return r;
 422         r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &base);
 423         if (unlikely(r != 0)) {
 424                 radeon_bo_unreserve(rbo);
 425                 return -EINVAL;
 426         }
 427         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
 428         radeon_bo_unreserve(rbo);
 429         if (tiling_flags & RADEON_TILING_MICRO)
 430                 DRM_ERROR("trying to scanout microtiled buffer\n");
 431
 432         /* if scanout was in GTT this really wouldn't work */
 433         /* crtc offset is from display base addr not FB location */
 434         radeon_crtc->legacy_display_base_addr = rdev->mc.vram_start;
 435
 436         base -= radeon_crtc->legacy_display_base_addr;
 437
 438         crtc_offset_cntl = 0;
 439
 440         pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8);
 441         crtc_pitch  = (((pitch_pixels * target_fb->bits_per_pixel) +
 442                         ((target_fb->bits_per_pixel * 8) - 1)) /
 443                        (target_fb->bits_per_pixel * 8));
 444         crtc_pitch |= crtc_pitch << 16;
 445
 446
 447         if (tiling_flags & RADEON_TILING_MACRO) {
 448                 if (ASIC_IS_R300(rdev))
 449                         crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
 450                                              R300_CRTC_MICRO_TILE_BUFFER_DIS |
 451                                              R300_CRTC_MACRO_TILE_EN);
 452                 else
 453                         crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
 454         } else {
 455                 if (ASIC_IS_R300(rdev))
 456                         crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
 457                                               R300_CRTC_MICRO_TILE_BUFFER_DIS |
 458                                               R300_CRTC_MACRO_TILE_EN);
 459                 else
 460                         crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
 461         }
 462
 463         if (tiling_flags & RADEON_TILING_MACRO) {
 464                 if (ASIC_IS_R300(rdev)) {
 465                         crtc_tile_x0_y0 = x | (y << 16);
 466                         base &= ~0x7ff;
 467                 } else {
 468                         int byteshift = target_fb->bits_per_pixel >> 4;
 469                         int tile_addr = (((y >> 3) * pitch_pixels +  x) >> (8 - byteshift)) << 11;
 470                         base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
 471                         crtc_offset_cntl |= (y % 16);
 472                 }
 473         } else {
 474                 int offset = y * pitch_pixels + x;
 475                 switch (target_fb->bits_per_pixel) {
 476                 case 8:
 477                         offset *= 1;
 478                         break;
 479                 case 15:
 480                 case 16:
 481                         offset *= 2;
 482                         break;
 483                 case 24:
 484                         offset *= 3;
 485                         break;
 486                 case 32:
 487                         offset *= 4;
 488                         break;
 489                 default:
 490                         return false;
 491                 }
 492                 base += offset;
 493         }
 494
 495         base &= ~7;
 496
 497         if (radeon_crtc->crtc_id == 1)
 498                 gen_cntl_reg = RADEON_CRTC2_GEN_CNTL;
 499         else
 500                 gen_cntl_reg = RADEON_CRTC_GEN_CNTL;
 501
 502         gen_cntl_val = RREG32(gen_cntl_reg);
 503         gen_cntl_val &= ~(0xf << 8);
 504         gen_cntl_val |= (format << 8);
 505         WREG32(gen_cntl_reg, gen_cntl_val);
 506
 507         crtc_offset = (u32)base;
 508
 509         WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);
 510
 511         if (ASIC_IS_R300(rdev)) {
 512                 if (radeon_crtc->crtc_id)
 513                         WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0);
 514                 else
 515                         WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0);
 516         }
 517         WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl);
 518         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);
 519         WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
 520
 521         if (!atomic && fb && fb != crtc->fb) {
 522                 radeon_fb = to_radeon_framebuffer(fb);
 523                 rbo = radeon_fb->obj->driver_private;
 524                 r = radeon_bo_reserve(rbo, false);
 525                 if (unlikely(r != 0))
 526                         return r;
 527                 radeon_bo_unpin(rbo);
 528                 radeon_bo_unreserve(rbo);
 529         }
 530
 531         /* Bytes per pixel may have changed */
 532         radeon_bandwidth_update(rdev);
 533
 534         return 0;
 535 }
 536
 537 static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
 538 {
 539         struct drm_device *dev = crtc->dev;
 540         struct radeon_device *rdev = dev->dev_private;
 541         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 542         struct drm_encoder *encoder;
 543         int format;
 544         int hsync_start;
 545         int hsync_wid;
 546         int vsync_wid;
 547         uint32_t crtc_h_total_disp;
 548         uint32_t crtc_h_sync_strt_wid;
 549         uint32_t crtc_v_total_disp;
 550         uint32_t crtc_v_sync_strt_wid;
 551         bool is_tv = false;
 552
 553         DRM_DEBUG_KMS("\n");
 554         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 555                 if (encoder->crtc == crtc) {
 556                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 557                         if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
 558                                 is_tv = true;
 559                                 DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id);
 560                                 break;
 561                         }
 562                 }
 563         }
 564
 565         switch (crtc->fb->bits_per_pixel) {
 566         case 8:
 567                 format = 2;
 568                 break;
 569         case 15:      /*  555 */
 570                 format = 3;
 571                 break;
 572         case 16:      /*  565 */
 573                 format = 4;
 574                 break;
 575         case 24:      /*  RGB */
 576                 format = 5;
 577                 break;
 578         case 32:      /* xRGB */
 579                 format = 6;
 580                 break;
 581         default:
 582                 return false;
 583         }
 584
 585         crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
 586                              | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 587
 588         hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
 589         if (!hsync_wid)
 590                 hsync_wid = 1;
 591         hsync_start = mode->crtc_hsync_start - 8;
 592
 593         crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
 594                                 | ((hsync_wid & 0x3f) << 16)
 595                                 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
 596                                    ? RADEON_CRTC_H_SYNC_POL
 597                                    : 0));
 598
 599         /* This works for double scan mode. */
 600         crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
 601                              | ((mode->crtc_vdisplay - 1) << 16));
 602
 603         vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
 604         if (!vsync_wid)
 605                 vsync_wid = 1;
 606
 607         crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
 608                                 | ((vsync_wid & 0x1f) << 16)
 609                                 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 610                                    ? RADEON_CRTC_V_SYNC_POL
 611                                    : 0));
 612
 613         if (radeon_crtc->crtc_id) {
 614                 uint32_t crtc2_gen_cntl;
 615                 uint32_t disp2_merge_cntl;
 616
 617                 /* if TV DAC is enabled for another crtc and keep it enabled */
 618                 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0x00718080;
 619                 crtc2_gen_cntl |= ((format << 8)
 620                                    | RADEON_CRTC2_VSYNC_DIS
 621                                    | RADEON_CRTC2_HSYNC_DIS
 622                                    | RADEON_CRTC2_DISP_DIS
 623                                    | RADEON_CRTC2_DISP_REQ_EN_B
 624                                    | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
 625                                       ? RADEON_CRTC2_DBL_SCAN_EN
 626                                       : 0)
 627                                    | ((mode->flags & DRM_MODE_FLAG_CSYNC)
 628                                       ? RADEON_CRTC2_CSYNC_EN
 629                                       : 0)
 630                                    | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 631                                       ? RADEON_CRTC2_INTERLACE_EN
 632                                       : 0));
 633
 634                 /* rs4xx chips seem to like to have the crtc enabled when the timing is set */
 635                 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480))
 636                         crtc2_gen_cntl |= RADEON_CRTC2_EN;
 637
 638                 disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
 639                 disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
 640
 641                 WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl);
 642                 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 643
 644                 WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid);
 645                 WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid);
 646         } else {
 647                 uint32_t crtc_gen_cntl;
 648                 uint32_t crtc_ext_cntl;
 649                 uint32_t disp_merge_cntl;
 650
 651                 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0x00718000;
 652                 crtc_gen_cntl |= (RADEON_CRTC_EXT_DISP_EN
 653                                  | (format << 8)
 654                                  | RADEON_CRTC_DISP_REQ_EN_B
 655                                  | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
 656                                     ? RADEON_CRTC_DBL_SCAN_EN
 657                                     : 0)
 658                                  | ((mode->flags & DRM_MODE_FLAG_CSYNC)
 659                                     ? RADEON_CRTC_CSYNC_EN
 660                                     : 0)
 661                                  | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 662                                     ? RADEON_CRTC_INTERLACE_EN
 663                                     : 0));
 664
 665                 /* rs4xx chips seem to like to have the crtc enabled when the timing is set */
 666                 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480))
 667                         crtc_gen_cntl |= RADEON_CRTC_EN;
 668
 669                 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
 670                 crtc_ext_cntl |= (RADEON_XCRT_CNT_EN |
 671                                   RADEON_CRTC_VSYNC_DIS |
 672                                   RADEON_CRTC_HSYNC_DIS |
 673                                   RADEON_CRTC_DISPLAY_DIS);
 674
 675                 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
 676                 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
 677
 678                 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
 679                 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
 680                 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 681         }
 682
 683         if (is_tv)
 684                 radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp,
 685                                                  &crtc_h_sync_strt_wid, &crtc_v_total_disp,
 686                                                  &crtc_v_sync_strt_wid);
 687
 688         WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp);
 689         WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid);
 690         WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp);
 691         WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid);
 692
 693         return true;
 694 }
 695
 696 static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 697 {
 698         struct drm_device *dev = crtc->dev;
 699         struct radeon_device *rdev = dev->dev_private;
 700         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 701         struct drm_encoder *encoder;
 702         uint32_t feedback_div = 0;
 703         uint32_t frac_fb_div = 0;
 704         uint32_t reference_div = 0;
 705         uint32_t post_divider = 0;
 706         uint32_t freq = 0;
 707         uint8_t pll_gain;
 708         bool use_bios_divs = false;
 709         /* PLL registers */
 710         uint32_t pll_ref_div = 0;
 711         uint32_t pll_fb_post_div = 0;
 712         uint32_t htotal_cntl = 0;
 713         bool is_tv = false;
 714         struct radeon_pll *pll;
 715
 716         struct {
 717                 int divider;
 718                 int bitvalue;
 719         } *post_div, post_divs[]   = {
 720                 /* From RAGE 128 VR/RAGE 128 GL Register
 721                  * Reference Manual (Technical Reference
 722                  * Manual P/N RRG-G04100-C Rev. 0.04), page
 723                  * 3-17 (PLL_DIV_[3:0]).
 724                  */
 725                 {  1, 0 },              /* VCLK_SRC                 */
 726                 {  2, 1 },              /* VCLK_SRC/2               */
 727                 {  4, 2 },              /* VCLK_SRC/4               */
 728                 {  8, 3 },              /* VCLK_SRC/8               */
 729                 {  3, 4 },              /* VCLK_SRC/3               */
 730                 { 16, 5 },              /* VCLK_SRC/16              */
 731                 {  6, 6 },              /* VCLK_SRC/6               */
 732                 { 12, 7 },              /* VCLK_SRC/12              */
 733                 {  0, 0 }
 734         };
 735
 736         if (radeon_crtc->crtc_id)
 737                 pll = &rdev->clock.p2pll;
 738         else
 739                 pll = &rdev->clock.p1pll;
 740
 741         pll->flags = RADEON_PLL_LEGACY;
 742
 743         if (mode->clock > 200000) /* range limits??? */
 744                 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 745         else
 746                 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 747
 748         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 749                 if (encoder->crtc == crtc) {
 750                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 751
 752                         if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
 753                                 is_tv = true;
 754                                 break;
 755                         }
 756
 757                         if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
 758                                 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
 759                         if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
 760                                 if (!rdev->is_atom_bios) {
 761                                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 762                                         struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
 763                                         if (lvds) {
 764                                                 if (lvds->use_bios_dividers) {
 765                                                         pll_ref_div = lvds->panel_ref_divider;
 766                                                         pll_fb_post_div   = (lvds->panel_fb_divider |
 767                                                                              (lvds->panel_post_divider << 16));
 768                                                         htotal_cntl  = 0;
 769                                                         use_bios_divs = true;
 770                                                 }
 771                                         }
 772                                 }
 773                                 pll->flags |= RADEON_PLL_USE_REF_DIV;
 774                         }
 775                 }
 776         }
 777
 778         DRM_DEBUG_KMS("\n");
 779
 780         if (!use_bios_divs) {
 781                 radeon_compute_pll(pll, mode->clock,
 782                                    &freq, &feedback_div, &frac_fb_div,
 783                                    &reference_div, &post_divider);
 784
 785                 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
 786                         if (post_div->divider == post_divider)
 787                                 break;
 788                 }
 789
 790                 if (!post_div->divider)
 791                         post_div = &post_divs[0];
 792
 793                 DRM_DEBUG_KMS("dc=%u, fd=%d, rd=%d, pd=%d\n",
 794                           (unsigned)freq,
 795                           feedback_div,
 796                           reference_div,
 797                           post_divider);
 798
 799                 pll_ref_div   = reference_div;
 800 #if defined(__powerpc__) && (0) /* TODO */
 801                 /* apparently programming this otherwise causes a hang??? */
 802                 if (info->MacModel == RADEON_MAC_IBOOK)
 803                         pll_fb_post_div = 0x000600ad;
 804                 else
 805 #endif
 806                         pll_fb_post_div     = (feedback_div | (post_div->bitvalue << 16));
 807
 808                 htotal_cntl    = mode->htotal & 0x7;
 809
 810         }
 811
 812         pll_gain = radeon_compute_pll_gain(pll->reference_freq,
 813                                            pll_ref_div & 0x3ff,
 814                                            pll_fb_post_div & 0x7ff);
 815
 816         if (radeon_crtc->crtc_id) {
 817                 uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) &
 818                                           ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
 819                                          RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
 820
 821                 if (is_tv) {
 822                         radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl,
 823                                                      &pll_ref_div, &pll_fb_post_div,
 824                                                      &pixclks_cntl);
 825                 }
 826
 827                 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
 828                              RADEON_PIX2CLK_SRC_SEL_CPUCLK,
 829                              ~(RADEON_PIX2CLK_SRC_SEL_MASK));
 830
 831                 WREG32_PLL_P(RADEON_P2PLL_CNTL,
 832                              RADEON_P2PLL_RESET
 833                              | RADEON_P2PLL_ATOMIC_UPDATE_EN
 834                              | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT),
 835                              ~(RADEON_P2PLL_RESET
 836                                | RADEON_P2PLL_ATOMIC_UPDATE_EN
 837                                | RADEON_P2PLL_PVG_MASK));
 838
 839                 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
 840                              pll_ref_div,
 841                              ~RADEON_P2PLL_REF_DIV_MASK);
 842
 843                 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
 844                              pll_fb_post_div,
 845                              ~RADEON_P2PLL_FB0_DIV_MASK);
 846
 847                 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
 848                              pll_fb_post_div,
 849                              ~RADEON_P2PLL_POST0_DIV_MASK);
 850
 851                 radeon_pll2_write_update(dev);
 852                 radeon_pll2_wait_for_read_update_complete(dev);
 853
 854                 WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl);
 855
 856                 WREG32_PLL_P(RADEON_P2PLL_CNTL,
 857                              0,
 858                              ~(RADEON_P2PLL_RESET
 859                                | RADEON_P2PLL_SLEEP
 860                                | RADEON_P2PLL_ATOMIC_UPDATE_EN));
 861
 862                 DRM_DEBUG_KMS("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
 863                           (unsigned)pll_ref_div,
 864                           (unsigned)pll_fb_post_div,
 865                           (unsigned)htotal_cntl,
 866                           RREG32_PLL(RADEON_P2PLL_CNTL));
 867                 DRM_DEBUG_KMS("Wrote2: rd=%u, fd=%u, pd=%u\n",
 868                           (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
 869                           (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK,
 870                           (unsigned)((pll_fb_post_div &
 871                                       RADEON_P2PLL_POST0_DIV_MASK) >> 16));
 872
 873                 mdelay(50); /* Let the clock to lock */
 874
 875                 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
 876                              RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
 877                              ~(RADEON_PIX2CLK_SRC_SEL_MASK));
 878
 879                 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
 880         } else {
 881                 uint32_t pixclks_cntl;
 882
 883
 884                 if (is_tv) {
 885                         pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
 886                         radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div,
 887                                                      &pll_fb_post_div, &pixclks_cntl);
 888                 }
 889
 890                 if (rdev->flags & RADEON_IS_MOBILITY) {
 891                         /* A temporal workaround for the occational blanking on certain laptop panels.
 892                            This appears to related to the PLL divider registers (fail to lock?).
 893                            It occurs even when all dividers are the same with their old settings.
 894                            In this case we really don't need to fiddle with PLL registers.
 895                            By doing this we can avoid the blanking problem with some panels.
 896                         */
 897                         if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
 898                             (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) &
 899                                                  (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) {
 900                                 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
 901                                          RADEON_PLL_DIV_SEL,
 902                                          ~(RADEON_PLL_DIV_SEL));
 903                                 r100_pll_errata_after_index(rdev);
 904                                 return;
 905                         }
 906                 }
 907
 908                 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
 909                              RADEON_VCLK_SRC_SEL_CPUCLK,
 910                              ~(RADEON_VCLK_SRC_SEL_MASK));
 911                 WREG32_PLL_P(RADEON_PPLL_CNTL,
 912                              RADEON_PPLL_RESET
 913                              | RADEON_PPLL_ATOMIC_UPDATE_EN
 914                              | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
 915                              | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT),
 916                              ~(RADEON_PPLL_RESET
 917                                | RADEON_PPLL_ATOMIC_UPDATE_EN
 918                                | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
 919                                | RADEON_PPLL_PVG_MASK));
 920
 921                 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
 922                          RADEON_PLL_DIV_SEL,
 923                          ~(RADEON_PLL_DIV_SEL));
 924                 r100_pll_errata_after_index(rdev);
 925
 926                 if (ASIC_IS_R300(rdev) ||
 927                     (rdev->family == CHIP_RS300) ||
 928                     (rdev->family == CHIP_RS400) ||
 929                     (rdev->family == CHIP_RS480)) {
 930                         if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
 931                                 /* When restoring console mode, use saved PPLL_REF_DIV
 932                                  * setting.
 933                                  */
 934                                 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 935                                              pll_ref_div,
 936                                              0);
 937                         } else {
 938                                 /* R300 uses ref_div_acc field as real ref divider */
 939                                 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 940                                              (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
 941                                              ~R300_PPLL_REF_DIV_ACC_MASK);
 942                         }
 943                 } else
 944                         WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 945                                      pll_ref_div,
 946                                      ~RADEON_PPLL_REF_DIV_MASK);
 947
 948                 WREG32_PLL_P(RADEON_PPLL_DIV_3,
 949                              pll_fb_post_div,
 950                              ~RADEON_PPLL_FB3_DIV_MASK);
 951
 952                 WREG32_PLL_P(RADEON_PPLL_DIV_3,
 953                              pll_fb_post_div,
 954                              ~RADEON_PPLL_POST3_DIV_MASK);
 955
 956                 radeon_pll_write_update(dev);
 957                 radeon_pll_wait_for_read_update_complete(dev);
 958
 959                 WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl);
 960
 961                 WREG32_PLL_P(RADEON_PPLL_CNTL,
 962                              0,
 963                              ~(RADEON_PPLL_RESET
 964                                | RADEON_PPLL_SLEEP
 965                                | RADEON_PPLL_ATOMIC_UPDATE_EN
 966                                | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
 967
 968                 DRM_DEBUG_KMS("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
 969                           pll_ref_div,
 970                           pll_fb_post_div,
 971                           (unsigned)htotal_cntl,
 972                           RREG32_PLL(RADEON_PPLL_CNTL));
 973                 DRM_DEBUG_KMS("Wrote: rd=%d, fd=%d, pd=%d\n",
 974                           pll_ref_div & RADEON_PPLL_REF_DIV_MASK,
 975                           pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK,
 976                           (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16);
 977
 978                 mdelay(50); /* Let the clock to lock */
 979
 980                 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
 981                              RADEON_VCLK_SRC_SEL_PPLLCLK,
 982                              ~(RADEON_VCLK_SRC_SEL_MASK));
 983
 984                 if (is_tv)
 985                         WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
 986         }
 987 }
 988
 989 static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
 990                                    struct drm_display_mode *mode,
 991                                    struct drm_display_mode *adjusted_mode)
 992 {
 993         struct drm_device *dev = crtc->dev;
 994         struct radeon_device *rdev = dev->dev_private;
 995
 996         /* adjust pm to upcoming mode change */
 997         radeon_pm_compute_clocks(rdev);
 998
 999         if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1000                 return false;
1001         return true;
1002 }
1003
1004 static int radeon_crtc_mode_set(struct drm_crtc *crtc,
1005                                  struct drm_display_mode *mode,
1006                                  struct drm_display_mode *adjusted_mode,
1007                                  int x, int y, struct drm_framebuffer *old_fb)
1008 {
1009         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1010
1011         /* TODO TV */
1012         radeon_crtc_set_base(crtc, x, y, old_fb);
1013         radeon_set_crtc_timing(crtc, adjusted_mode);
1014         radeon_set_pll(crtc, adjusted_mode);
1015         radeon_overscan_setup(crtc, adjusted_mode);
1016         if (radeon_crtc->crtc_id == 0) {
1017                 radeon_legacy_rmx_mode_set(crtc, adjusted_mode);
1018         } else {
1019                 if (radeon_crtc->rmx_type != RMX_OFF) {
1020                         /* FIXME: only first crtc has rmx what should we
1021                          * do ?
1022                          */
1023                         DRM_ERROR("Mode need scaling but only first crtc can do that.\n");
1024                 }
1025         }
1026         return 0;
1027 }
1028
1029 static void radeon_crtc_prepare(struct drm_crtc *crtc)
1030 {
1031         struct drm_device *dev = crtc->dev;
1032         struct drm_crtc *crtci;
1033
1034         /*
1035         * The hardware wedges sometimes if you reconfigure one CRTC
1036         * whilst another is running (see fdo bug #24611).
1037         */
1038         list_for_each_entry(crtci, &dev->mode_config.crtc_list, head)
1039                 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_OFF);
1040 }
1041
1042 static void radeon_crtc_commit(struct drm_crtc *crtc)
1043 {
1044         struct drm_device *dev = crtc->dev;
1045         struct drm_crtc *crtci;
1046
1047         /*
1048         * Reenable the CRTCs that should be running.
1049         */
1050         list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) {
1051                 if (crtci->enabled)
1052                         radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON);
1053         }
1054 }
1055
1056 static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
1057         .dpms = radeon_crtc_dpms,
1058         .mode_fixup = radeon_crtc_mode_fixup,
1059         .mode_set = radeon_crtc_mode_set,
1060         .mode_set_base = radeon_crtc_set_base,
1061         .mode_set_base_atomic = radeon_crtc_set_base_atomic,
1062         .prepare = radeon_crtc_prepare,
1063         .commit = radeon_crtc_commit,
1064         .load_lut = radeon_crtc_load_lut,
1065 };
1066
1067
1068 void radeon_legacy_init_crtc(struct drm_device *dev,
1069                                struct radeon_crtc *radeon_crtc)
1070 {
1071         if (radeon_crtc->crtc_id == 1)
1072                 radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP;
1073         drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs);
1074 }