2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
26 #include <linux/export.h>
29 #include "radeon_drm.h"
37 bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool requires_extended_probe)
42 struct i2c_msg msgs[] = {
57 /* Read 8 bytes from i2c for extended probe of EDID header */
58 if (requires_extended_probe)
61 /* on hw with routers, select right port */
62 if (radeon_connector->router.ddc_valid)
63 radeon_router_select_ddc_port(radeon_connector);
65 ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2);
67 /* Couldn't find an accessible DDC on this connector */
69 if (requires_extended_probe) {
70 /* Probe also for valid EDID header
71 * EDID header starts with:
72 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
73 * Only the first 6 bytes must be valid as
74 * drm_edid_block_valid() can fix the last 2 bytes */
75 if (drm_edid_header_is_valid(buf) < 6) {
76 /* Couldn't find an accessible EDID on this
86 static int pre_xfer(struct i2c_adapter *i2c_adap)
88 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
89 struct radeon_device *rdev = i2c->dev->dev_private;
90 struct radeon_i2c_bus_rec *rec = &i2c->rec;
93 /* RV410 appears to have a bug where the hw i2c in reset
94 * holds the i2c port in a bad state - switch hw i2c away before
95 * doing DDC - do this for all r200s/r300s/r400s for safety sake
97 if (rec->hw_capable) {
98 if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) {
101 if (rdev->family >= CHIP_RV350)
102 reg = RADEON_GPIO_MONID;
103 else if ((rdev->family == CHIP_R300) ||
104 (rdev->family == CHIP_R350))
105 reg = RADEON_GPIO_DVI_DDC;
107 reg = RADEON_GPIO_CRT2_DDC;
109 mutex_lock(&rdev->dc_hw_i2c_mutex);
110 if (rec->a_clk_reg == reg) {
111 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
112 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1)));
114 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
115 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3)));
117 mutex_unlock(&rdev->dc_hw_i2c_mutex);
121 /* switch the pads to ddc mode */
122 if (ASIC_IS_DCE3(rdev) && rec->hw_capable) {
123 temp = RREG32(rec->mask_clk_reg);
125 WREG32(rec->mask_clk_reg, temp);
128 /* clear the output pin values */
129 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
130 WREG32(rec->a_clk_reg, temp);
132 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;
133 WREG32(rec->a_data_reg, temp);
135 /* set the pins to input */
136 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
137 WREG32(rec->en_clk_reg, temp);
139 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
140 WREG32(rec->en_data_reg, temp);
142 /* mask the gpio pins for software use */
143 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask;
144 WREG32(rec->mask_clk_reg, temp);
145 temp = RREG32(rec->mask_clk_reg);
147 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask;
148 WREG32(rec->mask_data_reg, temp);
149 temp = RREG32(rec->mask_data_reg);
154 static void post_xfer(struct i2c_adapter *i2c_adap)
156 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
157 struct radeon_device *rdev = i2c->dev->dev_private;
158 struct radeon_i2c_bus_rec *rec = &i2c->rec;
161 /* unmask the gpio pins for software use */
162 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask;
163 WREG32(rec->mask_clk_reg, temp);
164 temp = RREG32(rec->mask_clk_reg);
166 temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask;
167 WREG32(rec->mask_data_reg, temp);
168 temp = RREG32(rec->mask_data_reg);
171 static int get_clock(void *i2c_priv)
173 struct radeon_i2c_chan *i2c = i2c_priv;
174 struct radeon_device *rdev = i2c->dev->dev_private;
175 struct radeon_i2c_bus_rec *rec = &i2c->rec;
178 /* read the value off the pin */
179 val = RREG32(rec->y_clk_reg);
180 val &= rec->y_clk_mask;
186 static int get_data(void *i2c_priv)
188 struct radeon_i2c_chan *i2c = i2c_priv;
189 struct radeon_device *rdev = i2c->dev->dev_private;
190 struct radeon_i2c_bus_rec *rec = &i2c->rec;
193 /* read the value off the pin */
194 val = RREG32(rec->y_data_reg);
195 val &= rec->y_data_mask;
200 static void set_clock(void *i2c_priv, int clock)
202 struct radeon_i2c_chan *i2c = i2c_priv;
203 struct radeon_device *rdev = i2c->dev->dev_private;
204 struct radeon_i2c_bus_rec *rec = &i2c->rec;
207 /* set pin direction */
208 val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
209 val |= clock ? 0 : rec->en_clk_mask;
210 WREG32(rec->en_clk_reg, val);
213 static void set_data(void *i2c_priv, int data)
215 struct radeon_i2c_chan *i2c = i2c_priv;
216 struct radeon_device *rdev = i2c->dev->dev_private;
217 struct radeon_i2c_bus_rec *rec = &i2c->rec;
220 /* set pin direction */
221 val = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
222 val |= data ? 0 : rec->en_data_mask;
223 WREG32(rec->en_data_reg, val);
228 static u32 radeon_get_i2c_prescale(struct radeon_device *rdev)
230 u32 sclk = rdev->pm.current_sclk;
236 switch (rdev->family) {
250 nm = (sclk * 10) / (i2c_clock * 4);
251 for (loop = 1; loop < 255; loop++) {
252 if ((nm / loop) < loop)
257 prescale = m | (n << 8);
265 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
279 if (rdev->family == CHIP_R520)
280 prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock));
282 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
308 DRM_ERROR("i2c: unhandled radeon chip\n");
315 /* hw i2c engine for r1xx-4xx hardware
316 * hw can buffer up to 15 bytes
318 static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
319 struct i2c_msg *msgs, int num)
321 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
322 struct radeon_device *rdev = i2c->dev->dev_private;
323 struct radeon_i2c_bus_rec *rec = &i2c->rec;
325 int i, j, k, ret = num;
327 u32 i2c_cntl_0, i2c_cntl_1, i2c_data;
330 mutex_lock(&rdev->dc_hw_i2c_mutex);
331 /* take the pm lock since we need a constant sclk */
332 mutex_lock(&rdev->pm.mutex);
334 prescale = radeon_get_i2c_prescale(rdev);
336 reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) |
337 RADEON_I2C_DRIVE_EN |
342 if (rdev->is_atom_bios) {
343 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
344 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
348 i2c_cntl_0 = RADEON_I2C_CNTL_0;
349 i2c_cntl_1 = RADEON_I2C_CNTL_1;
350 i2c_data = RADEON_I2C_DATA;
352 i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0;
353 i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1;
354 i2c_data = RADEON_DVI_I2C_DATA;
356 switch (rdev->family) {
363 switch (rec->mask_clk_reg) {
364 case RADEON_GPIO_DVI_DDC:
365 /* no gpio select bit */
368 DRM_ERROR("gpio not supported with hw i2c\n");
374 /* only bit 4 on r200 */
375 switch (rec->mask_clk_reg) {
376 case RADEON_GPIO_DVI_DDC:
377 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
379 case RADEON_GPIO_MONID:
380 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
383 DRM_ERROR("gpio not supported with hw i2c\n");
391 switch (rec->mask_clk_reg) {
392 case RADEON_GPIO_DVI_DDC:
393 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
395 case RADEON_GPIO_VGA_DDC:
396 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
398 case RADEON_GPIO_CRT2_DDC:
399 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
402 DRM_ERROR("gpio not supported with hw i2c\n");
409 /* only bit 4 on r300/r350 */
410 switch (rec->mask_clk_reg) {
411 case RADEON_GPIO_VGA_DDC:
412 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
414 case RADEON_GPIO_DVI_DDC:
415 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
418 DRM_ERROR("gpio not supported with hw i2c\n");
431 switch (rec->mask_clk_reg) {
432 case RADEON_GPIO_VGA_DDC:
433 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
435 case RADEON_GPIO_DVI_DDC:
436 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
438 case RADEON_GPIO_MONID:
439 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
442 DRM_ERROR("gpio not supported with hw i2c\n");
448 DRM_ERROR("unsupported asic\n");
455 /* check for bus probe */
457 if ((num == 1) && (p->len == 0)) {
458 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
461 RADEON_I2C_SOFT_RST));
462 WREG32(i2c_data, (p->addr << 1) & 0xff);
464 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
465 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
467 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
468 WREG32(i2c_cntl_0, reg);
469 for (k = 0; k < 32; k++) {
471 tmp = RREG32(i2c_cntl_0);
472 if (tmp & RADEON_I2C_GO)
474 tmp = RREG32(i2c_cntl_0);
475 if (tmp & RADEON_I2C_DONE)
478 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
479 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
487 for (i = 0; i < num; i++) {
489 for (j = 0; j < p->len; j++) {
490 if (p->flags & I2C_M_RD) {
491 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
494 RADEON_I2C_SOFT_RST));
495 WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1);
496 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
497 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
499 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
500 WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE);
501 for (k = 0; k < 32; k++) {
503 tmp = RREG32(i2c_cntl_0);
504 if (tmp & RADEON_I2C_GO)
506 tmp = RREG32(i2c_cntl_0);
507 if (tmp & RADEON_I2C_DONE)
510 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
511 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
516 p->buf[j] = RREG32(i2c_data) & 0xff;
518 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
521 RADEON_I2C_SOFT_RST));
522 WREG32(i2c_data, (p->addr << 1) & 0xff);
523 WREG32(i2c_data, p->buf[j]);
524 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
525 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
527 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
528 WREG32(i2c_cntl_0, reg);
529 for (k = 0; k < 32; k++) {
531 tmp = RREG32(i2c_cntl_0);
532 if (tmp & RADEON_I2C_GO)
534 tmp = RREG32(i2c_cntl_0);
535 if (tmp & RADEON_I2C_DONE)
538 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
539 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
549 WREG32(i2c_cntl_0, 0);
550 WREG32(i2c_cntl_1, 0);
551 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
554 RADEON_I2C_SOFT_RST));
556 if (rdev->is_atom_bios) {
557 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
558 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
559 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
562 mutex_unlock(&rdev->pm.mutex);
563 mutex_unlock(&rdev->dc_hw_i2c_mutex);
568 /* hw i2c engine for r5xx hardware
569 * hw can buffer up to 15 bytes
571 static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
572 struct i2c_msg *msgs, int num)
574 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
575 struct radeon_device *rdev = i2c->dev->dev_private;
576 struct radeon_i2c_bus_rec *rec = &i2c->rec;
578 int i, j, remaining, current_count, buffer_offset, ret = num;
583 mutex_lock(&rdev->dc_hw_i2c_mutex);
584 /* take the pm lock since we need a constant sclk */
585 mutex_lock(&rdev->pm.mutex);
587 prescale = radeon_get_i2c_prescale(rdev);
589 /* clear gpio mask bits */
590 tmp = RREG32(rec->mask_clk_reg);
591 tmp &= ~rec->mask_clk_mask;
592 WREG32(rec->mask_clk_reg, tmp);
593 tmp = RREG32(rec->mask_clk_reg);
595 tmp = RREG32(rec->mask_data_reg);
596 tmp &= ~rec->mask_data_mask;
597 WREG32(rec->mask_data_reg, tmp);
598 tmp = RREG32(rec->mask_data_reg);
600 /* clear pin values */
601 tmp = RREG32(rec->a_clk_reg);
602 tmp &= ~rec->a_clk_mask;
603 WREG32(rec->a_clk_reg, tmp);
604 tmp = RREG32(rec->a_clk_reg);
606 tmp = RREG32(rec->a_data_reg);
607 tmp &= ~rec->a_data_mask;
608 WREG32(rec->a_data_reg, tmp);
609 tmp = RREG32(rec->a_data_reg);
611 /* set the pins to input */
612 tmp = RREG32(rec->en_clk_reg);
613 tmp &= ~rec->en_clk_mask;
614 WREG32(rec->en_clk_reg, tmp);
615 tmp = RREG32(rec->en_clk_reg);
617 tmp = RREG32(rec->en_data_reg);
618 tmp &= ~rec->en_data_mask;
619 WREG32(rec->en_data_reg, tmp);
620 tmp = RREG32(rec->en_data_reg);
623 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
624 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
625 saved1 = RREG32(AVIVO_DC_I2C_CONTROL1);
626 saved2 = RREG32(0x494);
627 WREG32(0x494, saved2 | 0x1);
629 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C);
630 for (i = 0; i < 50; i++) {
632 if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C)
636 DRM_ERROR("failed to get i2c bus\n");
641 reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN;
642 switch (rec->mask_clk_reg) {
643 case AVIVO_DC_GPIO_DDC1_MASK:
644 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1);
646 case AVIVO_DC_GPIO_DDC2_MASK:
647 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2);
649 case AVIVO_DC_GPIO_DDC3_MASK:
650 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3);
653 DRM_ERROR("gpio not supported with hw i2c\n");
658 /* check for bus probe */
660 if ((num == 1) && (p->len == 0)) {
661 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
664 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
666 WREG32(AVIVO_DC_I2C_RESET, 0);
668 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
669 WREG32(AVIVO_DC_I2C_DATA, 0);
671 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
672 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
673 AVIVO_DC_I2C_DATA_COUNT(1) |
675 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
676 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
677 for (j = 0; j < 200; j++) {
679 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
680 if (tmp & AVIVO_DC_I2C_GO)
682 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
683 if (tmp & AVIVO_DC_I2C_DONE)
686 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
687 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
695 for (i = 0; i < num; i++) {
699 if (p->flags & I2C_M_RD) {
704 current_count = remaining;
705 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
708 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
710 WREG32(AVIVO_DC_I2C_RESET, 0);
712 WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1);
713 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
714 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
715 AVIVO_DC_I2C_DATA_COUNT(current_count) |
717 WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE);
718 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
719 for (j = 0; j < 200; j++) {
721 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
722 if (tmp & AVIVO_DC_I2C_GO)
724 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
725 if (tmp & AVIVO_DC_I2C_DONE)
728 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
729 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
734 for (j = 0; j < current_count; j++)
735 p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff;
736 remaining -= current_count;
737 buffer_offset += current_count;
744 current_count = remaining;
745 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
748 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
750 WREG32(AVIVO_DC_I2C_RESET, 0);
752 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
753 for (j = 0; j < current_count; j++)
754 WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]);
756 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
757 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
758 AVIVO_DC_I2C_DATA_COUNT(current_count) |
760 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
761 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
762 for (j = 0; j < 200; j++) {
764 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
765 if (tmp & AVIVO_DC_I2C_GO)
767 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
768 if (tmp & AVIVO_DC_I2C_DONE)
771 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
772 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
777 remaining -= current_count;
778 buffer_offset += current_count;
784 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
787 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
789 WREG32(AVIVO_DC_I2C_RESET, 0);
791 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C);
792 WREG32(AVIVO_DC_I2C_CONTROL1, saved1);
793 WREG32(0x494, saved2);
794 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
795 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
796 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
798 mutex_unlock(&rdev->pm.mutex);
799 mutex_unlock(&rdev->dc_hw_i2c_mutex);
804 static int radeon_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
805 struct i2c_msg *msgs, int num)
807 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
808 struct radeon_device *rdev = i2c->dev->dev_private;
809 struct radeon_i2c_bus_rec *rec = &i2c->rec;
812 switch (rdev->family) {
831 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
836 /* XXX fill in hw i2c implementation */
845 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
847 ret = r500_hw_i2c_xfer(i2c_adap, msgs, num);
853 /* XXX fill in hw i2c implementation */
863 /* XXX fill in hw i2c implementation */
870 /* XXX fill in hw i2c implementation */
873 DRM_ERROR("i2c: unhandled radeon chip\n");
881 static u32 radeon_hw_i2c_func(struct i2c_adapter *adap)
883 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
886 static const struct i2c_algorithm radeon_i2c_algo = {
887 .master_xfer = radeon_hw_i2c_xfer,
888 .functionality = radeon_hw_i2c_func,
891 struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
892 struct radeon_i2c_bus_rec *rec,
895 struct radeon_device *rdev = dev->dev_private;
896 struct radeon_i2c_chan *i2c;
899 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
904 i2c->adapter.owner = THIS_MODULE;
905 i2c->adapter.class = I2C_CLASS_DDC;
907 i2c_set_adapdata(&i2c->adapter, i2c);
911 ((rdev->family <= CHIP_RS480) ||
912 ((rdev->family >= CHIP_RV515) && (rdev->family <= CHIP_R580))))) {
913 /* set the radeon hw i2c adapter */
914 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
915 "Radeon i2c hw bus %s", name);
916 i2c->adapter.algo = &radeon_i2c_algo;
917 ret = i2c_add_adapter(&i2c->adapter);
919 DRM_ERROR("Failed to register hw i2c %s\n", name);
923 /* set the radeon bit adapter */
924 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
925 "Radeon i2c bit bus %s", name);
926 i2c->adapter.algo_data = &i2c->algo.bit;
927 i2c->algo.bit.pre_xfer = pre_xfer;
928 i2c->algo.bit.post_xfer = post_xfer;
929 i2c->algo.bit.setsda = set_data;
930 i2c->algo.bit.setscl = set_clock;
931 i2c->algo.bit.getsda = get_data;
932 i2c->algo.bit.getscl = get_clock;
933 i2c->algo.bit.udelay = 20;
934 /* vesa says 2.2 ms is enough, 1 jiffy doesn't seem to always
935 * make this, 2 jiffies is a lot more reliable */
936 i2c->algo.bit.timeout = 2;
937 i2c->algo.bit.data = i2c;
938 ret = i2c_bit_add_bus(&i2c->adapter);
940 DRM_ERROR("Failed to register bit i2c %s\n", name);
952 struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
953 struct radeon_i2c_bus_rec *rec,
956 struct radeon_i2c_chan *i2c;
959 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
964 i2c->adapter.owner = THIS_MODULE;
965 i2c->adapter.class = I2C_CLASS_DDC;
967 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
968 "Radeon aux bus %s", name);
969 i2c_set_adapdata(&i2c->adapter, i2c);
970 i2c->adapter.algo_data = &i2c->algo.dp;
971 i2c->algo.dp.aux_ch = radeon_dp_i2c_aux_ch;
972 i2c->algo.dp.address = 0;
973 ret = i2c_dp_aux_add_bus(&i2c->adapter);
975 DRM_INFO("Failed to register i2c %s\n", name);
986 void radeon_i2c_destroy(struct radeon_i2c_chan *i2c)
990 i2c_del_adapter(&i2c->adapter);
994 /* Add the default buses */
995 void radeon_i2c_init(struct radeon_device *rdev)
997 if (rdev->is_atom_bios)
998 radeon_atombios_i2c_init(rdev);
1000 radeon_combios_i2c_init(rdev);
1003 /* remove all the buses */
1004 void radeon_i2c_fini(struct radeon_device *rdev)
1008 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1009 if (rdev->i2c_bus[i]) {
1010 radeon_i2c_destroy(rdev->i2c_bus[i]);
1011 rdev->i2c_bus[i] = NULL;
1016 /* Add additional buses */
1017 void radeon_i2c_add(struct radeon_device *rdev,
1018 struct radeon_i2c_bus_rec *rec,
1021 struct drm_device *dev = rdev->ddev;
1024 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1025 if (!rdev->i2c_bus[i]) {
1026 rdev->i2c_bus[i] = radeon_i2c_create(dev, rec, name);
1032 /* looks up bus based on id */
1033 struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
1034 struct radeon_i2c_bus_rec *i2c_bus)
1038 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1039 if (rdev->i2c_bus[i] &&
1040 (rdev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) {
1041 return rdev->i2c_bus[i];
1047 struct drm_encoder *radeon_best_encoder(struct drm_connector *connector)
1052 void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
1059 struct i2c_msg msgs[] = {
1077 if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) {
1079 DRM_DEBUG("val = 0x%02x\n", *val);
1081 DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n",
1086 void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus,
1092 struct i2c_msg msg = {
1102 if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1)
1103 DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n",
1107 /* ddc router switching */
1108 void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector)
1112 if (!radeon_connector->router.ddc_valid)
1115 if (!radeon_connector->router_bus)
1118 radeon_i2c_get_byte(radeon_connector->router_bus,
1119 radeon_connector->router.i2c_addr,
1121 val &= ~radeon_connector->router.ddc_mux_control_pin;
1122 radeon_i2c_put_byte(radeon_connector->router_bus,
1123 radeon_connector->router.i2c_addr,
1125 radeon_i2c_get_byte(radeon_connector->router_bus,
1126 radeon_connector->router.i2c_addr,
1128 val &= ~radeon_connector->router.ddc_mux_control_pin;
1129 val |= radeon_connector->router.ddc_mux_state;
1130 radeon_i2c_put_byte(radeon_connector->router_bus,
1131 radeon_connector->router.i2c_addr,
1135 /* clock/data router switching */
1136 void radeon_router_select_cd_port(struct radeon_connector *radeon_connector)
1140 if (!radeon_connector->router.cd_valid)
1143 if (!radeon_connector->router_bus)
1146 radeon_i2c_get_byte(radeon_connector->router_bus,
1147 radeon_connector->router.i2c_addr,
1149 val &= ~radeon_connector->router.cd_mux_control_pin;
1150 radeon_i2c_put_byte(radeon_connector->router_bus,
1151 radeon_connector->router.i2c_addr,
1153 radeon_i2c_get_byte(radeon_connector->router_bus,
1154 radeon_connector->router.i2c_addr,
1156 val &= ~radeon_connector->router.cd_mux_control_pin;
1157 val |= radeon_connector->router.cd_mux_state;
1158 radeon_i2c_put_byte(radeon_connector->router_bus,
1159 radeon_connector->router.i2c_addr,