2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "drm_crtc_helper.h"
28 #include "radeon_drm.h"
32 extern int atom_debug;
34 /* evil but including atombios.h is much worse */
35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
36 struct drm_display_mode *mode);
38 static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
40 struct drm_device *dev = encoder->dev;
41 struct radeon_device *rdev = dev->dev_private;
42 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
43 struct drm_encoder *clone_encoder;
44 uint32_t index_mask = 0;
47 /* DIG routing gets problematic */
48 if (rdev->family >= CHIP_R600)
50 /* LVDS/TV are too wacky */
51 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
53 /* DVO requires 2x ppll clocks depending on tmds chip */
54 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
58 list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
59 struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
62 if (clone_encoder == encoder)
64 if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT))
66 if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT)
69 index_mask |= (1 << count);
74 void radeon_setup_encoder_clones(struct drm_device *dev)
76 struct drm_encoder *encoder;
78 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
79 encoder->possible_clones = radeon_encoder_clones(encoder);
84 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
86 struct radeon_device *rdev = dev->dev_private;
89 switch (supported_device) {
90 case ATOM_DEVICE_CRT1_SUPPORT:
91 case ATOM_DEVICE_TV1_SUPPORT:
92 case ATOM_DEVICE_TV2_SUPPORT:
93 case ATOM_DEVICE_CRT2_SUPPORT:
94 case ATOM_DEVICE_CV_SUPPORT:
97 if ((rdev->family == CHIP_RS300) ||
98 (rdev->family == CHIP_RS400) ||
99 (rdev->family == CHIP_RS480))
100 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
101 else if (ASIC_IS_AVIVO(rdev))
102 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1;
104 ret = ENCODER_OBJECT_ID_INTERNAL_DAC1;
107 if (ASIC_IS_AVIVO(rdev))
108 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2;
110 /*if (rdev->family == CHIP_R200)
111 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
113 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
116 case 3: /* external dac */
117 if (ASIC_IS_AVIVO(rdev))
118 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
120 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
124 case ATOM_DEVICE_LCD1_SUPPORT:
125 if (ASIC_IS_AVIVO(rdev))
126 ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
128 ret = ENCODER_OBJECT_ID_INTERNAL_LVDS;
130 case ATOM_DEVICE_DFP1_SUPPORT:
131 if ((rdev->family == CHIP_RS300) ||
132 (rdev->family == CHIP_RS400) ||
133 (rdev->family == CHIP_RS480))
134 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
135 else if (ASIC_IS_AVIVO(rdev))
136 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1;
138 ret = ENCODER_OBJECT_ID_INTERNAL_TMDS1;
140 case ATOM_DEVICE_LCD2_SUPPORT:
141 case ATOM_DEVICE_DFP2_SUPPORT:
142 if ((rdev->family == CHIP_RS600) ||
143 (rdev->family == CHIP_RS690) ||
144 (rdev->family == CHIP_RS740))
145 ret = ENCODER_OBJECT_ID_INTERNAL_DDI;
146 else if (ASIC_IS_AVIVO(rdev))
147 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
149 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
151 case ATOM_DEVICE_DFP3_SUPPORT:
152 ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
159 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
161 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
162 switch (radeon_encoder->encoder_id) {
163 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
164 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
165 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
166 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
167 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
168 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
169 case ENCODER_OBJECT_ID_INTERNAL_DDI:
170 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
171 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
172 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
173 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
180 radeon_link_encoder_connector(struct drm_device *dev)
182 struct drm_connector *connector;
183 struct radeon_connector *radeon_connector;
184 struct drm_encoder *encoder;
185 struct radeon_encoder *radeon_encoder;
187 /* walk the list and link encoders to connectors */
188 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
189 radeon_connector = to_radeon_connector(connector);
190 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
191 radeon_encoder = to_radeon_encoder(encoder);
192 if (radeon_encoder->devices & radeon_connector->devices)
193 drm_mode_connector_attach_encoder(connector, encoder);
198 void radeon_encoder_set_active_device(struct drm_encoder *encoder)
200 struct drm_device *dev = encoder->dev;
201 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
202 struct drm_connector *connector;
204 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
205 if (connector->encoder == encoder) {
206 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
207 radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
208 DRM_DEBUG("setting active device to %08x from %08x %08x for encoder %d\n",
209 radeon_encoder->active_device, radeon_encoder->devices,
210 radeon_connector->devices, encoder->encoder_type);
215 static struct drm_connector *
216 radeon_get_connector_for_encoder(struct drm_encoder *encoder)
218 struct drm_device *dev = encoder->dev;
219 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
220 struct drm_connector *connector;
221 struct radeon_connector *radeon_connector;
223 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
224 radeon_connector = to_radeon_connector(connector);
225 if (radeon_encoder->active_device & radeon_connector->devices)
231 static struct radeon_connector_atom_dig *
232 radeon_get_atom_connector_priv_from_encoder(struct drm_encoder *encoder)
234 struct drm_device *dev = encoder->dev;
235 struct radeon_device *rdev = dev->dev_private;
236 struct drm_connector *connector;
237 struct radeon_connector *radeon_connector;
238 struct radeon_connector_atom_dig *dig_connector;
240 if (!rdev->is_atom_bios)
243 connector = radeon_get_connector_for_encoder(encoder);
247 radeon_connector = to_radeon_connector(connector);
249 if (!radeon_connector->con_priv)
252 dig_connector = radeon_connector->con_priv;
254 return dig_connector;
257 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
258 struct drm_display_mode *mode,
259 struct drm_display_mode *adjusted_mode)
261 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
262 struct drm_device *dev = encoder->dev;
263 struct radeon_device *rdev = dev->dev_private;
265 /* adjust pm to upcoming mode change */
266 radeon_pm_compute_clocks(rdev);
268 /* set the active encoder to connector routing */
269 radeon_encoder_set_active_device(encoder);
270 drm_mode_set_crtcinfo(adjusted_mode, 0);
273 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
274 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
275 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
277 /* get the native mode for LVDS */
278 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
279 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
280 int mode_id = adjusted_mode->base.id;
281 *adjusted_mode = *native_mode;
282 if (!ASIC_IS_AVIVO(rdev)) {
283 adjusted_mode->hdisplay = mode->hdisplay;
284 adjusted_mode->vdisplay = mode->vdisplay;
285 adjusted_mode->crtc_hdisplay = mode->hdisplay;
286 adjusted_mode->crtc_vdisplay = mode->vdisplay;
288 adjusted_mode->base.id = mode_id;
291 /* get the native mode for TV */
292 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
293 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
295 if (tv_dac->tv_std == TV_STD_NTSC ||
296 tv_dac->tv_std == TV_STD_NTSC_J ||
297 tv_dac->tv_std == TV_STD_PAL_M)
298 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
300 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
304 if (ASIC_IS_DCE3(rdev) &&
305 (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT))) {
306 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
307 radeon_dp_set_link_config(connector, mode);
314 atombios_dac_setup(struct drm_encoder *encoder, int action)
316 struct drm_device *dev = encoder->dev;
317 struct radeon_device *rdev = dev->dev_private;
318 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
319 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
321 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
323 memset(&args, 0, sizeof(args));
325 switch (radeon_encoder->encoder_id) {
326 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
327 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
328 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
330 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
331 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
332 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
336 args.ucAction = action;
338 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
339 args.ucDacStandard = ATOM_DAC1_PS2;
340 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
341 args.ucDacStandard = ATOM_DAC1_CV;
343 switch (dac_info->tv_std) {
346 case TV_STD_SCART_PAL:
349 args.ucDacStandard = ATOM_DAC1_PAL;
355 args.ucDacStandard = ATOM_DAC1_NTSC;
359 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
361 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
366 atombios_tv_setup(struct drm_encoder *encoder, int action)
368 struct drm_device *dev = encoder->dev;
369 struct radeon_device *rdev = dev->dev_private;
370 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
371 TV_ENCODER_CONTROL_PS_ALLOCATION args;
373 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
375 memset(&args, 0, sizeof(args));
377 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
379 args.sTVEncoder.ucAction = action;
381 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
382 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
384 switch (dac_info->tv_std) {
386 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
389 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
392 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
395 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
398 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
400 case TV_STD_SCART_PAL:
401 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
404 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
407 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
410 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
415 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
417 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
422 atombios_external_tmds_setup(struct drm_encoder *encoder, int action)
424 struct drm_device *dev = encoder->dev;
425 struct radeon_device *rdev = dev->dev_private;
426 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
427 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args;
430 memset(&args, 0, sizeof(args));
432 index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
434 args.sXTmdsEncoder.ucEnable = action;
436 if (radeon_encoder->pixel_clock > 165000)
437 args.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL;
439 /*if (pScrn->rgbBits == 8)*/
440 args.sXTmdsEncoder.ucMisc |= (1 << 1);
442 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
447 atombios_ddia_setup(struct drm_encoder *encoder, int action)
449 struct drm_device *dev = encoder->dev;
450 struct radeon_device *rdev = dev->dev_private;
451 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
452 DVO_ENCODER_CONTROL_PS_ALLOCATION args;
455 memset(&args, 0, sizeof(args));
457 index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
459 args.sDVOEncoder.ucAction = action;
460 args.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
462 if (radeon_encoder->pixel_clock > 165000)
463 args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL;
465 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
469 union lvds_encoder_control {
470 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
471 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
475 atombios_digital_setup(struct drm_encoder *encoder, int action)
477 struct drm_device *dev = encoder->dev;
478 struct radeon_device *rdev = dev->dev_private;
479 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
480 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
481 struct radeon_connector_atom_dig *dig_connector =
482 radeon_get_atom_connector_priv_from_encoder(encoder);
483 union lvds_encoder_control args;
485 int hdmi_detected = 0;
488 if (!dig || !dig_connector)
491 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
494 memset(&args, 0, sizeof(args));
496 switch (radeon_encoder->encoder_id) {
497 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
498 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
500 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
501 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
502 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
504 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
505 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
506 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
508 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
512 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
521 args.v1.ucAction = action;
523 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
524 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
525 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
526 if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
527 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
528 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
529 args.v1.ucMisc |= (1 << 1);
531 if (dig_connector->linkb)
532 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
533 if (radeon_encoder->pixel_clock > 165000)
534 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
535 /*if (pScrn->rgbBits == 8) */
536 args.v1.ucMisc |= (1 << 1);
542 args.v2.ucAction = action;
544 if (dig->coherent_mode)
545 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
548 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
549 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
550 args.v2.ucTruncate = 0;
551 args.v2.ucSpatial = 0;
552 args.v2.ucTemporal = 0;
554 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
555 if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
556 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
557 if (dig->lvds_misc & ATOM_PANEL_MISC_SPATIAL) {
558 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
559 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
560 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
562 if (dig->lvds_misc & ATOM_PANEL_MISC_TEMPORAL) {
563 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
564 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
565 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
566 if (((dig->lvds_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
567 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
570 if (dig_connector->linkb)
571 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
572 if (radeon_encoder->pixel_clock > 165000)
573 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
577 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
582 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
586 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
590 atombios_get_encoder_mode(struct drm_encoder *encoder)
592 struct drm_connector *connector;
593 struct radeon_connector *radeon_connector;
594 struct radeon_connector_atom_dig *dig_connector;
596 connector = radeon_get_connector_for_encoder(encoder);
600 radeon_connector = to_radeon_connector(connector);
602 switch (connector->connector_type) {
603 case DRM_MODE_CONNECTOR_DVII:
604 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
605 if (drm_detect_hdmi_monitor(radeon_connector->edid))
606 return ATOM_ENCODER_MODE_HDMI;
607 else if (radeon_connector->use_digital)
608 return ATOM_ENCODER_MODE_DVI;
610 return ATOM_ENCODER_MODE_CRT;
612 case DRM_MODE_CONNECTOR_DVID:
613 case DRM_MODE_CONNECTOR_HDMIA:
615 if (drm_detect_hdmi_monitor(radeon_connector->edid))
616 return ATOM_ENCODER_MODE_HDMI;
618 return ATOM_ENCODER_MODE_DVI;
620 case DRM_MODE_CONNECTOR_LVDS:
621 return ATOM_ENCODER_MODE_LVDS;
623 case DRM_MODE_CONNECTOR_DisplayPort:
624 case DRM_MODE_CONNECTOR_eDP:
625 dig_connector = radeon_connector->con_priv;
626 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
627 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
628 return ATOM_ENCODER_MODE_DP;
629 else if (drm_detect_hdmi_monitor(radeon_connector->edid))
630 return ATOM_ENCODER_MODE_HDMI;
632 return ATOM_ENCODER_MODE_DVI;
634 case DRM_MODE_CONNECTOR_DVIA:
635 case DRM_MODE_CONNECTOR_VGA:
636 return ATOM_ENCODER_MODE_CRT;
638 case DRM_MODE_CONNECTOR_Composite:
639 case DRM_MODE_CONNECTOR_SVIDEO:
640 case DRM_MODE_CONNECTOR_9PinDIN:
642 return ATOM_ENCODER_MODE_TV;
643 /*return ATOM_ENCODER_MODE_CV;*/
649 * DIG Encoder/Transmitter Setup
652 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
653 * Supports up to 3 digital outputs
654 * - 2 DIG encoder blocks.
655 * DIG1 can drive UNIPHY link A or link B
656 * DIG2 can drive UNIPHY link B or LVTMA
659 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
660 * Supports up to 5 digital outputs
661 * - 2 DIG encoder blocks.
662 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
665 * - 3 DIG transmitter blocks UNPHY0/1/2 (links A and B).
666 * Supports up to 6 digital outputs
667 * - 6 DIG encoder blocks.
668 * - DIG to PHY mapping is hardcoded
669 * DIG1 drives UNIPHY0 link A, A+B
670 * DIG2 drives UNIPHY0 link B
671 * DIG3 drives UNIPHY1 link A, A+B
672 * DIG4 drives UNIPHY1 link B
673 * DIG5 drives UNIPHY2 link A, A+B
674 * DIG6 drives UNIPHY2 link B
677 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
679 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
680 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
681 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
682 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
685 union dig_encoder_control {
686 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
687 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
688 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
692 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
694 struct drm_device *dev = encoder->dev;
695 struct radeon_device *rdev = dev->dev_private;
696 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
697 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
698 struct radeon_connector_atom_dig *dig_connector =
699 radeon_get_atom_connector_priv_from_encoder(encoder);
700 union dig_encoder_control args;
704 if (!dig || !dig_connector)
707 memset(&args, 0, sizeof(args));
709 if (ASIC_IS_DCE4(rdev))
710 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
712 if (dig->dig_encoder)
713 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
715 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
718 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
721 args.v1.ucAction = action;
722 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
723 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
725 if (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
726 if (dig_connector->dp_clock == 270000)
727 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
728 args.v1.ucLaneNum = dig_connector->dp_lane_count;
729 } else if (radeon_encoder->pixel_clock > 165000)
730 args.v1.ucLaneNum = 8;
732 args.v1.ucLaneNum = 4;
734 if (ASIC_IS_DCE4(rdev)) {
735 args.v3.acConfig.ucDigSel = dig->dig_encoder;
736 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
738 switch (radeon_encoder->encoder_id) {
739 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
740 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
742 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
743 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
744 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
746 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
747 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
750 if (dig_connector->linkb)
751 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
753 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
756 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
760 union dig_transmitter_control {
761 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
762 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
763 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
767 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
769 struct drm_device *dev = encoder->dev;
770 struct radeon_device *rdev = dev->dev_private;
771 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
772 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
773 struct radeon_connector_atom_dig *dig_connector =
774 radeon_get_atom_connector_priv_from_encoder(encoder);
775 struct drm_connector *connector;
776 struct radeon_connector *radeon_connector;
777 union dig_transmitter_control args;
783 if (!dig || !dig_connector)
786 connector = radeon_get_connector_for_encoder(encoder);
787 radeon_connector = to_radeon_connector(connector);
789 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP)
792 memset(&args, 0, sizeof(args));
794 if (ASIC_IS_DCE32(rdev) || ASIC_IS_DCE4(rdev))
795 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
797 switch (radeon_encoder->encoder_id) {
798 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
799 index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl);
801 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
802 index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl);
807 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
810 args.v1.ucAction = action;
811 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
812 args.v1.usInitInfo = radeon_connector->connector_object_id;
813 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
814 args.v1.asMode.ucLaneSel = lane_num;
815 args.v1.asMode.ucLaneSet = lane_set;
818 args.v1.usPixelClock =
819 cpu_to_le16(dig_connector->dp_clock / 10);
820 else if (radeon_encoder->pixel_clock > 165000)
821 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
823 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
825 if (ASIC_IS_DCE4(rdev)) {
827 args.v3.ucLaneNum = dig_connector->dp_lane_count;
828 else if (radeon_encoder->pixel_clock > 165000)
829 args.v3.ucLaneNum = 8;
831 args.v3.ucLaneNum = 4;
833 if (dig_connector->linkb) {
834 args.v3.acConfig.ucLinkSel = 1;
835 args.v3.acConfig.ucEncoderSel = 1;
838 /* Select the PLL for the PHY
839 * DP PHY should be clocked from external src if there is
843 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
844 pll_id = radeon_crtc->pll_id;
846 if (is_dp && rdev->clock.dp_extclk)
847 args.v3.acConfig.ucRefClkSource = 2; /* external src */
849 args.v3.acConfig.ucRefClkSource = pll_id;
851 switch (radeon_encoder->encoder_id) {
852 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
853 args.v3.acConfig.ucTransmitterSel = 0;
855 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
856 args.v3.acConfig.ucTransmitterSel = 1;
858 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
859 args.v3.acConfig.ucTransmitterSel = 2;
864 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
865 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
866 if (dig->coherent_mode)
867 args.v3.acConfig.fCoherentMode = 1;
869 } else if (ASIC_IS_DCE32(rdev)) {
870 args.v2.acConfig.ucEncoderSel = dig->dig_encoder;
871 if (dig_connector->linkb)
872 args.v2.acConfig.ucLinkSel = 1;
874 switch (radeon_encoder->encoder_id) {
875 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
876 args.v2.acConfig.ucTransmitterSel = 0;
878 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
879 args.v2.acConfig.ucTransmitterSel = 1;
881 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
882 args.v2.acConfig.ucTransmitterSel = 2;
887 args.v2.acConfig.fCoherentMode = 1;
888 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
889 if (dig->coherent_mode)
890 args.v2.acConfig.fCoherentMode = 1;
893 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
895 if (dig->dig_encoder)
896 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
898 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
900 if ((rdev->flags & RADEON_IS_IGP) &&
901 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
902 if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
903 if (dig_connector->igp_lane_info & 0x1)
904 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
905 else if (dig_connector->igp_lane_info & 0x2)
906 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
907 else if (dig_connector->igp_lane_info & 0x4)
908 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
909 else if (dig_connector->igp_lane_info & 0x8)
910 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
912 if (dig_connector->igp_lane_info & 0x3)
913 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
914 else if (dig_connector->igp_lane_info & 0xc)
915 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
919 if (dig_connector->linkb)
920 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
922 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
925 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
926 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
927 if (dig->coherent_mode)
928 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
929 if (radeon_encoder->pixel_clock > 165000)
930 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
934 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
938 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
940 struct drm_device *dev = encoder->dev;
941 struct radeon_device *rdev = dev->dev_private;
942 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
943 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
944 ENABLE_YUV_PS_ALLOCATION args;
945 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
948 memset(&args, 0, sizeof(args));
950 if (rdev->family >= CHIP_R600)
951 reg = R600_BIOS_3_SCRATCH;
953 reg = RADEON_BIOS_3_SCRATCH;
955 /* XXX: fix up scratch reg handling */
957 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
958 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
959 (radeon_crtc->crtc_id << 18)));
960 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
961 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
966 args.ucEnable = ATOM_ENABLE;
967 args.ucCRTC = radeon_crtc->crtc_id;
969 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
975 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
977 struct drm_device *dev = encoder->dev;
978 struct radeon_device *rdev = dev->dev_private;
979 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
980 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
984 memset(&args, 0, sizeof(args));
986 DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
987 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
988 radeon_encoder->active_device);
989 switch (radeon_encoder->encoder_id) {
990 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
991 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
992 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
994 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
995 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
996 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
997 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1000 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1001 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1002 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1003 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1005 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1006 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1008 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1009 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1010 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1012 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1014 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1015 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1016 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1017 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1018 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1019 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1021 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1023 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1024 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1025 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1026 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1027 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1028 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1030 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1036 case DRM_MODE_DPMS_ON:
1037 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1038 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1040 dp_link_train(encoder, connector);
1041 if (ASIC_IS_DCE4(rdev))
1042 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON);
1044 if (!ASIC_IS_DCE4(rdev))
1045 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1047 case DRM_MODE_DPMS_STANDBY:
1048 case DRM_MODE_DPMS_SUSPEND:
1049 case DRM_MODE_DPMS_OFF:
1050 if (!ASIC_IS_DCE4(rdev))
1051 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1052 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1053 if (ASIC_IS_DCE4(rdev))
1054 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF);
1060 case DRM_MODE_DPMS_ON:
1061 args.ucAction = ATOM_ENABLE;
1063 case DRM_MODE_DPMS_STANDBY:
1064 case DRM_MODE_DPMS_SUSPEND:
1065 case DRM_MODE_DPMS_OFF:
1066 args.ucAction = ATOM_DISABLE;
1069 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1071 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1073 /* adjust pm to dpms change */
1074 radeon_pm_compute_clocks(rdev);
1077 union crtc_source_param {
1078 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1079 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1083 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1085 struct drm_device *dev = encoder->dev;
1086 struct radeon_device *rdev = dev->dev_private;
1087 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1088 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1089 union crtc_source_param args;
1090 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1092 struct radeon_encoder_atom_dig *dig;
1094 memset(&args, 0, sizeof(args));
1096 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1104 if (ASIC_IS_AVIVO(rdev))
1105 args.v1.ucCRTC = radeon_crtc->crtc_id;
1107 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1108 args.v1.ucCRTC = radeon_crtc->crtc_id;
1110 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1113 switch (radeon_encoder->encoder_id) {
1114 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1115 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1116 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1118 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1119 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1120 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1121 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1123 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1125 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1126 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1127 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1128 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1130 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1131 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1132 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1133 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1134 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1135 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1137 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1139 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1140 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1141 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1142 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1143 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1144 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1146 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1151 args.v2.ucCRTC = radeon_crtc->crtc_id;
1152 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1153 switch (radeon_encoder->encoder_id) {
1154 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1155 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1156 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1157 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1158 dig = radeon_encoder->enc_priv;
1159 switch (dig->dig_encoder) {
1161 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1164 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1167 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1170 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1173 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1176 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1180 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1181 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1183 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1184 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1185 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1186 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1187 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1189 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1191 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1192 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1193 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1194 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1195 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1197 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1204 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1208 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1210 /* update scratch regs with new routing */
1211 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1215 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1216 struct drm_display_mode *mode)
1218 struct drm_device *dev = encoder->dev;
1219 struct radeon_device *rdev = dev->dev_private;
1220 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1221 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1223 /* Funky macbooks */
1224 if ((dev->pdev->device == 0x71C5) &&
1225 (dev->pdev->subsystem_vendor == 0x106b) &&
1226 (dev->pdev->subsystem_device == 0x0080)) {
1227 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1228 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1230 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1231 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1233 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1237 /* set scaler clears this on some chips */
1238 /* XXX check DCE4 */
1239 if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) {
1240 if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE))
1241 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1242 AVIVO_D1MODE_INTERLEAVE_EN);
1246 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1248 struct drm_device *dev = encoder->dev;
1249 struct radeon_device *rdev = dev->dev_private;
1250 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1251 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1252 struct drm_encoder *test_encoder;
1253 struct radeon_encoder_atom_dig *dig;
1254 uint32_t dig_enc_in_use = 0;
1256 if (ASIC_IS_DCE4(rdev)) {
1257 struct radeon_connector_atom_dig *dig_connector =
1258 radeon_get_atom_connector_priv_from_encoder(encoder);
1260 switch (radeon_encoder->encoder_id) {
1261 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1262 if (dig_connector->linkb)
1267 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1268 if (dig_connector->linkb)
1273 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1274 if (dig_connector->linkb)
1282 /* on DCE32 and encoder can driver any block so just crtc id */
1283 if (ASIC_IS_DCE32(rdev)) {
1284 return radeon_crtc->crtc_id;
1287 /* on DCE3 - LVTMA can only be driven by DIGB */
1288 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1289 struct radeon_encoder *radeon_test_encoder;
1291 if (encoder == test_encoder)
1294 if (!radeon_encoder_is_digital(test_encoder))
1297 radeon_test_encoder = to_radeon_encoder(test_encoder);
1298 dig = radeon_test_encoder->enc_priv;
1300 if (dig->dig_encoder >= 0)
1301 dig_enc_in_use |= (1 << dig->dig_encoder);
1304 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1305 if (dig_enc_in_use & 0x2)
1306 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1309 if (!(dig_enc_in_use & 1))
1315 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1316 struct drm_display_mode *mode,
1317 struct drm_display_mode *adjusted_mode)
1319 struct drm_device *dev = encoder->dev;
1320 struct radeon_device *rdev = dev->dev_private;
1321 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1323 radeon_encoder->pixel_clock = adjusted_mode->clock;
1325 if (ASIC_IS_AVIVO(rdev)) {
1326 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1327 atombios_yuv_setup(encoder, true);
1329 atombios_yuv_setup(encoder, false);
1332 switch (radeon_encoder->encoder_id) {
1333 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1334 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1335 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1336 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1337 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1339 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1340 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1341 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1342 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1343 if (ASIC_IS_DCE4(rdev)) {
1344 /* disable the transmitter */
1345 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1346 /* setup and enable the encoder */
1347 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP);
1349 /* init and enable the transmitter */
1350 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1351 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1353 /* disable the encoder and transmitter */
1354 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1355 atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1357 /* setup and enable the encoder and transmitter */
1358 atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
1359 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1360 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1361 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1364 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1365 atombios_ddia_setup(encoder, ATOM_ENABLE);
1367 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1368 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1369 atombios_external_tmds_setup(encoder, ATOM_ENABLE);
1371 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1372 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1373 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1374 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1375 atombios_dac_setup(encoder, ATOM_ENABLE);
1376 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1377 atombios_tv_setup(encoder, ATOM_ENABLE);
1380 atombios_apply_encoder_quirks(encoder, adjusted_mode);
1382 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1383 r600_hdmi_enable(encoder);
1384 r600_hdmi_setmode(encoder, adjusted_mode);
1389 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1391 struct drm_device *dev = encoder->dev;
1392 struct radeon_device *rdev = dev->dev_private;
1393 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1394 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1396 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1397 ATOM_DEVICE_CV_SUPPORT |
1398 ATOM_DEVICE_CRT_SUPPORT)) {
1399 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1400 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1403 memset(&args, 0, sizeof(args));
1405 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1408 args.sDacload.ucMisc = 0;
1410 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1411 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1412 args.sDacload.ucDacType = ATOM_DAC_A;
1414 args.sDacload.ucDacType = ATOM_DAC_B;
1416 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1417 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1418 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1419 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1420 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1421 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1423 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1424 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1425 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1427 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1430 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1437 static enum drm_connector_status
1438 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1440 struct drm_device *dev = encoder->dev;
1441 struct radeon_device *rdev = dev->dev_private;
1442 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1443 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1444 uint32_t bios_0_scratch;
1446 if (!atombios_dac_load_detect(encoder, connector)) {
1447 DRM_DEBUG("detect returned false \n");
1448 return connector_status_unknown;
1451 if (rdev->family >= CHIP_R600)
1452 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1454 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1456 DRM_DEBUG("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1457 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1458 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1459 return connector_status_connected;
1461 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1462 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1463 return connector_status_connected;
1465 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1466 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1467 return connector_status_connected;
1469 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1470 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1471 return connector_status_connected; /* CTV */
1472 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1473 return connector_status_connected; /* STV */
1475 return connector_status_disconnected;
1478 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1480 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1482 if (radeon_encoder->active_device &
1483 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) {
1484 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1486 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
1489 radeon_atom_output_lock(encoder, true);
1490 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1492 /* this is needed for the pll/ss setup to work correctly in some cases */
1493 atombios_set_encoder_crtc_source(encoder);
1496 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1498 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1499 radeon_atom_output_lock(encoder, false);
1502 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1504 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1505 struct radeon_encoder_atom_dig *dig;
1506 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1508 if (radeon_encoder_is_digital(encoder)) {
1509 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
1510 r600_hdmi_disable(encoder);
1511 dig = radeon_encoder->enc_priv;
1512 dig->dig_encoder = -1;
1514 radeon_encoder->active_device = 0;
1517 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
1518 .dpms = radeon_atom_encoder_dpms,
1519 .mode_fixup = radeon_atom_mode_fixup,
1520 .prepare = radeon_atom_encoder_prepare,
1521 .mode_set = radeon_atom_encoder_mode_set,
1522 .commit = radeon_atom_encoder_commit,
1523 .disable = radeon_atom_encoder_disable,
1524 /* no detect for TMDS/LVDS yet */
1527 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
1528 .dpms = radeon_atom_encoder_dpms,
1529 .mode_fixup = radeon_atom_mode_fixup,
1530 .prepare = radeon_atom_encoder_prepare,
1531 .mode_set = radeon_atom_encoder_mode_set,
1532 .commit = radeon_atom_encoder_commit,
1533 .detect = radeon_atom_dac_detect,
1536 void radeon_enc_destroy(struct drm_encoder *encoder)
1538 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1539 kfree(radeon_encoder->enc_priv);
1540 drm_encoder_cleanup(encoder);
1541 kfree(radeon_encoder);
1544 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
1545 .destroy = radeon_enc_destroy,
1548 struct radeon_encoder_atom_dac *
1549 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
1551 struct drm_device *dev = radeon_encoder->base.dev;
1552 struct radeon_device *rdev = dev->dev_private;
1553 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
1558 dac->tv_std = radeon_atombios_get_tv_info(rdev);
1562 struct radeon_encoder_atom_dig *
1563 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
1565 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1570 /* coherent mode by default */
1571 dig->coherent_mode = true;
1572 dig->dig_encoder = -1;
1578 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
1580 struct radeon_device *rdev = dev->dev_private;
1581 struct drm_encoder *encoder;
1582 struct radeon_encoder *radeon_encoder;
1584 /* see if we already added it */
1585 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1586 radeon_encoder = to_radeon_encoder(encoder);
1587 if (radeon_encoder->encoder_id == encoder_id) {
1588 radeon_encoder->devices |= supported_device;
1595 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1596 if (!radeon_encoder)
1599 encoder = &radeon_encoder->base;
1600 switch (rdev->num_crtc) {
1602 encoder->possible_crtcs = 0x1;
1606 encoder->possible_crtcs = 0x3;
1609 encoder->possible_crtcs = 0x3f;
1613 radeon_encoder->enc_priv = NULL;
1615 radeon_encoder->encoder_id = encoder_id;
1616 radeon_encoder->devices = supported_device;
1617 radeon_encoder->rmx_type = RMX_OFF;
1619 switch (radeon_encoder->encoder_id) {
1620 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1621 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1622 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1623 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1624 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1625 radeon_encoder->rmx_type = RMX_FULL;
1626 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1627 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1629 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1630 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1632 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1634 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1635 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
1636 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
1637 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1639 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1640 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1641 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1642 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1643 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
1644 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1646 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1647 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1648 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1649 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1650 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1651 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1652 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1653 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1654 radeon_encoder->rmx_type = RMX_FULL;
1655 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1656 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1658 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1659 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1661 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);