drivers/gpu/drm/radeon/radeon_encoders.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "drm_crtc_helper.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 extern int atom_debug;
  33
  34 /* evil but including atombios.h is much worse */
  35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
  36                                 struct drm_display_mode *mode);
  37
  38 static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
  39 {
  40         struct drm_device *dev = encoder->dev;
  41         struct radeon_device *rdev = dev->dev_private;
  42         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  43         struct drm_encoder *clone_encoder;
  44         uint32_t index_mask = 0;
  45         int count;
  46
  47         /* DIG routing gets problematic */
  48         if (rdev->family >= CHIP_R600)
  49                 return index_mask;
  50         /* LVDS/TV are too wacky */
  51         if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
  52                 return index_mask;
  53         /* DVO requires 2x ppll clocks depending on tmds chip */
  54         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
  55                 return index_mask;
  56
  57         count = -1;
  58         list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
  59                 struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
  60                 count++;
  61
  62                 if (clone_encoder == encoder)
  63                         continue;
  64                 if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT))
  65                         continue;
  66                 if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT)
  67                         continue;
  68                 else
  69                         index_mask |= (1 << count);
  70         }
  71         return index_mask;
  72 }
  73
  74 void radeon_setup_encoder_clones(struct drm_device *dev)
  75 {
  76         struct drm_encoder *encoder;
  77
  78         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  79                 encoder->possible_clones = radeon_encoder_clones(encoder);
  80         }
  81 }
  82
  83 uint32_t
  84 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
  85 {
  86         struct radeon_device *rdev = dev->dev_private;
  87         uint32_t ret = 0;
  88
  89         switch (supported_device) {
  90         case ATOM_DEVICE_CRT1_SUPPORT:
  91         case ATOM_DEVICE_TV1_SUPPORT:
  92         case ATOM_DEVICE_TV2_SUPPORT:
  93         case ATOM_DEVICE_CRT2_SUPPORT:
  94         case ATOM_DEVICE_CV_SUPPORT:
  95                 switch (dac) {
  96                 case 1: /* dac a */
  97                         if ((rdev->family == CHIP_RS300) ||
  98                             (rdev->family == CHIP_RS400) ||
  99                             (rdev->family == CHIP_RS480))
 100                                 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
 101                         else if (ASIC_IS_AVIVO(rdev))
 102                                 ret = ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1;
 103                         else
 104                                 ret = ENCODER_INTERNAL_DAC1_ENUM_ID1;
 105                         break;
 106                 case 2: /* dac b */
 107                         if (ASIC_IS_AVIVO(rdev))
 108                                 ret = ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1;
 109                         else {
 110                                 /*if (rdev->family == CHIP_R200)
 111                                   ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
 112                                   else*/
 113                                 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
 114                         }
 115                         break;
 116                 case 3: /* external dac */
 117                         if (ASIC_IS_AVIVO(rdev))
 118                                 ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
 119                         else
 120                                 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
 121                         break;
 122                 }
 123                 break;
 124         case ATOM_DEVICE_LCD1_SUPPORT:
 125                 if (ASIC_IS_AVIVO(rdev))
 126                         ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
 127                 else
 128                         ret = ENCODER_INTERNAL_LVDS_ENUM_ID1;
 129                 break;
 130         case ATOM_DEVICE_DFP1_SUPPORT:
 131                 if ((rdev->family == CHIP_RS300) ||
 132                     (rdev->family == CHIP_RS400) ||
 133                     (rdev->family == CHIP_RS480))
 134                         ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
 135                 else if (ASIC_IS_AVIVO(rdev))
 136                         ret = ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1;
 137                 else
 138                         ret = ENCODER_INTERNAL_TMDS1_ENUM_ID1;
 139                 break;
 140         case ATOM_DEVICE_LCD2_SUPPORT:
 141         case ATOM_DEVICE_DFP2_SUPPORT:
 142                 if ((rdev->family == CHIP_RS600) ||
 143                     (rdev->family == CHIP_RS690) ||
 144                     (rdev->family == CHIP_RS740))
 145                         ret = ENCODER_INTERNAL_DDI_ENUM_ID1;
 146                 else if (ASIC_IS_AVIVO(rdev))
 147                         ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
 148                 else
 149                         ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
 150                 break;
 151         case ATOM_DEVICE_DFP3_SUPPORT:
 152                 ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
 153                 break;
 154         }
 155
 156         return ret;
 157 }
 158
 159 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
 160 {
 161         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 162         switch (radeon_encoder->encoder_id) {
 163         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 164         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 165         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 166         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 167         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
 168         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 169         case ENCODER_OBJECT_ID_INTERNAL_DDI:
 170         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 171         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 172         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 173         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 174                 return true;
 175         default:
 176                 return false;
 177         }
 178 }
 179
 180 void
 181 radeon_link_encoder_connector(struct drm_device *dev)
 182 {
 183         struct drm_connector *connector;
 184         struct radeon_connector *radeon_connector;
 185         struct drm_encoder *encoder;
 186         struct radeon_encoder *radeon_encoder;
 187
 188         /* walk the list and link encoders to connectors */
 189         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 190                 radeon_connector = to_radeon_connector(connector);
 191                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 192                         radeon_encoder = to_radeon_encoder(encoder);
 193                         if (radeon_encoder->devices & radeon_connector->devices)
 194                                 drm_mode_connector_attach_encoder(connector, encoder);
 195                 }
 196         }
 197 }
 198
 199 void radeon_encoder_set_active_device(struct drm_encoder *encoder)
 200 {
 201         struct drm_device *dev = encoder->dev;
 202         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 203         struct drm_connector *connector;
 204
 205         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 206                 if (connector->encoder == encoder) {
 207                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 208                         radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
 209                         DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n",
 210                                   radeon_encoder->active_device, radeon_encoder->devices,
 211                                   radeon_connector->devices, encoder->encoder_type);
 212                 }
 213         }
 214 }
 215
 216 struct drm_connector *
 217 radeon_get_connector_for_encoder(struct drm_encoder *encoder)
 218 {
 219         struct drm_device *dev = encoder->dev;
 220         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 221         struct drm_connector *connector;
 222         struct radeon_connector *radeon_connector;
 223
 224         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 225                 radeon_connector = to_radeon_connector(connector);
 226                 if (radeon_encoder->active_device & radeon_connector->devices)
 227                         return connector;
 228         }
 229         return NULL;
 230 }
 231
 232 static struct drm_connector *
 233 radeon_get_connector_for_encoder_init(struct drm_encoder *encoder)
 234 {
 235         struct drm_device *dev = encoder->dev;
 236         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 237         struct drm_connector *connector;
 238         struct radeon_connector *radeon_connector;
 239
 240         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 241                 radeon_connector = to_radeon_connector(connector);
 242                 if (radeon_encoder->devices & radeon_connector->devices)
 243                         return connector;
 244         }
 245         return NULL;
 246 }
 247
 248 struct drm_encoder *radeon_atom_get_external_encoder(struct drm_encoder *encoder)
 249 {
 250         struct drm_device *dev = encoder->dev;
 251         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 252         struct drm_encoder *other_encoder;
 253         struct radeon_encoder *other_radeon_encoder;
 254
 255         if (radeon_encoder->is_ext_encoder)
 256                 return NULL;
 257
 258         list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
 259                 if (other_encoder == encoder)
 260                         continue;
 261                 other_radeon_encoder = to_radeon_encoder(other_encoder);
 262                 if (other_radeon_encoder->is_ext_encoder &&
 263                     (radeon_encoder->devices & other_radeon_encoder->devices))
 264                         return other_encoder;
 265         }
 266         return NULL;
 267 }
 268
 269 bool radeon_encoder_is_dp_bridge(struct drm_encoder *encoder)
 270 {
 271         struct drm_encoder *other_encoder = radeon_atom_get_external_encoder(encoder);
 272
 273         if (other_encoder) {
 274                 struct radeon_encoder *radeon_encoder = to_radeon_encoder(other_encoder);
 275
 276                 switch (radeon_encoder->encoder_id) {
 277                 case ENCODER_OBJECT_ID_TRAVIS:
 278                 case ENCODER_OBJECT_ID_NUTMEG:
 279                         return true;
 280                 default:
 281                         return false;
 282                 }
 283         }
 284
 285         return false;
 286 }
 287
 288 void radeon_panel_mode_fixup(struct drm_encoder *encoder,
 289                              struct drm_display_mode *adjusted_mode)
 290 {
 291         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 292         struct drm_device *dev = encoder->dev;
 293         struct radeon_device *rdev = dev->dev_private;
 294         struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
 295         unsigned hblank = native_mode->htotal - native_mode->hdisplay;
 296         unsigned vblank = native_mode->vtotal - native_mode->vdisplay;
 297         unsigned hover = native_mode->hsync_start - native_mode->hdisplay;
 298         unsigned vover = native_mode->vsync_start - native_mode->vdisplay;
 299         unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start;
 300         unsigned vsync_width = native_mode->vsync_end - native_mode->vsync_start;
 301
 302         adjusted_mode->clock = native_mode->clock;
 303         adjusted_mode->flags = native_mode->flags;
 304
 305         if (ASIC_IS_AVIVO(rdev)) {
 306                 adjusted_mode->hdisplay = native_mode->hdisplay;
 307                 adjusted_mode->vdisplay = native_mode->vdisplay;
 308         }
 309
 310         adjusted_mode->htotal = native_mode->hdisplay + hblank;
 311         adjusted_mode->hsync_start = native_mode->hdisplay + hover;
 312         adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width;
 313
 314         adjusted_mode->vtotal = native_mode->vdisplay + vblank;
 315         adjusted_mode->vsync_start = native_mode->vdisplay + vover;
 316         adjusted_mode->vsync_end = adjusted_mode->vsync_start + vsync_width;
 317
 318         drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
 319
 320         if (ASIC_IS_AVIVO(rdev)) {
 321                 adjusted_mode->crtc_hdisplay = native_mode->hdisplay;
 322                 adjusted_mode->crtc_vdisplay = native_mode->vdisplay;
 323         }
 324
 325         adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + hblank;
 326         adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + hover;
 327         adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + hsync_width;
 328
 329         adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + vblank;
 330         adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + vover;
 331         adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + vsync_width;
 332
 333 }
 334
 335 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
 336                                    struct drm_display_mode *mode,
 337                                    struct drm_display_mode *adjusted_mode)
 338 {
 339         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 340         struct drm_device *dev = encoder->dev;
 341         struct radeon_device *rdev = dev->dev_private;
 342
 343         /* set the active encoder to connector routing */
 344         radeon_encoder_set_active_device(encoder);
 345         drm_mode_set_crtcinfo(adjusted_mode, 0);
 346
 347         /* hw bug */
 348         if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 349             && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
 350                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
 351
 352         /* get the native mode for LVDS */
 353         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
 354                 radeon_panel_mode_fixup(encoder, adjusted_mode);
 355
 356         /* get the native mode for TV */
 357         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
 358                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 359                 if (tv_dac) {
 360                         if (tv_dac->tv_std == TV_STD_NTSC ||
 361                             tv_dac->tv_std == TV_STD_NTSC_J ||
 362                             tv_dac->tv_std == TV_STD_PAL_M)
 363                                 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
 364                         else
 365                                 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
 366                 }
 367         }
 368
 369         if (ASIC_IS_DCE3(rdev) &&
 370             (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT))) {
 371                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 372                 radeon_dp_set_link_config(connector, mode);
 373         }
 374
 375         return true;
 376 }
 377
 378 static void
 379 atombios_dac_setup(struct drm_encoder *encoder, int action)
 380 {
 381         struct drm_device *dev = encoder->dev;
 382         struct radeon_device *rdev = dev->dev_private;
 383         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 384         DAC_ENCODER_CONTROL_PS_ALLOCATION args;
 385         int index = 0;
 386         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 387
 388         memset(&args, 0, sizeof(args));
 389
 390         switch (radeon_encoder->encoder_id) {
 391         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 392         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 393                 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
 394                 break;
 395         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 396         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 397                 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
 398                 break;
 399         }
 400
 401         args.ucAction = action;
 402
 403         if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
 404                 args.ucDacStandard = ATOM_DAC1_PS2;
 405         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 406                 args.ucDacStandard = ATOM_DAC1_CV;
 407         else {
 408                 switch (dac_info->tv_std) {
 409                 case TV_STD_PAL:
 410                 case TV_STD_PAL_M:
 411                 case TV_STD_SCART_PAL:
 412                 case TV_STD_SECAM:
 413                 case TV_STD_PAL_CN:
 414                         args.ucDacStandard = ATOM_DAC1_PAL;
 415                         break;
 416                 case TV_STD_NTSC:
 417                 case TV_STD_NTSC_J:
 418                 case TV_STD_PAL_60:
 419                 default:
 420                         args.ucDacStandard = ATOM_DAC1_NTSC;
 421                         break;
 422                 }
 423         }
 424         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 425
 426         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 427
 428 }
 429
 430 static void
 431 atombios_tv_setup(struct drm_encoder *encoder, int action)
 432 {
 433         struct drm_device *dev = encoder->dev;
 434         struct radeon_device *rdev = dev->dev_private;
 435         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 436         TV_ENCODER_CONTROL_PS_ALLOCATION args;
 437         int index = 0;
 438         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 439
 440         memset(&args, 0, sizeof(args));
 441
 442         index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
 443
 444         args.sTVEncoder.ucAction = action;
 445
 446         if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 447                 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
 448         else {
 449                 switch (dac_info->tv_std) {
 450                 case TV_STD_NTSC:
 451                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 452                         break;
 453                 case TV_STD_PAL:
 454                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
 455                         break;
 456                 case TV_STD_PAL_M:
 457                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
 458                         break;
 459                 case TV_STD_PAL_60:
 460                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
 461                         break;
 462                 case TV_STD_NTSC_J:
 463                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
 464                         break;
 465                 case TV_STD_SCART_PAL:
 466                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
 467                         break;
 468                 case TV_STD_SECAM:
 469                         args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
 470                         break;
 471                 case TV_STD_PAL_CN:
 472                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
 473                         break;
 474                 default:
 475                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 476                         break;
 477                 }
 478         }
 479
 480         args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 481
 482         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 483
 484 }
 485
 486 union dvo_encoder_control {
 487         ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
 488         DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
 489         DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
 490 };
 491
 492 void
 493 atombios_dvo_setup(struct drm_encoder *encoder, int action)
 494 {
 495         struct drm_device *dev = encoder->dev;
 496         struct radeon_device *rdev = dev->dev_private;
 497         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 498         union dvo_encoder_control args;
 499         int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 500
 501         memset(&args, 0, sizeof(args));
 502
 503         if (ASIC_IS_DCE3(rdev)) {
 504                 /* DCE3+ */
 505                 args.dvo_v3.ucAction = action;
 506                 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 507                 args.dvo_v3.ucDVOConfig = 0; /* XXX */
 508         } else if (ASIC_IS_DCE2(rdev)) {
 509                 /* DCE2 (pre-DCE3 R6xx, RS600/690/740 */
 510                 args.dvo.sDVOEncoder.ucAction = action;
 511                 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 512                 /* DFP1, CRT1, TV1 depending on the type of port */
 513                 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
 514
 515                 if (radeon_encoder->pixel_clock > 165000)
 516                         args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
 517         } else {
 518                 /* R4xx, R5xx */
 519                 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
 520
 521                 if (radeon_encoder->pixel_clock > 165000)
 522                         args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 523
 524                 /*if (pScrn->rgbBits == 8)*/
 525                 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
 526         }
 527
 528         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 529 }
 530
 531 union lvds_encoder_control {
 532         LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
 533         LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
 534 };
 535
 536 void
 537 atombios_digital_setup(struct drm_encoder *encoder, int action)
 538 {
 539         struct drm_device *dev = encoder->dev;
 540         struct radeon_device *rdev = dev->dev_private;
 541         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 542         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 543         union lvds_encoder_control args;
 544         int index = 0;
 545         int hdmi_detected = 0;
 546         uint8_t frev, crev;
 547
 548         if (!dig)
 549                 return;
 550
 551         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
 552                 hdmi_detected = 1;
 553
 554         memset(&args, 0, sizeof(args));
 555
 556         switch (radeon_encoder->encoder_id) {
 557         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 558                 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 559                 break;
 560         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 561         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 562                 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
 563                 break;
 564         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 565                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 566                         index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 567                 else
 568                         index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
 569                 break;
 570         }
 571
 572         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 573                 return;
 574
 575         switch (frev) {
 576         case 1:
 577         case 2:
 578                 switch (crev) {
 579                 case 1:
 580                         args.v1.ucMisc = 0;
 581                         args.v1.ucAction = action;
 582                         if (hdmi_detected)
 583                                 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 584                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 585                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 586                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 587                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 588                                 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 589                                         args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 590                         } else {
 591                                 if (dig->linkb)
 592                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 593                                 if (radeon_encoder->pixel_clock > 165000)
 594                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 595                                 /*if (pScrn->rgbBits == 8) */
 596                                 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 597                         }
 598                         break;
 599                 case 2:
 600                 case 3:
 601                         args.v2.ucMisc = 0;
 602                         args.v2.ucAction = action;
 603                         if (crev == 3) {
 604                                 if (dig->coherent_mode)
 605                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
 606                         }
 607                         if (hdmi_detected)
 608                                 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 609                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 610                         args.v2.ucTruncate = 0;
 611                         args.v2.ucSpatial = 0;
 612                         args.v2.ucTemporal = 0;
 613                         args.v2.ucFRC = 0;
 614                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 615                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 616                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 617                                 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
 618                                         args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
 619                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 620                                                 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
 621                                 }
 622                                 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
 623                                         args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
 624                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 625                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
 626                                         if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
 627                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
 628                                 }
 629                         } else {
 630                                 if (dig->linkb)
 631                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 632                                 if (radeon_encoder->pixel_clock > 165000)
 633                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 634                         }
 635                         break;
 636                 default:
 637                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 638                         break;
 639                 }
 640                 break;
 641         default:
 642                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 643                 break;
 644         }
 645
 646         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 647 }
 648
 649 int
 650 atombios_get_encoder_mode(struct drm_encoder *encoder)
 651 {
 652         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 653         struct drm_device *dev = encoder->dev;
 654         struct radeon_device *rdev = dev->dev_private;
 655         struct drm_connector *connector;
 656         struct radeon_connector *radeon_connector;
 657         struct radeon_connector_atom_dig *dig_connector;
 658
 659         /* dp bridges are always DP */
 660         if (radeon_encoder_is_dp_bridge(encoder))
 661                 return ATOM_ENCODER_MODE_DP;
 662
 663         connector = radeon_get_connector_for_encoder(encoder);
 664         if (!connector) {
 665                 switch (radeon_encoder->encoder_id) {
 666                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 667                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 668                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 669                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 670                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 671                         return ATOM_ENCODER_MODE_DVI;
 672                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 673                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 674                 default:
 675                         return ATOM_ENCODER_MODE_CRT;
 676                 }
 677         }
 678         radeon_connector = to_radeon_connector(connector);
 679
 680         switch (connector->connector_type) {
 681         case DRM_MODE_CONNECTOR_DVII:
 682         case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
 683                 if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
 684                         /* fix me */
 685                         if (ASIC_IS_DCE4(rdev))
 686                                 return ATOM_ENCODER_MODE_DVI;
 687                         else
 688                                 return ATOM_ENCODER_MODE_HDMI;
 689                 } else if (radeon_connector->use_digital)
 690                         return ATOM_ENCODER_MODE_DVI;
 691                 else
 692                         return ATOM_ENCODER_MODE_CRT;
 693                 break;
 694         case DRM_MODE_CONNECTOR_DVID:
 695         case DRM_MODE_CONNECTOR_HDMIA:
 696         default:
 697                 if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
 698                         /* fix me */
 699                         if (ASIC_IS_DCE4(rdev))
 700                                 return ATOM_ENCODER_MODE_DVI;
 701                         else
 702                                 return ATOM_ENCODER_MODE_HDMI;
 703                 } else
 704                         return ATOM_ENCODER_MODE_DVI;
 705                 break;
 706         case DRM_MODE_CONNECTOR_LVDS:
 707                 return ATOM_ENCODER_MODE_LVDS;
 708                 break;
 709         case DRM_MODE_CONNECTOR_DisplayPort:
 710                 dig_connector = radeon_connector->con_priv;
 711                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 712                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
 713                         return ATOM_ENCODER_MODE_DP;
 714                 else if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
 715                         /* fix me */
 716                         if (ASIC_IS_DCE4(rdev))
 717                                 return ATOM_ENCODER_MODE_DVI;
 718                         else
 719                                 return ATOM_ENCODER_MODE_HDMI;
 720                 } else
 721                         return ATOM_ENCODER_MODE_DVI;
 722                 break;
 723         case DRM_MODE_CONNECTOR_eDP:
 724                 return ATOM_ENCODER_MODE_DP;
 725         case DRM_MODE_CONNECTOR_DVIA:
 726         case DRM_MODE_CONNECTOR_VGA:
 727                 return ATOM_ENCODER_MODE_CRT;
 728                 break;
 729         case DRM_MODE_CONNECTOR_Composite:
 730         case DRM_MODE_CONNECTOR_SVIDEO:
 731         case DRM_MODE_CONNECTOR_9PinDIN:
 732                 /* fix me */
 733                 return ATOM_ENCODER_MODE_TV;
 734                 /*return ATOM_ENCODER_MODE_CV;*/
 735                 break;
 736         }
 737 }
 738
 739 /*
 740  * DIG Encoder/Transmitter Setup
 741  *
 742  * DCE 3.0/3.1
 743  * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
 744  * Supports up to 3 digital outputs
 745  * - 2 DIG encoder blocks.
 746  * DIG1 can drive UNIPHY link A or link B
 747  * DIG2 can drive UNIPHY link B or LVTMA
 748  *
 749  * DCE 3.2
 750  * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
 751  * Supports up to 5 digital outputs
 752  * - 2 DIG encoder blocks.
 753  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 754  *
 755  * DCE 4.0/5.0
 756  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 757  * Supports up to 6 digital outputs
 758  * - 6 DIG encoder blocks.
 759  * - DIG to PHY mapping is hardcoded
 760  * DIG1 drives UNIPHY0 link A, A+B
 761  * DIG2 drives UNIPHY0 link B
 762  * DIG3 drives UNIPHY1 link A, A+B
 763  * DIG4 drives UNIPHY1 link B
 764  * DIG5 drives UNIPHY2 link A, A+B
 765  * DIG6 drives UNIPHY2 link B
 766  *
 767  * DCE 4.1
 768  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 769  * Supports up to 6 digital outputs
 770  * - 2 DIG encoder blocks.
 771  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 772  *
 773  * Routing
 774  * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
 775  * Examples:
 776  * crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
 777  * crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
 778  * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
 779  * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
 780  */
 781
 782 union dig_encoder_control {
 783         DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
 784         DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
 785         DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
 786         DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
 787 };
 788
 789 void
 790 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
 791 {
 792         struct drm_device *dev = encoder->dev;
 793         struct radeon_device *rdev = dev->dev_private;
 794         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 795         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 796         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 797         union dig_encoder_control args;
 798         int index = 0;
 799         uint8_t frev, crev;
 800         int dp_clock = 0;
 801         int dp_lane_count = 0;
 802         int hpd_id = RADEON_HPD_NONE;
 803         int bpc = 8;
 804
 805         if (connector) {
 806                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 807                 struct radeon_connector_atom_dig *dig_connector =
 808                         radeon_connector->con_priv;
 809
 810                 dp_clock = dig_connector->dp_clock;
 811                 dp_lane_count = dig_connector->dp_lane_count;
 812                 hpd_id = radeon_connector->hpd.hpd;
 813                 bpc = connector->display_info.bpc;
 814         }
 815
 816         /* no dig encoder assigned */
 817         if (dig->dig_encoder == -1)
 818                 return;
 819
 820         memset(&args, 0, sizeof(args));
 821
 822         if (ASIC_IS_DCE4(rdev))
 823                 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
 824         else {
 825                 if (dig->dig_encoder)
 826                         index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 827                 else
 828                         index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
 829         }
 830
 831         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 832                 return;
 833
 834         args.v1.ucAction = action;
 835         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 836         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 837                 args.v3.ucPanelMode = panel_mode;
 838         else
 839                 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
 840
 841         if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) ||
 842             (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST))
 843                 args.v1.ucLaneNum = dp_lane_count;
 844         else if (radeon_encoder->pixel_clock > 165000)
 845                 args.v1.ucLaneNum = 8;
 846         else
 847                 args.v1.ucLaneNum = 4;
 848
 849         if (ASIC_IS_DCE5(rdev)) {
 850                 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) ||
 851                     (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST)) {
 852                         if (dp_clock == 270000)
 853                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
 854                         else if (dp_clock == 540000)
 855                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
 856                 }
 857                 args.v4.acConfig.ucDigSel = dig->dig_encoder;
 858                 switch (bpc) {
 859                 case 0:
 860                         args.v4.ucBitPerColor = PANEL_BPC_UNDEFINE;
 861                         break;
 862                 case 6:
 863                         args.v4.ucBitPerColor = PANEL_6BIT_PER_COLOR;
 864                         break;
 865                 case 8:
 866                 default:
 867                         args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR;
 868                         break;
 869                 case 10:
 870                         args.v4.ucBitPerColor = PANEL_10BIT_PER_COLOR;
 871                         break;
 872                 case 12:
 873                         args.v4.ucBitPerColor = PANEL_12BIT_PER_COLOR;
 874                         break;
 875                 case 16:
 876                         args.v4.ucBitPerColor = PANEL_16BIT_PER_COLOR;
 877                         break;
 878                 }
 879                 if (hpd_id == RADEON_HPD_NONE)
 880                         args.v4.ucHPD_ID = 0;
 881                 else
 882                         args.v4.ucHPD_ID = hpd_id + 1;
 883         } else if (ASIC_IS_DCE4(rdev)) {
 884                 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000))
 885                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
 886                 args.v3.acConfig.ucDigSel = dig->dig_encoder;
 887                 switch (bpc) {
 888                 case 0:
 889                         args.v3.ucBitPerColor = PANEL_BPC_UNDEFINE;
 890                         break;
 891                 case 6:
 892                         args.v3.ucBitPerColor = PANEL_6BIT_PER_COLOR;
 893                         break;
 894                 case 8:
 895                 default:
 896                         args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
 897                         break;
 898                 case 10:
 899                         args.v3.ucBitPerColor = PANEL_10BIT_PER_COLOR;
 900                         break;
 901                 case 12:
 902                         args.v3.ucBitPerColor = PANEL_12BIT_PER_COLOR;
 903                         break;
 904                 case 16:
 905                         args.v3.ucBitPerColor = PANEL_16BIT_PER_COLOR;
 906                         break;
 907                 }
 908         } else {
 909                 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000))
 910                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
 911                 switch (radeon_encoder->encoder_id) {
 912                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 913                         args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
 914                         break;
 915                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 916                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 917                         args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
 918                         break;
 919                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 920                         args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
 921                         break;
 922                 }
 923                 if (dig->linkb)
 924                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
 925                 else
 926                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
 927         }
 928
 929         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 930
 931 }
 932
 933 union dig_transmitter_control {
 934         DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
 935         DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
 936         DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
 937         DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
 938 };
 939
 940 void
 941 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
 942 {
 943         struct drm_device *dev = encoder->dev;
 944         struct radeon_device *rdev = dev->dev_private;
 945         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 946         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 947         struct drm_connector *connector;
 948         union dig_transmitter_control args;
 949         int index = 0;
 950         uint8_t frev, crev;
 951         bool is_dp = false;
 952         int pll_id = 0;
 953         int dp_clock = 0;
 954         int dp_lane_count = 0;
 955         int connector_object_id = 0;
 956         int igp_lane_info = 0;
 957
 958         if (action == ATOM_TRANSMITTER_ACTION_INIT)
 959                 connector = radeon_get_connector_for_encoder_init(encoder);
 960         else
 961                 connector = radeon_get_connector_for_encoder(encoder);
 962
 963         if (connector) {
 964                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 965                 struct radeon_connector_atom_dig *dig_connector =
 966                         radeon_connector->con_priv;
 967
 968                 dp_clock = dig_connector->dp_clock;
 969                 dp_lane_count = dig_connector->dp_lane_count;
 970                 connector_object_id =
 971                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 972                 igp_lane_info = dig_connector->igp_lane_info;
 973         }
 974
 975         /* no dig encoder assigned */
 976         if (dig->dig_encoder == -1)
 977                 return;
 978
 979         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP)
 980                 is_dp = true;
 981
 982         memset(&args, 0, sizeof(args));
 983
 984         switch (radeon_encoder->encoder_id) {
 985         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 986                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
 987                 break;
 988         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 989         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 990         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 991                 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
 992                 break;
 993         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 994                 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
 995                 break;
 996         }
 997
 998         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 999                 return;
1000
1001         args.v1.ucAction = action;
1002         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1003                 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1004         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1005                 args.v1.asMode.ucLaneSel = lane_num;
1006                 args.v1.asMode.ucLaneSet = lane_set;
1007         } else {
1008                 if (is_dp)
1009                         args.v1.usPixelClock =
1010                                 cpu_to_le16(dp_clock / 10);
1011                 else if (radeon_encoder->pixel_clock > 165000)
1012                         args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1013                 else
1014                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1015         }
1016         if (ASIC_IS_DCE4(rdev)) {
1017                 if (is_dp)
1018                         args.v3.ucLaneNum = dp_lane_count;
1019                 else if (radeon_encoder->pixel_clock > 165000)
1020                         args.v3.ucLaneNum = 8;
1021                 else
1022                         args.v3.ucLaneNum = 4;
1023
1024                 if (dig->linkb)
1025                         args.v3.acConfig.ucLinkSel = 1;
1026                 if (dig->dig_encoder & 1)
1027                         args.v3.acConfig.ucEncoderSel = 1;
1028
1029                 /* Select the PLL for the PHY
1030                  * DP PHY should be clocked from external src if there is
1031                  * one.
1032                  */
1033                 if (encoder->crtc) {
1034                         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1035                         pll_id = radeon_crtc->pll_id;
1036                 }
1037
1038                 if (ASIC_IS_DCE5(rdev)) {
1039                         /* On DCE5 DCPLL usually generates the DP ref clock */
1040                         if (is_dp) {
1041                                 if (rdev->clock.dp_extclk)
1042                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1043                                 else
1044                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1045                         } else
1046                                 args.v4.acConfig.ucRefClkSource = pll_id;
1047                 } else {
1048                         /* On DCE4, if there is an external clock, it generates the DP ref clock */
1049                         if (is_dp && rdev->clock.dp_extclk)
1050                                 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1051                         else
1052                                 args.v3.acConfig.ucRefClkSource = pll_id;
1053                 }
1054
1055                 switch (radeon_encoder->encoder_id) {
1056                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1057                         args.v3.acConfig.ucTransmitterSel = 0;
1058                         break;
1059                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1060                         args.v3.acConfig.ucTransmitterSel = 1;
1061                         break;
1062                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1063                         args.v3.acConfig.ucTransmitterSel = 2;
1064                         break;
1065                 }
1066
1067                 if (is_dp)
1068                         args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1069                 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1070                         if (dig->coherent_mode)
1071                                 args.v3.acConfig.fCoherentMode = 1;
1072                         if (radeon_encoder->pixel_clock > 165000)
1073                                 args.v3.acConfig.fDualLinkConnector = 1;
1074                 }
1075         } else if (ASIC_IS_DCE32(rdev)) {
1076                 args.v2.acConfig.ucEncoderSel = dig->dig_encoder;
1077                 if (dig->linkb)
1078                         args.v2.acConfig.ucLinkSel = 1;
1079
1080                 switch (radeon_encoder->encoder_id) {
1081                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1082                         args.v2.acConfig.ucTransmitterSel = 0;
1083                         break;
1084                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1085                         args.v2.acConfig.ucTransmitterSel = 1;
1086                         break;
1087                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1088                         args.v2.acConfig.ucTransmitterSel = 2;
1089                         break;
1090                 }
1091
1092                 if (is_dp)
1093                         args.v2.acConfig.fCoherentMode = 1;
1094                 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1095                         if (dig->coherent_mode)
1096                                 args.v2.acConfig.fCoherentMode = 1;
1097                         if (radeon_encoder->pixel_clock > 165000)
1098                                 args.v2.acConfig.fDualLinkConnector = 1;
1099                 }
1100         } else {
1101                 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1102
1103                 if (dig->dig_encoder)
1104                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1105                 else
1106                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1107
1108                 if ((rdev->flags & RADEON_IS_IGP) &&
1109                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1110                         if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
1111                                 if (igp_lane_info & 0x1)
1112                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1113                                 else if (igp_lane_info & 0x2)
1114                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1115                                 else if (igp_lane_info & 0x4)
1116                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1117                                 else if (igp_lane_info & 0x8)
1118                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1119                         } else {
1120                                 if (igp_lane_info & 0x3)
1121                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1122                                 else if (igp_lane_info & 0xc)
1123                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1124                         }
1125                 }
1126
1127                 if (dig->linkb)
1128                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1129                 else
1130                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1131
1132                 if (is_dp)
1133                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1134                 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1135                         if (dig->coherent_mode)
1136                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1137                         if (radeon_encoder->pixel_clock > 165000)
1138                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1139                 }
1140         }
1141
1142         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1143 }
1144
1145 bool
1146 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1147 {
1148         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1149         struct drm_device *dev = radeon_connector->base.dev;
1150         struct radeon_device *rdev = dev->dev_private;
1151         union dig_transmitter_control args;
1152         int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1153         uint8_t frev, crev;
1154
1155         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1156                 goto done;
1157
1158         if (!ASIC_IS_DCE4(rdev))
1159                 goto done;
1160
1161         if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1162             (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1163                 goto done;
1164
1165         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1166                 goto done;
1167
1168         memset(&args, 0, sizeof(args));
1169
1170         args.v1.ucAction = action;
1171
1172         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1173
1174         /* wait for the panel to power up */
1175         if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1176                 int i;
1177
1178                 for (i = 0; i < 300; i++) {
1179                         if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1180                                 return true;
1181                         mdelay(1);
1182                 }
1183                 return false;
1184         }
1185 done:
1186         return true;
1187 }
1188
1189 union external_encoder_control {
1190         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1191         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1192 };
1193
1194 static void
1195 atombios_external_encoder_setup(struct drm_encoder *encoder,
1196                                 struct drm_encoder *ext_encoder,
1197                                 int action)
1198 {
1199         struct drm_device *dev = encoder->dev;
1200         struct radeon_device *rdev = dev->dev_private;
1201         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1202         struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1203         union external_encoder_control args;
1204         struct drm_connector *connector;
1205         int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1206         u8 frev, crev;
1207         int dp_clock = 0;
1208         int dp_lane_count = 0;
1209         int connector_object_id = 0;
1210         u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1211         int bpc = 8;
1212
1213         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1214                 connector = radeon_get_connector_for_encoder_init(encoder);
1215         else
1216                 connector = radeon_get_connector_for_encoder(encoder);
1217
1218         if (connector) {
1219                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1220                 struct radeon_connector_atom_dig *dig_connector =
1221                         radeon_connector->con_priv;
1222
1223                 dp_clock = dig_connector->dp_clock;
1224                 dp_lane_count = dig_connector->dp_lane_count;
1225                 connector_object_id =
1226                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1227                 bpc = connector->display_info.bpc;
1228         }
1229
1230         memset(&args, 0, sizeof(args));
1231
1232         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1233                 return;
1234
1235         switch (frev) {
1236         case 1:
1237                 /* no params on frev 1 */
1238                 break;
1239         case 2:
1240                 switch (crev) {
1241                 case 1:
1242                 case 2:
1243                         args.v1.sDigEncoder.ucAction = action;
1244                         args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1245                         args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1246
1247                         if (args.v1.sDigEncoder.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
1248                                 if (dp_clock == 270000)
1249                                         args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1250                                 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1251                         } else if (radeon_encoder->pixel_clock > 165000)
1252                                 args.v1.sDigEncoder.ucLaneNum = 8;
1253                         else
1254                                 args.v1.sDigEncoder.ucLaneNum = 4;
1255                         break;
1256                 case 3:
1257                         args.v3.sExtEncoder.ucAction = action;
1258                         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1259                                 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1260                         else
1261                                 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1262                         args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1263
1264                         if (args.v3.sExtEncoder.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
1265                                 if (dp_clock == 270000)
1266                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1267                                 else if (dp_clock == 540000)
1268                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1269                                 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1270                         } else if (radeon_encoder->pixel_clock > 165000)
1271                                 args.v3.sExtEncoder.ucLaneNum = 8;
1272                         else
1273                                 args.v3.sExtEncoder.ucLaneNum = 4;
1274                         switch (ext_enum) {
1275                         case GRAPH_OBJECT_ENUM_ID1:
1276                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1277                                 break;
1278                         case GRAPH_OBJECT_ENUM_ID2:
1279                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1280                                 break;
1281                         case GRAPH_OBJECT_ENUM_ID3:
1282                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1283                                 break;
1284                         }
1285                         switch (bpc) {
1286                         case 0:
1287                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_BPC_UNDEFINE;
1288                                 break;
1289                         case 6:
1290                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_6BIT_PER_COLOR;
1291                                 break;
1292                         case 8:
1293                         default:
1294                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR;
1295                                 break;
1296                         case 10:
1297                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_10BIT_PER_COLOR;
1298                                 break;
1299                         case 12:
1300                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_12BIT_PER_COLOR;
1301                                 break;
1302                         case 16:
1303                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_16BIT_PER_COLOR;
1304                                 break;
1305                         }
1306                         break;
1307                 default:
1308                         DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1309                         return;
1310                 }
1311                 break;
1312         default:
1313                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1314                 return;
1315         }
1316         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1317 }
1318
1319 static void
1320 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1321 {
1322         struct drm_device *dev = encoder->dev;
1323         struct radeon_device *rdev = dev->dev_private;
1324         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1325         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1326         ENABLE_YUV_PS_ALLOCATION args;
1327         int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1328         uint32_t temp, reg;
1329
1330         memset(&args, 0, sizeof(args));
1331
1332         if (rdev->family >= CHIP_R600)
1333                 reg = R600_BIOS_3_SCRATCH;
1334         else
1335                 reg = RADEON_BIOS_3_SCRATCH;
1336
1337         /* XXX: fix up scratch reg handling */
1338         temp = RREG32(reg);
1339         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1340                 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1341                              (radeon_crtc->crtc_id << 18)));
1342         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1343                 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1344         else
1345                 WREG32(reg, 0);
1346
1347         if (enable)
1348                 args.ucEnable = ATOM_ENABLE;
1349         args.ucCRTC = radeon_crtc->crtc_id;
1350
1351         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1352
1353         WREG32(reg, temp);
1354 }
1355
1356 static void
1357 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1358 {
1359         struct drm_device *dev = encoder->dev;
1360         struct radeon_device *rdev = dev->dev_private;
1361         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1362         struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
1363         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1364         int index = 0;
1365         bool is_dig = false;
1366         bool is_dce5_dac = false;
1367         bool is_dce5_dvo = false;
1368
1369         memset(&args, 0, sizeof(args));
1370
1371         DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1372                   radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1373                   radeon_encoder->active_device);
1374         switch (radeon_encoder->encoder_id) {
1375         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1376         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1377                 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1378                 break;
1379         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1380         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1381         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1382         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1383                 is_dig = true;
1384                 break;
1385         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1386         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1387                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1388                 break;
1389         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1390                 if (ASIC_IS_DCE5(rdev))
1391                         is_dce5_dvo = true;
1392                 else if (ASIC_IS_DCE3(rdev))
1393                         is_dig = true;
1394                 else
1395                         index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1396                 break;
1397         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1398                 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1399                 break;
1400         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1401                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1402                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1403                 else
1404                         index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1405                 break;
1406         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1407         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1408                 if (ASIC_IS_DCE5(rdev))
1409                         is_dce5_dac = true;
1410                 else {
1411                         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1412                                 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1413                         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1414                                 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1415                         else
1416                                 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1417                 }
1418                 break;
1419         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1420         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1421                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1422                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1423                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1424                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1425                 else
1426                         index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1427                 break;
1428         }
1429
1430         if (is_dig) {
1431                 switch (mode) {
1432                 case DRM_MODE_DPMS_ON:
1433                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1434                         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1435                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1436
1437                                 if (connector &&
1438                                     (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
1439                                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1440                                         struct radeon_connector_atom_dig *radeon_dig_connector =
1441                                                 radeon_connector->con_priv;
1442                                         atombios_set_edp_panel_power(connector,
1443                                                                      ATOM_TRANSMITTER_ACTION_POWER_ON);
1444                                         radeon_dig_connector->edp_on = true;
1445                                 }
1446                                 if (ASIC_IS_DCE4(rdev))
1447                                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1448                                 radeon_dp_link_train(encoder, connector);
1449                                 if (ASIC_IS_DCE4(rdev))
1450                                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1451                         }
1452                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1453                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1454                         break;
1455                 case DRM_MODE_DPMS_STANDBY:
1456                 case DRM_MODE_DPMS_SUSPEND:
1457                 case DRM_MODE_DPMS_OFF:
1458                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1459                         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1460                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1461
1462                                 if (ASIC_IS_DCE4(rdev))
1463                                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1464                                 if (connector &&
1465                                     (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
1466                                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1467                                         struct radeon_connector_atom_dig *radeon_dig_connector =
1468                                                 radeon_connector->con_priv;
1469                                         atombios_set_edp_panel_power(connector,
1470                                                                      ATOM_TRANSMITTER_ACTION_POWER_OFF);
1471                                         radeon_dig_connector->edp_on = false;
1472                                 }
1473                         }
1474                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1475                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1476                         break;
1477                 }
1478         } else if (is_dce5_dac) {
1479                 switch (mode) {
1480                 case DRM_MODE_DPMS_ON:
1481                         atombios_dac_setup(encoder, ATOM_ENABLE);
1482                         break;
1483                 case DRM_MODE_DPMS_STANDBY:
1484                 case DRM_MODE_DPMS_SUSPEND:
1485                 case DRM_MODE_DPMS_OFF:
1486                         atombios_dac_setup(encoder, ATOM_DISABLE);
1487                         break;
1488                 }
1489         } else if (is_dce5_dvo) {
1490                 switch (mode) {
1491                 case DRM_MODE_DPMS_ON:
1492                         atombios_dvo_setup(encoder, ATOM_ENABLE);
1493                         break;
1494                 case DRM_MODE_DPMS_STANDBY:
1495                 case DRM_MODE_DPMS_SUSPEND:
1496                 case DRM_MODE_DPMS_OFF:
1497                         atombios_dvo_setup(encoder, ATOM_DISABLE);
1498                         break;
1499                 }
1500         } else {
1501                 switch (mode) {
1502                 case DRM_MODE_DPMS_ON:
1503                         args.ucAction = ATOM_ENABLE;
1504                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1505                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1506                                 args.ucAction = ATOM_LCD_BLON;
1507                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1508                         }
1509                         break;
1510                 case DRM_MODE_DPMS_STANDBY:
1511                 case DRM_MODE_DPMS_SUSPEND:
1512                 case DRM_MODE_DPMS_OFF:
1513                         args.ucAction = ATOM_DISABLE;
1514                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1515                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1516                                 args.ucAction = ATOM_LCD_BLOFF;
1517                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1518                         }
1519                         break;
1520                 }
1521         }
1522
1523         if (ext_encoder) {
1524                 int action;
1525
1526                 switch (mode) {
1527                 case DRM_MODE_DPMS_ON:
1528                 default:
1529                         if (ASIC_IS_DCE41(rdev))
1530                                 action = EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT;
1531                         else
1532                                 action = ATOM_ENABLE;
1533                         break;
1534                 case DRM_MODE_DPMS_STANDBY:
1535                 case DRM_MODE_DPMS_SUSPEND:
1536                 case DRM_MODE_DPMS_OFF:
1537                         if (ASIC_IS_DCE41(rdev))
1538                                 action = EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT;
1539                         else
1540                                 action = ATOM_DISABLE;
1541                         break;
1542                 }
1543                 atombios_external_encoder_setup(encoder, ext_encoder, action);
1544         }
1545
1546         radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1547
1548 }
1549
1550 union crtc_source_param {
1551         SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1552         SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1553 };
1554
1555 static void
1556 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1557 {
1558         struct drm_device *dev = encoder->dev;
1559         struct radeon_device *rdev = dev->dev_private;
1560         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1561         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1562         union crtc_source_param args;
1563         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1564         uint8_t frev, crev;
1565         struct radeon_encoder_atom_dig *dig;
1566
1567         memset(&args, 0, sizeof(args));
1568
1569         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1570                 return;
1571
1572         switch (frev) {
1573         case 1:
1574                 switch (crev) {
1575                 case 1:
1576                 default:
1577                         if (ASIC_IS_AVIVO(rdev))
1578                                 args.v1.ucCRTC = radeon_crtc->crtc_id;
1579                         else {
1580                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1581                                         args.v1.ucCRTC = radeon_crtc->crtc_id;
1582                                 } else {
1583                                         args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1584                                 }
1585                         }
1586                         switch (radeon_encoder->encoder_id) {
1587                         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1588                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1589                                 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1590                                 break;
1591                         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1592                         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1593                                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1594                                         args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1595                                 else
1596                                         args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1597                                 break;
1598                         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1599                         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1600                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1601                                 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1602                                 break;
1603                         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1604                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1605                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1606                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1607                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1608                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1609                                 else
1610                                         args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1611                                 break;
1612                         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1613                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1614                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1615                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1616                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1617                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1618                                 else
1619                                         args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1620                                 break;
1621                         }
1622                         break;
1623                 case 2:
1624                         args.v2.ucCRTC = radeon_crtc->crtc_id;
1625                         args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1626                         switch (radeon_encoder->encoder_id) {
1627                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1628                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1629                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1630                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1631                                 dig = radeon_encoder->enc_priv;
1632                                 switch (dig->dig_encoder) {
1633                                 case 0:
1634                                         args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1635                                         break;
1636                                 case 1:
1637                                         args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1638                                         break;
1639                                 case 2:
1640                                         args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1641                                         break;
1642                                 case 3:
1643                                         args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1644                                         break;
1645                                 case 4:
1646                                         args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1647                                         break;
1648                                 case 5:
1649                                         args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1650                                         break;
1651                                 }
1652                                 break;
1653                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1654                                 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1655                                 break;
1656                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1657                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1658                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1659                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1660                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1661                                 else
1662                                         args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1663                                 break;
1664                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1665                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1666                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1667                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1668                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1669                                 else
1670                                         args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1671                                 break;
1672                         }
1673                         break;
1674                 }
1675                 break;
1676         default:
1677                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1678                 return;
1679         }
1680
1681         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1682
1683         /* update scratch regs with new routing */
1684         radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1685 }
1686
1687 static void
1688 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1689                               struct drm_display_mode *mode)
1690 {
1691         struct drm_device *dev = encoder->dev;
1692         struct radeon_device *rdev = dev->dev_private;
1693         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1694         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1695
1696         /* Funky macbooks */
1697         if ((dev->pdev->device == 0x71C5) &&
1698             (dev->pdev->subsystem_vendor == 0x106b) &&
1699             (dev->pdev->subsystem_device == 0x0080)) {
1700                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1701                         uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1702
1703                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1704                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1705
1706                         WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1707                 }
1708         }
1709
1710         /* set scaler clears this on some chips */
1711         if (ASIC_IS_AVIVO(rdev) &&
1712             (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1713                 if (ASIC_IS_DCE4(rdev)) {
1714                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1715                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1716                                        EVERGREEN_INTERLEAVE_EN);
1717                         else
1718                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1719                 } else {
1720                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1721                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1722                                        AVIVO_D1MODE_INTERLEAVE_EN);
1723                         else
1724                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1725                 }
1726         }
1727 }
1728
1729 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1730 {
1731         struct drm_device *dev = encoder->dev;
1732         struct radeon_device *rdev = dev->dev_private;
1733         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1734         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1735         struct drm_encoder *test_encoder;
1736         struct radeon_encoder_atom_dig *dig;
1737         uint32_t dig_enc_in_use = 0;
1738
1739         /* DCE4/5 */
1740         if (ASIC_IS_DCE4(rdev)) {
1741                 dig = radeon_encoder->enc_priv;
1742                 if (ASIC_IS_DCE41(rdev))
1743                         return radeon_crtc->crtc_id;
1744                 else {
1745                         switch (radeon_encoder->encoder_id) {
1746                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1747                                 if (dig->linkb)
1748                                         return 1;
1749                                 else
1750                                         return 0;
1751                                 break;
1752                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1753                                 if (dig->linkb)
1754                                         return 3;
1755                                 else
1756                                         return 2;
1757                                 break;
1758                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1759                                 if (dig->linkb)
1760                                         return 5;
1761                                 else
1762                                         return 4;
1763                                 break;
1764                         }
1765                 }
1766         }
1767
1768         /* on DCE32 and encoder can driver any block so just crtc id */
1769         if (ASIC_IS_DCE32(rdev)) {
1770                 return radeon_crtc->crtc_id;
1771         }
1772
1773         /* on DCE3 - LVTMA can only be driven by DIGB */
1774         list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1775                 struct radeon_encoder *radeon_test_encoder;
1776
1777                 if (encoder == test_encoder)
1778                         continue;
1779
1780                 if (!radeon_encoder_is_digital(test_encoder))
1781                         continue;
1782
1783                 radeon_test_encoder = to_radeon_encoder(test_encoder);
1784                 dig = radeon_test_encoder->enc_priv;
1785
1786                 if (dig->dig_encoder >= 0)
1787                         dig_enc_in_use |= (1 << dig->dig_encoder);
1788         }
1789
1790         if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1791                 if (dig_enc_in_use & 0x2)
1792                         DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1793                 return 1;
1794         }
1795         if (!(dig_enc_in_use & 1))
1796                 return 0;
1797         return 1;
1798 }
1799
1800 /* This only needs to be called once at startup */
1801 void
1802 radeon_atom_encoder_init(struct radeon_device *rdev)
1803 {
1804         struct drm_device *dev = rdev->ddev;
1805         struct drm_encoder *encoder;
1806
1807         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1808                 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1809                 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
1810
1811                 switch (radeon_encoder->encoder_id) {
1812                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1813                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1814                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1815                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1816                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1817                         break;
1818                 default:
1819                         break;
1820                 }
1821
1822                 if (ext_encoder && ASIC_IS_DCE41(rdev))
1823                         atombios_external_encoder_setup(encoder, ext_encoder,
1824                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
1825         }
1826 }
1827
1828 static void
1829 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1830                              struct drm_display_mode *mode,
1831                              struct drm_display_mode *adjusted_mode)
1832 {
1833         struct drm_device *dev = encoder->dev;
1834         struct radeon_device *rdev = dev->dev_private;
1835         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1836         struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
1837
1838         radeon_encoder->pixel_clock = adjusted_mode->clock;
1839
1840         if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
1841                 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1842                         atombios_yuv_setup(encoder, true);
1843                 else
1844                         atombios_yuv_setup(encoder, false);
1845         }
1846
1847         switch (radeon_encoder->encoder_id) {
1848         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1849         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1850         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1851         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1852                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1853                 break;
1854         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1855         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1856         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1857         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1858                 if (ASIC_IS_DCE4(rdev)) {
1859                         /* disable the transmitter */
1860                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1861                         /* setup and enable the encoder */
1862                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1863
1864                         /* enable the transmitter */
1865                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1866                 } else {
1867                         /* disable the encoder and transmitter */
1868                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1869                         atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1870
1871                         /* setup and enable the encoder and transmitter */
1872                         atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1873                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1874                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1875                 }
1876                 break;
1877         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1878         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1879         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1880                 atombios_dvo_setup(encoder, ATOM_ENABLE);
1881                 break;
1882         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1883         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1884         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1885         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1886                 atombios_dac_setup(encoder, ATOM_ENABLE);
1887                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
1888                         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1889                                 atombios_tv_setup(encoder, ATOM_ENABLE);
1890                         else
1891                                 atombios_tv_setup(encoder, ATOM_DISABLE);
1892                 }
1893                 break;
1894         }
1895
1896         if (ext_encoder) {
1897                 if (ASIC_IS_DCE41(rdev))
1898                         atombios_external_encoder_setup(encoder, ext_encoder,
1899                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1900                 else
1901                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1902         }
1903
1904         atombios_apply_encoder_quirks(encoder, adjusted_mode);
1905
1906         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1907                 r600_hdmi_enable(encoder);
1908                 r600_hdmi_setmode(encoder, adjusted_mode);
1909         }
1910 }
1911
1912 static bool
1913 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1914 {
1915         struct drm_device *dev = encoder->dev;
1916         struct radeon_device *rdev = dev->dev_private;
1917         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1918         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1919
1920         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1921                                        ATOM_DEVICE_CV_SUPPORT |
1922                                        ATOM_DEVICE_CRT_SUPPORT)) {
1923                 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1924                 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1925                 uint8_t frev, crev;
1926
1927                 memset(&args, 0, sizeof(args));
1928
1929                 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1930                         return false;
1931
1932                 args.sDacload.ucMisc = 0;
1933
1934                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1935                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1936                         args.sDacload.ucDacType = ATOM_DAC_A;
1937                 else
1938                         args.sDacload.ucDacType = ATOM_DAC_B;
1939
1940                 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1941                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1942                 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1943                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1944                 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1945                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1946                         if (crev >= 3)
1947                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1948                 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1949                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1950                         if (crev >= 3)
1951                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1952                 }
1953
1954                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1955
1956                 return true;
1957         } else
1958                 return false;
1959 }
1960
1961 static enum drm_connector_status
1962 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1963 {
1964         struct drm_device *dev = encoder->dev;
1965         struct radeon_device *rdev = dev->dev_private;
1966         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1967         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1968         uint32_t bios_0_scratch;
1969
1970         if (!atombios_dac_load_detect(encoder, connector)) {
1971                 DRM_DEBUG_KMS("detect returned false \n");
1972                 return connector_status_unknown;
1973         }
1974
1975         if (rdev->family >= CHIP_R600)
1976                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1977         else
1978                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1979
1980         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1981         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1982                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1983                         return connector_status_connected;
1984         }
1985         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1986                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1987                         return connector_status_connected;
1988         }
1989         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1990                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1991                         return connector_status_connected;
1992         }
1993         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1994                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1995                         return connector_status_connected; /* CTV */
1996                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1997                         return connector_status_connected; /* STV */
1998         }
1999         return connector_status_disconnected;
2000 }
2001
2002 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2003 {
2004         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2005         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2006
2007         if ((radeon_encoder->active_device &
2008              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2009             radeon_encoder_is_dp_bridge(encoder)) {
2010                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2011                 if (dig)
2012                         dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
2013         }
2014
2015         radeon_atom_output_lock(encoder, true);
2016         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2017
2018         if (connector) {
2019                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2020
2021                 /* select the clock/data port if it uses a router */
2022                 if (radeon_connector->router.cd_valid)
2023                         radeon_router_select_cd_port(radeon_connector);
2024
2025                 /* turn eDP panel on for mode set */
2026                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2027                         atombios_set_edp_panel_power(connector,
2028                                                      ATOM_TRANSMITTER_ACTION_POWER_ON);
2029         }
2030
2031         /* this is needed for the pll/ss setup to work correctly in some cases */
2032         atombios_set_encoder_crtc_source(encoder);
2033 }
2034
2035 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2036 {
2037         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2038         radeon_atom_output_lock(encoder, false);
2039 }
2040
2041 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2042 {
2043         struct drm_device *dev = encoder->dev;
2044         struct radeon_device *rdev = dev->dev_private;
2045         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2046         struct radeon_encoder_atom_dig *dig;
2047
2048         /* check for pre-DCE3 cards with shared encoders;
2049          * can't really use the links individually, so don't disable
2050          * the encoder if it's in use by another connector
2051          */
2052         if (!ASIC_IS_DCE3(rdev)) {
2053                 struct drm_encoder *other_encoder;
2054                 struct radeon_encoder *other_radeon_encoder;
2055
2056                 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2057                         other_radeon_encoder = to_radeon_encoder(other_encoder);
2058                         if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2059                             drm_helper_encoder_in_use(other_encoder))
2060                                 goto disable_done;
2061                 }
2062         }
2063
2064         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2065
2066         switch (radeon_encoder->encoder_id) {
2067         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2068         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2069         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2070         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2071                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2072                 break;
2073         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2074         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2075         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2076         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2077                 if (ASIC_IS_DCE4(rdev))
2078                         /* disable the transmitter */
2079                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
2080                 else {
2081                         /* disable the encoder and transmitter */
2082                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
2083                         atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
2084                 }
2085                 break;
2086         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2087         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2088         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2089                 atombios_dvo_setup(encoder, ATOM_DISABLE);
2090                 break;
2091         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2092         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2093         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2094         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2095                 atombios_dac_setup(encoder, ATOM_DISABLE);
2096                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2097                         atombios_tv_setup(encoder, ATOM_DISABLE);
2098                 break;
2099         }
2100
2101 disable_done:
2102         if (radeon_encoder_is_digital(encoder)) {
2103                 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
2104                         r600_hdmi_disable(encoder);
2105                 dig = radeon_encoder->enc_priv;
2106                 dig->dig_encoder = -1;
2107         }
2108         radeon_encoder->active_device = 0;
2109 }
2110
2111 /* these are handled by the primary encoders */
2112 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2113 {
2114
2115 }
2116
2117 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2118 {
2119
2120 }
2121
2122 static void
2123 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2124                          struct drm_display_mode *mode,
2125                          struct drm_display_mode *adjusted_mode)
2126 {
2127
2128 }
2129
2130 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2131 {
2132
2133 }
2134
2135 static void
2136 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2137 {
2138
2139 }
2140
2141 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2142                                        struct drm_display_mode *mode,
2143                                        struct drm_display_mode *adjusted_mode)
2144 {
2145         return true;
2146 }
2147
2148 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2149         .dpms = radeon_atom_ext_dpms,
2150         .mode_fixup = radeon_atom_ext_mode_fixup,
2151         .prepare = radeon_atom_ext_prepare,
2152         .mode_set = radeon_atom_ext_mode_set,
2153         .commit = radeon_atom_ext_commit,
2154         .disable = radeon_atom_ext_disable,
2155         /* no detect for TMDS/LVDS yet */
2156 };
2157
2158 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2159         .dpms = radeon_atom_encoder_dpms,
2160         .mode_fixup = radeon_atom_mode_fixup,
2161         .prepare = radeon_atom_encoder_prepare,
2162         .mode_set = radeon_atom_encoder_mode_set,
2163         .commit = radeon_atom_encoder_commit,
2164         .disable = radeon_atom_encoder_disable,
2165         /* no detect for TMDS/LVDS yet */
2166 };
2167
2168 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2169         .dpms = radeon_atom_encoder_dpms,
2170         .mode_fixup = radeon_atom_mode_fixup,
2171         .prepare = radeon_atom_encoder_prepare,
2172         .mode_set = radeon_atom_encoder_mode_set,
2173         .commit = radeon_atom_encoder_commit,
2174         .detect = radeon_atom_dac_detect,
2175 };
2176
2177 void radeon_enc_destroy(struct drm_encoder *encoder)
2178 {
2179         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2180         kfree(radeon_encoder->enc_priv);
2181         drm_encoder_cleanup(encoder);
2182         kfree(radeon_encoder);
2183 }
2184
2185 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2186         .destroy = radeon_enc_destroy,
2187 };
2188
2189 struct radeon_encoder_atom_dac *
2190 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2191 {
2192         struct drm_device *dev = radeon_encoder->base.dev;
2193         struct radeon_device *rdev = dev->dev_private;
2194         struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2195
2196         if (!dac)
2197                 return NULL;
2198
2199         dac->tv_std = radeon_atombios_get_tv_info(rdev);
2200         return dac;
2201 }
2202
2203 struct radeon_encoder_atom_dig *
2204 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2205 {
2206         int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2207         struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2208
2209         if (!dig)
2210                 return NULL;
2211
2212         /* coherent mode by default */
2213         dig->coherent_mode = true;
2214         dig->dig_encoder = -1;
2215
2216         if (encoder_enum == 2)
2217                 dig->linkb = true;
2218         else
2219                 dig->linkb = false;
2220
2221         return dig;
2222 }
2223
2224 void
2225 radeon_add_atom_encoder(struct drm_device *dev,
2226                         uint32_t encoder_enum,
2227                         uint32_t supported_device,
2228                         u16 caps)
2229 {
2230         struct radeon_device *rdev = dev->dev_private;
2231         struct drm_encoder *encoder;
2232         struct radeon_encoder *radeon_encoder;
2233
2234         /* see if we already added it */
2235         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2236                 radeon_encoder = to_radeon_encoder(encoder);
2237                 if (radeon_encoder->encoder_enum == encoder_enum) {
2238                         radeon_encoder->devices |= supported_device;
2239                         return;
2240                 }
2241
2242         }
2243
2244         /* add a new one */
2245         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2246         if (!radeon_encoder)
2247                 return;
2248
2249         encoder = &radeon_encoder->base;
2250         switch (rdev->num_crtc) {
2251         case 1:
2252                 encoder->possible_crtcs = 0x1;
2253                 break;
2254         case 2:
2255         default:
2256                 encoder->possible_crtcs = 0x3;
2257                 break;
2258         case 6:
2259                 encoder->possible_crtcs = 0x3f;
2260                 break;
2261         }
2262
2263         radeon_encoder->enc_priv = NULL;
2264
2265         radeon_encoder->encoder_enum = encoder_enum;
2266         radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2267         radeon_encoder->devices = supported_device;
2268         radeon_encoder->rmx_type = RMX_OFF;
2269         radeon_encoder->underscan_type = UNDERSCAN_OFF;
2270         radeon_encoder->is_ext_encoder = false;
2271         radeon_encoder->caps = caps;
2272
2273         switch (radeon_encoder->encoder_id) {
2274         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2275         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2276         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2277         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2278                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2279                         radeon_encoder->rmx_type = RMX_FULL;
2280                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2281                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2282                 } else {
2283                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2284                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2285                 }
2286                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2287                 break;
2288         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2289                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2290                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2291                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2292                 break;
2293         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2294         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2295         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2296                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2297                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2298                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2299                 break;
2300         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2301         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2302         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2303         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2304         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2305         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2306         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2307                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2308                         radeon_encoder->rmx_type = RMX_FULL;
2309                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2310                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2311                 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2312                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2313                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2314                 } else {
2315                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2316                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2317                 }
2318                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2319                 break;
2320         case ENCODER_OBJECT_ID_SI170B:
2321         case ENCODER_OBJECT_ID_CH7303:
2322         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2323         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2324         case ENCODER_OBJECT_ID_TITFP513:
2325         case ENCODER_OBJECT_ID_VT1623:
2326         case ENCODER_OBJECT_ID_HDMI_SI1930:
2327         case ENCODER_OBJECT_ID_TRAVIS:
2328         case ENCODER_OBJECT_ID_NUTMEG:
2329                 /* these are handled by the primary encoders */
2330                 radeon_encoder->is_ext_encoder = true;
2331                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2332                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2333                 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2334                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2335                 else
2336                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2337                 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2338                 break;
2339         }
2340 }