drivers/gpu/drm/radeon/radeon_display.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include <asm/div64.h>
  32
  33 #include "drm_crtc_helper.h"
  34 #include "drm_edid.h"
  35
  36 static int radeon_ddc_dump(struct drm_connector *connector);
  37
  38 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
  39 {
  40         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  41         struct drm_device *dev = crtc->dev;
  42         struct radeon_device *rdev = dev->dev_private;
  43         int i;
  44
  45         DRM_DEBUG("%d\n", radeon_crtc->crtc_id);
  46         WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
  47
  48         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  49         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  50         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  51
  52         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  53         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  54         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  55
  56         WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
  57         WREG32(AVIVO_DC_LUT_RW_MODE, 0);
  58         WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
  59
  60         WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
  61         for (i = 0; i < 256; i++) {
  62                 WREG32(AVIVO_DC_LUT_30_COLOR,
  63                              (radeon_crtc->lut_r[i] << 20) |
  64                              (radeon_crtc->lut_g[i] << 10) |
  65                              (radeon_crtc->lut_b[i] << 0));
  66         }
  67
  68         WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
  69 }
  70
  71 static void evergreen_crtc_load_lut(struct drm_crtc *crtc)
  72 {
  73         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  74         struct drm_device *dev = crtc->dev;
  75         struct radeon_device *rdev = dev->dev_private;
  76         int i;
  77
  78         DRM_DEBUG("%d\n", radeon_crtc->crtc_id);
  79         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
  80
  81         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  82         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  83         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  84
  85         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  86         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  87         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  88
  89         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
  90         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
  91
  92         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
  93         for (i = 0; i < 256; i++) {
  94                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
  95                        (radeon_crtc->lut_r[i] << 20) |
  96                        (radeon_crtc->lut_g[i] << 10) |
  97                        (radeon_crtc->lut_b[i] << 0));
  98         }
  99 }
 100
 101 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
 102 {
 103         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 104         struct drm_device *dev = crtc->dev;
 105         struct radeon_device *rdev = dev->dev_private;
 106         int i;
 107         uint32_t dac2_cntl;
 108
 109         dac2_cntl = RREG32(RADEON_DAC_CNTL2);
 110         if (radeon_crtc->crtc_id == 0)
 111                 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
 112         else
 113                 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
 114         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 115
 116         WREG8(RADEON_PALETTE_INDEX, 0);
 117         for (i = 0; i < 256; i++) {
 118                 WREG32(RADEON_PALETTE_30_DATA,
 119                              (radeon_crtc->lut_r[i] << 20) |
 120                              (radeon_crtc->lut_g[i] << 10) |
 121                              (radeon_crtc->lut_b[i] << 0));
 122         }
 123 }
 124
 125 void radeon_crtc_load_lut(struct drm_crtc *crtc)
 126 {
 127         struct drm_device *dev = crtc->dev;
 128         struct radeon_device *rdev = dev->dev_private;
 129
 130         if (!crtc->enabled)
 131                 return;
 132
 133         if (ASIC_IS_DCE4(rdev))
 134                 evergreen_crtc_load_lut(crtc);
 135         else if (ASIC_IS_AVIVO(rdev))
 136                 avivo_crtc_load_lut(crtc);
 137         else
 138                 legacy_crtc_load_lut(crtc);
 139 }
 140
 141 /** Sets the color ramps on behalf of fbcon */
 142 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 143                               u16 blue, int regno)
 144 {
 145         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 146
 147         radeon_crtc->lut_r[regno] = red >> 6;
 148         radeon_crtc->lut_g[regno] = green >> 6;
 149         radeon_crtc->lut_b[regno] = blue >> 6;
 150 }
 151
 152 /** Gets the color ramps on behalf of fbcon */
 153 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 154                               u16 *blue, int regno)
 155 {
 156         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 157
 158         *red = radeon_crtc->lut_r[regno] << 6;
 159         *green = radeon_crtc->lut_g[regno] << 6;
 160         *blue = radeon_crtc->lut_b[regno] << 6;
 161 }
 162
 163 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
 164                                   u16 *blue, uint32_t size)
 165 {
 166         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 167         int i;
 168
 169         if (size != 256) {
 170                 return;
 171         }
 172
 173         /* userspace palettes are always correct as is */
 174         for (i = 0; i < 256; i++) {
 175                 radeon_crtc->lut_r[i] = red[i] >> 6;
 176                 radeon_crtc->lut_g[i] = green[i] >> 6;
 177                 radeon_crtc->lut_b[i] = blue[i] >> 6;
 178         }
 179         radeon_crtc_load_lut(crtc);
 180 }
 181
 182 static void radeon_crtc_destroy(struct drm_crtc *crtc)
 183 {
 184         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 185
 186         drm_crtc_cleanup(crtc);
 187         kfree(radeon_crtc);
 188 }
 189
 190 static const struct drm_crtc_funcs radeon_crtc_funcs = {
 191         .cursor_set = radeon_crtc_cursor_set,
 192         .cursor_move = radeon_crtc_cursor_move,
 193         .gamma_set = radeon_crtc_gamma_set,
 194         .set_config = drm_crtc_helper_set_config,
 195         .destroy = radeon_crtc_destroy,
 196 };
 197
 198 static void radeon_crtc_init(struct drm_device *dev, int index)
 199 {
 200         struct radeon_device *rdev = dev->dev_private;
 201         struct radeon_crtc *radeon_crtc;
 202         int i;
 203
 204         radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
 205         if (radeon_crtc == NULL)
 206                 return;
 207
 208         drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
 209
 210         drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
 211         radeon_crtc->crtc_id = index;
 212         rdev->mode_info.crtcs[index] = radeon_crtc;
 213
 214 #if 0
 215         radeon_crtc->mode_set.crtc = &radeon_crtc->base;
 216         radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
 217         radeon_crtc->mode_set.num_connectors = 0;
 218 #endif
 219
 220         for (i = 0; i < 256; i++) {
 221                 radeon_crtc->lut_r[i] = i << 2;
 222                 radeon_crtc->lut_g[i] = i << 2;
 223                 radeon_crtc->lut_b[i] = i << 2;
 224         }
 225
 226         if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
 227                 radeon_atombios_init_crtc(dev, radeon_crtc);
 228         else
 229                 radeon_legacy_init_crtc(dev, radeon_crtc);
 230 }
 231
 232 static const char *encoder_names[34] = {
 233         "NONE",
 234         "INTERNAL_LVDS",
 235         "INTERNAL_TMDS1",
 236         "INTERNAL_TMDS2",
 237         "INTERNAL_DAC1",
 238         "INTERNAL_DAC2",
 239         "INTERNAL_SDVOA",
 240         "INTERNAL_SDVOB",
 241         "SI170B",
 242         "CH7303",
 243         "CH7301",
 244         "INTERNAL_DVO1",
 245         "EXTERNAL_SDVOA",
 246         "EXTERNAL_SDVOB",
 247         "TITFP513",
 248         "INTERNAL_LVTM1",
 249         "VT1623",
 250         "HDMI_SI1930",
 251         "HDMI_INTERNAL",
 252         "INTERNAL_KLDSCP_TMDS1",
 253         "INTERNAL_KLDSCP_DVO1",
 254         "INTERNAL_KLDSCP_DAC1",
 255         "INTERNAL_KLDSCP_DAC2",
 256         "SI178",
 257         "MVPU_FPGA",
 258         "INTERNAL_DDI",
 259         "VT1625",
 260         "HDMI_SI1932",
 261         "DP_AN9801",
 262         "DP_DP501",
 263         "INTERNAL_UNIPHY",
 264         "INTERNAL_KLDSCP_LVTMA",
 265         "INTERNAL_UNIPHY1",
 266         "INTERNAL_UNIPHY2",
 267 };
 268
 269 static const char *connector_names[15] = {
 270         "Unknown",
 271         "VGA",
 272         "DVI-I",
 273         "DVI-D",
 274         "DVI-A",
 275         "Composite",
 276         "S-video",
 277         "LVDS",
 278         "Component",
 279         "DIN",
 280         "DisplayPort",
 281         "HDMI-A",
 282         "HDMI-B",
 283         "TV",
 284         "eDP",
 285 };
 286
 287 static const char *hpd_names[7] = {
 288         "NONE",
 289         "HPD1",
 290         "HPD2",
 291         "HPD3",
 292         "HPD4",
 293         "HPD5",
 294         "HPD6",
 295 };
 296
 297 static void radeon_print_display_setup(struct drm_device *dev)
 298 {
 299         struct drm_connector *connector;
 300         struct radeon_connector *radeon_connector;
 301         struct drm_encoder *encoder;
 302         struct radeon_encoder *radeon_encoder;
 303         uint32_t devices;
 304         int i = 0;
 305
 306         DRM_INFO("Radeon Display Connectors\n");
 307         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 308                 radeon_connector = to_radeon_connector(connector);
 309                 DRM_INFO("Connector %d:\n", i);
 310                 DRM_INFO("  %s\n", connector_names[connector->connector_type]);
 311                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
 312                         DRM_INFO("  %s\n", hpd_names[radeon_connector->hpd.hpd]);
 313                 if (radeon_connector->ddc_bus) {
 314                         DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
 315                                  radeon_connector->ddc_bus->rec.mask_clk_reg,
 316                                  radeon_connector->ddc_bus->rec.mask_data_reg,
 317                                  radeon_connector->ddc_bus->rec.a_clk_reg,
 318                                  radeon_connector->ddc_bus->rec.a_data_reg,
 319                                  radeon_connector->ddc_bus->rec.en_clk_reg,
 320                                  radeon_connector->ddc_bus->rec.en_data_reg,
 321                                  radeon_connector->ddc_bus->rec.y_clk_reg,
 322                                  radeon_connector->ddc_bus->rec.y_data_reg);
 323                 } else {
 324                         if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
 325                             connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
 326                             connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
 327                             connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
 328                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
 329                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
 330                                 DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
 331                 }
 332                 DRM_INFO("  Encoders:\n");
 333                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 334                         radeon_encoder = to_radeon_encoder(encoder);
 335                         devices = radeon_encoder->devices & radeon_connector->devices;
 336                         if (devices) {
 337                                 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
 338                                         DRM_INFO("    CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 339                                 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
 340                                         DRM_INFO("    CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 341                                 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
 342                                         DRM_INFO("    LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 343                                 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
 344                                         DRM_INFO("    DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 345                                 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
 346                                         DRM_INFO("    DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 347                                 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
 348                                         DRM_INFO("    DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
 349                                 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
 350                                         DRM_INFO("    DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
 351                                 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
 352                                         DRM_INFO("    DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
 353                                 if (devices & ATOM_DEVICE_TV1_SUPPORT)
 354                                         DRM_INFO("    TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 355                                 if (devices & ATOM_DEVICE_CV_SUPPORT)
 356                                         DRM_INFO("    CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
 357                         }
 358                 }
 359                 i++;
 360         }
 361 }
 362
 363 static bool radeon_setup_enc_conn(struct drm_device *dev)
 364 {
 365         struct radeon_device *rdev = dev->dev_private;
 366         struct drm_connector *drm_connector;
 367         bool ret = false;
 368
 369         if (rdev->bios) {
 370                 if (rdev->is_atom_bios) {
 371                         ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
 372                         if (ret == false)
 373                                 ret = radeon_get_atom_connector_info_from_object_table(dev);
 374                 } else {
 375                         ret = radeon_get_legacy_connector_info_from_bios(dev);
 376                         if (ret == false)
 377                                 ret = radeon_get_legacy_connector_info_from_table(dev);
 378                 }
 379         } else {
 380                 if (!ASIC_IS_AVIVO(rdev))
 381                         ret = radeon_get_legacy_connector_info_from_table(dev);
 382         }
 383         if (ret) {
 384                 radeon_setup_encoder_clones(dev);
 385                 radeon_print_display_setup(dev);
 386                 list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head)
 387                         radeon_ddc_dump(drm_connector);
 388         }
 389
 390         return ret;
 391 }
 392
 393 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
 394 {
 395         struct drm_device *dev = radeon_connector->base.dev;
 396         struct radeon_device *rdev = dev->dev_private;
 397         int ret = 0;
 398
 399         if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
 400             (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
 401                 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
 402                 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
 403                      dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
 404                         radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter);
 405         }
 406         if (!radeon_connector->ddc_bus)
 407                 return -1;
 408         if (!radeon_connector->edid) {
 409                 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
 410         }
 411         /* some servers provide a hardcoded edid in rom for KVMs */
 412         if (!radeon_connector->edid)
 413                 radeon_connector->edid = radeon_combios_get_hardcoded_edid(rdev);
 414         if (radeon_connector->edid) {
 415                 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
 416                 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
 417                 return ret;
 418         }
 419         drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
 420         return 0;
 421 }
 422
 423 static int radeon_ddc_dump(struct drm_connector *connector)
 424 {
 425         struct edid *edid;
 426         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 427         int ret = 0;
 428
 429         if (!radeon_connector->ddc_bus)
 430                 return -1;
 431         edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter);
 432         if (edid) {
 433                 kfree(edid);
 434         }
 435         return ret;
 436 }
 437
 438 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
 439 {
 440         uint64_t mod;
 441
 442         n += d / 2;
 443
 444         mod = do_div(n, d);
 445         return n;
 446 }
 447
 448 static void radeon_compute_pll_legacy(struct radeon_pll *pll,
 449                                       uint64_t freq,
 450                                       uint32_t *dot_clock_p,
 451                                       uint32_t *fb_div_p,
 452                                       uint32_t *frac_fb_div_p,
 453                                       uint32_t *ref_div_p,
 454                                       uint32_t *post_div_p)
 455 {
 456         uint32_t min_ref_div = pll->min_ref_div;
 457         uint32_t max_ref_div = pll->max_ref_div;
 458         uint32_t min_post_div = pll->min_post_div;
 459         uint32_t max_post_div = pll->max_post_div;
 460         uint32_t min_fractional_feed_div = 0;
 461         uint32_t max_fractional_feed_div = 0;
 462         uint32_t best_vco = pll->best_vco;
 463         uint32_t best_post_div = 1;
 464         uint32_t best_ref_div = 1;
 465         uint32_t best_feedback_div = 1;
 466         uint32_t best_frac_feedback_div = 0;
 467         uint32_t best_freq = -1;
 468         uint32_t best_error = 0xffffffff;
 469         uint32_t best_vco_diff = 1;
 470         uint32_t post_div;
 471         u32 pll_out_min, pll_out_max;
 472
 473         DRM_DEBUG("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
 474         freq = freq * 1000;
 475
 476         if (pll->flags & RADEON_PLL_IS_LCD) {
 477                 pll_out_min = pll->lcd_pll_out_min;
 478                 pll_out_max = pll->lcd_pll_out_max;
 479         } else {
 480                 pll_out_min = pll->pll_out_min;
 481                 pll_out_max = pll->pll_out_max;
 482         }
 483
 484         if (pll->flags & RADEON_PLL_USE_REF_DIV)
 485                 min_ref_div = max_ref_div = pll->reference_div;
 486         else {
 487                 while (min_ref_div < max_ref_div-1) {
 488                         uint32_t mid = (min_ref_div + max_ref_div) / 2;
 489                         uint32_t pll_in = pll->reference_freq / mid;
 490                         if (pll_in < pll->pll_in_min)
 491                                 max_ref_div = mid;
 492                         else if (pll_in > pll->pll_in_max)
 493                                 min_ref_div = mid;
 494                         else
 495                                 break;
 496                 }
 497         }
 498
 499         if (pll->flags & RADEON_PLL_USE_POST_DIV)
 500                 min_post_div = max_post_div = pll->post_div;
 501
 502         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 503                 min_fractional_feed_div = pll->min_frac_feedback_div;
 504                 max_fractional_feed_div = pll->max_frac_feedback_div;
 505         }
 506
 507         for (post_div = min_post_div; post_div <= max_post_div; ++post_div) {
 508                 uint32_t ref_div;
 509
 510                 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
 511                         continue;
 512
 513                 /* legacy radeons only have a few post_divs */
 514                 if (pll->flags & RADEON_PLL_LEGACY) {
 515                         if ((post_div == 5) ||
 516                             (post_div == 7) ||
 517                             (post_div == 9) ||
 518                             (post_div == 10) ||
 519                             (post_div == 11) ||
 520                             (post_div == 13) ||
 521                             (post_div == 14) ||
 522                             (post_div == 15))
 523                                 continue;
 524                 }
 525
 526                 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
 527                         uint32_t feedback_div, current_freq = 0, error, vco_diff;
 528                         uint32_t pll_in = pll->reference_freq / ref_div;
 529                         uint32_t min_feed_div = pll->min_feedback_div;
 530                         uint32_t max_feed_div = pll->max_feedback_div + 1;
 531
 532                         if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
 533                                 continue;
 534
 535                         while (min_feed_div < max_feed_div) {
 536                                 uint32_t vco;
 537                                 uint32_t min_frac_feed_div = min_fractional_feed_div;
 538                                 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
 539                                 uint32_t frac_feedback_div;
 540                                 uint64_t tmp;
 541
 542                                 feedback_div = (min_feed_div + max_feed_div) / 2;
 543
 544                                 tmp = (uint64_t)pll->reference_freq * feedback_div;
 545                                 vco = radeon_div(tmp, ref_div);
 546
 547                                 if (vco < pll_out_min) {
 548                                         min_feed_div = feedback_div + 1;
 549                                         continue;
 550                                 } else if (vco > pll_out_max) {
 551                                         max_feed_div = feedback_div;
 552                                         continue;
 553                                 }
 554
 555                                 while (min_frac_feed_div < max_frac_feed_div) {
 556                                         frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
 557                                         tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
 558                                         tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
 559                                         current_freq = radeon_div(tmp, ref_div * post_div);
 560
 561                                         if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
 562                                                 error = freq - current_freq;
 563                                                 error = error < 0 ? 0xffffffff : error;
 564                                         } else
 565                                                 error = abs(current_freq - freq);
 566                                         vco_diff = abs(vco - best_vco);
 567
 568                                         if ((best_vco == 0 && error < best_error) ||
 569                                             (best_vco != 0 &&
 570                                              (error < best_error - 100 ||
 571                                               (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
 572                                                 best_post_div = post_div;
 573                                                 best_ref_div = ref_div;
 574                                                 best_feedback_div = feedback_div;
 575                                                 best_frac_feedback_div = frac_feedback_div;
 576                                                 best_freq = current_freq;
 577                                                 best_error = error;
 578                                                 best_vco_diff = vco_diff;
 579                                         } else if (current_freq == freq) {
 580                                                 if (best_freq == -1) {
 581                                                         best_post_div = post_div;
 582                                                         best_ref_div = ref_div;
 583                                                         best_feedback_div = feedback_div;
 584                                                         best_frac_feedback_div = frac_feedback_div;
 585                                                         best_freq = current_freq;
 586                                                         best_error = error;
 587                                                         best_vco_diff = vco_diff;
 588                                                 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
 589                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
 590                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
 591                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
 592                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
 593                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
 594                                                         best_post_div = post_div;
 595                                                         best_ref_div = ref_div;
 596                                                         best_feedback_div = feedback_div;
 597                                                         best_frac_feedback_div = frac_feedback_div;
 598                                                         best_freq = current_freq;
 599                                                         best_error = error;
 600                                                         best_vco_diff = vco_diff;
 601                                                 }
 602                                         }
 603                                         if (current_freq < freq)
 604                                                 min_frac_feed_div = frac_feedback_div + 1;
 605                                         else
 606                                                 max_frac_feed_div = frac_feedback_div;
 607                                 }
 608                                 if (current_freq < freq)
 609                                         min_feed_div = feedback_div + 1;
 610                                 else
 611                                         max_feed_div = feedback_div;
 612                         }
 613                 }
 614         }
 615
 616         *dot_clock_p = best_freq / 10000;
 617         *fb_div_p = best_feedback_div;
 618         *frac_fb_div_p = best_frac_feedback_div;
 619         *ref_div_p = best_ref_div;
 620         *post_div_p = best_post_div;
 621 }
 622
 623 static bool
 624 calc_fb_div(struct radeon_pll *pll,
 625             uint32_t freq,
 626             uint32_t post_div,
 627             uint32_t ref_div,
 628             uint32_t *fb_div,
 629             uint32_t *fb_div_frac)
 630 {
 631         fixed20_12 feedback_divider, a, b;
 632         u32 vco_freq;
 633
 634         vco_freq = freq * post_div;
 635         /* feedback_divider = vco_freq * ref_div / pll->reference_freq; */
 636         a.full = dfixed_const(pll->reference_freq);
 637         feedback_divider.full = dfixed_const(vco_freq);
 638         feedback_divider.full = dfixed_div(feedback_divider, a);
 639         a.full = dfixed_const(ref_div);
 640         feedback_divider.full = dfixed_mul(feedback_divider, a);
 641
 642         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 643                 /* feedback_divider = floor((feedback_divider * 10.0) + 0.5) * 0.1; */
 644                 a.full = dfixed_const(10);
 645                 feedback_divider.full = dfixed_mul(feedback_divider, a);
 646                 feedback_divider.full += dfixed_const_half(0);
 647                 feedback_divider.full = dfixed_floor(feedback_divider);
 648                 feedback_divider.full = dfixed_div(feedback_divider, a);
 649
 650                 /* *fb_div = floor(feedback_divider); */
 651                 a.full = dfixed_floor(feedback_divider);
 652                 *fb_div = dfixed_trunc(a);
 653                 /* *fb_div_frac = fmod(feedback_divider, 1.0) * 10.0; */
 654                 a.full = dfixed_const(10);
 655                 b.full = dfixed_mul(feedback_divider, a);
 656
 657                 feedback_divider.full = dfixed_floor(feedback_divider);
 658                 feedback_divider.full = dfixed_mul(feedback_divider, a);
 659                 feedback_divider.full = b.full - feedback_divider.full;
 660                 *fb_div_frac = dfixed_trunc(feedback_divider);
 661         } else {
 662                 /* *fb_div = floor(feedback_divider + 0.5); */
 663                 feedback_divider.full += dfixed_const_half(0);
 664                 feedback_divider.full = dfixed_floor(feedback_divider);
 665
 666                 *fb_div = dfixed_trunc(feedback_divider);
 667                 *fb_div_frac = 0;
 668         }
 669
 670         if (((*fb_div) < pll->min_feedback_div) || ((*fb_div) > pll->max_feedback_div))
 671                 return false;
 672         else
 673                 return true;
 674 }
 675
 676 static bool
 677 calc_fb_ref_div(struct radeon_pll *pll,
 678                 uint32_t freq,
 679                 uint32_t post_div,
 680                 uint32_t *fb_div,
 681                 uint32_t *fb_div_frac,
 682                 uint32_t *ref_div)
 683 {
 684         fixed20_12 ffreq, max_error, error, pll_out, a;
 685         u32 vco;
 686         u32 pll_out_min, pll_out_max;
 687
 688         if (pll->flags & RADEON_PLL_IS_LCD) {
 689                 pll_out_min = pll->lcd_pll_out_min;
 690                 pll_out_max = pll->lcd_pll_out_max;
 691         } else {
 692                 pll_out_min = pll->pll_out_min;
 693                 pll_out_max = pll->pll_out_max;
 694         }
 695
 696         ffreq.full = dfixed_const(freq);
 697         /* max_error = ffreq * 0.0025; */
 698         a.full = dfixed_const(400);
 699         max_error.full = dfixed_div(ffreq, a);
 700
 701         for ((*ref_div) = pll->min_ref_div; (*ref_div) < pll->max_ref_div; ++(*ref_div)) {
 702                 if (calc_fb_div(pll, freq, post_div, (*ref_div), fb_div, fb_div_frac)) {
 703                         vco = pll->reference_freq * (((*fb_div) * 10) + (*fb_div_frac));
 704                         vco = vco / ((*ref_div) * 10);
 705
 706                         if ((vco < pll_out_min) || (vco > pll_out_max))
 707                                 continue;
 708
 709                         /* pll_out = vco / post_div; */
 710                         a.full = dfixed_const(post_div);
 711                         pll_out.full = dfixed_const(vco);
 712                         pll_out.full = dfixed_div(pll_out, a);
 713
 714                         if (pll_out.full >= ffreq.full) {
 715                                 error.full = pll_out.full - ffreq.full;
 716                                 if (error.full <= max_error.full)
 717                                         return true;
 718                         }
 719                 }
 720         }
 721         return false;
 722 }
 723
 724 static void radeon_compute_pll_new(struct radeon_pll *pll,
 725                                    uint64_t freq,
 726                                    uint32_t *dot_clock_p,
 727                                    uint32_t *fb_div_p,
 728                                    uint32_t *frac_fb_div_p,
 729                                    uint32_t *ref_div_p,
 730                                    uint32_t *post_div_p)
 731 {
 732         u32 fb_div = 0, fb_div_frac = 0, post_div = 0, ref_div = 0;
 733         u32 best_freq = 0, vco_frequency;
 734         u32 pll_out_min, pll_out_max;
 735
 736         if (pll->flags & RADEON_PLL_IS_LCD) {
 737                 pll_out_min = pll->lcd_pll_out_min;
 738                 pll_out_max = pll->lcd_pll_out_max;
 739         } else {
 740                 pll_out_min = pll->pll_out_min;
 741                 pll_out_max = pll->pll_out_max;
 742         }
 743
 744         /* freq = freq / 10; */
 745         do_div(freq, 10);
 746
 747         if (pll->flags & RADEON_PLL_USE_POST_DIV) {
 748                 post_div = pll->post_div;
 749                 if ((post_div < pll->min_post_div) || (post_div > pll->max_post_div))
 750                         goto done;
 751
 752                 vco_frequency = freq * post_div;
 753                 if ((vco_frequency < pll_out_min) || (vco_frequency > pll_out_max))
 754                         goto done;
 755
 756                 if (pll->flags & RADEON_PLL_USE_REF_DIV) {
 757                         ref_div = pll->reference_div;
 758                         if ((ref_div < pll->min_ref_div) || (ref_div > pll->max_ref_div))
 759                                 goto done;
 760                         if (!calc_fb_div(pll, freq, post_div, ref_div, &fb_div, &fb_div_frac))
 761                                 goto done;
 762                 }
 763         } else {
 764                 for (post_div = pll->max_post_div; post_div >= pll->min_post_div; --post_div) {
 765                         if (pll->flags & RADEON_PLL_LEGACY) {
 766                                 if ((post_div == 5) ||
 767                                     (post_div == 7) ||
 768                                     (post_div == 9) ||
 769                                     (post_div == 10) ||
 770                                     (post_div == 11))
 771                                         continue;
 772                         }
 773
 774                         if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
 775                                 continue;
 776
 777                         vco_frequency = freq * post_div;
 778                         if ((vco_frequency < pll_out_min) || (vco_frequency > pll_out_max))
 779                                 continue;
 780                         if (pll->flags & RADEON_PLL_USE_REF_DIV) {
 781                                 ref_div = pll->reference_div;
 782                                 if ((ref_div < pll->min_ref_div) || (ref_div > pll->max_ref_div))
 783                                         goto done;
 784                                 if (calc_fb_div(pll, freq, post_div, ref_div, &fb_div, &fb_div_frac))
 785                                         break;
 786                         } else {
 787                                 if (calc_fb_ref_div(pll, freq, post_div, &fb_div, &fb_div_frac, &ref_div))
 788                                         break;
 789                         }
 790                 }
 791         }
 792
 793         best_freq = pll->reference_freq * 10 * fb_div;
 794         best_freq += pll->reference_freq * fb_div_frac;
 795         best_freq = best_freq / (ref_div * post_div);
 796
 797 done:
 798         if (best_freq == 0)
 799                 DRM_ERROR("Couldn't find valid PLL dividers\n");
 800
 801         *dot_clock_p = best_freq / 10;
 802         *fb_div_p = fb_div;
 803         *frac_fb_div_p = fb_div_frac;
 804         *ref_div_p = ref_div;
 805         *post_div_p = post_div;
 806
 807         DRM_DEBUG("%u %d.%d, %d, %d\n", *dot_clock_p, *fb_div_p, *frac_fb_div_p, *ref_div_p, *post_div_p);
 808 }
 809
 810 void radeon_compute_pll(struct radeon_pll *pll,
 811                         uint64_t freq,
 812                         uint32_t *dot_clock_p,
 813                         uint32_t *fb_div_p,
 814                         uint32_t *frac_fb_div_p,
 815                         uint32_t *ref_div_p,
 816                         uint32_t *post_div_p)
 817 {
 818         switch (pll->algo) {
 819         case PLL_ALGO_NEW:
 820                 radeon_compute_pll_new(pll, freq, dot_clock_p, fb_div_p,
 821                                        frac_fb_div_p, ref_div_p, post_div_p);
 822                 break;
 823         case PLL_ALGO_LEGACY:
 824         default:
 825                 radeon_compute_pll_legacy(pll, freq, dot_clock_p, fb_div_p,
 826                                           frac_fb_div_p, ref_div_p, post_div_p);
 827                 break;
 828         }
 829 }
 830
 831 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
 832 {
 833         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
 834
 835         if (radeon_fb->obj)
 836                 drm_gem_object_unreference_unlocked(radeon_fb->obj);
 837         drm_framebuffer_cleanup(fb);
 838         kfree(radeon_fb);
 839 }
 840
 841 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
 842                                                   struct drm_file *file_priv,
 843                                                   unsigned int *handle)
 844 {
 845         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
 846
 847         return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
 848 }
 849
 850 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
 851         .destroy = radeon_user_framebuffer_destroy,
 852         .create_handle = radeon_user_framebuffer_create_handle,
 853 };
 854
 855 void
 856 radeon_framebuffer_init(struct drm_device *dev,
 857                         struct radeon_framebuffer *rfb,
 858                         struct drm_mode_fb_cmd *mode_cmd,
 859                         struct drm_gem_object *obj)
 860 {
 861         rfb->obj = obj;
 862         drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
 863         drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
 864 }
 865
 866 static struct drm_framebuffer *
 867 radeon_user_framebuffer_create(struct drm_device *dev,
 868                                struct drm_file *file_priv,
 869                                struct drm_mode_fb_cmd *mode_cmd)
 870 {
 871         struct drm_gem_object *obj;
 872         struct radeon_framebuffer *radeon_fb;
 873
 874         obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle);
 875         if (obj ==  NULL) {
 876                 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
 877                         "can't create framebuffer\n", mode_cmd->handle);
 878                 return NULL;
 879         }
 880
 881         radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
 882         if (radeon_fb == NULL) {
 883                 return NULL;
 884         }
 885
 886         radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
 887
 888         return &radeon_fb->base;
 889 }
 890
 891 static void radeon_output_poll_changed(struct drm_device *dev)
 892 {
 893         struct radeon_device *rdev = dev->dev_private;
 894         radeon_fb_output_poll_changed(rdev);
 895 }
 896
 897 static const struct drm_mode_config_funcs radeon_mode_funcs = {
 898         .fb_create = radeon_user_framebuffer_create,
 899         .output_poll_changed = radeon_output_poll_changed
 900 };
 901
 902 struct drm_prop_enum_list {
 903         int type;
 904         char *name;
 905 };
 906
 907 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
 908 {       { 0, "driver" },
 909         { 1, "bios" },
 910 };
 911
 912 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
 913 {       { TV_STD_NTSC, "ntsc" },
 914         { TV_STD_PAL, "pal" },
 915         { TV_STD_PAL_M, "pal-m" },
 916         { TV_STD_PAL_60, "pal-60" },
 917         { TV_STD_NTSC_J, "ntsc-j" },
 918         { TV_STD_SCART_PAL, "scart-pal" },
 919         { TV_STD_PAL_CN, "pal-cn" },
 920         { TV_STD_SECAM, "secam" },
 921 };
 922
 923 static int radeon_modeset_create_props(struct radeon_device *rdev)
 924 {
 925         int i, sz;
 926
 927         if (rdev->is_atom_bios) {
 928                 rdev->mode_info.coherent_mode_property =
 929                         drm_property_create(rdev->ddev,
 930                                             DRM_MODE_PROP_RANGE,
 931                                             "coherent", 2);
 932                 if (!rdev->mode_info.coherent_mode_property)
 933                         return -ENOMEM;
 934
 935                 rdev->mode_info.coherent_mode_property->values[0] = 0;
 936                 rdev->mode_info.coherent_mode_property->values[1] = 1;
 937         }
 938
 939         if (!ASIC_IS_AVIVO(rdev)) {
 940                 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
 941                 rdev->mode_info.tmds_pll_property =
 942                         drm_property_create(rdev->ddev,
 943                                             DRM_MODE_PROP_ENUM,
 944                                             "tmds_pll", sz);
 945                 for (i = 0; i < sz; i++) {
 946                         drm_property_add_enum(rdev->mode_info.tmds_pll_property,
 947                                               i,
 948                                               radeon_tmds_pll_enum_list[i].type,
 949                                               radeon_tmds_pll_enum_list[i].name);
 950                 }
 951         }
 952
 953         rdev->mode_info.load_detect_property =
 954                 drm_property_create(rdev->ddev,
 955                                     DRM_MODE_PROP_RANGE,
 956                                     "load detection", 2);
 957         if (!rdev->mode_info.load_detect_property)
 958                 return -ENOMEM;
 959         rdev->mode_info.load_detect_property->values[0] = 0;
 960         rdev->mode_info.load_detect_property->values[1] = 1;
 961
 962         drm_mode_create_scaling_mode_property(rdev->ddev);
 963
 964         sz = ARRAY_SIZE(radeon_tv_std_enum_list);
 965         rdev->mode_info.tv_std_property =
 966                 drm_property_create(rdev->ddev,
 967                                     DRM_MODE_PROP_ENUM,
 968                                     "tv standard", sz);
 969         for (i = 0; i < sz; i++) {
 970                 drm_property_add_enum(rdev->mode_info.tv_std_property,
 971                                       i,
 972                                       radeon_tv_std_enum_list[i].type,
 973                                       radeon_tv_std_enum_list[i].name);
 974         }
 975
 976         return 0;
 977 }
 978
 979 void radeon_update_display_priority(struct radeon_device *rdev)
 980 {
 981         /* adjustment options for the display watermarks */
 982         if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
 983                 /* set display priority to high for r3xx, rv515 chips
 984                  * this avoids flickering due to underflow to the
 985                  * display controllers during heavy acceleration.
 986                  * Don't force high on rs4xx igp chips as it seems to
 987                  * affect the sound card.  See kernel bug 15982.
 988                  */
 989                 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
 990                     !(rdev->flags & RADEON_IS_IGP))
 991                         rdev->disp_priority = 2;
 992                 else
 993                         rdev->disp_priority = 0;
 994         } else
 995                 rdev->disp_priority = radeon_disp_priority;
 996
 997 }
 998
 999 int radeon_modeset_init(struct radeon_device *rdev)
1000 {
1001         int i;
1002         int ret;
1003
1004         drm_mode_config_init(rdev->ddev);
1005         rdev->mode_info.mode_config_initialized = true;
1006
1007         rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs;
1008
1009         if (ASIC_IS_AVIVO(rdev)) {
1010                 rdev->ddev->mode_config.max_width = 8192;
1011                 rdev->ddev->mode_config.max_height = 8192;
1012         } else {
1013                 rdev->ddev->mode_config.max_width = 4096;
1014                 rdev->ddev->mode_config.max_height = 4096;
1015         }
1016
1017         rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1018
1019         ret = radeon_modeset_create_props(rdev);
1020         if (ret) {
1021                 return ret;
1022         }
1023
1024         /* check combios for a valid hardcoded EDID - Sun servers */
1025         if (!rdev->is_atom_bios) {
1026                 /* check for hardcoded EDID in BIOS */
1027                 radeon_combios_check_hardcoded_edid(rdev);
1028         }
1029
1030         /* allocate crtcs */
1031         for (i = 0; i < rdev->num_crtc; i++) {
1032                 radeon_crtc_init(rdev->ddev, i);
1033         }
1034
1035         /* okay we should have all the bios connectors */
1036         ret = radeon_setup_enc_conn(rdev->ddev);
1037         if (!ret) {
1038                 return ret;
1039         }
1040         /* initialize hpd */
1041         radeon_hpd_init(rdev);
1042
1043         /* Initialize power management */
1044         radeon_pm_init(rdev);
1045
1046         radeon_fbdev_init(rdev);
1047         drm_kms_helper_poll_init(rdev->ddev);
1048
1049         return 0;
1050 }
1051
1052 void radeon_modeset_fini(struct radeon_device *rdev)
1053 {
1054         radeon_fbdev_fini(rdev);
1055         kfree(rdev->mode_info.bios_hardcoded_edid);
1056         radeon_pm_fini(rdev);
1057
1058         if (rdev->mode_info.mode_config_initialized) {
1059                 drm_kms_helper_poll_fini(rdev->ddev);
1060                 radeon_hpd_fini(rdev);
1061                 drm_mode_config_cleanup(rdev->ddev);
1062                 rdev->mode_info.mode_config_initialized = false;
1063         }
1064 }
1065
1066 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1067                                 struct drm_display_mode *mode,
1068                                 struct drm_display_mode *adjusted_mode)
1069 {
1070         struct drm_device *dev = crtc->dev;
1071         struct drm_encoder *encoder;
1072         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1073         struct radeon_encoder *radeon_encoder;
1074         bool first = true;
1075
1076         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1077                 radeon_encoder = to_radeon_encoder(encoder);
1078                 if (encoder->crtc != crtc)
1079                         continue;
1080                 if (first) {
1081                         /* set scaling */
1082                         if (radeon_encoder->rmx_type == RMX_OFF)
1083                                 radeon_crtc->rmx_type = RMX_OFF;
1084                         else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1085                                  mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1086                                 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1087                         else
1088                                 radeon_crtc->rmx_type = RMX_OFF;
1089                         /* copy native mode */
1090                         memcpy(&radeon_crtc->native_mode,
1091                                &radeon_encoder->native_mode,
1092                                 sizeof(struct drm_display_mode));
1093                         first = false;
1094                 } else {
1095                         if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1096                                 /* WARNING: Right now this can't happen but
1097                                  * in the future we need to check that scaling
1098                                  * are consistent accross different encoder
1099                                  * (ie all encoder can work with the same
1100                                  *  scaling).
1101                                  */
1102                                 DRM_ERROR("Scaling not consistent accross encoder.\n");
1103                                 return false;
1104                         }
1105                 }
1106         }
1107         if (radeon_crtc->rmx_type != RMX_OFF) {
1108                 fixed20_12 a, b;
1109                 a.full = dfixed_const(crtc->mode.vdisplay);
1110                 b.full = dfixed_const(radeon_crtc->native_mode.hdisplay);
1111                 radeon_crtc->vsc.full = dfixed_div(a, b);
1112                 a.full = dfixed_const(crtc->mode.hdisplay);
1113                 b.full = dfixed_const(radeon_crtc->native_mode.vdisplay);
1114                 radeon_crtc->hsc.full = dfixed_div(a, b);
1115         } else {
1116                 radeon_crtc->vsc.full = dfixed_const(1);
1117                 radeon_crtc->hsc.full = dfixed_const(1);
1118         }
1119         return true;
1120 }