drivers/gpu/drm/radeon/radeon_device.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/console.h>
  29 #include <linux/slab.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm_crtc_helper.h>
  32 #include <drm/radeon_drm.h>
  33 #include <linux/vgaarb.h>
  34 #include <linux/vga_switcheroo.h>
  35 #include "radeon_reg.h"
  36 #include "radeon.h"
  37 #include "atom.h"
  38
  39 static const char radeon_family_name[][16] = {
  40         "R100",
  41         "RV100",
  42         "RS100",
  43         "RV200",
  44         "RS200",
  45         "R200",
  46         "RV250",
  47         "RS300",
  48         "RV280",
  49         "R300",
  50         "R350",
  51         "RV350",
  52         "RV380",
  53         "R420",
  54         "R423",
  55         "RV410",
  56         "RS400",
  57         "RS480",
  58         "RS600",
  59         "RS690",
  60         "RS740",
  61         "RV515",
  62         "R520",
  63         "RV530",
  64         "RV560",
  65         "RV570",
  66         "R580",
  67         "R600",
  68         "RV610",
  69         "RV630",
  70         "RV670",
  71         "RV620",
  72         "RV635",
  73         "RS780",
  74         "RS880",
  75         "RV770",
  76         "RV730",
  77         "RV710",
  78         "RV740",
  79         "CEDAR",
  80         "REDWOOD",
  81         "JUNIPER",
  82         "CYPRESS",
  83         "HEMLOCK",
  84         "PALM",
  85         "SUMO",
  86         "SUMO2",
  87         "BARTS",
  88         "TURKS",
  89         "CAICOS",
  90         "CAYMAN",
  91         "LAST",
  92 };
  93
  94 /*
  95  * Clear GPU surface registers.
  96  */
  97 void radeon_surface_init(struct radeon_device *rdev)
  98 {
  99         /* FIXME: check this out */
 100         if (rdev->family < CHIP_R600) {
 101                 int i;
 102
 103                 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
 104                         if (rdev->surface_regs[i].bo)
 105                                 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
 106                         else
 107                                 radeon_clear_surface_reg(rdev, i);
 108                 }
 109                 /* enable surfaces */
 110                 WREG32(RADEON_SURFACE_CNTL, 0);
 111         }
 112 }
 113
 114 /*
 115  * GPU scratch registers helpers function.
 116  */
 117 void radeon_scratch_init(struct radeon_device *rdev)
 118 {
 119         int i;
 120
 121         /* FIXME: check this out */
 122         if (rdev->family < CHIP_R300) {
 123                 rdev->scratch.num_reg = 5;
 124         } else {
 125                 rdev->scratch.num_reg = 7;
 126         }
 127         rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
 128         for (i = 0; i < rdev->scratch.num_reg; i++) {
 129                 rdev->scratch.free[i] = true;
 130                 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
 131         }
 132 }
 133
 134 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
 135 {
 136         int i;
 137
 138         for (i = 0; i < rdev->scratch.num_reg; i++) {
 139                 if (rdev->scratch.free[i]) {
 140                         rdev->scratch.free[i] = false;
 141                         *reg = rdev->scratch.reg[i];
 142                         return 0;
 143                 }
 144         }
 145         return -EINVAL;
 146 }
 147
 148 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
 149 {
 150         int i;
 151
 152         for (i = 0; i < rdev->scratch.num_reg; i++) {
 153                 if (rdev->scratch.reg[i] == reg) {
 154                         rdev->scratch.free[i] = true;
 155                         return;
 156                 }
 157         }
 158 }
 159
 160 void radeon_wb_disable(struct radeon_device *rdev)
 161 {
 162         int r;
 163
 164         if (rdev->wb.wb_obj) {
 165                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
 166                 if (unlikely(r != 0))
 167                         return;
 168                 radeon_bo_kunmap(rdev->wb.wb_obj);
 169                 radeon_bo_unpin(rdev->wb.wb_obj);
 170                 radeon_bo_unreserve(rdev->wb.wb_obj);
 171         }
 172         rdev->wb.enabled = false;
 173 }
 174
 175 void radeon_wb_fini(struct radeon_device *rdev)
 176 {
 177         radeon_wb_disable(rdev);
 178         if (rdev->wb.wb_obj) {
 179                 radeon_bo_unref(&rdev->wb.wb_obj);
 180                 rdev->wb.wb = NULL;
 181                 rdev->wb.wb_obj = NULL;
 182         }
 183 }
 184
 185 int radeon_wb_init(struct radeon_device *rdev)
 186 {
 187         int r;
 188
 189         if (rdev->wb.wb_obj == NULL) {
 190                 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
 191                                 RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj);
 192                 if (r) {
 193                         dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
 194                         return r;
 195                 }
 196         }
 197         r = radeon_bo_reserve(rdev->wb.wb_obj, false);
 198         if (unlikely(r != 0)) {
 199                 radeon_wb_fini(rdev);
 200                 return r;
 201         }
 202         r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
 203                           &rdev->wb.gpu_addr);
 204         if (r) {
 205                 radeon_bo_unreserve(rdev->wb.wb_obj);
 206                 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
 207                 radeon_wb_fini(rdev);
 208                 return r;
 209         }
 210         r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
 211         radeon_bo_unreserve(rdev->wb.wb_obj);
 212         if (r) {
 213                 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
 214                 radeon_wb_fini(rdev);
 215                 return r;
 216         }
 217
 218         /* clear wb memory */
 219         memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE);
 220         /* disable event_write fences */
 221         rdev->wb.use_event = false;
 222         /* disabled via module param */
 223         if (radeon_no_wb == 1)
 224                 rdev->wb.enabled = false;
 225         else {
 226                 /* often unreliable on AGP */
 227                 if (rdev->flags & RADEON_IS_AGP) {
 228                         rdev->wb.enabled = false;
 229                 } else {
 230                         rdev->wb.enabled = true;
 231                         /* event_write fences are only available on r600+ */
 232                         if (rdev->family >= CHIP_R600)
 233                                 rdev->wb.use_event = true;
 234                 }
 235         }
 236         /* always use writeback/events on NI */
 237         if (ASIC_IS_DCE5(rdev)) {
 238                 rdev->wb.enabled = true;
 239                 rdev->wb.use_event = true;
 240         }
 241
 242         dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
 243
 244         return 0;
 245 }
 246
 247 /**
 248  * radeon_vram_location - try to find VRAM location
 249  * @rdev: radeon device structure holding all necessary informations
 250  * @mc: memory controller structure holding memory informations
 251  * @base: base address at which to put VRAM
 252  *
 253  * Function will place try to place VRAM at base address provided
 254  * as parameter (which is so far either PCI aperture address or
 255  * for IGP TOM base address).
 256  *
 257  * If there is not enough space to fit the unvisible VRAM in the 32bits
 258  * address space then we limit the VRAM size to the aperture.
 259  *
 260  * If we are using AGP and if the AGP aperture doesn't allow us to have
 261  * room for all the VRAM than we restrict the VRAM to the PCI aperture
 262  * size and print a warning.
 263  *
 264  * This function will never fails, worst case are limiting VRAM.
 265  *
 266  * Note: GTT start, end, size should be initialized before calling this
 267  * function on AGP platform.
 268  *
 269  * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
 270  * this shouldn't be a problem as we are using the PCI aperture as a reference.
 271  * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
 272  * not IGP.
 273  *
 274  * Note: we use mc_vram_size as on some board we need to program the mc to
 275  * cover the whole aperture even if VRAM size is inferior to aperture size
 276  * Novell bug 204882 + along with lots of ubuntu ones
 277  *
 278  * Note: when limiting vram it's safe to overwritte real_vram_size because
 279  * we are not in case where real_vram_size is inferior to mc_vram_size (ie
 280  * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
 281  * ones)
 282  *
 283  * Note: IGP TOM addr should be the same as the aperture addr, we don't
 284  * explicitly check for that thought.
 285  *
 286  * FIXME: when reducing VRAM size align new size on power of 2.
 287  */
 288 void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
 289 {
 290         mc->vram_start = base;
 291         if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) {
 292                 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
 293                 mc->real_vram_size = mc->aper_size;
 294                 mc->mc_vram_size = mc->aper_size;
 295         }
 296         mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 297         if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
 298                 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
 299                 mc->real_vram_size = mc->aper_size;
 300                 mc->mc_vram_size = mc->aper_size;
 301         }
 302         mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 303         dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
 304                         mc->mc_vram_size >> 20, mc->vram_start,
 305                         mc->vram_end, mc->real_vram_size >> 20);
 306 }
 307
 308 /**
 309  * radeon_gtt_location - try to find GTT location
 310  * @rdev: radeon device structure holding all necessary informations
 311  * @mc: memory controller structure holding memory informations
 312  *
 313  * Function will place try to place GTT before or after VRAM.
 314  *
 315  * If GTT size is bigger than space left then we ajust GTT size.
 316  * Thus function will never fails.
 317  *
 318  * FIXME: when reducing GTT size align new size on power of 2.
 319  */
 320 void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
 321 {
 322         u64 size_af, size_bf;
 323
 324         size_af = ((0xFFFFFFFF - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
 325         size_bf = mc->vram_start & ~mc->gtt_base_align;
 326         if (size_bf > size_af) {
 327                 if (mc->gtt_size > size_bf) {
 328                         dev_warn(rdev->dev, "limiting GTT\n");
 329                         mc->gtt_size = size_bf;
 330                 }
 331                 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
 332         } else {
 333                 if (mc->gtt_size > size_af) {
 334                         dev_warn(rdev->dev, "limiting GTT\n");
 335                         mc->gtt_size = size_af;
 336                 }
 337                 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
 338         }
 339         mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
 340         dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
 341                         mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
 342 }
 343
 344 /*
 345  * GPU helpers function.
 346  */
 347 bool radeon_card_posted(struct radeon_device *rdev)
 348 {
 349         uint32_t reg;
 350
 351         /* first check CRTCs */
 352         if (ASIC_IS_DCE41(rdev)) {
 353                 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
 354                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
 355                 if (reg & EVERGREEN_CRTC_MASTER_EN)
 356                         return true;
 357         } else if (ASIC_IS_DCE4(rdev)) {
 358                 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
 359                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
 360                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
 361                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
 362                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
 363                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
 364                 if (reg & EVERGREEN_CRTC_MASTER_EN)
 365                         return true;
 366         } else if (ASIC_IS_AVIVO(rdev)) {
 367                 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
 368                       RREG32(AVIVO_D2CRTC_CONTROL);
 369                 if (reg & AVIVO_CRTC_EN) {
 370                         return true;
 371                 }
 372         } else {
 373                 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
 374                       RREG32(RADEON_CRTC2_GEN_CNTL);
 375                 if (reg & RADEON_CRTC_EN) {
 376                         return true;
 377                 }
 378         }
 379
 380         /* then check MEM_SIZE, in case the crtcs are off */
 381         if (rdev->family >= CHIP_R600)
 382                 reg = RREG32(R600_CONFIG_MEMSIZE);
 383         else
 384                 reg = RREG32(RADEON_CONFIG_MEMSIZE);
 385
 386         if (reg)
 387                 return true;
 388
 389         return false;
 390
 391 }
 392
 393 void radeon_update_bandwidth_info(struct radeon_device *rdev)
 394 {
 395         fixed20_12 a;
 396         u32 sclk = rdev->pm.current_sclk;
 397         u32 mclk = rdev->pm.current_mclk;
 398
 399         /* sclk/mclk in Mhz */
 400         a.full = dfixed_const(100);
 401         rdev->pm.sclk.full = dfixed_const(sclk);
 402         rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
 403         rdev->pm.mclk.full = dfixed_const(mclk);
 404         rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
 405
 406         if (rdev->flags & RADEON_IS_IGP) {
 407                 a.full = dfixed_const(16);
 408                 /* core_bandwidth = sclk(Mhz) * 16 */
 409                 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
 410         }
 411 }
 412
 413 bool radeon_boot_test_post_card(struct radeon_device *rdev)
 414 {
 415         if (radeon_card_posted(rdev))
 416                 return true;
 417
 418         if (rdev->bios) {
 419                 DRM_INFO("GPU not posted. posting now...\n");
 420                 if (rdev->is_atom_bios)
 421                         atom_asic_init(rdev->mode_info.atom_context);
 422                 else
 423                         radeon_combios_asic_init(rdev->ddev);
 424                 return true;
 425         } else {
 426                 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
 427                 return false;
 428         }
 429 }
 430
 431 int radeon_dummy_page_init(struct radeon_device *rdev)
 432 {
 433         if (rdev->dummy_page.page)
 434                 return 0;
 435         rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
 436         if (rdev->dummy_page.page == NULL)
 437                 return -ENOMEM;
 438         rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
 439                                         0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 440         if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) {
 441                 dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n");
 442                 __free_page(rdev->dummy_page.page);
 443                 rdev->dummy_page.page = NULL;
 444                 return -ENOMEM;
 445         }
 446         return 0;
 447 }
 448
 449 void radeon_dummy_page_fini(struct radeon_device *rdev)
 450 {
 451         if (rdev->dummy_page.page == NULL)
 452                 return;
 453         pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
 454                         PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 455         __free_page(rdev->dummy_page.page);
 456         rdev->dummy_page.page = NULL;
 457 }
 458
 459
 460 /* ATOM accessor methods */
 461 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
 462 {
 463         struct radeon_device *rdev = info->dev->dev_private;
 464         uint32_t r;
 465
 466         r = rdev->pll_rreg(rdev, reg);
 467         return r;
 468 }
 469
 470 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
 471 {
 472         struct radeon_device *rdev = info->dev->dev_private;
 473
 474         rdev->pll_wreg(rdev, reg, val);
 475 }
 476
 477 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
 478 {
 479         struct radeon_device *rdev = info->dev->dev_private;
 480         uint32_t r;
 481
 482         r = rdev->mc_rreg(rdev, reg);
 483         return r;
 484 }
 485
 486 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
 487 {
 488         struct radeon_device *rdev = info->dev->dev_private;
 489
 490         rdev->mc_wreg(rdev, reg, val);
 491 }
 492
 493 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
 494 {
 495         struct radeon_device *rdev = info->dev->dev_private;
 496
 497         WREG32(reg*4, val);
 498 }
 499
 500 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
 501 {
 502         struct radeon_device *rdev = info->dev->dev_private;
 503         uint32_t r;
 504
 505         r = RREG32(reg*4);
 506         return r;
 507 }
 508
 509 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
 510 {
 511         struct radeon_device *rdev = info->dev->dev_private;
 512
 513         WREG32_IO(reg*4, val);
 514 }
 515
 516 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
 517 {
 518         struct radeon_device *rdev = info->dev->dev_private;
 519         uint32_t r;
 520
 521         r = RREG32_IO(reg*4);
 522         return r;
 523 }
 524
 525 int radeon_atombios_init(struct radeon_device *rdev)
 526 {
 527         struct card_info *atom_card_info =
 528             kzalloc(sizeof(struct card_info), GFP_KERNEL);
 529
 530         if (!atom_card_info)
 531                 return -ENOMEM;
 532
 533         rdev->mode_info.atom_card_info = atom_card_info;
 534         atom_card_info->dev = rdev->ddev;
 535         atom_card_info->reg_read = cail_reg_read;
 536         atom_card_info->reg_write = cail_reg_write;
 537         /* needed for iio ops */
 538         if (rdev->rio_mem) {
 539                 atom_card_info->ioreg_read = cail_ioreg_read;
 540                 atom_card_info->ioreg_write = cail_ioreg_write;
 541         } else {
 542                 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
 543                 atom_card_info->ioreg_read = cail_reg_read;
 544                 atom_card_info->ioreg_write = cail_reg_write;
 545         }
 546         atom_card_info->mc_read = cail_mc_read;
 547         atom_card_info->mc_write = cail_mc_write;
 548         atom_card_info->pll_read = cail_pll_read;
 549         atom_card_info->pll_write = cail_pll_write;
 550
 551         rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
 552         mutex_init(&rdev->mode_info.atom_context->mutex);
 553         radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
 554         atom_allocate_fb_scratch(rdev->mode_info.atom_context);
 555         return 0;
 556 }
 557
 558 void radeon_atombios_fini(struct radeon_device *rdev)
 559 {
 560         if (rdev->mode_info.atom_context) {
 561                 kfree(rdev->mode_info.atom_context->scratch);
 562                 kfree(rdev->mode_info.atom_context);
 563         }
 564         kfree(rdev->mode_info.atom_card_info);
 565 }
 566
 567 int radeon_combios_init(struct radeon_device *rdev)
 568 {
 569         radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
 570         return 0;
 571 }
 572
 573 void radeon_combios_fini(struct radeon_device *rdev)
 574 {
 575 }
 576
 577 /* if we get transitioned to only one device, tak VGA back */
 578 static unsigned int radeon_vga_set_decode(void *cookie, bool state)
 579 {
 580         struct radeon_device *rdev = cookie;
 581         radeon_vga_set_state(rdev, state);
 582         if (state)
 583                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 584                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 585         else
 586                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 587 }
 588
 589 void radeon_check_arguments(struct radeon_device *rdev)
 590 {
 591         /* vramlimit must be a power of two */
 592         switch (radeon_vram_limit) {
 593         case 0:
 594         case 4:
 595         case 8:
 596         case 16:
 597         case 32:
 598         case 64:
 599         case 128:
 600         case 256:
 601         case 512:
 602         case 1024:
 603         case 2048:
 604         case 4096:
 605                 break;
 606         default:
 607                 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
 608                                 radeon_vram_limit);
 609                 radeon_vram_limit = 0;
 610                 break;
 611         }
 612         radeon_vram_limit = radeon_vram_limit << 20;
 613         /* gtt size must be power of two and greater or equal to 32M */
 614         switch (radeon_gart_size) {
 615         case 4:
 616         case 8:
 617         case 16:
 618                 dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n",
 619                                 radeon_gart_size);
 620                 radeon_gart_size = 512;
 621                 break;
 622         case 32:
 623         case 64:
 624         case 128:
 625         case 256:
 626         case 512:
 627         case 1024:
 628         case 2048:
 629         case 4096:
 630                 break;
 631         default:
 632                 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
 633                                 radeon_gart_size);
 634                 radeon_gart_size = 512;
 635                 break;
 636         }
 637         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 638         /* AGP mode can only be -1, 1, 2, 4, 8 */
 639         switch (radeon_agpmode) {
 640         case -1:
 641         case 0:
 642         case 1:
 643         case 2:
 644         case 4:
 645         case 8:
 646                 break;
 647         default:
 648                 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
 649                                 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
 650                 radeon_agpmode = 0;
 651                 break;
 652         }
 653 }
 654
 655 static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 656 {
 657         struct drm_device *dev = pci_get_drvdata(pdev);
 658         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 659         if (state == VGA_SWITCHEROO_ON) {
 660                 printk(KERN_INFO "radeon: switched on\n");
 661                 /* don't suspend or resume card normally */
 662                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 663                 radeon_resume_kms(dev);
 664                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 665                 drm_kms_helper_poll_enable(dev);
 666         } else {
 667                 printk(KERN_INFO "radeon: switched off\n");
 668                 drm_kms_helper_poll_disable(dev);
 669                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 670                 radeon_suspend_kms(dev, pmm);
 671                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 672         }
 673 }
 674
 675 static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
 676 {
 677         struct drm_device *dev = pci_get_drvdata(pdev);
 678         bool can_switch;
 679
 680         spin_lock(&dev->count_lock);
 681         can_switch = (dev->open_count == 0);
 682         spin_unlock(&dev->count_lock);
 683         return can_switch;
 684 }
 685
 686
 687 int radeon_device_init(struct radeon_device *rdev,
 688                        struct drm_device *ddev,
 689                        struct pci_dev *pdev,
 690                        uint32_t flags)
 691 {
 692         int r, i;
 693         int dma_bits;
 694
 695         rdev->shutdown = false;
 696         rdev->dev = &pdev->dev;
 697         rdev->ddev = ddev;
 698         rdev->pdev = pdev;
 699         rdev->flags = flags;
 700         rdev->family = flags & RADEON_FAMILY_MASK;
 701         rdev->is_atom_bios = false;
 702         rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
 703         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 704         rdev->gpu_lockup = false;
 705         rdev->accel_working = false;
 706
 707         DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X).\n",
 708                 radeon_family_name[rdev->family], pdev->vendor, pdev->device);
 709
 710         /* mutex initialization are all done here so we
 711          * can recall function without having locking issues */
 712         mutex_init(&rdev->cs_mutex);
 713         mutex_init(&rdev->ib_pool.mutex);
 714         mutex_init(&rdev->cp.mutex);
 715         mutex_init(&rdev->dc_hw_i2c_mutex);
 716         if (rdev->family >= CHIP_R600)
 717                 spin_lock_init(&rdev->ih.lock);
 718         mutex_init(&rdev->gem.mutex);
 719         mutex_init(&rdev->pm.mutex);
 720         mutex_init(&rdev->vram_mutex);
 721         rwlock_init(&rdev->fence_drv.lock);
 722         INIT_LIST_HEAD(&rdev->gem.objects);
 723         init_waitqueue_head(&rdev->irq.vblank_queue);
 724         init_waitqueue_head(&rdev->irq.idle_queue);
 725
 726         /* Set asic functions */
 727         r = radeon_asic_init(rdev);
 728         if (r)
 729                 return r;
 730         radeon_check_arguments(rdev);
 731
 732         /* all of the newer IGP chips have an internal gart
 733          * However some rs4xx report as AGP, so remove that here.
 734          */
 735         if ((rdev->family >= CHIP_RS400) &&
 736             (rdev->flags & RADEON_IS_IGP)) {
 737                 rdev->flags &= ~RADEON_IS_AGP;
 738         }
 739
 740         if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
 741                 radeon_agp_disable(rdev);
 742         }
 743
 744         /* set DMA mask + need_dma32 flags.
 745          * PCIE - can handle 40-bits.
 746          * IGP - can handle 40-bits (in theory)
 747          * AGP - generally dma32 is safest
 748          * PCI - only dma32
 749          */
 750         rdev->need_dma32 = false;
 751         if (rdev->flags & RADEON_IS_AGP)
 752                 rdev->need_dma32 = true;
 753         if (rdev->flags & RADEON_IS_PCI)
 754                 rdev->need_dma32 = true;
 755
 756         dma_bits = rdev->need_dma32 ? 32 : 40;
 757         r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
 758         if (r) {
 759                 rdev->need_dma32 = true;
 760                 printk(KERN_WARNING "radeon: No suitable DMA available.\n");
 761         }
 762
 763         /* Registers mapping */
 764         /* TODO: block userspace mapping of io register */
 765         rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
 766         rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
 767         rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
 768         if (rdev->rmmio == NULL) {
 769                 return -ENOMEM;
 770         }
 771         DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
 772         DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
 773
 774         /* io port mapping */
 775         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
 776                 if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) {
 777                         rdev->rio_mem_size = pci_resource_len(rdev->pdev, i);
 778                         rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
 779                         break;
 780                 }
 781         }
 782         if (rdev->rio_mem == NULL)
 783                 DRM_ERROR("Unable to find PCI I/O BAR\n");
 784
 785         /* if we have > 1 VGA cards, then disable the radeon VGA resources */
 786         /* this will fail for cards that aren't VGA class devices, just
 787          * ignore it */
 788         vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
 789         vga_switcheroo_register_client(rdev->pdev,
 790                                        radeon_switcheroo_set_state,
 791                                        NULL,
 792                                        radeon_switcheroo_can_switch);
 793
 794         r = radeon_init(rdev);
 795         if (r)
 796                 return r;
 797
 798         if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
 799                 /* Acceleration not working on AGP card try again
 800                  * with fallback to PCI or PCIE GART
 801                  */
 802                 radeon_asic_reset(rdev);
 803                 radeon_fini(rdev);
 804                 radeon_agp_disable(rdev);
 805                 r = radeon_init(rdev);
 806                 if (r)
 807                         return r;
 808         }
 809         if (radeon_testing) {
 810                 radeon_test_moves(rdev);
 811         }
 812         if (radeon_benchmarking) {
 813                 radeon_benchmark(rdev);
 814         }
 815         return 0;
 816 }
 817
 818 void radeon_device_fini(struct radeon_device *rdev)
 819 {
 820         DRM_INFO("radeon: finishing device.\n");
 821         rdev->shutdown = true;
 822         /* evict vram memory */
 823         radeon_bo_evict_vram(rdev);
 824         radeon_fini(rdev);
 825         vga_switcheroo_unregister_client(rdev->pdev);
 826         vga_client_register(rdev->pdev, NULL, NULL, NULL);
 827         if (rdev->rio_mem)
 828                 pci_iounmap(rdev->pdev, rdev->rio_mem);
 829         rdev->rio_mem = NULL;
 830         iounmap(rdev->rmmio);
 831         rdev->rmmio = NULL;
 832 }
 833
 834
 835 /*
 836  * Suspend & resume.
 837  */
 838 int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
 839 {
 840         struct radeon_device *rdev;
 841         struct drm_crtc *crtc;
 842         struct drm_connector *connector;
 843         int r;
 844
 845         if (dev == NULL || dev->dev_private == NULL) {
 846                 return -ENODEV;
 847         }
 848         if (state.event == PM_EVENT_PRETHAW) {
 849                 return 0;
 850         }
 851         rdev = dev->dev_private;
 852
 853         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 854                 return 0;
 855
 856         /* turn off display hw */
 857         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 858                 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
 859         }
 860
 861         /* unpin the front buffers */
 862         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 863                 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
 864                 struct radeon_bo *robj;
 865
 866                 if (rfb == NULL || rfb->obj == NULL) {
 867                         continue;
 868                 }
 869                 robj = gem_to_radeon_bo(rfb->obj);
 870                 /* don't unpin kernel fb objects */
 871                 if (!radeon_fbdev_robj_is_fb(rdev, robj)) {
 872                         r = radeon_bo_reserve(robj, false);
 873                         if (r == 0) {
 874                                 radeon_bo_unpin(robj);
 875                                 radeon_bo_unreserve(robj);
 876                         }
 877                 }
 878         }
 879         /* evict vram memory */
 880         radeon_bo_evict_vram(rdev);
 881         /* wait for gpu to finish processing current batch */
 882         radeon_fence_wait_last(rdev);
 883
 884         radeon_save_bios_scratch_regs(rdev);
 885
 886         radeon_pm_suspend(rdev);
 887         radeon_suspend(rdev);
 888         radeon_hpd_fini(rdev);
 889         /* evict remaining vram memory */
 890         radeon_bo_evict_vram(rdev);
 891
 892         radeon_agp_suspend(rdev);
 893
 894         pci_save_state(dev->pdev);
 895         if (state.event == PM_EVENT_SUSPEND) {
 896                 /* Shut down the device */
 897                 pci_disable_device(dev->pdev);
 898                 pci_set_power_state(dev->pdev, PCI_D3hot);
 899         }
 900         console_lock();
 901         radeon_fbdev_set_suspend(rdev, 1);
 902         console_unlock();
 903         return 0;
 904 }
 905
 906 int radeon_resume_kms(struct drm_device *dev)
 907 {
 908         struct drm_connector *connector;
 909         struct radeon_device *rdev = dev->dev_private;
 910
 911         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 912                 return 0;
 913
 914         console_lock();
 915         pci_set_power_state(dev->pdev, PCI_D0);
 916         pci_restore_state(dev->pdev);
 917         if (pci_enable_device(dev->pdev)) {
 918                 console_unlock();
 919                 return -1;
 920         }
 921         pci_set_master(dev->pdev);
 922         /* resume AGP if in use */
 923         radeon_agp_resume(rdev);
 924         radeon_resume(rdev);
 925         radeon_pm_resume(rdev);
 926         radeon_restore_bios_scratch_regs(rdev);
 927
 928         radeon_fbdev_set_suspend(rdev, 0);
 929         console_unlock();
 930
 931         /* init dig PHYs */
 932         if (rdev->is_atom_bios)
 933                 radeon_atom_encoder_init(rdev);
 934         /* reset hpd state */
 935         radeon_hpd_init(rdev);
 936         /* blat the mode back in */
 937         drm_helper_resume_force_mode(dev);
 938         /* turn on display hw */
 939         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 940                 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
 941         }
 942         return 0;
 943 }
 944
 945 int radeon_gpu_reset(struct radeon_device *rdev)
 946 {
 947         int r;
 948         int resched;
 949
 950         radeon_save_bios_scratch_regs(rdev);
 951         /* block TTM */
 952         resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
 953         radeon_suspend(rdev);
 954
 955         r = radeon_asic_reset(rdev);
 956         if (!r) {
 957                 dev_info(rdev->dev, "GPU reset succeed\n");
 958                 radeon_resume(rdev);
 959                 radeon_restore_bios_scratch_regs(rdev);
 960                 drm_helper_resume_force_mode(rdev->ddev);
 961                 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
 962                 return 0;
 963         }
 964         /* bad news, how to tell it to userspace ? */
 965         dev_info(rdev->dev, "GPU reset failed\n");
 966         return r;
 967 }
 968
 969
 970 /*
 971  * Debugfs
 972  */
 973 struct radeon_debugfs {
 974         struct drm_info_list    *files;
 975         unsigned                num_files;
 976 };
 977 static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES];
 978 static unsigned _radeon_debugfs_count = 0;
 979
 980 int radeon_debugfs_add_files(struct radeon_device *rdev,
 981                              struct drm_info_list *files,
 982                              unsigned nfiles)
 983 {
 984         unsigned i;
 985
 986         for (i = 0; i < _radeon_debugfs_count; i++) {
 987                 if (_radeon_debugfs[i].files == files) {
 988                         /* Already registered */
 989                         return 0;
 990                 }
 991         }
 992         if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) {
 993                 DRM_ERROR("Reached maximum number of debugfs files.\n");
 994                 DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n");
 995                 return -EINVAL;
 996         }
 997         _radeon_debugfs[_radeon_debugfs_count].files = files;
 998         _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles;
 999         _radeon_debugfs_count++;
1000 #if defined(CONFIG_DEBUG_FS)
1001         drm_debugfs_create_files(files, nfiles,
1002                                  rdev->ddev->control->debugfs_root,
1003                                  rdev->ddev->control);
1004         drm_debugfs_create_files(files, nfiles,
1005                                  rdev->ddev->primary->debugfs_root,
1006                                  rdev->ddev->primary);
1007 #endif
1008         return 0;
1009 }
1010
1011 #if defined(CONFIG_DEBUG_FS)
1012 int radeon_debugfs_init(struct drm_minor *minor)
1013 {
1014         return 0;
1015 }
1016
1017 void radeon_debugfs_cleanup(struct drm_minor *minor)
1018 {
1019         unsigned i;
1020
1021         for (i = 0; i < _radeon_debugfs_count; i++) {
1022                 drm_debugfs_remove_files(_radeon_debugfs[i].files,
1023                                          _radeon_debugfs[i].num_files, minor);
1024         }
1025 }
1026 #endif