drivers/gpu/drm/radeon/radeon_combios.c

   1 /*
   2  * Copyright 2004 ATI Technologies Inc., Markham, Ontario
   3  * Copyright 2007-8 Advanced Micro Devices, Inc.
   4  * Copyright 2008 Red Hat Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  */
  27 #include "drmP.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 #ifdef CONFIG_PPC_PMAC
  33 /* not sure which of these are needed */
  34 #include <asm/machdep.h>
  35 #include <asm/pmac_feature.h>
  36 #include <asm/prom.h>
  37 #include <asm/pci-bridge.h>
  38 #endif /* CONFIG_PPC_PMAC */
  39
  40 /* from radeon_encoder.c */
  41 extern uint32_t
  42 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
  43                         uint8_t dac);
  44 extern void radeon_link_encoder_connector(struct drm_device *dev);
  45
  46 /* from radeon_connector.c */
  47 extern void
  48 radeon_add_legacy_connector(struct drm_device *dev,
  49                             uint32_t connector_id,
  50                             uint32_t supported_device,
  51                             int connector_type,
  52                             struct radeon_i2c_bus_rec *i2c_bus,
  53                             uint16_t connector_object_id,
  54                             struct radeon_hpd *hpd);
  55
  56 /* from radeon_legacy_encoder.c */
  57 extern void
  58 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
  59                           uint32_t supported_device);
  60
  61 /* old legacy ATI BIOS routines */
  62
  63 /* COMBIOS table offsets */
  64 enum radeon_combios_table_offset {
  65         /* absolute offset tables */
  66         COMBIOS_ASIC_INIT_1_TABLE,
  67         COMBIOS_BIOS_SUPPORT_TABLE,
  68         COMBIOS_DAC_PROGRAMMING_TABLE,
  69         COMBIOS_MAX_COLOR_DEPTH_TABLE,
  70         COMBIOS_CRTC_INFO_TABLE,
  71         COMBIOS_PLL_INFO_TABLE,
  72         COMBIOS_TV_INFO_TABLE,
  73         COMBIOS_DFP_INFO_TABLE,
  74         COMBIOS_HW_CONFIG_INFO_TABLE,
  75         COMBIOS_MULTIMEDIA_INFO_TABLE,
  76         COMBIOS_TV_STD_PATCH_TABLE,
  77         COMBIOS_LCD_INFO_TABLE,
  78         COMBIOS_MOBILE_INFO_TABLE,
  79         COMBIOS_PLL_INIT_TABLE,
  80         COMBIOS_MEM_CONFIG_TABLE,
  81         COMBIOS_SAVE_MASK_TABLE,
  82         COMBIOS_HARDCODED_EDID_TABLE,
  83         COMBIOS_ASIC_INIT_2_TABLE,
  84         COMBIOS_CONNECTOR_INFO_TABLE,
  85         COMBIOS_DYN_CLK_1_TABLE,
  86         COMBIOS_RESERVED_MEM_TABLE,
  87         COMBIOS_EXT_TMDS_INFO_TABLE,
  88         COMBIOS_MEM_CLK_INFO_TABLE,
  89         COMBIOS_EXT_DAC_INFO_TABLE,
  90         COMBIOS_MISC_INFO_TABLE,
  91         COMBIOS_CRT_INFO_TABLE,
  92         COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
  93         COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
  94         COMBIOS_FAN_SPEED_INFO_TABLE,
  95         COMBIOS_OVERDRIVE_INFO_TABLE,
  96         COMBIOS_OEM_INFO_TABLE,
  97         COMBIOS_DYN_CLK_2_TABLE,
  98         COMBIOS_POWER_CONNECTOR_INFO_TABLE,
  99         COMBIOS_I2C_INFO_TABLE,
 100         /* relative offset tables */
 101         COMBIOS_ASIC_INIT_3_TABLE,      /* offset from misc info */
 102         COMBIOS_ASIC_INIT_4_TABLE,      /* offset from misc info */
 103         COMBIOS_DETECTED_MEM_TABLE,     /* offset from misc info */
 104         COMBIOS_ASIC_INIT_5_TABLE,      /* offset from misc info */
 105         COMBIOS_RAM_RESET_TABLE,        /* offset from mem config */
 106         COMBIOS_POWERPLAY_INFO_TABLE,   /* offset from mobile info */
 107         COMBIOS_GPIO_INFO_TABLE,        /* offset from mobile info */
 108         COMBIOS_LCD_DDC_INFO_TABLE,     /* offset from mobile info */
 109         COMBIOS_TMDS_POWER_TABLE,       /* offset from mobile info */
 110         COMBIOS_TMDS_POWER_ON_TABLE,    /* offset from tmds power */
 111         COMBIOS_TMDS_POWER_OFF_TABLE,   /* offset from tmds power */
 112 };
 113
 114 enum radeon_combios_ddc {
 115         DDC_NONE_DETECTED,
 116         DDC_MONID,
 117         DDC_DVI,
 118         DDC_VGA,
 119         DDC_CRT2,
 120         DDC_LCD,
 121         DDC_GPIO,
 122 };
 123
 124 enum radeon_combios_connector {
 125         CONNECTOR_NONE_LEGACY,
 126         CONNECTOR_PROPRIETARY_LEGACY,
 127         CONNECTOR_CRT_LEGACY,
 128         CONNECTOR_DVI_I_LEGACY,
 129         CONNECTOR_DVI_D_LEGACY,
 130         CONNECTOR_CTV_LEGACY,
 131         CONNECTOR_STV_LEGACY,
 132         CONNECTOR_UNSUPPORTED_LEGACY
 133 };
 134
 135 const int legacy_connector_convert[] = {
 136         DRM_MODE_CONNECTOR_Unknown,
 137         DRM_MODE_CONNECTOR_DVID,
 138         DRM_MODE_CONNECTOR_VGA,
 139         DRM_MODE_CONNECTOR_DVII,
 140         DRM_MODE_CONNECTOR_DVID,
 141         DRM_MODE_CONNECTOR_Composite,
 142         DRM_MODE_CONNECTOR_SVIDEO,
 143         DRM_MODE_CONNECTOR_Unknown,
 144 };
 145
 146 static uint16_t combios_get_table_offset(struct drm_device *dev,
 147                                          enum radeon_combios_table_offset table)
 148 {
 149         struct radeon_device *rdev = dev->dev_private;
 150         int rev;
 151         uint16_t offset = 0, check_offset;
 152
 153         if (!rdev->bios)
 154                 return 0;
 155
 156         switch (table) {
 157                 /* absolute offset tables */
 158         case COMBIOS_ASIC_INIT_1_TABLE:
 159                 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
 160                 if (check_offset)
 161                         offset = check_offset;
 162                 break;
 163         case COMBIOS_BIOS_SUPPORT_TABLE:
 164                 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
 165                 if (check_offset)
 166                         offset = check_offset;
 167                 break;
 168         case COMBIOS_DAC_PROGRAMMING_TABLE:
 169                 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
 170                 if (check_offset)
 171                         offset = check_offset;
 172                 break;
 173         case COMBIOS_MAX_COLOR_DEPTH_TABLE:
 174                 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
 175                 if (check_offset)
 176                         offset = check_offset;
 177                 break;
 178         case COMBIOS_CRTC_INFO_TABLE:
 179                 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
 180                 if (check_offset)
 181                         offset = check_offset;
 182                 break;
 183         case COMBIOS_PLL_INFO_TABLE:
 184                 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
 185                 if (check_offset)
 186                         offset = check_offset;
 187                 break;
 188         case COMBIOS_TV_INFO_TABLE:
 189                 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
 190                 if (check_offset)
 191                         offset = check_offset;
 192                 break;
 193         case COMBIOS_DFP_INFO_TABLE:
 194                 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
 195                 if (check_offset)
 196                         offset = check_offset;
 197                 break;
 198         case COMBIOS_HW_CONFIG_INFO_TABLE:
 199                 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
 200                 if (check_offset)
 201                         offset = check_offset;
 202                 break;
 203         case COMBIOS_MULTIMEDIA_INFO_TABLE:
 204                 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
 205                 if (check_offset)
 206                         offset = check_offset;
 207                 break;
 208         case COMBIOS_TV_STD_PATCH_TABLE:
 209                 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
 210                 if (check_offset)
 211                         offset = check_offset;
 212                 break;
 213         case COMBIOS_LCD_INFO_TABLE:
 214                 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
 215                 if (check_offset)
 216                         offset = check_offset;
 217                 break;
 218         case COMBIOS_MOBILE_INFO_TABLE:
 219                 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
 220                 if (check_offset)
 221                         offset = check_offset;
 222                 break;
 223         case COMBIOS_PLL_INIT_TABLE:
 224                 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
 225                 if (check_offset)
 226                         offset = check_offset;
 227                 break;
 228         case COMBIOS_MEM_CONFIG_TABLE:
 229                 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
 230                 if (check_offset)
 231                         offset = check_offset;
 232                 break;
 233         case COMBIOS_SAVE_MASK_TABLE:
 234                 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
 235                 if (check_offset)
 236                         offset = check_offset;
 237                 break;
 238         case COMBIOS_HARDCODED_EDID_TABLE:
 239                 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
 240                 if (check_offset)
 241                         offset = check_offset;
 242                 break;
 243         case COMBIOS_ASIC_INIT_2_TABLE:
 244                 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
 245                 if (check_offset)
 246                         offset = check_offset;
 247                 break;
 248         case COMBIOS_CONNECTOR_INFO_TABLE:
 249                 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
 250                 if (check_offset)
 251                         offset = check_offset;
 252                 break;
 253         case COMBIOS_DYN_CLK_1_TABLE:
 254                 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
 255                 if (check_offset)
 256                         offset = check_offset;
 257                 break;
 258         case COMBIOS_RESERVED_MEM_TABLE:
 259                 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
 260                 if (check_offset)
 261                         offset = check_offset;
 262                 break;
 263         case COMBIOS_EXT_TMDS_INFO_TABLE:
 264                 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
 265                 if (check_offset)
 266                         offset = check_offset;
 267                 break;
 268         case COMBIOS_MEM_CLK_INFO_TABLE:
 269                 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
 270                 if (check_offset)
 271                         offset = check_offset;
 272                 break;
 273         case COMBIOS_EXT_DAC_INFO_TABLE:
 274                 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
 275                 if (check_offset)
 276                         offset = check_offset;
 277                 break;
 278         case COMBIOS_MISC_INFO_TABLE:
 279                 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
 280                 if (check_offset)
 281                         offset = check_offset;
 282                 break;
 283         case COMBIOS_CRT_INFO_TABLE:
 284                 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
 285                 if (check_offset)
 286                         offset = check_offset;
 287                 break;
 288         case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
 289                 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
 290                 if (check_offset)
 291                         offset = check_offset;
 292                 break;
 293         case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
 294                 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
 295                 if (check_offset)
 296                         offset = check_offset;
 297                 break;
 298         case COMBIOS_FAN_SPEED_INFO_TABLE:
 299                 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
 300                 if (check_offset)
 301                         offset = check_offset;
 302                 break;
 303         case COMBIOS_OVERDRIVE_INFO_TABLE:
 304                 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
 305                 if (check_offset)
 306                         offset = check_offset;
 307                 break;
 308         case COMBIOS_OEM_INFO_TABLE:
 309                 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
 310                 if (check_offset)
 311                         offset = check_offset;
 312                 break;
 313         case COMBIOS_DYN_CLK_2_TABLE:
 314                 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
 315                 if (check_offset)
 316                         offset = check_offset;
 317                 break;
 318         case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
 319                 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
 320                 if (check_offset)
 321                         offset = check_offset;
 322                 break;
 323         case COMBIOS_I2C_INFO_TABLE:
 324                 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
 325                 if (check_offset)
 326                         offset = check_offset;
 327                 break;
 328                 /* relative offset tables */
 329         case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
 330                 check_offset =
 331                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 332                 if (check_offset) {
 333                         rev = RBIOS8(check_offset);
 334                         if (rev > 0) {
 335                                 check_offset = RBIOS16(check_offset + 0x3);
 336                                 if (check_offset)
 337                                         offset = check_offset;
 338                         }
 339                 }
 340                 break;
 341         case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
 342                 check_offset =
 343                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 344                 if (check_offset) {
 345                         rev = RBIOS8(check_offset);
 346                         if (rev > 0) {
 347                                 check_offset = RBIOS16(check_offset + 0x5);
 348                                 if (check_offset)
 349                                         offset = check_offset;
 350                         }
 351                 }
 352                 break;
 353         case COMBIOS_DETECTED_MEM_TABLE:        /* offset from misc info */
 354                 check_offset =
 355                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 356                 if (check_offset) {
 357                         rev = RBIOS8(check_offset);
 358                         if (rev > 0) {
 359                                 check_offset = RBIOS16(check_offset + 0x7);
 360                                 if (check_offset)
 361                                         offset = check_offset;
 362                         }
 363                 }
 364                 break;
 365         case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
 366                 check_offset =
 367                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 368                 if (check_offset) {
 369                         rev = RBIOS8(check_offset);
 370                         if (rev == 2) {
 371                                 check_offset = RBIOS16(check_offset + 0x9);
 372                                 if (check_offset)
 373                                         offset = check_offset;
 374                         }
 375                 }
 376                 break;
 377         case COMBIOS_RAM_RESET_TABLE:   /* offset from mem config */
 378                 check_offset =
 379                     combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
 380                 if (check_offset) {
 381                         while (RBIOS8(check_offset++));
 382                         check_offset += 2;
 383                         if (check_offset)
 384                                 offset = check_offset;
 385                 }
 386                 break;
 387         case COMBIOS_POWERPLAY_INFO_TABLE:      /* offset from mobile info */
 388                 check_offset =
 389                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 390                 if (check_offset) {
 391                         check_offset = RBIOS16(check_offset + 0x11);
 392                         if (check_offset)
 393                                 offset = check_offset;
 394                 }
 395                 break;
 396         case COMBIOS_GPIO_INFO_TABLE:   /* offset from mobile info */
 397                 check_offset =
 398                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 399                 if (check_offset) {
 400                         check_offset = RBIOS16(check_offset + 0x13);
 401                         if (check_offset)
 402                                 offset = check_offset;
 403                 }
 404                 break;
 405         case COMBIOS_LCD_DDC_INFO_TABLE:        /* offset from mobile info */
 406                 check_offset =
 407                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 408                 if (check_offset) {
 409                         check_offset = RBIOS16(check_offset + 0x15);
 410                         if (check_offset)
 411                                 offset = check_offset;
 412                 }
 413                 break;
 414         case COMBIOS_TMDS_POWER_TABLE:  /* offset from mobile info */
 415                 check_offset =
 416                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 417                 if (check_offset) {
 418                         check_offset = RBIOS16(check_offset + 0x17);
 419                         if (check_offset)
 420                                 offset = check_offset;
 421                 }
 422                 break;
 423         case COMBIOS_TMDS_POWER_ON_TABLE:       /* offset from tmds power */
 424                 check_offset =
 425                     combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 426                 if (check_offset) {
 427                         check_offset = RBIOS16(check_offset + 0x2);
 428                         if (check_offset)
 429                                 offset = check_offset;
 430                 }
 431                 break;
 432         case COMBIOS_TMDS_POWER_OFF_TABLE:      /* offset from tmds power */
 433                 check_offset =
 434                     combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 435                 if (check_offset) {
 436                         check_offset = RBIOS16(check_offset + 0x4);
 437                         if (check_offset)
 438                                 offset = check_offset;
 439                 }
 440                 break;
 441         default:
 442                 break;
 443         }
 444
 445         return offset;
 446
 447 }
 448
 449 bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
 450 {
 451         int edid_info, size;
 452         struct edid *edid;
 453         unsigned char *raw;
 454         edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
 455         if (!edid_info)
 456                 return false;
 457
 458         raw = rdev->bios + edid_info;
 459         size = EDID_LENGTH * (raw[0x7e] + 1);
 460         edid = kmalloc(size, GFP_KERNEL);
 461         if (edid == NULL)
 462                 return false;
 463
 464         memcpy((unsigned char *)edid, raw, size);
 465
 466         if (!drm_edid_is_valid(edid)) {
 467                 kfree(edid);
 468                 return false;
 469         }
 470
 471         rdev->mode_info.bios_hardcoded_edid = edid;
 472         rdev->mode_info.bios_hardcoded_edid_size = size;
 473         return true;
 474 }
 475
 476 /* this is used for atom LCDs as well */
 477 struct edid *
 478 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev)
 479 {
 480         struct edid *edid;
 481
 482         if (rdev->mode_info.bios_hardcoded_edid) {
 483                 edid = kmalloc(rdev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
 484                 if (edid) {
 485                         memcpy((unsigned char *)edid,
 486                                (unsigned char *)rdev->mode_info.bios_hardcoded_edid,
 487                                rdev->mode_info.bios_hardcoded_edid_size);
 488                         return edid;
 489                 }
 490         }
 491         return NULL;
 492 }
 493
 494 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
 495                                                        enum radeon_combios_ddc ddc,
 496                                                        u32 clk_mask,
 497                                                        u32 data_mask)
 498 {
 499         struct radeon_i2c_bus_rec i2c;
 500         int ddc_line = 0;
 501
 502         /* ddc id            = mask reg
 503          * DDC_NONE_DETECTED = none
 504          * DDC_DVI           = RADEON_GPIO_DVI_DDC
 505          * DDC_VGA           = RADEON_GPIO_VGA_DDC
 506          * DDC_LCD           = RADEON_GPIOPAD_MASK
 507          * DDC_GPIO          = RADEON_MDGPIO_MASK
 508          * r1xx
 509          * DDC_MONID         = RADEON_GPIO_MONID
 510          * DDC_CRT2          = RADEON_GPIO_CRT2_DDC
 511          * r200
 512          * DDC_MONID         = RADEON_GPIO_MONID
 513          * DDC_CRT2          = RADEON_GPIO_DVI_DDC
 514          * r300/r350
 515          * DDC_MONID         = RADEON_GPIO_DVI_DDC
 516          * DDC_CRT2          = RADEON_GPIO_DVI_DDC
 517          * rv2xx/rv3xx
 518          * DDC_MONID         = RADEON_GPIO_MONID
 519          * DDC_CRT2          = RADEON_GPIO_MONID
 520          * rs3xx/rs4xx
 521          * DDC_MONID         = RADEON_GPIOPAD_MASK
 522          * DDC_CRT2          = RADEON_GPIO_MONID
 523          */
 524         switch (ddc) {
 525         case DDC_NONE_DETECTED:
 526         default:
 527                 ddc_line = 0;
 528                 break;
 529         case DDC_DVI:
 530                 ddc_line = RADEON_GPIO_DVI_DDC;
 531                 break;
 532         case DDC_VGA:
 533                 ddc_line = RADEON_GPIO_VGA_DDC;
 534                 break;
 535         case DDC_LCD:
 536                 ddc_line = RADEON_GPIOPAD_MASK;
 537                 break;
 538         case DDC_GPIO:
 539                 ddc_line = RADEON_MDGPIO_MASK;
 540                 break;
 541         case DDC_MONID:
 542                 if (rdev->family == CHIP_RS300 ||
 543                     rdev->family == CHIP_RS400 ||
 544                     rdev->family == CHIP_RS480)
 545                         ddc_line = RADEON_GPIOPAD_MASK;
 546                 else if (rdev->family == CHIP_R300 ||
 547                          rdev->family == CHIP_R350) {
 548                         ddc_line = RADEON_GPIO_DVI_DDC;
 549                         ddc = DDC_DVI;
 550                 } else
 551                         ddc_line = RADEON_GPIO_MONID;
 552                 break;
 553         case DDC_CRT2:
 554                 if (rdev->family == CHIP_R200 ||
 555                     rdev->family == CHIP_R300 ||
 556                     rdev->family == CHIP_R350) {
 557                         ddc_line = RADEON_GPIO_DVI_DDC;
 558                         ddc = DDC_DVI;
 559                 } else if (rdev->family == CHIP_RS300 ||
 560                            rdev->family == CHIP_RS400 ||
 561                            rdev->family == CHIP_RS480)
 562                         ddc_line = RADEON_GPIO_MONID;
 563                 else if (rdev->family >= CHIP_RV350) {
 564                         ddc_line = RADEON_GPIO_MONID;
 565                         ddc = DDC_MONID;
 566                 } else
 567                         ddc_line = RADEON_GPIO_CRT2_DDC;
 568                 break;
 569         }
 570
 571         if (ddc_line == RADEON_GPIOPAD_MASK) {
 572                 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
 573                 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
 574                 i2c.a_clk_reg = RADEON_GPIOPAD_A;
 575                 i2c.a_data_reg = RADEON_GPIOPAD_A;
 576                 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
 577                 i2c.en_data_reg = RADEON_GPIOPAD_EN;
 578                 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
 579                 i2c.y_data_reg = RADEON_GPIOPAD_Y;
 580         } else if (ddc_line == RADEON_MDGPIO_MASK) {
 581                 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
 582                 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
 583                 i2c.a_clk_reg = RADEON_MDGPIO_A;
 584                 i2c.a_data_reg = RADEON_MDGPIO_A;
 585                 i2c.en_clk_reg = RADEON_MDGPIO_EN;
 586                 i2c.en_data_reg = RADEON_MDGPIO_EN;
 587                 i2c.y_clk_reg = RADEON_MDGPIO_Y;
 588                 i2c.y_data_reg = RADEON_MDGPIO_Y;
 589         } else {
 590                 i2c.mask_clk_reg = ddc_line;
 591                 i2c.mask_data_reg = ddc_line;
 592                 i2c.a_clk_reg = ddc_line;
 593                 i2c.a_data_reg = ddc_line;
 594                 i2c.en_clk_reg = ddc_line;
 595                 i2c.en_data_reg = ddc_line;
 596                 i2c.y_clk_reg = ddc_line;
 597                 i2c.y_data_reg = ddc_line;
 598         }
 599
 600         if (clk_mask && data_mask) {
 601                 /* system specific masks */
 602                 i2c.mask_clk_mask = clk_mask;
 603                 i2c.mask_data_mask = data_mask;
 604                 i2c.a_clk_mask = clk_mask;
 605                 i2c.a_data_mask = data_mask;
 606                 i2c.en_clk_mask = clk_mask;
 607                 i2c.en_data_mask = data_mask;
 608                 i2c.y_clk_mask = clk_mask;
 609                 i2c.y_data_mask = data_mask;
 610         } else if ((ddc_line == RADEON_GPIOPAD_MASK) ||
 611                    (ddc_line == RADEON_MDGPIO_MASK)) {
 612                 /* default gpiopad masks */
 613                 i2c.mask_clk_mask = (0x20 << 8);
 614                 i2c.mask_data_mask = 0x80;
 615                 i2c.a_clk_mask = (0x20 << 8);
 616                 i2c.a_data_mask = 0x80;
 617                 i2c.en_clk_mask = (0x20 << 8);
 618                 i2c.en_data_mask = 0x80;
 619                 i2c.y_clk_mask = (0x20 << 8);
 620                 i2c.y_data_mask = 0x80;
 621         } else {
 622                 /* default masks for ddc pads */
 623                 i2c.mask_clk_mask = RADEON_GPIO_EN_1;
 624                 i2c.mask_data_mask = RADEON_GPIO_EN_0;
 625                 i2c.a_clk_mask = RADEON_GPIO_A_1;
 626                 i2c.a_data_mask = RADEON_GPIO_A_0;
 627                 i2c.en_clk_mask = RADEON_GPIO_EN_1;
 628                 i2c.en_data_mask = RADEON_GPIO_EN_0;
 629                 i2c.y_clk_mask = RADEON_GPIO_Y_1;
 630                 i2c.y_data_mask = RADEON_GPIO_Y_0;
 631         }
 632
 633         switch (rdev->family) {
 634         case CHIP_R100:
 635         case CHIP_RV100:
 636         case CHIP_RS100:
 637         case CHIP_RV200:
 638         case CHIP_RS200:
 639         case CHIP_RS300:
 640                 switch (ddc_line) {
 641                 case RADEON_GPIO_DVI_DDC:
 642                         i2c.hw_capable = true;
 643                         break;
 644                 default:
 645                         i2c.hw_capable = false;
 646                         break;
 647                 }
 648                 break;
 649         case CHIP_R200:
 650                 switch (ddc_line) {
 651                 case RADEON_GPIO_DVI_DDC:
 652                 case RADEON_GPIO_MONID:
 653                         i2c.hw_capable = true;
 654                         break;
 655                 default:
 656                         i2c.hw_capable = false;
 657                         break;
 658                 }
 659                 break;
 660         case CHIP_RV250:
 661         case CHIP_RV280:
 662                 switch (ddc_line) {
 663                 case RADEON_GPIO_VGA_DDC:
 664                 case RADEON_GPIO_DVI_DDC:
 665                 case RADEON_GPIO_CRT2_DDC:
 666                         i2c.hw_capable = true;
 667                         break;
 668                 default:
 669                         i2c.hw_capable = false;
 670                         break;
 671                 }
 672                 break;
 673         case CHIP_R300:
 674         case CHIP_R350:
 675                 switch (ddc_line) {
 676                 case RADEON_GPIO_VGA_DDC:
 677                 case RADEON_GPIO_DVI_DDC:
 678                         i2c.hw_capable = true;
 679                         break;
 680                 default:
 681                         i2c.hw_capable = false;
 682                         break;
 683                 }
 684                 break;
 685         case CHIP_RV350:
 686         case CHIP_RV380:
 687         case CHIP_RS400:
 688         case CHIP_RS480:
 689                 switch (ddc_line) {
 690                 case RADEON_GPIO_VGA_DDC:
 691                 case RADEON_GPIO_DVI_DDC:
 692                         i2c.hw_capable = true;
 693                         break;
 694                 case RADEON_GPIO_MONID:
 695                         /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
 696                          * reliably on some pre-r4xx hardware; not sure why.
 697                          */
 698                         i2c.hw_capable = false;
 699                         break;
 700                 default:
 701                         i2c.hw_capable = false;
 702                         break;
 703                 }
 704                 break;
 705         default:
 706                 i2c.hw_capable = false;
 707                 break;
 708         }
 709         i2c.mm_i2c = false;
 710
 711         i2c.i2c_id = ddc;
 712         i2c.hpd = RADEON_HPD_NONE;
 713
 714         if (ddc_line)
 715                 i2c.valid = true;
 716         else
 717                 i2c.valid = false;
 718
 719         return i2c;
 720 }
 721
 722 void radeon_combios_i2c_init(struct radeon_device *rdev)
 723 {
 724         struct drm_device *dev = rdev->ddev;
 725         struct radeon_i2c_bus_rec i2c;
 726
 727         /* actual hw pads
 728          * r1xx/rs2xx/rs3xx
 729          * 0x60, 0x64, 0x68, 0x6c, gpiopads, mm
 730          * r200
 731          * 0x60, 0x64, 0x68, mm
 732          * r300/r350
 733          * 0x60, 0x64, mm
 734          * rv2xx/rv3xx/rs4xx
 735          * 0x60, 0x64, 0x68, gpiopads, mm
 736          */
 737
 738         /* 0x60 */
 739         i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
 740         rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC");
 741         /* 0x64 */
 742         i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
 743         rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC");
 744
 745         /* mm i2c */
 746         i2c.valid = true;
 747         i2c.hw_capable = true;
 748         i2c.mm_i2c = true;
 749         i2c.i2c_id = 0xa0;
 750         rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C");
 751
 752         if (rdev->family == CHIP_R300 ||
 753             rdev->family == CHIP_R350) {
 754                 /* only 2 sw i2c pads */
 755         } else if (rdev->family == CHIP_RS300 ||
 756                    rdev->family == CHIP_RS400 ||
 757                    rdev->family == CHIP_RS480) {
 758                 u16 offset;
 759                 u8 id, blocks, clk, data;
 760                 int i;
 761
 762                 /* 0x68 */
 763                 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
 764                 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
 765
 766                 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
 767                 if (offset) {
 768                         blocks = RBIOS8(offset + 2);
 769                         for (i = 0; i < blocks; i++) {
 770                                 id = RBIOS8(offset + 3 + (i * 5) + 0);
 771                                 if (id == 136) {
 772                                         clk = RBIOS8(offset + 3 + (i * 5) + 3);
 773                                         data = RBIOS8(offset + 3 + (i * 5) + 4);
 774                                         /* gpiopad */
 775                                         i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
 776                                                                     (1 << clk), (1 << data));
 777                                         rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
 778                                         break;
 779                                 }
 780                         }
 781                 }
 782         } else if (rdev->family >= CHIP_R200) {
 783                 /* 0x68 */
 784                 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
 785                 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
 786         } else {
 787                 /* 0x68 */
 788                 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
 789                 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
 790                 /* 0x6c */
 791                 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
 792                 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC");
 793         }
 794 }
 795
 796 bool radeon_combios_get_clock_info(struct drm_device *dev)
 797 {
 798         struct radeon_device *rdev = dev->dev_private;
 799         uint16_t pll_info;
 800         struct radeon_pll *p1pll = &rdev->clock.p1pll;
 801         struct radeon_pll *p2pll = &rdev->clock.p2pll;
 802         struct radeon_pll *spll = &rdev->clock.spll;
 803         struct radeon_pll *mpll = &rdev->clock.mpll;
 804         int8_t rev;
 805         uint16_t sclk, mclk;
 806
 807         pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
 808         if (pll_info) {
 809                 rev = RBIOS8(pll_info);
 810
 811                 /* pixel clocks */
 812                 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
 813                 p1pll->reference_div = RBIOS16(pll_info + 0x10);
 814                 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
 815                 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
 816                 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
 817                 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
 818
 819                 if (rev > 9) {
 820                         p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
 821                         p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
 822                 } else {
 823                         p1pll->pll_in_min = 40;
 824                         p1pll->pll_in_max = 500;
 825                 }
 826                 *p2pll = *p1pll;
 827
 828                 /* system clock */
 829                 spll->reference_freq = RBIOS16(pll_info + 0x1a);
 830                 spll->reference_div = RBIOS16(pll_info + 0x1c);
 831                 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
 832                 spll->pll_out_max = RBIOS32(pll_info + 0x22);
 833
 834                 if (rev > 10) {
 835                         spll->pll_in_min = RBIOS32(pll_info + 0x48);
 836                         spll->pll_in_max = RBIOS32(pll_info + 0x4c);
 837                 } else {
 838                         /* ??? */
 839                         spll->pll_in_min = 40;
 840                         spll->pll_in_max = 500;
 841                 }
 842
 843                 /* memory clock */
 844                 mpll->reference_freq = RBIOS16(pll_info + 0x26);
 845                 mpll->reference_div = RBIOS16(pll_info + 0x28);
 846                 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
 847                 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
 848
 849                 if (rev > 10) {
 850                         mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
 851                         mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
 852                 } else {
 853                         /* ??? */
 854                         mpll->pll_in_min = 40;
 855                         mpll->pll_in_max = 500;
 856                 }
 857
 858                 /* default sclk/mclk */
 859                 sclk = RBIOS16(pll_info + 0xa);
 860                 mclk = RBIOS16(pll_info + 0x8);
 861                 if (sclk == 0)
 862                         sclk = 200 * 100;
 863                 if (mclk == 0)
 864                         mclk = 200 * 100;
 865
 866                 rdev->clock.default_sclk = sclk;
 867                 rdev->clock.default_mclk = mclk;
 868
 869                 if (RBIOS32(pll_info + 0x16))
 870                         rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16);
 871                 else
 872                         rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */
 873
 874                 return true;
 875         }
 876         return false;
 877 }
 878
 879 bool radeon_combios_sideport_present(struct radeon_device *rdev)
 880 {
 881         struct drm_device *dev = rdev->ddev;
 882         u16 igp_info;
 883
 884         /* sideport is AMD only */
 885         if (rdev->family == CHIP_RS400)
 886                 return false;
 887
 888         igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
 889
 890         if (igp_info) {
 891                 if (RBIOS16(igp_info + 0x4))
 892                         return true;
 893         }
 894         return false;
 895 }
 896
 897 static const uint32_t default_primarydac_adj[CHIP_LAST] = {
 898         0x00000808,             /* r100  */
 899         0x00000808,             /* rv100 */
 900         0x00000808,             /* rs100 */
 901         0x00000808,             /* rv200 */
 902         0x00000808,             /* rs200 */
 903         0x00000808,             /* r200  */
 904         0x00000808,             /* rv250 */
 905         0x00000000,             /* rs300 */
 906         0x00000808,             /* rv280 */
 907         0x00000808,             /* r300  */
 908         0x00000808,             /* r350  */
 909         0x00000808,             /* rv350 */
 910         0x00000808,             /* rv380 */
 911         0x00000808,             /* r420  */
 912         0x00000808,             /* r423  */
 913         0x00000808,             /* rv410 */
 914         0x00000000,             /* rs400 */
 915         0x00000000,             /* rs480 */
 916 };
 917
 918 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
 919                                                           struct radeon_encoder_primary_dac *p_dac)
 920 {
 921         p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
 922         return;
 923 }
 924
 925 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
 926                                                                        radeon_encoder
 927                                                                        *encoder)
 928 {
 929         struct drm_device *dev = encoder->base.dev;
 930         struct radeon_device *rdev = dev->dev_private;
 931         uint16_t dac_info;
 932         uint8_t rev, bg, dac;
 933         struct radeon_encoder_primary_dac *p_dac = NULL;
 934         int found = 0;
 935
 936         p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
 937                         GFP_KERNEL);
 938
 939         if (!p_dac)
 940                 return NULL;
 941
 942         /* check CRT table */
 943         dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
 944         if (dac_info) {
 945                 rev = RBIOS8(dac_info) & 0x3;
 946                 if (rev < 2) {
 947                         bg = RBIOS8(dac_info + 0x2) & 0xf;
 948                         dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
 949                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 950                 } else {
 951                         bg = RBIOS8(dac_info + 0x2) & 0xf;
 952                         dac = RBIOS8(dac_info + 0x3) & 0xf;
 953                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 954                 }
 955                 /* if the values are all zeros, use the table */
 956                 if (p_dac->ps2_pdac_adj)
 957                         found = 1;
 958         }
 959
 960         if (!found) /* fallback to defaults */
 961                 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
 962
 963         return p_dac;
 964 }
 965
 966 enum radeon_tv_std
 967 radeon_combios_get_tv_info(struct radeon_device *rdev)
 968 {
 969         struct drm_device *dev = rdev->ddev;
 970         uint16_t tv_info;
 971         enum radeon_tv_std tv_std = TV_STD_NTSC;
 972
 973         tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
 974         if (tv_info) {
 975                 if (RBIOS8(tv_info + 6) == 'T') {
 976                         switch (RBIOS8(tv_info + 7) & 0xf) {
 977                         case 1:
 978                                 tv_std = TV_STD_NTSC;
 979                                 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
 980                                 break;
 981                         case 2:
 982                                 tv_std = TV_STD_PAL;
 983                                 DRM_DEBUG_KMS("Default TV standard: PAL\n");
 984                                 break;
 985                         case 3:
 986                                 tv_std = TV_STD_PAL_M;
 987                                 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
 988                                 break;
 989                         case 4:
 990                                 tv_std = TV_STD_PAL_60;
 991                                 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
 992                                 break;
 993                         case 5:
 994                                 tv_std = TV_STD_NTSC_J;
 995                                 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
 996                                 break;
 997                         case 6:
 998                                 tv_std = TV_STD_SCART_PAL;
 999                                 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n");
1000                                 break;
1001                         default:
1002                                 tv_std = TV_STD_NTSC;
1003                                 DRM_DEBUG_KMS
1004                                     ("Unknown TV standard; defaulting to NTSC\n");
1005                                 break;
1006                         }
1007
1008                         switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
1009                         case 0:
1010                                 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n");
1011                                 break;
1012                         case 1:
1013                                 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n");
1014                                 break;
1015                         case 2:
1016                                 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n");
1017                                 break;
1018                         case 3:
1019                                 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n");
1020                                 break;
1021                         default:
1022                                 break;
1023                         }
1024                 }
1025         }
1026         return tv_std;
1027 }
1028
1029 static const uint32_t default_tvdac_adj[CHIP_LAST] = {
1030         0x00000000,             /* r100  */
1031         0x00280000,             /* rv100 */
1032         0x00000000,             /* rs100 */
1033         0x00880000,             /* rv200 */
1034         0x00000000,             /* rs200 */
1035         0x00000000,             /* r200  */
1036         0x00770000,             /* rv250 */
1037         0x00290000,             /* rs300 */
1038         0x00560000,             /* rv280 */
1039         0x00780000,             /* r300  */
1040         0x00770000,             /* r350  */
1041         0x00780000,             /* rv350 */
1042         0x00780000,             /* rv380 */
1043         0x01080000,             /* r420  */
1044         0x01080000,             /* r423  */
1045         0x01080000,             /* rv410 */
1046         0x00780000,             /* rs400 */
1047         0x00780000,             /* rs480 */
1048 };
1049
1050 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
1051                                                      struct radeon_encoder_tv_dac *tv_dac)
1052 {
1053         tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
1054         if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
1055                 tv_dac->ps2_tvdac_adj = 0x00880000;
1056         tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1057         tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1058         return;
1059 }
1060
1061 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
1062                                                              radeon_encoder
1063                                                              *encoder)
1064 {
1065         struct drm_device *dev = encoder->base.dev;
1066         struct radeon_device *rdev = dev->dev_private;
1067         uint16_t dac_info;
1068         uint8_t rev, bg, dac;
1069         struct radeon_encoder_tv_dac *tv_dac = NULL;
1070         int found = 0;
1071
1072         tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1073         if (!tv_dac)
1074                 return NULL;
1075
1076         /* first check TV table */
1077         dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
1078         if (dac_info) {
1079                 rev = RBIOS8(dac_info + 0x3);
1080                 if (rev > 4) {
1081                         bg = RBIOS8(dac_info + 0xc) & 0xf;
1082                         dac = RBIOS8(dac_info + 0xd) & 0xf;
1083                         tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1084
1085                         bg = RBIOS8(dac_info + 0xe) & 0xf;
1086                         dac = RBIOS8(dac_info + 0xf) & 0xf;
1087                         tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1088
1089                         bg = RBIOS8(dac_info + 0x10) & 0xf;
1090                         dac = RBIOS8(dac_info + 0x11) & 0xf;
1091                         tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1092                         /* if the values are all zeros, use the table */
1093                         if (tv_dac->ps2_tvdac_adj)
1094                                 found = 1;
1095                 } else if (rev > 1) {
1096                         bg = RBIOS8(dac_info + 0xc) & 0xf;
1097                         dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
1098                         tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1099
1100                         bg = RBIOS8(dac_info + 0xd) & 0xf;
1101                         dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
1102                         tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1103
1104                         bg = RBIOS8(dac_info + 0xe) & 0xf;
1105                         dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
1106                         tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1107                         /* if the values are all zeros, use the table */
1108                         if (tv_dac->ps2_tvdac_adj)
1109                                 found = 1;
1110                 }
1111                 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
1112         }
1113         if (!found) {
1114                 /* then check CRT table */
1115                 dac_info =
1116                     combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
1117                 if (dac_info) {
1118                         rev = RBIOS8(dac_info) & 0x3;
1119                         if (rev < 2) {
1120                                 bg = RBIOS8(dac_info + 0x3) & 0xf;
1121                                 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
1122                                 tv_dac->ps2_tvdac_adj =
1123                                     (bg << 16) | (dac << 20);
1124                                 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1125                                 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1126                                 /* if the values are all zeros, use the table */
1127                                 if (tv_dac->ps2_tvdac_adj)
1128                                         found = 1;
1129                         } else {
1130                                 bg = RBIOS8(dac_info + 0x4) & 0xf;
1131                                 dac = RBIOS8(dac_info + 0x5) & 0xf;
1132                                 tv_dac->ps2_tvdac_adj =
1133                                     (bg << 16) | (dac << 20);
1134                                 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1135                                 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1136                                 /* if the values are all zeros, use the table */
1137                                 if (tv_dac->ps2_tvdac_adj)
1138                                         found = 1;
1139                         }
1140                 } else {
1141                         DRM_INFO("No TV DAC info found in BIOS\n");
1142                 }
1143         }
1144
1145         if (!found) /* fallback to defaults */
1146                 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
1147
1148         return tv_dac;
1149 }
1150
1151 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
1152                                                                          radeon_device
1153                                                                          *rdev)
1154 {
1155         struct radeon_encoder_lvds *lvds = NULL;
1156         uint32_t fp_vert_stretch, fp_horz_stretch;
1157         uint32_t ppll_div_sel, ppll_val;
1158         uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
1159
1160         lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1161
1162         if (!lvds)
1163                 return NULL;
1164
1165         fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
1166         fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
1167
1168         /* These should be fail-safe defaults, fingers crossed */
1169         lvds->panel_pwr_delay = 200;
1170         lvds->panel_vcc_delay = 2000;
1171
1172         lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
1173         lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
1174         lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
1175
1176         if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
1177                 lvds->native_mode.vdisplay =
1178                     ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
1179                      RADEON_VERT_PANEL_SHIFT) + 1;
1180         else
1181                 lvds->native_mode.vdisplay =
1182                     (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
1183
1184         if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
1185                 lvds->native_mode.hdisplay =
1186                     (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
1187                       RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
1188         else
1189                 lvds->native_mode.hdisplay =
1190                     ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
1191
1192         if ((lvds->native_mode.hdisplay < 640) ||
1193             (lvds->native_mode.vdisplay < 480)) {
1194                 lvds->native_mode.hdisplay = 640;
1195                 lvds->native_mode.vdisplay = 480;
1196         }
1197
1198         ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
1199         ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
1200         if ((ppll_val & 0x000707ff) == 0x1bb)
1201                 lvds->use_bios_dividers = false;
1202         else {
1203                 lvds->panel_ref_divider =
1204                     RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1205                 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1206                 lvds->panel_fb_divider = ppll_val & 0x7ff;
1207
1208                 if ((lvds->panel_ref_divider != 0) &&
1209                     (lvds->panel_fb_divider > 3))
1210                         lvds->use_bios_dividers = true;
1211         }
1212         lvds->panel_vcc_delay = 200;
1213
1214         DRM_INFO("Panel info derived from registers\n");
1215         DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1216                  lvds->native_mode.vdisplay);
1217
1218         return lvds;
1219 }
1220
1221 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1222                                                          *encoder)
1223 {
1224         struct drm_device *dev = encoder->base.dev;
1225         struct radeon_device *rdev = dev->dev_private;
1226         uint16_t lcd_info;
1227         uint32_t panel_setup;
1228         char stmp[30];
1229         int tmp, i;
1230         struct radeon_encoder_lvds *lvds = NULL;
1231
1232         lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1233
1234         if (lcd_info) {
1235                 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1236
1237                 if (!lvds)
1238                         return NULL;
1239
1240                 for (i = 0; i < 24; i++)
1241                         stmp[i] = RBIOS8(lcd_info + i + 1);
1242                 stmp[24] = 0;
1243
1244                 DRM_INFO("Panel ID String: %s\n", stmp);
1245
1246                 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1247                 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1248
1249                 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1250                          lvds->native_mode.vdisplay);
1251
1252                 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1253                 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1254
1255                 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1256                 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1257                 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1258
1259                 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1260                 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1261                 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1262                 if ((lvds->panel_ref_divider != 0) &&
1263                     (lvds->panel_fb_divider > 3))
1264                         lvds->use_bios_dividers = true;
1265
1266                 panel_setup = RBIOS32(lcd_info + 0x39);
1267                 lvds->lvds_gen_cntl = 0xff00;
1268                 if (panel_setup & 0x1)
1269                         lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1270
1271                 if ((panel_setup >> 4) & 0x1)
1272                         lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1273
1274                 switch ((panel_setup >> 8) & 0x7) {
1275                 case 0:
1276                         lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1277                         break;
1278                 case 1:
1279                         lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1280                         break;
1281                 case 2:
1282                         lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1283                         break;
1284                 default:
1285                         break;
1286                 }
1287
1288                 if ((panel_setup >> 16) & 0x1)
1289                         lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1290
1291                 if ((panel_setup >> 17) & 0x1)
1292                         lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1293
1294                 if ((panel_setup >> 18) & 0x1)
1295                         lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1296
1297                 if ((panel_setup >> 23) & 0x1)
1298                         lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1299
1300                 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1301
1302                 for (i = 0; i < 32; i++) {
1303                         tmp = RBIOS16(lcd_info + 64 + i * 2);
1304                         if (tmp == 0)
1305                                 break;
1306
1307                         if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1308                             (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
1309                                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1310                                         (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
1311                                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1312                                         (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
1313                                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1314                                         (RBIOS8(tmp + 23) * 8);
1315
1316                                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1317                                         (RBIOS16(tmp + 24) - RBIOS16(tmp + 26));
1318                                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1319                                         ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));
1320                                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1321                                         ((RBIOS16(tmp + 28) & 0xf800) >> 11);
1322
1323                                 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1324                                 lvds->native_mode.flags = 0;
1325                                 /* set crtc values */
1326                                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1327
1328                         }
1329                 }
1330         } else {
1331                 DRM_INFO("No panel info found in BIOS\n");
1332                 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1333         }
1334
1335         if (lvds)
1336                 encoder->native_mode = lvds->native_mode;
1337         return lvds;
1338 }
1339
1340 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1341         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R100  */
1342         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV100 */
1343         {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS100 */
1344         {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV200 */
1345         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RS200 */
1346         {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R200  */
1347         {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}},  /* CHIP_RV250 */
1348         {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS300 */
1349         {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}},    /* CHIP_RV280 */
1350         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R300  */
1351         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R350  */
1352         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV350 */
1353         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV380 */
1354         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R420  */
1355         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R423  */
1356         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_RV410 */
1357         { {0, 0}, {0, 0}, {0, 0}, {0, 0} },     /* CHIP_RS400 */
1358         { {0, 0}, {0, 0}, {0, 0}, {0, 0} },     /* CHIP_RS480 */
1359 };
1360
1361 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1362                                             struct radeon_encoder_int_tmds *tmds)
1363 {
1364         struct drm_device *dev = encoder->base.dev;
1365         struct radeon_device *rdev = dev->dev_private;
1366         int i;
1367
1368         for (i = 0; i < 4; i++) {
1369                 tmds->tmds_pll[i].value =
1370                         default_tmds_pll[rdev->family][i].value;
1371                 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1372         }
1373
1374         return true;
1375 }
1376
1377 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1378                                               struct radeon_encoder_int_tmds *tmds)
1379 {
1380         struct drm_device *dev = encoder->base.dev;
1381         struct radeon_device *rdev = dev->dev_private;
1382         uint16_t tmds_info;
1383         int i, n;
1384         uint8_t ver;
1385
1386         tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1387
1388         if (tmds_info) {
1389                 ver = RBIOS8(tmds_info);
1390                 DRM_DEBUG_KMS("DFP table revision: %d\n", ver);
1391                 if (ver == 3) {
1392                         n = RBIOS8(tmds_info + 5) + 1;
1393                         if (n > 4)
1394                                 n = 4;
1395                         for (i = 0; i < n; i++) {
1396                                 tmds->tmds_pll[i].value =
1397                                     RBIOS32(tmds_info + i * 10 + 0x08);
1398                                 tmds->tmds_pll[i].freq =
1399                                     RBIOS16(tmds_info + i * 10 + 0x10);
1400                                 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1401                                           tmds->tmds_pll[i].freq,
1402                                           tmds->tmds_pll[i].value);
1403                         }
1404                 } else if (ver == 4) {
1405                         int stride = 0;
1406                         n = RBIOS8(tmds_info + 5) + 1;
1407                         if (n > 4)
1408                                 n = 4;
1409                         for (i = 0; i < n; i++) {
1410                                 tmds->tmds_pll[i].value =
1411                                     RBIOS32(tmds_info + stride + 0x08);
1412                                 tmds->tmds_pll[i].freq =
1413                                     RBIOS16(tmds_info + stride + 0x10);
1414                                 if (i == 0)
1415                                         stride += 10;
1416                                 else
1417                                         stride += 6;
1418                                 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1419                                           tmds->tmds_pll[i].freq,
1420                                           tmds->tmds_pll[i].value);
1421                         }
1422                 }
1423         } else {
1424                 DRM_INFO("No TMDS info found in BIOS\n");
1425                 return false;
1426         }
1427         return true;
1428 }
1429
1430 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1431                                                 struct radeon_encoder_ext_tmds *tmds)
1432 {
1433         struct drm_device *dev = encoder->base.dev;
1434         struct radeon_device *rdev = dev->dev_private;
1435         struct radeon_i2c_bus_rec i2c_bus;
1436
1437         /* default for macs */
1438         i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1439         tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1440
1441         /* XXX some macs have duallink chips */
1442         switch (rdev->mode_info.connector_table) {
1443         case CT_POWERBOOK_EXTERNAL:
1444         case CT_MINI_EXTERNAL:
1445         default:
1446                 tmds->dvo_chip = DVO_SIL164;
1447                 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1448                 break;
1449         }
1450
1451         return true;
1452 }
1453
1454 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1455                                                   struct radeon_encoder_ext_tmds *tmds)
1456 {
1457         struct drm_device *dev = encoder->base.dev;
1458         struct radeon_device *rdev = dev->dev_private;
1459         uint16_t offset;
1460         uint8_t ver;
1461         enum radeon_combios_ddc gpio;
1462         struct radeon_i2c_bus_rec i2c_bus;
1463
1464         tmds->i2c_bus = NULL;
1465         if (rdev->flags & RADEON_IS_IGP) {
1466                 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1467                 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1468                 tmds->dvo_chip = DVO_SIL164;
1469                 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1470         } else {
1471                 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1472                 if (offset) {
1473                         ver = RBIOS8(offset);
1474                         DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver);
1475                         tmds->slave_addr = RBIOS8(offset + 4 + 2);
1476                         tmds->slave_addr >>= 1; /* 7 bit addressing */
1477                         gpio = RBIOS8(offset + 4 + 3);
1478                         if (gpio == DDC_LCD) {
1479                                 /* MM i2c */
1480                                 i2c_bus.valid = true;
1481                                 i2c_bus.hw_capable = true;
1482                                 i2c_bus.mm_i2c = true;
1483                                 i2c_bus.i2c_id = 0xa0;
1484                         } else
1485                                 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
1486                         tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1487                 }
1488         }
1489
1490         if (!tmds->i2c_bus) {
1491                 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1492                 return false;
1493         }
1494
1495         return true;
1496 }
1497
1498 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1499 {
1500         struct radeon_device *rdev = dev->dev_private;
1501         struct radeon_i2c_bus_rec ddc_i2c;
1502         struct radeon_hpd hpd;
1503
1504         rdev->mode_info.connector_table = radeon_connector_table;
1505         if (rdev->mode_info.connector_table == CT_NONE) {
1506 #ifdef CONFIG_PPC_PMAC
1507                 if (of_machine_is_compatible("PowerBook3,3")) {
1508                         /* powerbook with VGA */
1509                         rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1510                 } else if (of_machine_is_compatible("PowerBook3,4") ||
1511                            of_machine_is_compatible("PowerBook3,5")) {
1512                         /* powerbook with internal tmds */
1513                         rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1514                 } else if (of_machine_is_compatible("PowerBook5,1") ||
1515                            of_machine_is_compatible("PowerBook5,2") ||
1516                            of_machine_is_compatible("PowerBook5,3") ||
1517                            of_machine_is_compatible("PowerBook5,4") ||
1518                            of_machine_is_compatible("PowerBook5,5")) {
1519                         /* powerbook with external single link tmds (sil164) */
1520                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1521                 } else if (of_machine_is_compatible("PowerBook5,6")) {
1522                         /* powerbook with external dual or single link tmds */
1523                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1524                 } else if (of_machine_is_compatible("PowerBook5,7") ||
1525                            of_machine_is_compatible("PowerBook5,8") ||
1526                            of_machine_is_compatible("PowerBook5,9")) {
1527                         /* PowerBook6,2 ? */
1528                         /* powerbook with external dual link tmds (sil1178?) */
1529                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1530                 } else if (of_machine_is_compatible("PowerBook4,1") ||
1531                            of_machine_is_compatible("PowerBook4,2") ||
1532                            of_machine_is_compatible("PowerBook4,3") ||
1533                            of_machine_is_compatible("PowerBook6,3") ||
1534                            of_machine_is_compatible("PowerBook6,5") ||
1535                            of_machine_is_compatible("PowerBook6,7")) {
1536                         /* ibook */
1537                         rdev->mode_info.connector_table = CT_IBOOK;
1538                 } else if (of_machine_is_compatible("PowerMac4,4")) {
1539                         /* emac */
1540                         rdev->mode_info.connector_table = CT_EMAC;
1541                 } else if (of_machine_is_compatible("PowerMac10,1")) {
1542                         /* mini with internal tmds */
1543                         rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1544                 } else if (of_machine_is_compatible("PowerMac10,2")) {
1545                         /* mini with external tmds */
1546                         rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1547                 } else if (of_machine_is_compatible("PowerMac12,1")) {
1548                         /* PowerMac8,1 ? */
1549                         /* imac g5 isight */
1550                         rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1551                 } else if ((rdev->pdev->device == 0x4a48) &&
1552                            (rdev->pdev->subsystem_vendor == 0x1002) &&
1553                            (rdev->pdev->subsystem_device == 0x4a48)) {
1554                         /* Mac X800 */
1555                         rdev->mode_info.connector_table = CT_MAC_X800;
1556                 } else if ((of_machine_is_compatible("PowerMac7,2") ||
1557                             of_machine_is_compatible("PowerMac7,3")) &&
1558                            (rdev->pdev->device == 0x4150) &&
1559                            (rdev->pdev->subsystem_vendor == 0x1002) &&
1560                            (rdev->pdev->subsystem_device == 0x4150)) {
1561                         /* Mac G5 tower 9600 */
1562                         rdev->mode_info.connector_table = CT_MAC_G5_9600;
1563                 } else
1564 #endif /* CONFIG_PPC_PMAC */
1565 #ifdef CONFIG_PPC64
1566                 if (ASIC_IS_RN50(rdev))
1567                         rdev->mode_info.connector_table = CT_RN50_POWER;
1568                 else
1569 #endif
1570                         rdev->mode_info.connector_table = CT_GENERIC;
1571         }
1572
1573         switch (rdev->mode_info.connector_table) {
1574         case CT_GENERIC:
1575                 DRM_INFO("Connector Table: %d (generic)\n",
1576                          rdev->mode_info.connector_table);
1577                 /* these are the most common settings */
1578                 if (rdev->flags & RADEON_SINGLE_CRTC) {
1579                         /* VGA - primary dac */
1580                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1581                         hpd.hpd = RADEON_HPD_NONE;
1582                         radeon_add_legacy_encoder(dev,
1583                                                   radeon_get_encoder_enum(dev,
1584                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1585                                                                         1),
1586                                                   ATOM_DEVICE_CRT1_SUPPORT);
1587                         radeon_add_legacy_connector(dev, 0,
1588                                                     ATOM_DEVICE_CRT1_SUPPORT,
1589                                                     DRM_MODE_CONNECTOR_VGA,
1590                                                     &ddc_i2c,
1591                                                     CONNECTOR_OBJECT_ID_VGA,
1592                                                     &hpd);
1593                 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1594                         /* LVDS */
1595                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
1596                         hpd.hpd = RADEON_HPD_NONE;
1597                         radeon_add_legacy_encoder(dev,
1598                                                   radeon_get_encoder_enum(dev,
1599                                                                         ATOM_DEVICE_LCD1_SUPPORT,
1600                                                                         0),
1601                                                   ATOM_DEVICE_LCD1_SUPPORT);
1602                         radeon_add_legacy_connector(dev, 0,
1603                                                     ATOM_DEVICE_LCD1_SUPPORT,
1604                                                     DRM_MODE_CONNECTOR_LVDS,
1605                                                     &ddc_i2c,
1606                                                     CONNECTOR_OBJECT_ID_LVDS,
1607                                                     &hpd);
1608
1609                         /* VGA - primary dac */
1610                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1611                         hpd.hpd = RADEON_HPD_NONE;
1612                         radeon_add_legacy_encoder(dev,
1613                                                   radeon_get_encoder_enum(dev,
1614                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1615                                                                         1),
1616                                                   ATOM_DEVICE_CRT1_SUPPORT);
1617                         radeon_add_legacy_connector(dev, 1,
1618                                                     ATOM_DEVICE_CRT1_SUPPORT,
1619                                                     DRM_MODE_CONNECTOR_VGA,
1620                                                     &ddc_i2c,
1621                                                     CONNECTOR_OBJECT_ID_VGA,
1622                                                     &hpd);
1623                 } else {
1624                         /* DVI-I - tv dac, int tmds */
1625                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1626                         hpd.hpd = RADEON_HPD_1;
1627                         radeon_add_legacy_encoder(dev,
1628                                                   radeon_get_encoder_enum(dev,
1629                                                                         ATOM_DEVICE_DFP1_SUPPORT,
1630                                                                         0),
1631                                                   ATOM_DEVICE_DFP1_SUPPORT);
1632                         radeon_add_legacy_encoder(dev,
1633                                                   radeon_get_encoder_enum(dev,
1634                                                                         ATOM_DEVICE_CRT2_SUPPORT,
1635                                                                         2),
1636                                                   ATOM_DEVICE_CRT2_SUPPORT);
1637                         radeon_add_legacy_connector(dev, 0,
1638                                                     ATOM_DEVICE_DFP1_SUPPORT |
1639                                                     ATOM_DEVICE_CRT2_SUPPORT,
1640                                                     DRM_MODE_CONNECTOR_DVII,
1641                                                     &ddc_i2c,
1642                                                     CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1643                                                     &hpd);
1644
1645                         /* VGA - primary dac */
1646                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1647                         hpd.hpd = RADEON_HPD_NONE;
1648                         radeon_add_legacy_encoder(dev,
1649                                                   radeon_get_encoder_enum(dev,
1650                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1651                                                                         1),
1652                                                   ATOM_DEVICE_CRT1_SUPPORT);
1653                         radeon_add_legacy_connector(dev, 1,
1654                                                     ATOM_DEVICE_CRT1_SUPPORT,
1655                                                     DRM_MODE_CONNECTOR_VGA,
1656                                                     &ddc_i2c,
1657                                                     CONNECTOR_OBJECT_ID_VGA,
1658                                                     &hpd);
1659                 }
1660
1661                 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1662                         /* TV - tv dac */
1663                         ddc_i2c.valid = false;
1664                         hpd.hpd = RADEON_HPD_NONE;
1665                         radeon_add_legacy_encoder(dev,
1666                                                   radeon_get_encoder_enum(dev,
1667                                                                         ATOM_DEVICE_TV1_SUPPORT,
1668                                                                         2),
1669                                                   ATOM_DEVICE_TV1_SUPPORT);
1670                         radeon_add_legacy_connector(dev, 2,
1671                                                     ATOM_DEVICE_TV1_SUPPORT,
1672                                                     DRM_MODE_CONNECTOR_SVIDEO,
1673                                                     &ddc_i2c,
1674                                                     CONNECTOR_OBJECT_ID_SVIDEO,
1675                                                     &hpd);
1676                 }
1677                 break;
1678         case CT_IBOOK:
1679                 DRM_INFO("Connector Table: %d (ibook)\n",
1680                          rdev->mode_info.connector_table);
1681                 /* LVDS */
1682                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1683                 hpd.hpd = RADEON_HPD_NONE;
1684                 radeon_add_legacy_encoder(dev,
1685                                           radeon_get_encoder_enum(dev,
1686                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1687                                                                 0),
1688                                           ATOM_DEVICE_LCD1_SUPPORT);
1689                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1690                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1691                                             CONNECTOR_OBJECT_ID_LVDS,
1692                                             &hpd);
1693                 /* VGA - TV DAC */
1694                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1695                 hpd.hpd = RADEON_HPD_NONE;
1696                 radeon_add_legacy_encoder(dev,
1697                                           radeon_get_encoder_enum(dev,
1698                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1699                                                                 2),
1700                                           ATOM_DEVICE_CRT2_SUPPORT);
1701                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1702                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1703                                             CONNECTOR_OBJECT_ID_VGA,
1704                                             &hpd);
1705                 /* TV - TV DAC */
1706                 ddc_i2c.valid = false;
1707                 hpd.hpd = RADEON_HPD_NONE;
1708                 radeon_add_legacy_encoder(dev,
1709                                           radeon_get_encoder_enum(dev,
1710                                                                 ATOM_DEVICE_TV1_SUPPORT,
1711                                                                 2),
1712                                           ATOM_DEVICE_TV1_SUPPORT);
1713                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1714                                             DRM_MODE_CONNECTOR_SVIDEO,
1715                                             &ddc_i2c,
1716                                             CONNECTOR_OBJECT_ID_SVIDEO,
1717                                             &hpd);
1718                 break;
1719         case CT_POWERBOOK_EXTERNAL:
1720                 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1721                          rdev->mode_info.connector_table);
1722                 /* LVDS */
1723                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1724                 hpd.hpd = RADEON_HPD_NONE;
1725                 radeon_add_legacy_encoder(dev,
1726                                           radeon_get_encoder_enum(dev,
1727                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1728                                                                 0),
1729                                           ATOM_DEVICE_LCD1_SUPPORT);
1730                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1731                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1732                                             CONNECTOR_OBJECT_ID_LVDS,
1733                                             &hpd);
1734                 /* DVI-I - primary dac, ext tmds */
1735                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1736                 hpd.hpd = RADEON_HPD_2; /* ??? */
1737                 radeon_add_legacy_encoder(dev,
1738                                           radeon_get_encoder_enum(dev,
1739                                                                 ATOM_DEVICE_DFP2_SUPPORT,
1740                                                                 0),
1741                                           ATOM_DEVICE_DFP2_SUPPORT);
1742                 radeon_add_legacy_encoder(dev,
1743                                           radeon_get_encoder_enum(dev,
1744                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1745                                                                 1),
1746                                           ATOM_DEVICE_CRT1_SUPPORT);
1747                 /* XXX some are SL */
1748                 radeon_add_legacy_connector(dev, 1,
1749                                             ATOM_DEVICE_DFP2_SUPPORT |
1750                                             ATOM_DEVICE_CRT1_SUPPORT,
1751                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1752                                             CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1753                                             &hpd);
1754                 /* TV - TV DAC */
1755                 ddc_i2c.valid = false;
1756                 hpd.hpd = RADEON_HPD_NONE;
1757                 radeon_add_legacy_encoder(dev,
1758                                           radeon_get_encoder_enum(dev,
1759                                                                 ATOM_DEVICE_TV1_SUPPORT,
1760                                                                 2),
1761                                           ATOM_DEVICE_TV1_SUPPORT);
1762                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1763                                             DRM_MODE_CONNECTOR_SVIDEO,
1764                                             &ddc_i2c,
1765                                             CONNECTOR_OBJECT_ID_SVIDEO,
1766                                             &hpd);
1767                 break;
1768         case CT_POWERBOOK_INTERNAL:
1769                 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1770                          rdev->mode_info.connector_table);
1771                 /* LVDS */
1772                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1773                 hpd.hpd = RADEON_HPD_NONE;
1774                 radeon_add_legacy_encoder(dev,
1775                                           radeon_get_encoder_enum(dev,
1776                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1777                                                                 0),
1778                                           ATOM_DEVICE_LCD1_SUPPORT);
1779                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1780                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1781                                             CONNECTOR_OBJECT_ID_LVDS,
1782                                             &hpd);
1783                 /* DVI-I - primary dac, int tmds */
1784                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1785                 hpd.hpd = RADEON_HPD_1; /* ??? */
1786                 radeon_add_legacy_encoder(dev,
1787                                           radeon_get_encoder_enum(dev,
1788                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1789                                                                 0),
1790                                           ATOM_DEVICE_DFP1_SUPPORT);
1791                 radeon_add_legacy_encoder(dev,
1792                                           radeon_get_encoder_enum(dev,
1793                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1794                                                                 1),
1795                                           ATOM_DEVICE_CRT1_SUPPORT);
1796                 radeon_add_legacy_connector(dev, 1,
1797                                             ATOM_DEVICE_DFP1_SUPPORT |
1798                                             ATOM_DEVICE_CRT1_SUPPORT,
1799                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1800                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1801                                             &hpd);
1802                 /* TV - TV DAC */
1803                 ddc_i2c.valid = false;
1804                 hpd.hpd = RADEON_HPD_NONE;
1805                 radeon_add_legacy_encoder(dev,
1806                                           radeon_get_encoder_enum(dev,
1807                                                                 ATOM_DEVICE_TV1_SUPPORT,
1808                                                                 2),
1809                                           ATOM_DEVICE_TV1_SUPPORT);
1810                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1811                                             DRM_MODE_CONNECTOR_SVIDEO,
1812                                             &ddc_i2c,
1813                                             CONNECTOR_OBJECT_ID_SVIDEO,
1814                                             &hpd);
1815                 break;
1816         case CT_POWERBOOK_VGA:
1817                 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1818                          rdev->mode_info.connector_table);
1819                 /* LVDS */
1820                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1821                 hpd.hpd = RADEON_HPD_NONE;
1822                 radeon_add_legacy_encoder(dev,
1823                                           radeon_get_encoder_enum(dev,
1824                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1825                                                                 0),
1826                                           ATOM_DEVICE_LCD1_SUPPORT);
1827                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1828                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1829                                             CONNECTOR_OBJECT_ID_LVDS,
1830                                             &hpd);
1831                 /* VGA - primary dac */
1832                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1833                 hpd.hpd = RADEON_HPD_NONE;
1834                 radeon_add_legacy_encoder(dev,
1835                                           radeon_get_encoder_enum(dev,
1836                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1837                                                                 1),
1838                                           ATOM_DEVICE_CRT1_SUPPORT);
1839                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1840                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1841                                             CONNECTOR_OBJECT_ID_VGA,
1842                                             &hpd);
1843                 /* TV - TV DAC */
1844                 ddc_i2c.valid = false;
1845                 hpd.hpd = RADEON_HPD_NONE;
1846                 radeon_add_legacy_encoder(dev,
1847                                           radeon_get_encoder_enum(dev,
1848                                                                 ATOM_DEVICE_TV1_SUPPORT,
1849                                                                 2),
1850                                           ATOM_DEVICE_TV1_SUPPORT);
1851                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1852                                             DRM_MODE_CONNECTOR_SVIDEO,
1853                                             &ddc_i2c,
1854                                             CONNECTOR_OBJECT_ID_SVIDEO,
1855                                             &hpd);
1856                 break;
1857         case CT_MINI_EXTERNAL:
1858                 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1859                          rdev->mode_info.connector_table);
1860                 /* DVI-I - tv dac, ext tmds */
1861                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1862                 hpd.hpd = RADEON_HPD_2; /* ??? */
1863                 radeon_add_legacy_encoder(dev,
1864                                           radeon_get_encoder_enum(dev,
1865                                                                 ATOM_DEVICE_DFP2_SUPPORT,
1866                                                                 0),
1867                                           ATOM_DEVICE_DFP2_SUPPORT);
1868                 radeon_add_legacy_encoder(dev,
1869                                           radeon_get_encoder_enum(dev,
1870                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1871                                                                 2),
1872                                           ATOM_DEVICE_CRT2_SUPPORT);
1873                 /* XXX are any DL? */
1874                 radeon_add_legacy_connector(dev, 0,
1875                                             ATOM_DEVICE_DFP2_SUPPORT |
1876                                             ATOM_DEVICE_CRT2_SUPPORT,
1877                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1878                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1879                                             &hpd);
1880                 /* TV - TV DAC */
1881                 ddc_i2c.valid = false;
1882                 hpd.hpd = RADEON_HPD_NONE;
1883                 radeon_add_legacy_encoder(dev,
1884                                           radeon_get_encoder_enum(dev,
1885                                                                 ATOM_DEVICE_TV1_SUPPORT,
1886                                                                 2),
1887                                           ATOM_DEVICE_TV1_SUPPORT);
1888                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1889                                             DRM_MODE_CONNECTOR_SVIDEO,
1890                                             &ddc_i2c,
1891                                             CONNECTOR_OBJECT_ID_SVIDEO,
1892                                             &hpd);
1893                 break;
1894         case CT_MINI_INTERNAL:
1895                 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1896                          rdev->mode_info.connector_table);
1897                 /* DVI-I - tv dac, int tmds */
1898                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1899                 hpd.hpd = RADEON_HPD_1; /* ??? */
1900                 radeon_add_legacy_encoder(dev,
1901                                           radeon_get_encoder_enum(dev,
1902                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1903                                                                 0),
1904                                           ATOM_DEVICE_DFP1_SUPPORT);
1905                 radeon_add_legacy_encoder(dev,
1906                                           radeon_get_encoder_enum(dev,
1907                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1908                                                                 2),
1909                                           ATOM_DEVICE_CRT2_SUPPORT);
1910                 radeon_add_legacy_connector(dev, 0,
1911                                             ATOM_DEVICE_DFP1_SUPPORT |
1912                                             ATOM_DEVICE_CRT2_SUPPORT,
1913                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1914                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1915                                             &hpd);
1916                 /* TV - TV DAC */
1917                 ddc_i2c.valid = false;
1918                 hpd.hpd = RADEON_HPD_NONE;
1919                 radeon_add_legacy_encoder(dev,
1920                                           radeon_get_encoder_enum(dev,
1921                                                                 ATOM_DEVICE_TV1_SUPPORT,
1922                                                                 2),
1923                                           ATOM_DEVICE_TV1_SUPPORT);
1924                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1925                                             DRM_MODE_CONNECTOR_SVIDEO,
1926                                             &ddc_i2c,
1927                                             CONNECTOR_OBJECT_ID_SVIDEO,
1928                                             &hpd);
1929                 break;
1930         case CT_IMAC_G5_ISIGHT:
1931                 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1932                          rdev->mode_info.connector_table);
1933                 /* DVI-D - int tmds */
1934                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1935                 hpd.hpd = RADEON_HPD_1; /* ??? */
1936                 radeon_add_legacy_encoder(dev,
1937                                           radeon_get_encoder_enum(dev,
1938                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1939                                                                 0),
1940                                           ATOM_DEVICE_DFP1_SUPPORT);
1941                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1942                                             DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1943                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1944                                             &hpd);
1945                 /* VGA - tv dac */
1946                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1947                 hpd.hpd = RADEON_HPD_NONE;
1948                 radeon_add_legacy_encoder(dev,
1949                                           radeon_get_encoder_enum(dev,
1950                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1951                                                                 2),
1952                                           ATOM_DEVICE_CRT2_SUPPORT);
1953                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1954                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1955                                             CONNECTOR_OBJECT_ID_VGA,
1956                                             &hpd);
1957                 /* TV - TV DAC */
1958                 ddc_i2c.valid = false;
1959                 hpd.hpd = RADEON_HPD_NONE;
1960                 radeon_add_legacy_encoder(dev,
1961                                           radeon_get_encoder_enum(dev,
1962                                                                 ATOM_DEVICE_TV1_SUPPORT,
1963                                                                 2),
1964                                           ATOM_DEVICE_TV1_SUPPORT);
1965                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1966                                             DRM_MODE_CONNECTOR_SVIDEO,
1967                                             &ddc_i2c,
1968                                             CONNECTOR_OBJECT_ID_SVIDEO,
1969                                             &hpd);
1970                 break;
1971         case CT_EMAC:
1972                 DRM_INFO("Connector Table: %d (emac)\n",
1973                          rdev->mode_info.connector_table);
1974                 /* VGA - primary dac */
1975                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1976                 hpd.hpd = RADEON_HPD_NONE;
1977                 radeon_add_legacy_encoder(dev,
1978                                           radeon_get_encoder_enum(dev,
1979                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1980                                                                 1),
1981                                           ATOM_DEVICE_CRT1_SUPPORT);
1982                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1983                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1984                                             CONNECTOR_OBJECT_ID_VGA,
1985                                             &hpd);
1986                 /* VGA - tv dac */
1987                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1988                 hpd.hpd = RADEON_HPD_NONE;
1989                 radeon_add_legacy_encoder(dev,
1990                                           radeon_get_encoder_enum(dev,
1991                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1992                                                                 2),
1993                                           ATOM_DEVICE_CRT2_SUPPORT);
1994                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1995                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1996                                             CONNECTOR_OBJECT_ID_VGA,
1997                                             &hpd);
1998                 /* TV - TV DAC */
1999                 ddc_i2c.valid = false;
2000                 hpd.hpd = RADEON_HPD_NONE;
2001                 radeon_add_legacy_encoder(dev,
2002                                           radeon_get_encoder_enum(dev,
2003                                                                 ATOM_DEVICE_TV1_SUPPORT,
2004                                                                 2),
2005                                           ATOM_DEVICE_TV1_SUPPORT);
2006                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2007                                             DRM_MODE_CONNECTOR_SVIDEO,
2008                                             &ddc_i2c,
2009                                             CONNECTOR_OBJECT_ID_SVIDEO,
2010                                             &hpd);
2011                 break;
2012         case CT_RN50_POWER:
2013                 DRM_INFO("Connector Table: %d (rn50-power)\n",
2014                          rdev->mode_info.connector_table);
2015                 /* VGA - primary dac */
2016                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2017                 hpd.hpd = RADEON_HPD_NONE;
2018                 radeon_add_legacy_encoder(dev,
2019                                           radeon_get_encoder_enum(dev,
2020                                                                 ATOM_DEVICE_CRT1_SUPPORT,
2021                                                                 1),
2022                                           ATOM_DEVICE_CRT1_SUPPORT);
2023                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
2024                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2025                                             CONNECTOR_OBJECT_ID_VGA,
2026                                             &hpd);
2027                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
2028                 hpd.hpd = RADEON_HPD_NONE;
2029                 radeon_add_legacy_encoder(dev,
2030                                           radeon_get_encoder_enum(dev,
2031                                                                 ATOM_DEVICE_CRT2_SUPPORT,
2032                                                                 2),
2033                                           ATOM_DEVICE_CRT2_SUPPORT);
2034                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
2035                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2036                                             CONNECTOR_OBJECT_ID_VGA,
2037                                             &hpd);
2038                 break;
2039         case CT_MAC_X800:
2040                 DRM_INFO("Connector Table: %d (mac x800)\n",
2041                          rdev->mode_info.connector_table);
2042                 /* DVI - primary dac, internal tmds */
2043                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2044                 hpd.hpd = RADEON_HPD_1; /* ??? */
2045                 radeon_add_legacy_encoder(dev,
2046                                           radeon_get_encoder_enum(dev,
2047                                                                   ATOM_DEVICE_DFP1_SUPPORT,
2048                                                                   0),
2049                                           ATOM_DEVICE_DFP1_SUPPORT);
2050                 radeon_add_legacy_encoder(dev,
2051                                           radeon_get_encoder_enum(dev,
2052                                                                   ATOM_DEVICE_CRT1_SUPPORT,
2053                                                                   1),
2054                                           ATOM_DEVICE_CRT1_SUPPORT);
2055                 radeon_add_legacy_connector(dev, 0,
2056                                             ATOM_DEVICE_DFP1_SUPPORT |
2057                                             ATOM_DEVICE_CRT1_SUPPORT,
2058                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2059                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2060                                             &hpd);
2061                 /* DVI - tv dac, dvo */
2062                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2063                 hpd.hpd = RADEON_HPD_2; /* ??? */
2064                 radeon_add_legacy_encoder(dev,
2065                                           radeon_get_encoder_enum(dev,
2066                                                                   ATOM_DEVICE_DFP2_SUPPORT,
2067                                                                   0),
2068                                           ATOM_DEVICE_DFP2_SUPPORT);
2069                 radeon_add_legacy_encoder(dev,
2070                                           radeon_get_encoder_enum(dev,
2071                                                                   ATOM_DEVICE_CRT2_SUPPORT,
2072                                                                   2),
2073                                           ATOM_DEVICE_CRT2_SUPPORT);
2074                 radeon_add_legacy_connector(dev, 1,
2075                                             ATOM_DEVICE_DFP2_SUPPORT |
2076                                             ATOM_DEVICE_CRT2_SUPPORT,
2077                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2078                                             CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
2079                                             &hpd);
2080                 break;
2081         case CT_MAC_G5_9600:
2082                 DRM_INFO("Connector Table: %d (mac g5 9600)\n",
2083                          rdev->mode_info.connector_table);
2084                 /* DVI - tv dac, dvo */
2085                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2086                 hpd.hpd = RADEON_HPD_1; /* ??? */
2087                 radeon_add_legacy_encoder(dev,
2088                                           radeon_get_encoder_enum(dev,
2089                                                                   ATOM_DEVICE_DFP2_SUPPORT,
2090                                                                   0),
2091                                           ATOM_DEVICE_DFP2_SUPPORT);
2092                 radeon_add_legacy_encoder(dev,
2093                                           radeon_get_encoder_enum(dev,
2094                                                                   ATOM_DEVICE_CRT2_SUPPORT,
2095                                                                   2),
2096                                           ATOM_DEVICE_CRT2_SUPPORT);
2097                 radeon_add_legacy_connector(dev, 0,
2098                                             ATOM_DEVICE_DFP2_SUPPORT |
2099                                             ATOM_DEVICE_CRT2_SUPPORT,
2100                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2101                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2102                                             &hpd);
2103                 /* ADC - primary dac, internal tmds */
2104                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2105                 hpd.hpd = RADEON_HPD_2; /* ??? */
2106                 radeon_add_legacy_encoder(dev,
2107                                           radeon_get_encoder_enum(dev,
2108                                                                   ATOM_DEVICE_DFP1_SUPPORT,
2109                                                                   0),
2110                                           ATOM_DEVICE_DFP1_SUPPORT);
2111                 radeon_add_legacy_encoder(dev,
2112                                           radeon_get_encoder_enum(dev,
2113                                                                   ATOM_DEVICE_CRT1_SUPPORT,
2114                                                                   1),
2115                                           ATOM_DEVICE_CRT1_SUPPORT);
2116                 radeon_add_legacy_connector(dev, 1,
2117                                             ATOM_DEVICE_DFP1_SUPPORT |
2118                                             ATOM_DEVICE_CRT1_SUPPORT,
2119                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2120                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2121                                             &hpd);
2122                 /* TV - TV DAC */
2123                 ddc_i2c.valid = false;
2124                 hpd.hpd = RADEON_HPD_NONE;
2125                 radeon_add_legacy_encoder(dev,
2126                                           radeon_get_encoder_enum(dev,
2127                                                                 ATOM_DEVICE_TV1_SUPPORT,
2128                                                                 2),
2129                                           ATOM_DEVICE_TV1_SUPPORT);
2130                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2131                                             DRM_MODE_CONNECTOR_SVIDEO,
2132                                             &ddc_i2c,
2133                                             CONNECTOR_OBJECT_ID_SVIDEO,
2134                                             &hpd);
2135                 break;
2136         default:
2137                 DRM_INFO("Connector table: %d (invalid)\n",
2138                          rdev->mode_info.connector_table);
2139                 return false;
2140         }
2141
2142         radeon_link_encoder_connector(dev);
2143
2144         return true;
2145 }
2146
2147 static bool radeon_apply_legacy_quirks(struct drm_device *dev,
2148                                        int bios_index,
2149                                        enum radeon_combios_connector
2150                                        *legacy_connector,
2151                                        struct radeon_i2c_bus_rec *ddc_i2c,
2152                                        struct radeon_hpd *hpd)
2153 {
2154
2155         /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
2156            one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
2157         if (dev->pdev->device == 0x515e &&
2158             dev->pdev->subsystem_vendor == 0x1014) {
2159                 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
2160                     ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
2161                         return false;
2162         }
2163
2164         /* X300 card with extra non-existent DVI port */
2165         if (dev->pdev->device == 0x5B60 &&
2166             dev->pdev->subsystem_vendor == 0x17af &&
2167             dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
2168                 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
2169                         return false;
2170         }
2171
2172         return true;
2173 }
2174
2175 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
2176 {
2177         /* Acer 5102 has non-existent TV port */
2178         if (dev->pdev->device == 0x5975 &&
2179             dev->pdev->subsystem_vendor == 0x1025 &&
2180             dev->pdev->subsystem_device == 0x009f)
2181                 return false;
2182
2183         /* HP dc5750 has non-existent TV port */
2184         if (dev->pdev->device == 0x5974 &&
2185             dev->pdev->subsystem_vendor == 0x103c &&
2186             dev->pdev->subsystem_device == 0x280a)
2187                 return false;
2188
2189         /* MSI S270 has non-existent TV port */
2190         if (dev->pdev->device == 0x5955 &&
2191             dev->pdev->subsystem_vendor == 0x1462 &&
2192             dev->pdev->subsystem_device == 0x0131)
2193                 return false;
2194
2195         return true;
2196 }
2197
2198 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
2199 {
2200         struct radeon_device *rdev = dev->dev_private;
2201         uint32_t ext_tmds_info;
2202
2203         if (rdev->flags & RADEON_IS_IGP) {
2204                 if (is_dvi_d)
2205                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2206                 else
2207                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2208         }
2209         ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2210         if (ext_tmds_info) {
2211                 uint8_t rev = RBIOS8(ext_tmds_info);
2212                 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
2213                 if (rev >= 3) {
2214                         if (is_dvi_d)
2215                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2216                         else
2217                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2218                 } else {
2219                         if (flags & 1) {
2220                                 if (is_dvi_d)
2221                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2222                                 else
2223                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2224                         }
2225                 }
2226         }
2227         if (is_dvi_d)
2228                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2229         else
2230                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2231 }
2232
2233 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2234 {
2235         struct radeon_device *rdev = dev->dev_private;
2236         uint32_t conn_info, entry, devices;
2237         uint16_t tmp, connector_object_id;
2238         enum radeon_combios_ddc ddc_type;
2239         enum radeon_combios_connector connector;
2240         int i = 0;
2241         struct radeon_i2c_bus_rec ddc_i2c;
2242         struct radeon_hpd hpd;
2243
2244         conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
2245         if (conn_info) {
2246                 for (i = 0; i < 4; i++) {
2247                         entry = conn_info + 2 + i * 2;
2248
2249                         if (!RBIOS16(entry))
2250                                 break;
2251
2252                         tmp = RBIOS16(entry);
2253
2254                         connector = (tmp >> 12) & 0xf;
2255
2256                         ddc_type = (tmp >> 8) & 0xf;
2257                         ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2258
2259                         switch (connector) {
2260                         case CONNECTOR_PROPRIETARY_LEGACY:
2261                         case CONNECTOR_DVI_I_LEGACY:
2262                         case CONNECTOR_DVI_D_LEGACY:
2263                                 if ((tmp >> 4) & 0x1)
2264                                         hpd.hpd = RADEON_HPD_2;
2265                                 else
2266                                         hpd.hpd = RADEON_HPD_1;
2267                                 break;
2268                         default:
2269                                 hpd.hpd = RADEON_HPD_NONE;
2270                                 break;
2271                         }
2272
2273                         if (!radeon_apply_legacy_quirks(dev, i, &connector,
2274                                                         &ddc_i2c, &hpd))
2275                                 continue;
2276
2277                         switch (connector) {
2278                         case CONNECTOR_PROPRIETARY_LEGACY:
2279                                 if ((tmp >> 4) & 0x1)
2280                                         devices = ATOM_DEVICE_DFP2_SUPPORT;
2281                                 else
2282                                         devices = ATOM_DEVICE_DFP1_SUPPORT;
2283                                 radeon_add_legacy_encoder(dev,
2284                                                           radeon_get_encoder_enum
2285                                                           (dev, devices, 0),
2286                                                           devices);
2287                                 radeon_add_legacy_connector(dev, i, devices,
2288                                                             legacy_connector_convert
2289                                                             [connector],
2290                                                             &ddc_i2c,
2291                                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2292                                                             &hpd);
2293                                 break;
2294                         case CONNECTOR_CRT_LEGACY:
2295                                 if (tmp & 0x1) {
2296                                         devices = ATOM_DEVICE_CRT2_SUPPORT;
2297                                         radeon_add_legacy_encoder(dev,
2298                                                                   radeon_get_encoder_enum
2299                                                                   (dev,
2300                                                                    ATOM_DEVICE_CRT2_SUPPORT,
2301                                                                    2),
2302                                                                   ATOM_DEVICE_CRT2_SUPPORT);
2303                                 } else {
2304                                         devices = ATOM_DEVICE_CRT1_SUPPORT;
2305                                         radeon_add_legacy_encoder(dev,
2306                                                                   radeon_get_encoder_enum
2307                                                                   (dev,
2308                                                                    ATOM_DEVICE_CRT1_SUPPORT,
2309                                                                    1),
2310                                                                   ATOM_DEVICE_CRT1_SUPPORT);
2311                                 }
2312                                 radeon_add_legacy_connector(dev,
2313                                                             i,
2314                                                             devices,
2315                                                             legacy_connector_convert
2316                                                             [connector],
2317                                                             &ddc_i2c,
2318                                                             CONNECTOR_OBJECT_ID_VGA,
2319                                                             &hpd);
2320                                 break;
2321                         case CONNECTOR_DVI_I_LEGACY:
2322                                 devices = 0;
2323                                 if (tmp & 0x1) {
2324                                         devices |= ATOM_DEVICE_CRT2_SUPPORT;
2325                                         radeon_add_legacy_encoder(dev,
2326                                                                   radeon_get_encoder_enum
2327                                                                   (dev,
2328                                                                    ATOM_DEVICE_CRT2_SUPPORT,
2329                                                                    2),
2330                                                                   ATOM_DEVICE_CRT2_SUPPORT);
2331                                 } else {
2332                                         devices |= ATOM_DEVICE_CRT1_SUPPORT;
2333                                         radeon_add_legacy_encoder(dev,
2334                                                                   radeon_get_encoder_enum
2335                                                                   (dev,
2336                                                                    ATOM_DEVICE_CRT1_SUPPORT,
2337                                                                    1),
2338                                                                   ATOM_DEVICE_CRT1_SUPPORT);
2339                                 }
2340                                 if ((tmp >> 4) & 0x1) {
2341                                         devices |= ATOM_DEVICE_DFP2_SUPPORT;
2342                                         radeon_add_legacy_encoder(dev,
2343                                                                   radeon_get_encoder_enum
2344                                                                   (dev,
2345                                                                    ATOM_DEVICE_DFP2_SUPPORT,
2346                                                                    0),
2347                                                                   ATOM_DEVICE_DFP2_SUPPORT);
2348                                         connector_object_id = combios_check_dl_dvi(dev, 0);
2349                                 } else {
2350                                         devices |= ATOM_DEVICE_DFP1_SUPPORT;
2351                                         radeon_add_legacy_encoder(dev,
2352                                                                   radeon_get_encoder_enum
2353                                                                   (dev,
2354                                                                    ATOM_DEVICE_DFP1_SUPPORT,
2355                                                                    0),
2356                                                                   ATOM_DEVICE_DFP1_SUPPORT);
2357                                         connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2358                                 }
2359                                 radeon_add_legacy_connector(dev,
2360                                                             i,
2361                                                             devices,
2362                                                             legacy_connector_convert
2363                                                             [connector],
2364                                                             &ddc_i2c,
2365                                                             connector_object_id,
2366                                                             &hpd);
2367                                 break;
2368                         case CONNECTOR_DVI_D_LEGACY:
2369                                 if ((tmp >> 4) & 0x1) {
2370                                         devices = ATOM_DEVICE_DFP2_SUPPORT;
2371                                         connector_object_id = combios_check_dl_dvi(dev, 1);
2372                                 } else {
2373                                         devices = ATOM_DEVICE_DFP1_SUPPORT;
2374                                         connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2375                                 }
2376                                 radeon_add_legacy_encoder(dev,
2377                                                           radeon_get_encoder_enum
2378                                                           (dev, devices, 0),
2379                                                           devices);
2380                                 radeon_add_legacy_connector(dev, i, devices,
2381                                                             legacy_connector_convert
2382                                                             [connector],
2383                                                             &ddc_i2c,
2384                                                             connector_object_id,
2385                                                             &hpd);
2386                                 break;
2387                         case CONNECTOR_CTV_LEGACY:
2388                         case CONNECTOR_STV_LEGACY:
2389                                 radeon_add_legacy_encoder(dev,
2390                                                           radeon_get_encoder_enum
2391                                                           (dev,
2392                                                            ATOM_DEVICE_TV1_SUPPORT,
2393                                                            2),
2394                                                           ATOM_DEVICE_TV1_SUPPORT);
2395                                 radeon_add_legacy_connector(dev, i,
2396                                                             ATOM_DEVICE_TV1_SUPPORT,
2397                                                             legacy_connector_convert
2398                                                             [connector],
2399                                                             &ddc_i2c,
2400                                                             CONNECTOR_OBJECT_ID_SVIDEO,
2401                                                             &hpd);
2402                                 break;
2403                         default:
2404                                 DRM_ERROR("Unknown connector type: %d\n",
2405                                           connector);
2406                                 continue;
2407                         }
2408
2409                 }
2410         } else {
2411                 uint16_t tmds_info =
2412                     combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2413                 if (tmds_info) {
2414                         DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n");
2415
2416                         radeon_add_legacy_encoder(dev,
2417                                                   radeon_get_encoder_enum(dev,
2418                                                                         ATOM_DEVICE_CRT1_SUPPORT,
2419                                                                         1),
2420                                                   ATOM_DEVICE_CRT1_SUPPORT);
2421                         radeon_add_legacy_encoder(dev,
2422                                                   radeon_get_encoder_enum(dev,
2423                                                                         ATOM_DEVICE_DFP1_SUPPORT,
2424                                                                         0),
2425                                                   ATOM_DEVICE_DFP1_SUPPORT);
2426
2427                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2428                         hpd.hpd = RADEON_HPD_1;
2429                         radeon_add_legacy_connector(dev,
2430                                                     0,
2431                                                     ATOM_DEVICE_CRT1_SUPPORT |
2432                                                     ATOM_DEVICE_DFP1_SUPPORT,
2433                                                     DRM_MODE_CONNECTOR_DVII,
2434                                                     &ddc_i2c,
2435                                                     CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2436                                                     &hpd);
2437                 } else {
2438                         uint16_t crt_info =
2439                                 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2440                         DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n");
2441                         if (crt_info) {
2442                                 radeon_add_legacy_encoder(dev,
2443                                                           radeon_get_encoder_enum(dev,
2444                                                                                 ATOM_DEVICE_CRT1_SUPPORT,
2445                                                                                 1),
2446                                                           ATOM_DEVICE_CRT1_SUPPORT);
2447                                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2448                                 hpd.hpd = RADEON_HPD_NONE;
2449                                 radeon_add_legacy_connector(dev,
2450                                                             0,
2451                                                             ATOM_DEVICE_CRT1_SUPPORT,
2452                                                             DRM_MODE_CONNECTOR_VGA,
2453                                                             &ddc_i2c,
2454                                                             CONNECTOR_OBJECT_ID_VGA,
2455                                                             &hpd);
2456                         } else {
2457                                 DRM_DEBUG_KMS("No connector info found\n");
2458                                 return false;
2459                         }
2460                 }
2461         }
2462
2463         if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2464                 uint16_t lcd_info =
2465                     combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2466                 if (lcd_info) {
2467                         uint16_t lcd_ddc_info =
2468                             combios_get_table_offset(dev,
2469                                                      COMBIOS_LCD_DDC_INFO_TABLE);
2470
2471                         radeon_add_legacy_encoder(dev,
2472                                                   radeon_get_encoder_enum(dev,
2473                                                                         ATOM_DEVICE_LCD1_SUPPORT,
2474                                                                         0),
2475                                                   ATOM_DEVICE_LCD1_SUPPORT);
2476
2477                         if (lcd_ddc_info) {
2478                                 ddc_type = RBIOS8(lcd_ddc_info + 2);
2479                                 switch (ddc_type) {
2480                                 case DDC_LCD:
2481                                         ddc_i2c =
2482                                                 combios_setup_i2c_bus(rdev,
2483                                                                       DDC_LCD,
2484                                                                       RBIOS32(lcd_ddc_info + 3),
2485                                                                       RBIOS32(lcd_ddc_info + 7));
2486                                         radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2487                                         break;
2488                                 case DDC_GPIO:
2489                                         ddc_i2c =
2490                                                 combios_setup_i2c_bus(rdev,
2491                                                                       DDC_GPIO,
2492                                                                       RBIOS32(lcd_ddc_info + 3),
2493                                                                       RBIOS32(lcd_ddc_info + 7));
2494                                         radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2495                                         break;
2496                                 default:
2497                                         ddc_i2c =
2498                                                 combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2499                                         break;
2500                                 }
2501                                 DRM_DEBUG_KMS("LCD DDC Info Table found!\n");
2502                         } else
2503                                 ddc_i2c.valid = false;
2504
2505                         hpd.hpd = RADEON_HPD_NONE;
2506                         radeon_add_legacy_connector(dev,
2507                                                     5,
2508                                                     ATOM_DEVICE_LCD1_SUPPORT,
2509                                                     DRM_MODE_CONNECTOR_LVDS,
2510                                                     &ddc_i2c,
2511                                                     CONNECTOR_OBJECT_ID_LVDS,
2512                                                     &hpd);
2513                 }
2514         }
2515
2516         /* check TV table */
2517         if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2518                 uint32_t tv_info =
2519                     combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2520                 if (tv_info) {
2521                         if (RBIOS8(tv_info + 6) == 'T') {
2522                                 if (radeon_apply_legacy_tv_quirks(dev)) {
2523                                         hpd.hpd = RADEON_HPD_NONE;
2524                                         ddc_i2c.valid = false;
2525                                         radeon_add_legacy_encoder(dev,
2526                                                                   radeon_get_encoder_enum
2527                                                                   (dev,
2528                                                                    ATOM_DEVICE_TV1_SUPPORT,
2529                                                                    2),
2530                                                                   ATOM_DEVICE_TV1_SUPPORT);
2531                                         radeon_add_legacy_connector(dev, 6,
2532                                                                     ATOM_DEVICE_TV1_SUPPORT,
2533                                                                     DRM_MODE_CONNECTOR_SVIDEO,
2534                                                                     &ddc_i2c,
2535                                                                     CONNECTOR_OBJECT_ID_SVIDEO,
2536                                                                     &hpd);
2537                                 }
2538                         }
2539                 }
2540         }
2541
2542         radeon_link_encoder_connector(dev);
2543
2544         return true;
2545 }
2546
2547 static const char *thermal_controller_names[] = {
2548         "NONE",
2549         "lm63",
2550         "adm1032",
2551 };
2552
2553 void radeon_combios_get_power_modes(struct radeon_device *rdev)
2554 {
2555         struct drm_device *dev = rdev->ddev;
2556         u16 offset, misc, misc2 = 0;
2557         u8 rev, blocks, tmp;
2558         int state_index = 0;
2559
2560         rdev->pm.default_power_state_index = -1;
2561
2562         /* allocate 2 power states */
2563         rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2, GFP_KERNEL);
2564         if (!rdev->pm.power_state) {
2565                 rdev->pm.default_power_state_index = state_index;
2566                 rdev->pm.num_power_states = 0;
2567
2568                 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2569                 rdev->pm.current_clock_mode_index = 0;
2570                 return;
2571         }
2572
2573         /* check for a thermal chip */
2574         offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE);
2575         if (offset) {
2576                 u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0;
2577                 struct radeon_i2c_bus_rec i2c_bus;
2578
2579                 rev = RBIOS8(offset);
2580
2581                 if (rev == 0) {
2582                         thermal_controller = RBIOS8(offset + 3);
2583                         gpio = RBIOS8(offset + 4) & 0x3f;
2584                         i2c_addr = RBIOS8(offset + 5);
2585                 } else if (rev == 1) {
2586                         thermal_controller = RBIOS8(offset + 4);
2587                         gpio = RBIOS8(offset + 5) & 0x3f;
2588                         i2c_addr = RBIOS8(offset + 6);
2589                 } else if (rev == 2) {
2590                         thermal_controller = RBIOS8(offset + 4);
2591                         gpio = RBIOS8(offset + 5) & 0x3f;
2592                         i2c_addr = RBIOS8(offset + 6);
2593                         clk_bit = RBIOS8(offset + 0xa);
2594                         data_bit = RBIOS8(offset + 0xb);
2595                 }
2596                 if ((thermal_controller > 0) && (thermal_controller < 3)) {
2597                         DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2598                                  thermal_controller_names[thermal_controller],
2599                                  i2c_addr >> 1);
2600                         if (gpio == DDC_LCD) {
2601                                 /* MM i2c */
2602                                 i2c_bus.valid = true;
2603                                 i2c_bus.hw_capable = true;
2604                                 i2c_bus.mm_i2c = true;
2605                                 i2c_bus.i2c_id = 0xa0;
2606                         } else if (gpio == DDC_GPIO)
2607                                 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit);
2608                         else
2609                                 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
2610                         rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2611                         if (rdev->pm.i2c_bus) {
2612                                 struct i2c_board_info info = { };
2613                                 const char *name = thermal_controller_names[thermal_controller];
2614                                 info.addr = i2c_addr >> 1;
2615                                 strlcpy(info.type, name, sizeof(info.type));
2616                                 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2617                         }
2618                 }
2619         }
2620
2621         if (rdev->flags & RADEON_IS_MOBILITY) {
2622                 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2623                 if (offset) {
2624                         rev = RBIOS8(offset);
2625                         blocks = RBIOS8(offset + 0x2);
2626                         /* power mode 0 tends to be the only valid one */
2627                         rdev->pm.power_state[state_index].num_clock_modes = 1;
2628                         rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2629                         rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2630                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2631                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2632                                 goto default_mode;
2633                         rdev->pm.power_state[state_index].type =
2634                                 POWER_STATE_TYPE_BATTERY;
2635                         misc = RBIOS16(offset + 0x5 + 0x0);
2636                         if (rev > 4)
2637                                 misc2 = RBIOS16(offset + 0x5 + 0xe);
2638                         rdev->pm.power_state[state_index].misc = misc;
2639                         rdev->pm.power_state[state_index].misc2 = misc2;
2640                         if (misc & 0x4) {
2641                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2642                                 if (misc & 0x8)
2643                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2644                                                 true;
2645                                 else
2646                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2647                                                 false;
2648                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2649                                 if (rev < 6) {
2650                                         rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2651                                                 RBIOS16(offset + 0x5 + 0xb) * 4;
2652                                         tmp = RBIOS8(offset + 0x5 + 0xd);
2653                                         rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2654                                 } else {
2655                                         u8 entries = RBIOS8(offset + 0x5 + 0xb);
2656                                         u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2657                                         if (entries && voltage_table_offset) {
2658                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2659                                                         RBIOS16(voltage_table_offset) * 4;
2660                                                 tmp = RBIOS8(voltage_table_offset + 0x2);
2661                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2662                                         } else
2663                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2664                                 }
2665                                 switch ((misc2 & 0x700) >> 8) {
2666                                 case 0:
2667                                 default:
2668                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2669                                         break;
2670                                 case 1:
2671                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2672                                         break;
2673                                 case 2:
2674                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2675                                         break;
2676                                 case 3:
2677                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2678                                         break;
2679                                 case 4:
2680                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2681                                         break;
2682                                 }
2683                         } else
2684                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2685                         if (rev > 6)
2686                                 rdev->pm.power_state[state_index].pcie_lanes =
2687                                         RBIOS8(offset + 0x5 + 0x10);
2688                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2689                         state_index++;
2690                 } else {
2691                         /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2692                 }
2693         } else {
2694                 /* XXX figure out some good default low power mode for desktop cards */
2695         }
2696
2697 default_mode:
2698         /* add the default mode */
2699         rdev->pm.power_state[state_index].type =
2700                 POWER_STATE_TYPE_DEFAULT;
2701         rdev->pm.power_state[state_index].num_clock_modes = 1;
2702         rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2703         rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2704         rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
2705         if ((state_index > 0) &&
2706             (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO))
2707                 rdev->pm.power_state[state_index].clock_info[0].voltage =
2708                         rdev->pm.power_state[0].clock_info[0].voltage;
2709         else
2710                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2711         rdev->pm.power_state[state_index].pcie_lanes = 16;
2712         rdev->pm.power_state[state_index].flags = 0;
2713         rdev->pm.default_power_state_index = state_index;
2714         rdev->pm.num_power_states = state_index + 1;
2715
2716         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2717         rdev->pm.current_clock_mode_index = 0;
2718 }
2719
2720 void radeon_external_tmds_setup(struct drm_encoder *encoder)
2721 {
2722         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2723         struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2724
2725         if (!tmds)
2726                 return;
2727
2728         switch (tmds->dvo_chip) {
2729         case DVO_SIL164:
2730                 /* sil 164 */
2731                 radeon_i2c_put_byte(tmds->i2c_bus,
2732                                     tmds->slave_addr,
2733                                     0x08, 0x30);
2734                 radeon_i2c_put_byte(tmds->i2c_bus,
2735                                        tmds->slave_addr,
2736                                        0x09, 0x00);
2737                 radeon_i2c_put_byte(tmds->i2c_bus,
2738                                     tmds->slave_addr,
2739                                     0x0a, 0x90);
2740                 radeon_i2c_put_byte(tmds->i2c_bus,
2741                                     tmds->slave_addr,
2742                                     0x0c, 0x89);
2743                 radeon_i2c_put_byte(tmds->i2c_bus,
2744                                        tmds->slave_addr,
2745                                        0x08, 0x3b);
2746                 break;
2747         case DVO_SIL1178:
2748                 /* sil 1178 - untested */
2749                 /*
2750                  * 0x0f, 0x44
2751                  * 0x0f, 0x4c
2752                  * 0x0e, 0x01
2753                  * 0x0a, 0x80
2754                  * 0x09, 0x30
2755                  * 0x0c, 0xc9
2756                  * 0x0d, 0x70
2757                  * 0x08, 0x32
2758                  * 0x08, 0x33
2759                  */
2760                 break;
2761         default:
2762                 break;
2763         }
2764
2765 }
2766
2767 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2768 {
2769         struct drm_device *dev = encoder->dev;
2770         struct radeon_device *rdev = dev->dev_private;
2771         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2772         uint16_t offset;
2773         uint8_t blocks, slave_addr, rev;
2774         uint32_t index, id;
2775         uint32_t reg, val, and_mask, or_mask;
2776         struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2777
2778         if (!tmds)
2779                 return false;
2780
2781         if (rdev->flags & RADEON_IS_IGP) {
2782                 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2783                 rev = RBIOS8(offset);
2784                 if (offset) {
2785                         rev = RBIOS8(offset);
2786                         if (rev > 1) {
2787                                 blocks = RBIOS8(offset + 3);
2788                                 index = offset + 4;
2789                                 while (blocks > 0) {
2790                                         id = RBIOS16(index);
2791                                         index += 2;
2792                                         switch (id >> 13) {
2793                                         case 0:
2794                                                 reg = (id & 0x1fff) * 4;
2795                                                 val = RBIOS32(index);
2796                                                 index += 4;
2797                                                 WREG32(reg, val);
2798                                                 break;
2799                                         case 2:
2800                                                 reg = (id & 0x1fff) * 4;
2801                                                 and_mask = RBIOS32(index);
2802                                                 index += 4;
2803                                                 or_mask = RBIOS32(index);
2804                                                 index += 4;
2805                                                 val = RREG32(reg);
2806                                                 val = (val & and_mask) | or_mask;
2807                                                 WREG32(reg, val);
2808                                                 break;
2809                                         case 3:
2810                                                 val = RBIOS16(index);
2811                                                 index += 2;
2812                                                 udelay(val);
2813                                                 break;
2814                                         case 4:
2815                                                 val = RBIOS16(index);
2816                                                 index += 2;
2817                                                 udelay(val * 1000);
2818                                                 break;
2819                                         case 6:
2820                                                 slave_addr = id & 0xff;
2821                                                 slave_addr >>= 1; /* 7 bit addressing */
2822                                                 index++;
2823                                                 reg = RBIOS8(index);
2824                                                 index++;
2825                                                 val = RBIOS8(index);
2826                                                 index++;
2827                                                 radeon_i2c_put_byte(tmds->i2c_bus,
2828                                                                     slave_addr,
2829                                                                     reg, val);
2830                                                 break;
2831                                         default:
2832                                                 DRM_ERROR("Unknown id %d\n", id >> 13);
2833                                                 break;
2834                                         }
2835                                         blocks--;
2836                                 }
2837                                 return true;
2838                         }
2839                 }
2840         } else {
2841                 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2842                 if (offset) {
2843                         index = offset + 10;
2844                         id = RBIOS16(index);
2845                         while (id != 0xffff) {
2846                                 index += 2;
2847                                 switch (id >> 13) {
2848                                 case 0:
2849                                         reg = (id & 0x1fff) * 4;
2850                                         val = RBIOS32(index);
2851                                         WREG32(reg, val);
2852                                         break;
2853                                 case 2:
2854                                         reg = (id & 0x1fff) * 4;
2855                                         and_mask = RBIOS32(index);
2856                                         index += 4;
2857                                         or_mask = RBIOS32(index);
2858                                         index += 4;
2859                                         val = RREG32(reg);
2860                                         val = (val & and_mask) | or_mask;
2861                                         WREG32(reg, val);
2862                                         break;
2863                                 case 4:
2864                                         val = RBIOS16(index);
2865                                         index += 2;
2866                                         udelay(val);
2867                                         break;
2868                                 case 5:
2869                                         reg = id & 0x1fff;
2870                                         and_mask = RBIOS32(index);
2871                                         index += 4;
2872                                         or_mask = RBIOS32(index);
2873                                         index += 4;
2874                                         val = RREG32_PLL(reg);
2875                                         val = (val & and_mask) | or_mask;
2876                                         WREG32_PLL(reg, val);
2877                                         break;
2878                                 case 6:
2879                                         reg = id & 0x1fff;
2880                                         val = RBIOS8(index);
2881                                         index += 1;
2882                                         radeon_i2c_put_byte(tmds->i2c_bus,
2883                                                             tmds->slave_addr,
2884                                                             reg, val);
2885                                         break;
2886                                 default:
2887                                         DRM_ERROR("Unknown id %d\n", id >> 13);
2888                                         break;
2889                                 }
2890                                 id = RBIOS16(index);
2891                         }
2892                         return true;
2893                 }
2894         }
2895         return false;
2896 }
2897
2898 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
2899 {
2900         struct radeon_device *rdev = dev->dev_private;
2901
2902         if (offset) {
2903                 while (RBIOS16(offset)) {
2904                         uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
2905                         uint32_t addr = (RBIOS16(offset) & 0x1fff);
2906                         uint32_t val, and_mask, or_mask;
2907                         uint32_t tmp;
2908
2909                         offset += 2;
2910                         switch (cmd) {
2911                         case 0:
2912                                 val = RBIOS32(offset);
2913                                 offset += 4;
2914                                 WREG32(addr, val);
2915                                 break;
2916                         case 1:
2917                                 val = RBIOS32(offset);
2918                                 offset += 4;
2919                                 WREG32(addr, val);
2920                                 break;
2921                         case 2:
2922                                 and_mask = RBIOS32(offset);
2923                                 offset += 4;
2924                                 or_mask = RBIOS32(offset);
2925                                 offset += 4;
2926                                 tmp = RREG32(addr);
2927                                 tmp &= and_mask;
2928                                 tmp |= or_mask;
2929                                 WREG32(addr, tmp);
2930                                 break;
2931                         case 3:
2932                                 and_mask = RBIOS32(offset);
2933                                 offset += 4;
2934                                 or_mask = RBIOS32(offset);
2935                                 offset += 4;
2936                                 tmp = RREG32(addr);
2937                                 tmp &= and_mask;
2938                                 tmp |= or_mask;
2939                                 WREG32(addr, tmp);
2940                                 break;
2941                         case 4:
2942                                 val = RBIOS16(offset);
2943                                 offset += 2;
2944                                 udelay(val);
2945                                 break;
2946                         case 5:
2947                                 val = RBIOS16(offset);
2948                                 offset += 2;
2949                                 switch (addr) {
2950                                 case 8:
2951                                         while (val--) {
2952                                                 if (!
2953                                                     (RREG32_PLL
2954                                                      (RADEON_CLK_PWRMGT_CNTL) &
2955                                                      RADEON_MC_BUSY))
2956                                                         break;
2957                                         }
2958                                         break;
2959                                 case 9:
2960                                         while (val--) {
2961                                                 if ((RREG32(RADEON_MC_STATUS) &
2962                                                      RADEON_MC_IDLE))
2963                                                         break;
2964                                         }
2965                                         break;
2966                                 default:
2967                                         break;
2968                                 }
2969                                 break;
2970                         default:
2971                                 break;
2972                         }
2973                 }
2974         }
2975 }
2976
2977 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
2978 {
2979         struct radeon_device *rdev = dev->dev_private;
2980
2981         if (offset) {
2982                 while (RBIOS8(offset)) {
2983                         uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
2984                         uint8_t addr = (RBIOS8(offset) & 0x3f);
2985                         uint32_t val, shift, tmp;
2986                         uint32_t and_mask, or_mask;
2987
2988                         offset++;
2989                         switch (cmd) {
2990                         case 0:
2991                                 val = RBIOS32(offset);
2992                                 offset += 4;
2993                                 WREG32_PLL(addr, val);
2994                                 break;
2995                         case 1:
2996                                 shift = RBIOS8(offset) * 8;
2997                                 offset++;
2998                                 and_mask = RBIOS8(offset) << shift;
2999                                 and_mask |= ~(0xff << shift);
3000                                 offset++;
3001                                 or_mask = RBIOS8(offset) << shift;
3002                                 offset++;
3003                                 tmp = RREG32_PLL(addr);
3004                                 tmp &= and_mask;
3005                                 tmp |= or_mask;
3006                                 WREG32_PLL(addr, tmp);
3007                                 break;
3008                         case 2:
3009                         case 3:
3010                                 tmp = 1000;
3011                                 switch (addr) {
3012                                 case 1:
3013                                         udelay(150);
3014                                         break;
3015                                 case 2:
3016                                         udelay(1000);
3017                                         break;
3018                                 case 3:
3019                                         while (tmp--) {
3020                                                 if (!
3021                                                     (RREG32_PLL
3022                                                      (RADEON_CLK_PWRMGT_CNTL) &
3023                                                      RADEON_MC_BUSY))
3024                                                         break;
3025                                         }
3026                                         break;
3027                                 case 4:
3028                                         while (tmp--) {
3029                                                 if (RREG32_PLL
3030                                                     (RADEON_CLK_PWRMGT_CNTL) &
3031                                                     RADEON_DLL_READY)
3032                                                         break;
3033                                         }
3034                                         break;
3035                                 case 5:
3036                                         tmp =
3037                                             RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
3038                                         if (tmp & RADEON_CG_NO1_DEBUG_0) {
3039 #if 0
3040                                                 uint32_t mclk_cntl =
3041                                                     RREG32_PLL
3042                                                     (RADEON_MCLK_CNTL);
3043                                                 mclk_cntl &= 0xffff0000;
3044                                                 /*mclk_cntl |= 0x00001111;*//* ??? */
3045                                                 WREG32_PLL(RADEON_MCLK_CNTL,
3046                                                            mclk_cntl);
3047                                                 udelay(10000);
3048 #endif
3049                                                 WREG32_PLL
3050                                                     (RADEON_CLK_PWRMGT_CNTL,
3051                                                      tmp &
3052                                                      ~RADEON_CG_NO1_DEBUG_0);
3053                                                 udelay(10000);
3054                                         }
3055                                         break;
3056                                 default:
3057                                         break;
3058                                 }
3059                                 break;
3060                         default:
3061                                 break;
3062                         }
3063                 }
3064         }
3065 }
3066
3067 static void combios_parse_ram_reset_table(struct drm_device *dev,
3068                                           uint16_t offset)
3069 {
3070         struct radeon_device *rdev = dev->dev_private;
3071         uint32_t tmp;
3072
3073         if (offset) {
3074                 uint8_t val = RBIOS8(offset);
3075                 while (val != 0xff) {
3076                         offset++;
3077
3078                         if (val == 0x0f) {
3079                                 uint32_t channel_complete_mask;
3080
3081                                 if (ASIC_IS_R300(rdev))
3082                                         channel_complete_mask =
3083                                             R300_MEM_PWRUP_COMPLETE;
3084                                 else
3085                                         channel_complete_mask =
3086                                             RADEON_MEM_PWRUP_COMPLETE;
3087                                 tmp = 20000;
3088                                 while (tmp--) {
3089                                         if ((RREG32(RADEON_MEM_STR_CNTL) &
3090                                              channel_complete_mask) ==
3091                                             channel_complete_mask)
3092                                                 break;
3093                                 }
3094                         } else {
3095                                 uint32_t or_mask = RBIOS16(offset);
3096                                 offset += 2;
3097
3098                                 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3099                                 tmp &= RADEON_SDRAM_MODE_MASK;
3100                                 tmp |= or_mask;
3101                                 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3102
3103                                 or_mask = val << 24;
3104                                 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3105                                 tmp &= RADEON_B3MEM_RESET_MASK;
3106                                 tmp |= or_mask;
3107                                 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3108                         }
3109                         val = RBIOS8(offset);
3110                 }
3111         }
3112 }
3113
3114 static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
3115                                    int mem_addr_mapping)
3116 {
3117         struct radeon_device *rdev = dev->dev_private;
3118         uint32_t mem_cntl;
3119         uint32_t mem_size;
3120         uint32_t addr = 0;
3121
3122         mem_cntl = RREG32(RADEON_MEM_CNTL);
3123         if (mem_cntl & RV100_HALF_MODE)
3124                 ram /= 2;
3125         mem_size = ram;
3126         mem_cntl &= ~(0xff << 8);
3127         mem_cntl |= (mem_addr_mapping & 0xff) << 8;
3128         WREG32(RADEON_MEM_CNTL, mem_cntl);
3129         RREG32(RADEON_MEM_CNTL);
3130
3131         /* sdram reset ? */
3132
3133         /* something like this????  */
3134         while (ram--) {
3135                 addr = ram * 1024 * 1024;
3136                 /* write to each page */
3137                 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
3138                 WREG32(RADEON_MM_DATA, 0xdeadbeef);
3139                 /* read back and verify */
3140                 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
3141                 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
3142                         return 0;
3143         }
3144
3145         return mem_size;
3146 }
3147
3148 static void combios_write_ram_size(struct drm_device *dev)
3149 {
3150         struct radeon_device *rdev = dev->dev_private;
3151         uint8_t rev;
3152         uint16_t offset;
3153         uint32_t mem_size = 0;
3154         uint32_t mem_cntl = 0;
3155
3156         /* should do something smarter here I guess... */
3157         if (rdev->flags & RADEON_IS_IGP)
3158                 return;
3159
3160         /* first check detected mem table */
3161         offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
3162         if (offset) {
3163                 rev = RBIOS8(offset);
3164                 if (rev < 3) {
3165                         mem_cntl = RBIOS32(offset + 1);
3166                         mem_size = RBIOS16(offset + 5);
3167                         if ((rdev->family < CHIP_R200) &&
3168                             !ASIC_IS_RN50(rdev))
3169                                 WREG32(RADEON_MEM_CNTL, mem_cntl);
3170                 }
3171         }
3172
3173         if (!mem_size) {
3174                 offset =
3175                     combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
3176                 if (offset) {
3177                         rev = RBIOS8(offset - 1);
3178                         if (rev < 1) {
3179                                 if ((rdev->family < CHIP_R200)
3180                                     && !ASIC_IS_RN50(rdev)) {
3181                                         int ram = 0;
3182                                         int mem_addr_mapping = 0;
3183
3184                                         while (RBIOS8(offset)) {
3185                                                 ram = RBIOS8(offset);
3186                                                 mem_addr_mapping =
3187                                                     RBIOS8(offset + 1);
3188                                                 if (mem_addr_mapping != 0x25)
3189                                                         ram *= 2;
3190                                                 mem_size =
3191                                                     combios_detect_ram(dev, ram,
3192                                                                        mem_addr_mapping);
3193                                                 if (mem_size)
3194                                                         break;
3195                                                 offset += 2;
3196                                         }
3197                                 } else
3198                                         mem_size = RBIOS8(offset);
3199                         } else {
3200                                 mem_size = RBIOS8(offset);
3201                                 mem_size *= 2;  /* convert to MB */
3202                         }
3203                 }
3204         }
3205
3206         mem_size *= (1024 * 1024);      /* convert to bytes */
3207         WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
3208 }
3209
3210 void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
3211 {
3212         uint16_t dyn_clk_info =
3213             combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3214
3215         if (dyn_clk_info)
3216                 combios_parse_pll_table(dev, dyn_clk_info);
3217 }
3218
3219 void radeon_combios_asic_init(struct drm_device *dev)
3220 {
3221         struct radeon_device *rdev = dev->dev_private;
3222         uint16_t table;
3223
3224         /* port hardcoded mac stuff from radeonfb */
3225         if (rdev->bios == NULL)
3226                 return;
3227
3228         /* ASIC INIT 1 */
3229         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
3230         if (table)
3231                 combios_parse_mmio_table(dev, table);
3232
3233         /* PLL INIT */
3234         table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
3235         if (table)
3236                 combios_parse_pll_table(dev, table);
3237
3238         /* ASIC INIT 2 */
3239         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
3240         if (table)
3241                 combios_parse_mmio_table(dev, table);
3242
3243         if (!(rdev->flags & RADEON_IS_IGP)) {
3244                 /* ASIC INIT 4 */
3245                 table =
3246                     combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
3247                 if (table)
3248                         combios_parse_mmio_table(dev, table);
3249
3250                 /* RAM RESET */
3251                 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
3252                 if (table)
3253                         combios_parse_ram_reset_table(dev, table);
3254
3255                 /* ASIC INIT 3 */
3256                 table =
3257                     combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3258                 if (table)
3259                         combios_parse_mmio_table(dev, table);
3260
3261                 /* write CONFIG_MEMSIZE */
3262                 combios_write_ram_size(dev);
3263         }
3264
3265         /* quirk for rs4xx HP nx6125 laptop to make it resume
3266          * - it hangs on resume inside the dynclk 1 table.
3267          */
3268         if (rdev->family == CHIP_RS480 &&
3269             rdev->pdev->subsystem_vendor == 0x103c &&
3270             rdev->pdev->subsystem_device == 0x308b)
3271                 return;
3272
3273         /* quirk for rs4xx HP dv5000 laptop to make it resume
3274          * - it hangs on resume inside the dynclk 1 table.
3275          */
3276         if (rdev->family == CHIP_RS480 &&
3277             rdev->pdev->subsystem_vendor == 0x103c &&
3278             rdev->pdev->subsystem_device == 0x30a4)
3279                 return;
3280
3281         /* DYN CLK 1 */
3282         table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3283         if (table)
3284                 combios_parse_pll_table(dev, table);
3285
3286 }
3287
3288 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3289 {
3290         struct radeon_device *rdev = dev->dev_private;
3291         uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3292
3293         bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3294         bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3295         bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3296
3297         /* let the bios control the backlight */
3298         bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3299
3300         /* tell the bios not to handle mode switching */
3301         bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3302                            RADEON_ACC_MODE_CHANGE);
3303
3304         /* tell the bios a driver is loaded */
3305         bios_7_scratch |= RADEON_DRV_LOADED;
3306
3307         WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3308         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3309         WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3310 }
3311
3312 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3313 {
3314         struct drm_device *dev = encoder->dev;
3315         struct radeon_device *rdev = dev->dev_private;
3316         uint32_t bios_6_scratch;
3317
3318         bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3319
3320         if (lock)
3321                 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3322         else
3323                 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3324
3325         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3326 }
3327
3328 void
3329 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3330                                       struct drm_encoder *encoder,
3331                                       bool connected)
3332 {
3333         struct drm_device *dev = connector->dev;
3334         struct radeon_device *rdev = dev->dev_private;
3335         struct radeon_connector *radeon_connector =
3336             to_radeon_connector(connector);
3337         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3338         uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3339         uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3340
3341         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3342             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3343                 if (connected) {
3344                         DRM_DEBUG_KMS("TV1 connected\n");
3345                         /* fix me */
3346                         bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3347                         /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3348                         bios_5_scratch |= RADEON_TV1_ON;
3349                         bios_5_scratch |= RADEON_ACC_REQ_TV1;
3350                 } else {
3351                         DRM_DEBUG_KMS("TV1 disconnected\n");
3352                         bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3353                         bios_5_scratch &= ~RADEON_TV1_ON;
3354                         bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3355                 }
3356         }
3357         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3358             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3359                 if (connected) {
3360                         DRM_DEBUG_KMS("LCD1 connected\n");
3361                         bios_4_scratch |= RADEON_LCD1_ATTACHED;
3362                         bios_5_scratch |= RADEON_LCD1_ON;
3363                         bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3364                 } else {
3365                         DRM_DEBUG_KMS("LCD1 disconnected\n");
3366                         bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3367                         bios_5_scratch &= ~RADEON_LCD1_ON;
3368                         bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3369                 }
3370         }
3371         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3372             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3373                 if (connected) {
3374                         DRM_DEBUG_KMS("CRT1 connected\n");
3375                         bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3376                         bios_5_scratch |= RADEON_CRT1_ON;
3377                         bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3378                 } else {
3379                         DRM_DEBUG_KMS("CRT1 disconnected\n");
3380                         bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3381                         bios_5_scratch &= ~RADEON_CRT1_ON;
3382                         bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3383                 }
3384         }
3385         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3386             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3387                 if (connected) {
3388                         DRM_DEBUG_KMS("CRT2 connected\n");
3389                         bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3390                         bios_5_scratch |= RADEON_CRT2_ON;
3391                         bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3392                 } else {
3393                         DRM_DEBUG_KMS("CRT2 disconnected\n");
3394                         bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3395                         bios_5_scratch &= ~RADEON_CRT2_ON;
3396                         bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3397                 }
3398         }
3399         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3400             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3401                 if (connected) {
3402                         DRM_DEBUG_KMS("DFP1 connected\n");
3403                         bios_4_scratch |= RADEON_DFP1_ATTACHED;
3404                         bios_5_scratch |= RADEON_DFP1_ON;
3405                         bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3406                 } else {
3407                         DRM_DEBUG_KMS("DFP1 disconnected\n");
3408                         bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3409                         bios_5_scratch &= ~RADEON_DFP1_ON;
3410                         bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3411                 }
3412         }
3413         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3414             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3415                 if (connected) {
3416                         DRM_DEBUG_KMS("DFP2 connected\n");
3417                         bios_4_scratch |= RADEON_DFP2_ATTACHED;
3418                         bios_5_scratch |= RADEON_DFP2_ON;
3419                         bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3420                 } else {
3421                         DRM_DEBUG_KMS("DFP2 disconnected\n");
3422                         bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3423                         bios_5_scratch &= ~RADEON_DFP2_ON;
3424                         bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3425                 }
3426         }
3427         WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3428         WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3429 }
3430
3431 void
3432 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3433 {
3434         struct drm_device *dev = encoder->dev;
3435         struct radeon_device *rdev = dev->dev_private;
3436         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3437         uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3438
3439         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3440                 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3441                 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3442         }
3443         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3444                 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3445                 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3446         }
3447         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3448                 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3449                 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3450         }
3451         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3452                 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3453                 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3454         }
3455         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3456                 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3457                 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3458         }
3459         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3460                 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3461                 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3462         }
3463         WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3464 }
3465
3466 void
3467 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3468 {
3469         struct drm_device *dev = encoder->dev;
3470         struct radeon_device *rdev = dev->dev_private;
3471         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3472         uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3473
3474         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3475                 if (on)
3476                         bios_6_scratch |= RADEON_TV_DPMS_ON;
3477                 else
3478                         bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3479         }
3480         if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3481                 if (on)
3482                         bios_6_scratch |= RADEON_CRT_DPMS_ON;
3483                 else
3484                         bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3485         }
3486         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3487                 if (on)
3488                         bios_6_scratch |= RADEON_LCD_DPMS_ON;
3489                 else
3490                         bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3491         }
3492         if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3493                 if (on)
3494                         bios_6_scratch |= RADEON_DFP_DPMS_ON;
3495                 else
3496                         bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3497         }
3498         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3499 }